MIC2184 DATA SHEET (11/05/2015) DOWNLOAD

MIC2184
Micrel, Inc.
MIC2184
Low Voltage Buck PWM Control IC
General Description
Features
Micrel’s MIC2184 is a high efficiency PWM buck control IC.
With its wide input voltage range of 2.9V to 14V, the MIC2184
can be used to efficiently step voltages down in 1- or 2-cell Li
Ion battery powered applications, as well as in fixed 3.3V, 5V,
or 12V systems.
Efficiencies over 90% are achievable over a wide range of
load conditions with the MIC2184’s PWM control scheme.
The operating frequency can be divided by two by raising the
FREQ/2 pin to VDD. This allows the user to optimize efficiency
versus board space. It also allows the MIC2184 to be externally synchronized to frequencies below its nominal 400KHz.
The MIC2184 features an oscillator output, FreqOut, which
can be used to implement a simple charge pump in low
voltage applications. The output of the charge pump can be
fed into the gate drive power circuitry via the VINP pin,
allowing enhanced gate drive, hence higher efficiencies,
despite low input voltages.
MIC2184 features a 1µA shutdown mode, and a programmable undervoltage lockout, making it well suited for portable
applications.
The MIC2184 is available in 16 pin SOP and QSOP package
options with a junction temperture range range from –40°C
to +125°C.
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Input voltage range: 2.9V to 14V
>90% efficiency
Oscillator frequency of 400kHz
Frequency divide-by-two pin
Frequency sync to 600kHz
FrequOut oscillator output allows simple charge pump
implementation in low voltage systems
1.245V reference output
Front edge blanking
5Ω output driver
Soft start
PWM current mode control
1µA shutdown current
Cycle-by-cycle current limiting
Frequency foldback short circuit protection
Adjustable under-voltage lockout
16 pin narrow-body SOIC and QSOP package options
Applications
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3.3V to 2.5V/1.8V/1.5V conversion
DC power distribution systems
Wireless Modems
ADSL line cards
1-and 2-cell Li Ion battery operated equipment
Satellite Phones
Typical Application
VIN = 3.3V
16
15mΩ
VINP
1
7
2
16
10
4
3
13
VINA
CSH
EN/UVLO
CSL
FreqOut
FREQ/2
OUTP
MIC2184 EFFICIENCY
100
95
9
8
14
Q3
Si9803DY(x2)
VOUT
2.5V @5A
MIC2184
4.7µH
VDD
COMP
SS
PGND
VREF
SYNC
11
FB
12
220µF(x2)
6.3V
6
SGND
EFFICIENCY (%)
120µF (x2)
6.3V
90
85
80
75
70
65
60
55
50
0
VIN = 3.3V
VOUT = 2.5V
fS = 200kHz
1
2
3
4
OUTPUT CURRENT (A)
5
5
Adjustable Output Buck Converter
Micrel, Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2005
1
M9999-042205
MIC2184
Micrel, Inc.
Ordering Information
Part Number
Standard
Pb-Free
Output
Voltage
Frequency
Junction
Temp. Range
Package
MIC2184BM
MIC2184YM
Adj.
400KHz
–40°C to +125°C
16-lead SOP
MIC2184BQS
MIC2184YQS
Adj.
400KHz
–40°C to +125°C
16-lead QSOP
Pin Configuration
VINA 1
16 VINP
FreqOut 2
15 FREQ/2
SS 3
14 OUTP
COMP 4
13 VREF
SGND 5
12 PGND
FB 6
11 SYNC
EN/UVLO 7
10 VDD
CSL 8
9 CSH
16 Lead SOIC
(M)
M9999-042205
2
April 2005
MIC2184
Micrel, Inc.
Pin Description
Pin Number
Pin Name
1
VINA
2
FreqOut
3
SS
4
COMP
Compensation (Output): Internal error amplifier output. Connect to a
capacitor or series RC network to compensate the regulator’s control loop.
5
SGND
Small signal ground: must be routed separately from other grounds to the (-)
terminal of COUT.
6
FB
7
EN/UVLO
8
CSL
The (-) input to the current limit comparator. A built in offset of 100mV
between CSH and CSL in conjunction with the current sense resistor sets
the current limit threshold level. This is also the (-) input to the current
amplifier.
9
CSH
The (+) input to the current limit comparator. A built in offset of 100mV
between CSH and CSL in conjunction with the current sense resistor sets
the current limit threshold level. This is also the (+) input to the current
amplifier.
10
VDD
3V internal linear-regulator output. VDD is also the supply voltage bus for the
chip. Bypass to SGND with 1µF.
11
SYNC
Frequency Synchronization (Input): Connect an external clock signal to
synchronize the oscillator. Leading edge of signal above 1.5V starts the
switching cycle. Connect to SGND if not used.
12
PGND
MOSFET driver power ground, connects to source of synchronous MOSFET
and the (-) terminal of CIN.
13
VREF
The 1.245V voltage reference is available on this pin. A 0.1µF capacitor
should be connected from this pin to ground.
14
OUTP
High current drive for high side P channel MOSFET. Voltage swing is from
ground to VINP. On-resistance is typically 2.5Ω.
15
FREQ/2
When this is low, the oscillator frequency is 400KHz. When this pin is raised
to VDD, the oscillator frequency is 200KHz.
16
VINP
Power Input voltage to the circuit. The output gate drivers are powered from
this supply. The current sense resistor RCS should be connected as close as
possible to this pin.
April 2005
Pin Function
Analog voltage input voltage to the circuit. This powers up the analog
sections of the die and does not need to be the same voltage as Pin 16
(VINP).
This provides a digital signal output signal at half the switching frequency.
This signal swings from 0 to 3V, and can be used to drive an external
capacitive doubler to provide a higher voltage to the VINP input.
Soft start reduces the inrush current and delays and slows the output voltage
rise time. A 5µA current source will charge the capacitor up to VDD. A 1µF
capacitor will soft start the switching regulator in 1.5ms.
Feedback Input - the circuit regulates this pin to 1.245V.
Enable/UnderVoltage Lockout (input): A low level on this pin will power down
the device, reducing the quiescent current to under 5uA. This pin has two
separate thresholds, below 1.5V the output switching is disabled, and below
0.9V the part is forced into a complete micropower shutdown. The 1.5V
threshold functions as an accurate undervoltage lockout (UVLO) with 140mV
hysteresis.
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M9999-042205
MIC2184
Micrel, Inc.
Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 2)
Supply Voltage (VINA, VINP) ......................................... 15V
Digital Supply Voltage (VDD) ........................................... 7V
Comp Pin Voltage (VCOMP) ............................ –0.3V to +3V
Feedback Pin Voltage (VFB) .......................... –0.3V to +3V
Enable Pin Voltage (VEN/UVLO) ..................... –0.3V to 15V
Current Sense Voltage (VCSH–VCSL) ............... –0.3V to 1V
Sync Pin Voltage (VSYNC) ................................ –0.3V to 7V
Freq/2 Pin Voltage (VFREQ/2) ............................ -0.3V to 7V
Power Dissipation (PD)
16 lead SOIC ................................. 400mW @ TA = 85°C
16 lead QSOP ............................... 245mW @ TA = 80°C
Ambient Storage Temp ............................ –65°C to +150°C
ESD Rating, ............................................................. Note 3
Supply Voltage (VINA, VINP) ........................ +2.9V to +14V
Ambient Operating Temperature ......... –40°C ≤ TA ≤ +85°C
Junction Temperature ....................... –40°C ≤ TJ ≤ +125°C
Output Voltage Range ...................................... 1.3V to 12V
PackageThermal Resistance
θJA 16-lead SOP ............................................... 100°C/W
θJA 16-lead QSOP ............................................. 163°C/W
Electrical Characteristics
VINA = VINP = VCSH = 5V, VOUT = 3.3V, VEN/UVLO = 5V, VFREQ/2 = 0V, TJ = 25ºC, unless otherwise specified. Bold values indicate
–40ºC < TJ < +125ºC.
Parameter
Condition
Min
Typ
Max
Units
(±1%)
1.233
1.245
1.257
V
(±2%)
1.22
1.27
V
Regulation
Feedback Voltage Reference
Feedback Bias Current
50
nA
Output Voltage Line Regulation
5V ≤ VIN ≤ 12V
0.04
%/V
Output Voltage Load Regulation
0mV < (VCSH – VCSL) < 75mV
0.9
%
Output Voltage Total Regulation
5V ≤ VINA ≤ 12V, 0mV < (VCSH – VCSL) < 75mV (±3%)
1.208
1.282
V
Input & VDD Supply
VINA Input Current
0.7
mA
mA
VINP Input Current, Note 4
(Excluding external MOSFET gate current)
1.0
Shutdown Quiescent Current
VEN/UVLO = 0V; (IVINA + IVINP)
0.5
5
µA
Digital Supply Voltage (VDD)
IL = 0
3.0
3.18
V
Digital Supply load regulation
IL = 0 to 1mA
0.03
V
Undervoltage Lockout
VDD upper threshold (turn on threshold)
2.75
V
100
mV
2.82
UVLO Hysteresis
Reference Output(VREF)
Reference Voltage
(±1.5%)
1.226
(±2.5%)
1.213
1.245
1.264
V
1.276
V
Reference Voltage Line
Regulation
5V < VINA < 12V
2
mV
Reference Voltage Load
Regulation
0 < IREF < 100µA
1
mV
Enable/UVLO
Enable Input Threshold
UVLO Threshold
(Turn-on threshold)
UVLO Hysteresis
Enable Input Current
M9999-042205
0.6
0.9
1.2
V
1.4
1.5
1.6
V
140
VEN/UVLO = 5V
0.2
4
mV
5
µA
April 2005
MIC2184
Parameter
Micrel, Inc.
Condiion
Min
Typ
Max
Units
Soft Start
Soft Start Current
5
µA
100
mV
20
V/V
3.0
V/V
Current Limit
Current Limit Threshold Voltage
Voltage on CSH-CSL to trip current limit
Error Amplifier
Error Amplifier Gain
Current Amplifier
Current Amplifier Gain
Oscillator Section
Oscillator Frequency (fO)
360
Maximum Duty Cycle
VFB = 1.0V
Minimum On Time
VFB = 1.5V
Freq/2 Frequency (fO)
VFREQ/2 = 5V
Frequency Foldback Threshold
Measured on FB
440
kHz
100
%
185
170
Frequency Foldback Frequency
SYNC Threshold Level
0.6
SYNC Input Current
SYNC Minimum Pulse Width
SYNC Capture Range
400
200
ns
230
kHz
0.3
V
90
kHz
1.4
2.2
V
0.1
5
µA
200
Note 5
ns
fO +15 %
600
kHz
FreqOut Output
FreqOut Frequency
Note 6
fO / 2
kHz
FreqOut Current Drive
Sink
8
mA
Source
–6
mA
Rise/Fall Time
CL = 3300pF
50
ns
Output Driver Impedance
Source; VINP = 12V
1.8
4
Ω
Sink; VINP = 12V
1.6
3.5
Ω
Source; VINP = 5V
2.6
Ω
Sink; VINP = 5V
2.4
Ω
Gate Drivers
Note 1:
Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when
operating the device outside of its operating ratings. The maximum allowable power dissipation is a function of the maximum junction
temperature, TJ(Max), the junction-to-ambient thermal resistance, θJA, and the ambient temperature, TA.
Note 2.
The device is not guaranteed to function outside its operating rating.
Note 3.
Devices are ESD sensitive. Handling precautions recommended.
Note 4:
See application information for I(VINP) vs. VINP.
Note 5:
See application information for limitations on maximum operating frequency.
Note 6:
The frequency on FreqOut is half the frequency of the oscillator, or half the frequency of the external Sync signal.
April 2005
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MIC2184
Micrel, Inc.
Typical Characteristics
Quiescent Current
vs. Input Voltage
2.5
2
200kHz
1.5
1
ISTANDBY
0.5
0
0
5
10
INPUT VOLTAGE (V)
200kHz
0.8
VINA = VINP = 5V
2.985
2.980
2.85
3.00
2.98
VIN = 5V
2.92
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
0.2 0.4 0.6 0.8
1
1.2
VDD LOAD CURRENT (mA)
Error Amp Reference Voltage
vs. Temperature
1.2449
1.2447
1.2445
1.2443
1.2441
0
1.244
1.243
1.242
1.241
VIN = 3.3V
FREQUENCY VARIATION (%)
1.245
1.24
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
200kHz
1
0.5
0
-0.5
-1
400kHz
-1.5
-2
0
Soft Start Current vs.
Temperature
2
4
6
8 10 12
INPUT VOLTAGE (V)
400kHz
-3
-5
-7
-9
-11
-13
Overcurrent Threshold
vs. Temperature
102
100.0
101
98.0
96.0
94.0
4.5
92.0
4.4
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
90.0
0
M9999-042205
200kHz
1
-1
102.0
THRESHOLD (mV)
4.6
5
3
Overcurrent Threshold
vs. Input Voltage
THRESHOLD (mV)
CURRENT (µA)
4.7
4 6 8 10 12 14
INPUT VOLTAGE (V)
-15
-50 -30 -10 10 30 50 70 90 110
TEMPERATURE (°C)
14
4.9
4.8
2
Frequency Variation vs.
Temperature
2
1.5
15
1.2451
Frequency Variation
vs. Input Voltage
1.246
5
10
INPUT VOLTAGE (V)
Error Amp Reference Voltage
vs. Input Voltage
3.02
2.94
2.970
0
2.80
0
VDD vs. Temperature
2.96
2.975
2.95
2.90
IQ = IVINA + IVINP
0.2 V A = V P = 3.3V
IN
IN
3.04
VDD (V)
2.990
VINA = VINP
3.00
0.4
3.06
2.995
REFERENCE VOLTAGE (V)
ISTANDBY
0.6
3.08
3.000
VDD (V)
1.0
VDD vs. Input Voltage
3.05
0
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
15
VDD vs. Load
3.005
400kHz
VDD (V)
3
1.2
REFERENCE VOLTAGE (V)
3.5
IQ = IVINA + IVINP
SOFT START CURRENT (µA)
4
3.10
1.4
400kHz
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
4.5
Quiescent Current
vs. Temperature
VIN = 3.3V
100
99
98
97
96
2
4 6 8 10 12 14
INPUT VOLTAGE (V)
6
95
-40 -20 0 20 40 60 80 100120140
TEMPERATURE (°C)
April 2005
MIC2184
Micrel, Inc.
OUTP Drive Impedance vs.
Input Voltage
4
IMPEDANCE (Ω)
3.5
3
2.5
2
SINK
1.5
SOURCE
1
0
April 2005
5
10
INPUT VOLTAGE (V)
15
7
M9999-042205
MIC2184
Micrel, Inc.
Functional Diagram
VIN
CIN
CDECOUP
VINA
1
OVERCURRENT
COMPARATOR
VREF
1.245V
0.1V
EN/UVLO
VDD
9
CSH
8
CSL
16
VINP
14
OUTP
7
RSENSE
BIAS
10
GAIN
3.7
VDD
CURRENT
SENSE
AMP
ON
fs/4
CONTROL
Q1
L1
SYNC
11
FREQ/2
15
FreqOut
2
VOUT
D1
OSC
12
SLOPE
COMPENSATION
÷2
COUT
RESET
PGND
∑
PWM
COMPARATOR
SS
3
COMP
4
gm = 0.0002 VREF
gain = 20
ERROR
AMP
6
FB
5
SGND
100k
0.3V
fs/4
VREF
13
VREF
FREQUENCY
FOLDBACK
Figure 1. MIC2184 Block Diagram
P-Channel MOSFET, Q1. Current flows from the input to the
output through the current sense resistor, MOSFET and
inductor. The current amplitude increases, controlled by the
inductor. The voltage developed across the current sense
resistor, RSENSE, is amplified inside the MIC2184 and combined with an internal ramp for stability. This signal is compared to the output of the error amplifier. When the current
signal equals the error voltage signal, the P-channel MOSFET
is turned off. The inductor current flows through the diode, D1.
At the beginning of the next switching cycle, the P-channel
MOSFET is turned on which turns off the diode, D1.
Functional Characteristics
Controller Overview and Functional Description
The MIC2184 is a BiCMOS, switched mode, synchronous,
step down (buck) converter controller. It uses a P-Channel
MOSFET, which allows the controller to operate at 100% duty
cycle and eliminates the need for a high side drive bootstrap
circuit. Current mode control is used to achieve superior
transient line and load regulation. An internal corrective ramp
provides slope compensation for stable operation above a
50% duty cycle. The controller is optimized for high efficiency,
high performance DC-DC converter applications.
Figure 1 is a block diagram of the MIC2184 configured as a
synchronous buck converter. At the beginning of the switching cycle, the OUTP pin pulls low and turns on the high-side
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April 2005
MIC2184
Micrel, Inc.
The MIC2184 controller is broken down into 7 functions.
• Control loop
• PWM operation
• Current mode control
• Current limit
• Reference, enable and UVLO
• FreqOut
• MOSFET gate drive
• Oscillator and Sync
• Soft-start
Control Loop
Current Limit
The output current is detected by the voltage drop across the
external current sense resistor (RSENSE in Figure 1.). The
current sense resistor must be sized using the minimum
current limit threshold. The external components must be
designed to withstand the maximum current limit. The current
sense resistor value is calculated by the equation below:
RSENSE =
The maximum output current is:
PWM Control Loop
IOUT _ MAX =
The MIC2184 uses current mode control to regulate the
output voltage. This dual control loop method (illustrated in
Figure 2) senses the output voltage (outer loop) and the
inductor current (inner loop). It uses inductor current and
output voltage to determine the duty cycle of the buck
converter. Sampling the inductor current effectively removes
the inductor from the control loop, which simplifies compensation.
VOUT
Voltage
Divider
IINDUCTOR
Switch
Driver
VERROR
VREF
IINDUCTOR
VERROR
tON
tPER
D = tON/tPER
Figure 2. Current Mode Control Example
As shown in Figure 1, the inductor current is sensed by
measuring the voltage across the resistor, RSENSE. A ramp is
added to the amplified current sense signal to provide slope
compensation, which is required to prevent unstable operation at duty cycles greater than 50%.
A transconductance amplifier is used for the error amplifier,
which compares an attenuated sample of the output voltage
with a reference voltage. The output of the error amplifier is
the compensation pin (Comp), which is compared to the
current sense waveform in the PWM block. When the current
signal becomes greater than the error signal, the comparator
turns off the high side drive. The COMP pin provides access
to the output of the error amplifier and allows the use of
external components to stabilize the voltage loop.
April 2005
MAX _ CURRENT _ SENSE _ THRESHOLD
RSENSE
The current sense pins CSH (pin 9) and CSL (pin 8) are noise
sensitive due to the low signal level and high input impedance. The PCB traces should be short and routed close to
each other. A small (1nF) capacitor across the pins will
attenuate high frequency switching noise.
When the peak inductor current exceeds the current limit
threshold, the overcurrent comparator turns off the high side
MOSFET for the remainder of the switching cycle, effectively
decreasing the duty cycle. The output voltage drops as
additional load current is pulled from the converter. When the
voltage at the feedback pin (FB) reaches approximately 0.3V,
the circuit enters frequency foldback mode and the oscillator
frequency will drop to 1/4 of the switching frequency. This
limits the maximum output power delivered to the load under
a short circuit condition.
Reference, Enable and UVLO Circuits
The output drivers are enabled when the following conditions
are satisfied:
• The VDD voltage (pin 10) is greater than its
undervoltage threshold.
• The voltage on the enable pin (pin 7) is greater
than the enable UVLO threshold.
The enable pin (pin 7) has two threshold levels, allowing the
MIC2184 to shut down in a low current mode, or turn off output
switching in standby mode. An enable pin voltage lower than
the shutdown threshold turns off all the internal circuitry and
places the MIC2184 in a micropower shutdown mode.
If the enable pin voltage is between the shutdown and
standby thresholds, the internal bias, VDD and reference
voltages are turned on. The soft start pin is forced low by an
internal discharge MOSFET. The output drivers are inhibited
from switching. The OUTP pin is in a high state and the OUTN
pin remains in a low state. Raising the enable voltage above
the standby threshold allows the soft start capacitor to charge
and enables the output drivers. The standby threshold is
specified in the electrical characteristics. A resistor divider
can be used with the enable pin to prevent the power supply
from turning on until a specified input voltage is reached. The
circuit in Figure 3 shows how to connect the resistors.
VIN
Switching
Converter
MIN _ CURRENT _ SENSE _ THRESHOLD
IOUT _ MAX
9
M9999-042205
MIC2184
Micrel, Inc.
supply. The VINP pin and CSH pin must be connected to the
same potential.
MOSFET Selection
The P-channel MOSFET must have a VGS threshold voltage
equal to or lower than the input voltage when used in a buck
converter topology. There is a limit to the maximum gate
charge the MIC2184 will drive. Higher gate charge MOSFET
will slow down the turn-on and turn-off time of the MOSFET.
Slower transition times will cause higher power dissipation in
the MOSFET due to higher switching transition losses.
The MOSFET gate charge is also limited by power dissipation
in the MIC2184. The power dissipated by the gate drive
circuitry is calculated below:
MIC2184
VIN
1.5V
Typical
R1
R2
Bias
Circuitry
EN/UVLO
(7)
140mV
Hysteresis
(typical)
Figure 3. UVLO Circuitry
The line voltage turn on trip point is:
VINPUT _ ENABLE = VTHRESHOLD ×
R2
R1 + R2
PGATE_DRIVE = Q GATE × VINP × fS
where:
VTHRESHOLD is the voltage level of the internal
comparator reference, typically 1.5V
The input voltage hysteresis is equal to:
VINPUT _ HYST = VHYST ×
where: Qgate is the total gate charge of both the N and Pchannel MOSFETs.
fS is the switching frequency
VINP is the gate drive voltage at the VINP pin
The graph in Figure 4 shows the total gate charge that can be
driven by the MIC2184 over the input voltage range, for
different values of switching frequency.
R1 + R2
R2
where:
VHYST is the internal comparator hysteresis level,
typically 140mV.
VINPUT_HYST is the hysteresis at the input voltage
The MIC2184 will be disabled when the input voltage drops
back down to:
VINPUT_OFF =
VINPUT_ENABLE – VINPUT_HYST =
Frequency vs.
Max. Gate Charge
TOTAL GATE CHARGE (C)
200x10 -9
R2
R1 + R2
Either of 2 UVLO conditions will pull the soft start capacitor
low.
• When the VDD voltage drops below its
undervoltage lockout level.
• When the enable pin drops below the its enable
threshold
The internal bias circuit generates an internal 1.245V bandgap reference voltage for the voltage error amplifier and a 3V
VDD voltage for the internal control circuitry. The VREF pin (pin
13) should be decoupled with a 0.1µf capacitor placed close
to the pin. The VDD pin must be decoupled with a 1µF ceramic
capacitor. The capacitor must be placed close to the VDD pin.
The other end of the capacitor must be connected directly to
the ground plane.
MOSFET Gate Drive
The MIC2184 is designed to drive a high side P-channel
MOSFET. The source pin of the P-channel MOSFET is
connected to the input of the power supply. It is turned on
when OUTP pulls the gate of the MOSFET low. The advantage of using a P-channel MOSFET is that it does not require
a bootstrap circuit to boost the gate voltage higher than the
input, as would be required for an N-channel MOSFET.
The VINP pin (pin 16) supplies the drive voltage to the gate
drive pin, OUTP. VINP pin is usually connected to the input
(VTHRESHOLD – VHYST) ×
M9999-042205
180x10 -9
160x10 -9
140x10 -9
120x10 -9
200kHz
100x10 -9
80x10-9 500kHz
60x10-9
600kHz
40x10-9
300kHz
20x10-9
0x1003
5
400kHz
7
9 11 13 15 17
INPUT VOLTAGE (V)
Figure 4. MIC2184 Frequency vs Max. Gate Charge
Oscillator & Sync
The internal oscillator is free running and requires no external
components. The f/2 pin allows the user to select from two
switching frequencies. A low level set the oscillator frequency
to 400kHz and a high level set the oscillator frequency to
200kHz. The maximum duty cycle for both frequencies is
100%. This is another advantage of using a P-channel
MOSFET for the high-side drive; it can continuously turned
on.
A frequency foldback mode is enabled if the voltage on the
feedback pin (pin 6) is less than 0.3V. In frequency foldback,
the oscillator frequency is reduced by approximately a factor
of 4. Frequency foldback is used to limit the energy delivered
to the output during a short circuit fault condition.
The SYNC input (pin 11) lets the MIC2184 synchronize with
an external clock signal. The rising edge of the sync signal
generates a reset signal in the oscillator, which turns off the
low side gate drive output. The high side drive then turns on,
restarting the switching cycle. The sync signal is inhibited
when the controller operates in frequency foldback. The sync
signal frequency must be greater than the maximum speci10
April 2005
MIC2184
Micrel, Inc.
fied free running frequency of the MIC2184. If the synchronizing frequency is lower, double pulsing of the gate drive
outputs will occur. When not used, the sync pin must be
connected to ground.
The maximum recommended output switching frequency is
600kHz. Synchronizing to higher frequencies may be possible, however, higher power dissipation in the internal gate
drive circuits will occur. The MOSFET gates require charge
to turn on the device. The average current required by the
MOSFET gate increases with switching frequency.
Soft Start
Soft start reduces the power supply input surge current at
start up by controlling the output voltage risetime. The input
surge appears while the output capacitance is charged up. A
slower output risetime will draw a lower input surge current.
Soft start may also be used for power supply sequencing.
The soft start voltage is applied directly to the PWM comparator. A 5µA internal current source is used to charge up the soft
start capacitor. The capacitor is discharged when either the
enable pin voltage drops below the standby threshold or the
VDD voltage drops below its UVLO level.
The part switches at a low duty cycle when the soft start pin
voltage is zero. As the soft start voltage rises from 0V to 0.7V,
the duty cycle increases from the minimum duty cycle to the
operating duty cycle. The oscillator runs at the foldback
frequency (1/4 of the switching frequency) until the feedback
voltage rises above 0.3V. The risetime of the output is
dependent of the soft start capacitor output capacitance,
input and output voltage and load current.
Voltage Setting Components
The MIC2184 requires two resistors to set the output voltage
as shown in Figure 5.
Efficiency Considerations
Efficiency is the ratio of output power to input power. The
difference is dissipated as heat in the buck converter. Under
light output load, the significant contributors are:
• The VINA supply current
• The VINP supply current, which includes the current
required to switch the external MOSFET
• Core losses in the output inductor
To maximize efficiency at light loads:
• Use a low gate charge MOSFET or use the smallest
MOSFET, which is still adequate for maximum output
current.
• Use a ferrite material for the inductor core, which has
less core loss than an MPP or iron power core.
Under heavy output loads the significant contributors to
power loss are (in approximate order of magnitude):
• Resistive on time losses in the MOSFET
• Switching transition losses in the MOSFET
• Inductor resistive losses
• Current sense resistor losses
• Input capacitor resistive losses (due to the capacitors
ESR)
To minimize power loss under heavy loads:
• Use low on resistance MOSFETs. Use low threshold
logic level MOSFETs when the input voltage is below
5V. Multiplying the gate charge by the on resistance
gives a figure of merit, providing a good balance
between low load and high load efficiency.
• Slow transition times and oscillations on the voltage
and current waveforms dissipate more power during
the turn on and turn off of the MOSFET. A clean
layout will minimize parasitic inductance and capaci
tance in the gate drive and high current paths. This
will allow the fastest transition times and waveforms
without oscillations. Low gate charge MOSFETs will
transition faster than those with higher gate charge
requirements.
• For the same size inductor, a lower value will have
fewer turns and therefore, lower winding resistance.
However, using too small of a value will require more
output capacitors to filter the output ripple, which will
force a smaller bandwidth, slower transient response
and possible instability under certain conditions.
• Lowering the current sense resistor value will de
crease the power dissipated in the resistor. However,
it will also increase the overcurrent limit and will
require larger MOSFETs and inductor components.
• Use low ESR input capacitors to minimize the power
dissipated in the capacitors ESR.
VOUT
MIC2184
Voltage
Amplifier
R1
Pin 6
R2
VREF
1.245V
Figure 5
The output voltage is determined by the equation below.
R1
R2
Where: VREF for the MIC2184 is typically 1.245V.
Lower values of R1 are preferred to prevent noise from
appearing on the FB pin. A typically recommended value is
10kΩ. If R1 is too small in value it will decrease the efficiency
of the power supply, especially at low output loads.
Once R1 is selected, R2 can be calculated with the following
formula.
VOUT = VREF × 1 +
R2=
April 2005
VREF × R1
VOUT ± VREF
11
M9999-042205
MIC2184
Micrel, Inc.
Package Information
PIN 1
0.157 (3.99)
0.150 (3.81)
DIMENSIONS:
INCHES (MM)
0.020 (0.51)
REF
0.020 (0.51)
0.013 (0.33) 0.0098 (0.249)
0.0040 (0.102)
0.050 (1.27)
BSC
0.0648 (1.646)
0.0434 (1.102)
0.394 (10.00)
0.386 (9.80)
45°
0°–8°
0.050 (1.27)
0.016 (0.40)
SEATING
PLANE
0.244 (6.20)
0.228 (5.79)
16-Pin SOP (M)
PIN 1
DIMENSIONS:
INCHES (MM)
0.157 (3.99)
0.150 (3.81)
0.009 (0.2286)
REF
0.025 (0.635)
BSC
0.0098 (0.249)
0.0040 (0.102)
0.012 (0.30)
0.008 (0.20)
0.0098 (0.249)
0.0075 (0.190)
0.196 (4.98)
0.189 (4.80)
SEATING 0.0688 (1.748)
PLANE 0.0532 (1.351)
45°
8°
0°
0.050 (1.27)
0.016 (0.40)
0.2284 (5.801)
0.2240 (5.690)
16-Pin QSOP (QS)
MICREL INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
This information furnished by Micrel in this data sheet is believed to be accurate and reliable. However no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2001 Micrel Incorporated
M9999-042205
12
April 2005