CG5982AF 2K x 8 Automotive Dual-port Static RAM CG5982AF 2K x 8 Automotive Dual-port Static RAM Features Functional Description • True dual-ported memory cells that allow simultaneous reads of the same memory location • Automotive temperature operation: –40°C to +115°C • 2K x 8 organization • High-speed access: 55 ns • Low operating power: ICC = 120 mA (max.) • Fully asynchronous operation • Automatic power-down • Master CG5982AF easily expands data bus width to 16 or more bits using slave • BUSY output flag • INT flag for port-to-port communication The CG5982AF are high-speed CMOS 2K x 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CG5982AF can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CG5982AF SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CG5982AF is available in a 52-pin PLCC package. Logic Block Diagram R/WL CEL R/WR CER OER •• • I/O7L • •• I/O0L •• • OEL I/O Control I/O Control •• I/O7R • I/O0R [1] BUSYR [1] BUSYL A0L •• A10L • Address Decoder CEL [2] INTL Memory Array Address Decoder Arbitration Logic and Interrupt Logic OEL CER OER R/WL R/WR •• A10R • A0R INTR [2] Notes: 1. CG5982AF (Master): BUSY is open-drain output and requires pull-up resistor. 2. Open drain outputs; pull-up resistor required. Cypress Semiconductor Corporation Document #: 38-06067 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 6, 2005 [+] Feedback CG5982AF Pin Configurations BUSYR INTR A10R CER R/WR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R I/O5R I/O6R I/O2R I/O3R I/O4R NC GND I/O0R I/O1R 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 CG5982AF 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O6L I/O7L 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O4L I/O5L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L BUSYL R/W L CEL VCC A0L OEL A10L INTL PLCC Top View Selection Guide CG5982AF Unit Maximum Access Time 55 ns Maximum Operating Current 120 mA Maximum Standby Current 45 mA Maximum Ratings DC Input Voltage ............................................–3.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage to Ground Potential (Pin 48 to Pin 24) ........................................... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High-Z State ............................................... –0.5V to +7.0V Automotive[3] Ambient Temperature VCC –40°C to +115°C 5V ± 10% Electrical Characteristics Over the Operating Range[4] CG5982AF Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage IOL = 4.0 mA IOL = 16.0 VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Load Current IOZ Output Leakage Current IOS Output Short–Circuit Min. Max. 2.4 V 0.4 mA[5] V 0.5 2.2 Current[6] Unit V 0.8 V GND < VI < VCC –5 +5 µA GND < VO < VCC, Output Disabled –5 +5 µA –350 mA VCC = Max., VOUT = GND Note: 3. TA is the “instant on” case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. BUSY and INT pins only. 6. Duration of the short circuit should not exceed 30 seconds. Document #: 38-06067 Rev. *C Page 2 of 12 [+] Feedback CG5982AF Electrical Characteristics Over the Operating Range[4] (continued) CG5982AF Parameter Description Test Conditions Min. Max. Unit ICC VCC Operating Supply Current CE = VIL, Outputs Open, f = fMAX[7] Auto 120 mA ISB1 Standby Current Both Ports, TTL Inputs CEL and CER > VIH, f = fMAX[7] Auto 45 mA ISB2 Standby Current One Port, TTL Inputs CEL or CER > VIH, Active Port Outputs Open, f = fMAX[7] Auto 90 mA ISB3 Standby Current Both Ports, CMOS Inputs Both Ports CEL and CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0 Auto 15 mA ISB4 Standby Current One Port, CMOS Inputs One Port CEL or CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX[7] Auto 85 mA Capacitance[8] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 15 pF 10 pF TA = 25°C, f = 1 MHz, VCC = 5.0V AC Test Loads and Waveforms R1 893Ω 5V OUTPUT 5V R1 893Ω 5V OUTPUT R2 347Ω 30 pF Including Jig and Scope R2 347Ω 5 pF Including Jig and Scope (a) 30 pF BUSY Output Load (CY7C132/CY7C136 Only) (b) Equivalent to: THÉVENIN EQUIVALENT 250Ω OUTPUT 1.4V 281Ω BUSY OR INT 3.0V GND 10% < 5 ns All input pulses 90% 90% 10% < 5 ns Switching Characteristics Over the Operating Range[4, 9] CG5982AF Parameter Description Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid[10] tOHA Data Hold from Address Change tACE CE LOW to Data 55 0 Valid[10] [10] tDOE OE LOW to Data Valid tLZOE OE LOW to Low-Z[8, 11] ns 55 3 ns ns 55 ns 25 ns ns Notes: 7. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V. 8. This parameter is guaranteed but not tested. 9. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of the specified IOL/IOH, and 30-pF load capacitance. 10. AC test conditions use VOH = 1.6V and VOL = 1.4V. 11. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. Document #: 38-06067 Rev. *C Page 3 of 12 [+] Feedback CG5982AF Switching Characteristics Over the Operating Range[4, 9] (continued) CG5982AF Max. Unit tHZOE Parameter OE HIGH to High-Z[8, 11, 12] Description Min. 25 ns tHZCE [8, 11, 12] 25 ns CE HIGH to High-Z [8] tPU CE LOW to Power-Up 0 [8] tPD CE HIGH to Power-Down ns 35 ns Write Cycle[13] tWC Write Cycle Time 55 ns tSCE CE LOW to Write End 40 ns tAW Address Set-up to Write End 40 ns tHA Address Hold from Write End 2 ns tSA Address Set-up to Write Start 0 ns tPWE R/W Pulse Width 30 ns tSD Data Set-up to Write End 20 ns tHD Data Hold from Write End 0 tHZWE R/W LOW to High-Z [8] tLZWE Low-Z [8] R/W HIGH to ns 25 ns 0 ns Busy/Interrupt Timing tBLA BUSY LOW from Address Match Mismatch[14] 30 ns 30 ns tBHA BUSY HIGH from Address tBLC BUSY LOW from CE LOW 30 ns tBHC BUSY HIGH from CE HIGH[14] 30 ns tPS Port Set-up for Priority tWB tWH tBDD BUSY HIGH to Valid Data tDDD tWDD Interrupt 5 ns R/W LOW after BUSY LOW 0 ns R/W HIGH after BUSY HIGH 35 ns 45 ns Write Data Valid to Read Data Valid Note 15 ns Write Pulse to Data Delay Note 15 ns Timing[15] tWINS R/W to INTERRUPT Set Time 45 ns tEINS CE to INTERRUPT Set Time 45 ns tINS Address to INTERRUPT Set Time 45 ns tOINR OE to INTERRUPT Reset Time[14] 45 ns tEINR CE to INTERRUPT Reset Time[14] 45 ns 45 ns tINR Address to INTERRUPT Reset Time [14] Notes: 12. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5 pF, as in (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 13. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 14. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 15. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. Document #: 38-06067 Rev. *C Page 4 of 12 [+] Feedback CG5982AF Switching Waveforms Read Cycle No. 1 (Either Port-Address Access)[16, 17] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (Either Port-CE/OE)[16, 18] CE tHZCE tACE OE tLZOE tHZOE tDOE tLZCE DATA VALID DATA OUT tPU tPD ICC ISB Read Cycle No. 3 (Read with BUSY Master) tRC ADDRESSR ADDRESS MATCH R/WR tPWE DINR VALID tPS ADDRESS MATCH ADDRESSL tBHA BUSYL tBLA tBDD DOUTL VALID tWDD tDDD Notes: 16. R/W is HIGH for read cycle. 17. Device is continuously selected, CE = VIL and OE = VIL. 18. Address valid prior to or coincident with CE transition LOW. Document #: 38-06067 Rev. *C Page 5 of 12 [+] Feedback CG5982AF Switching Waveforms (continued) Write Cycle No.1 (OE Three-States Data I/Os—Either Port)[13, 19] tWC ADDRESS tSCE CE tHA tAW tSA tPWE R/W tSD DATAIN tHD DATA VALID OE tHZOE HIGH IMPEDANCE DOUT Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[13, 20] tWC ADDRESS tSCE tHA CE tSA tAW tPWE R/W tSD DATAIN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DOUT Notes: 19. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. 20. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state. Document #: 38-06067 Rev. *C Page 6 of 12 [+] Feedback CG5982AF Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First: ADDRESSL,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESSL,R ADDRESS MATCH CER tPS CEL tBLC tBHC BUSYL Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESSL ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSYR Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSYL Document #: 38-06067 Rev. *C Page 7 of 12 [+] Feedback CG5982AF Switching Waveforms (continued) Busy Timing Diagram No. 3 (Write with BUSY, Slave) CE tPWE R/W tWB tWH BUSY Interrupt Timing Diagrams[16] Left Side Sets INTR: tWC ADDRESSL WRITE 7FF tHA tINS CEL tEINS R/WL tSA tWINS INTR Right Side Clears INTR: tRC ADDRESSR READ 7FF tHA tINR CER tEINR R/WR OER tOINR INTR Right Side Sets INTL: tWC ADDRESSR WRITE 7FE tINS tHA CER tEINS R/WR INTL Document #: 38-06067 Rev. *C tSA tWINS Page 8 of 12 [+] Feedback CG5982AF Interrupt Timing Diagrams[16] (continued) Left Side Clears INTL: tRC ADDRESSL READ 7FE tHA CEL tINR tEINR R/WL OEL tOINR INTL Document #: 38-06067 Rev. *C Page 9 of 12 [+] Feedback CG5982AF Typical DC and AC Characteristics ICC 1.0 0.8 0.6 0.4 0.0 4.0 4.5 5.0 5.5 Supply Voltage (V) NORMALIZED tAA 0.6 VCC = 5.0V VIN = 5.0V 0.4 ISB3 25 Ambient Temperature (°C) 1.2 1.1 TA = 25°C 1.4 1.2 1.0 VCC = 5.0V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 Supply Voltage (V) 6.0 Typical Power-on Current vs. Supply Voltage 3.0 0.6 –55 30.0 2.5 25 Ambient Temperature (°C) 125 Typical Access Time Change vs. Output Loading DELTA tAA (ns) 20.0 15.0 1.5 0.5 1.0 2.0 3.0 4.0 5.0 0 VCC = 5.0V TA = 25°C 40 20 0 0 1.0 2.0 3.0 Output Voltage (V) 4.0 Output Sink Current vs. Output Voltage 140 120 100 80 60 40 VCC = 5.0V TA = 25°C 20 0 0.0 1.0 2.0 3.0 4.0 Normalized ICC vs. Cycle Time 1.25 1.0 VCC = 5.0V TA = 25°C VIN = 5.0V VCC =4.5V TA =25°C 5.0 0 60 0.75 10.0 1.0 80 Output Voltage (V) 25.0 2.0 100 125 Normalized Access Time vs. Ambient Temperature Output Source Current vs. Output Voltage 120 NORMALIZED ICC NORMALIZED tAA 1.3 NORMALIZED tPC 0.8 1.6 1.4 0.0 1.0 0.6 –55 6.0 Normalized Access Time vs. Supply Voltage 1.0 ICC 0.2 ISB3 0.2 OUTPUT SOURCE CURRENT (mA) 1.2 1.2 NORMALIZED ICC, ISB NORMALIZED ICC, ISB 1.4 Normalized Supply Current vs. Ambient Temperature OUTPUT SINK CURRENT (mA) Normalized Supply Current vs. Supply Voltage 0 Supply Voltage (V) 200 400 600 800 1000 Capacitance (pF) 0.50 10 20 30 40 Cycle Frequency (MHz) Ordering Information Speed (ns) 55 Ordering Code CG5982AF Document #: 38-06067 Rev. *C Package Name J69 Package Type 52-lead Plastic Leaded Chip Carrier Operating Range Automotive Page 10 of 12 [+] Feedback CG5982AF Package Diagrams 52-lead Plastic Leaded Chip Carrier J69 51-85004-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-06067 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CG5982AF Document History Page Document Title: CG5982AF 2K x 8 Automotive Dual-port Static RAM Document Number: 38-06067 REV. ECN Issue Date Orig. of Change ** 119657 10/10/02 NIM Customized data sheet to meet special requirements for CG5982AF; automotive temperature –40°C to +115°C; base part in CY7C136 *A 121488 12/09/02 OOR Fixed Typo- changed 5 mA to 5 µA (p.2) *B 393195 SEE ECN KGH Included the automotive temperature operation range to the Features section Removed the micron CMOS size and the 52-pin PLCC references from the Features section Added Automotive to the title description *C 421244 See ECN ODC Add to external web. Document #: 38-06067 Rev. *C Description of Change Page 12 of 12 [+] Feedback