NCV4275A D

NCV4275A
5.0 V, 3.3 V 450 mA
Low-Dropout Voltage
Regulator with Reset
The NCV4275A is an integrated low dropout regulator designed
for use in harsh automotive environments. It includes wide
operating temperature and input voltage ranges. The output is
regulated at 5.0 V or 3.3 V and is rated to 450 mA of output current.
It also provides a number of features, including overcurrent
protection, overtemperature protection and a programmable
microprocessor reset. The NCV4275A is available in the DPAK and
D2PAK surface mount packages. The output is stable over a wide
output capacitance and ESR range. The NCV4275A is pin for pin
compatible with NCV4275.
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MARKING
DIAGRAMS
DPAK, 5−PIN
DT SUFFIX
CASE 175AA
1
4275AxG
ALYWW
5
Features
•
•
•
•
•
•
•
5.0 V and 3.3 V, ±2% Output Voltage Options
450 mA Output Current
Very Low Current Consumption
Active Reset Output
Reset Low Down to VQ = 1.0 V
500 mV (max) Dropout Voltage
Fault Protection
♦ +45 V Peak Transient Voltage
♦ −42 V Reverse Voltage
♦ Short Circuit Protection
♦ Thermal Overload Protection
AEC−Q100 Grade 1 Qualified and PPAP Capable
Pin Compatible with NCV4275
These are Pb−Free Devices
•
•
•
1
D2PAK, 5−PIN
DS SUFFIX
CASE 936A
NC
V4275Ax
AWLYWWG
1
5
1
x
A
WL, L
Y
WW
G
= 5 (5.0 V Output)
or 3 (3.3 V Output)
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Pin
Applications
• Auto Body Electronics
I
Q
Error
Amplifier
Bandgap
Reference
Current Limit and
Saturation Sense
+
−
1. I
2. RO
Tab,
3. GND*
4. D
5. Q
* Tab is connected to
Pin 3 on all packages
ORDERING INFORMATION
See detailed ordering and shipping information in the
dimensions section on page 17 of this data sheet.
Thermal
Shutdown
Reset
Generator
D
GND
RO
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 4
1
Publication Order Number:
NCV4275A/D
NCV4275A
PIN FUNCTION DESCRIPTION
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Pin #
Symbol
1
I
2
RO
3, Tab
GND
Description
Input; Battery Supply Input Voltage. Bypass to ground with a ceramic capacitor.
Reset Output; Open Collector Active Reset (accurate when I > 1.0 V).
Ground; Pin 3 internally connected to tab.
4
D
Reset Delay; timing capacitor to GND for Reset Delay function.
5
Q
Output; ±2.0%, 450 mA output. Bypass with 22 F capacitor, ESR < 4.5 Ω (5.0 V Version), 3.5 Ω (3.3 V Version) to ground.
MAXIMUM RATINGS
Rating
Symbol
Min
Max
Unit
Input Voltage
VI
−42
45
V
Input Peak Transient Voltage
VI
−
45
V
Output Voltage
VQ
−1.0
16
V
Reset Output Voltage
VRO
−0.3
25
V
Reset Output Current
IRO
−5.0
5.0
mA
Reset Delay Voltage
VD
−0.3
7.0
V
Reset Delay Current
ID
−2.0
2.0
mA
ESDHBM
ESDMM
ESDCDM
4.0
200
1000
−
−
−
kV
V
V
Junction Temperature
TJ
−40
150
°C
Storage Temperature
Tstg
−55
150
°C
ESD Susceptibility (Note 1)
− Human Body Model
− Machine Model
− Charge Device Model
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC−Q100−002, ESD
Machine Model tested per AEC−Q100−003, ESD Charged Device Model tested per AEC−Q100−011, Latch−up tested per AEC−Q100−004.
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2
NCV4275A
OPERATING RANGE
Input Voltage Operating Range, 5.0 V Output
VI
5.5
42
V
Input Voltage Operating Range, 3.3 V Output
VI
4.4
42
V
Junction Temperature
TJ
−40
150
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the
Recommended Operating Ranges limits may affect device reliability.
LEAD TEMPERATURE SOLDERING REFLOW AND MSL (Note 2)
Lead Free, 60 sec−150 sec above 217°C
TSLD
Moisture Sensitivity Level
MSL
−
265 Peak
°C
1
THERMAL CHARACTERISTICS
Characteristic
Test Conditions (Typical Value)
Unit
DPAK 5−PIN PACKAGE
Junction−to−Tab (RJT)
Junction−to−Ambient (RJA)
Min Pad Board (Note 3)
1″ Pad Board (Note 4)
4.2
4.7
°C/W
100.9
46.8
°C/W
D2PAK 5−PIN PACKAGE
0.4 sq. in. Spreader Board (Note 5)
1.2 sq. in. Spreader Board (Note 6)
Junction−to−Tab (RJT)
3.8
4.0
°C/W
Junction−to−Ambient (RJA)
74.8
41.6
°C/W
2.
3.
4.
5.
6.
PRR IPC / JEDEC J−STD−020C
1 oz. copper, 0.26 inch2 (168 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 1.14 inch2 (736 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 0.373 inch2 (241 mm2) copper area, 0.062″ thick FR4.
1 oz. copper, 1.222 inch2 (788 mm2) copper area, 0.062″ thick FR4.
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3
NCV4275A
ELECTRICAL CHARACTERISTICS (VI = 13.5 V; −40°C < TJ < 150°C; unless otherwise noted.)
Characteristic
Symbol
Test Conditions
5.0V Output Voltage
3.3V Output Voltage
Min
Typ
Max
Min
Typ
Max
Unit
Output
Output Voltage
VQ
100 A v IQ v 400 mA
6.0V v VI v 28V (5.0V Version)
4.4V v VI v 28V (3.3V version)
4.9
5.0
5.1
3.23
3.3
3.37
V
Output Voltage
VQ
100 A v IQ v 200 mA
6.0V v VI v 40V (5.0V Version)
4.4V v VI v 40V (3.3V version)
4.9
5.0
5.1
3.23
3.3
3.37
V
Output Current Limitation
IQ
VQ = 0.9 x VQ,typ
450
700
−
450
700
−
mA
Quiescent Current
Iq = II − IQ
Iq
IQ = 1.0 mA
−
140
200
−
135
200
A
IQ = 1.0 mA, TJ = 25°C
−
140
150
−
135
150
A
IQ = 250 mA
−
10
15
−
10
15
mA
IQ = 400 mA
−
23
35
−
23
35
mA
Dropout Voltage
Vdr
IQ = 300 mA
Vdr = VI − VQ (Note 7)
−
250
500
−
1100
1170
mV
Load Regulation
VQ
IQ = 5.0 mA to 400 mA
−30
15
30
−30
15
30
mV
Line Regulation
VQ
VI = 8.0 V to 32 V,
IQ = 5.0 mA
−15
5.0
15
−15
5.0
15
mV
Power Supply Ripple Rejection
PSRR
fr = 100 Hz, Vr = 0.5 Vpp
−
60
−
−
60
−
dB
Temperature Output Voltage
Drift
dVQ/dT
−−
−
0.5
−
−
0.5
−
mV/K
Reset Switching Threshold
VQ,rt
−−
4.53
4.65
4.8
3.0
3.1
3.2
V
Reset Output Low Voltage
VROL
Rext ≥ 5.0 k, VQ ≥ 1.0V
−
0.2
0.4
−
0.2
0.4
V
Reset Output Leakage Current
IROH
VROH = 5.0V
−
0
10
−
0
10
A
Reset Charging Current
ID,C
VD = 1.0V
3.0
5.5
9.0
2.0
4.0
9.0
A
Upper Timing Threshold
VDU
−−
1.5
1.8
2.2
0.7
1.3
1.6
V
Lower Timing Threshold
VDL
−−
0.2
0.4
0.7
0.2
0.4
0.7
V
Reset Timing D and Output RO
Reset Delay Time
trd
CD = 47nF
10
16
22
10
16
22
ms
Reset Reaction Time
trr
CD = 47nF
−
1.5
4.0
−
1.5
4.0
s
150
−
210
150
−
210
°C
Thermal Shutdown
Shutdown Temperature (Note 8)
TSD
−−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Measured when output voltage VQ falls 100 mV below the regulated voltage at VI = 13.5 V. Vdr = VI − VQ.For output voltage set < 4.4 V, Vdr
will be constrained by the minimum input voltage.
8. Guaranteed by design, not tested in production.
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4
NCV4275A
TYPICAL PERFORMANCE CHARACTERISTICS
5.0 V Version
3.3 V Version
10
10
Stable ESR Region
Stable ESR Region
1
1
CQ = 22 F
ESR ()
ESR ()
CQ = 22 F
0.1
0.1
VQ(nom) = 5.0 V
0.01
0
100
200
300
VQ(nom) = 3.3 V
0.01
400
0
100
IQ, OUTPUT CURRENT (mA)
200
300
400
IQ, OUTPUT CURRENT (mA)
Figure 2. Output Stability with Output
Capacitor ESR
Figure 3. Output Stability with Output
Capacitor ESR
100
100
10
ESR ()
ESR ()
10
Stable ESR Region
1
CQ = 1 F
Stable ESR Region
1
CQ = 1 F
0.1
VQ(nom) = 5.0 V
VQ(nom) = 3.3 V
0.01
0.1
0
100
200
300
400
0
100
IQ, OUTPUT CURRENT (mA)
300
400
IQ, OUTPUT CURRENT (mA)
Figure 4. Output Stability with Output
Capacitor ESR
Figure 5. Output Stability with Output
Capacitor ESR
5.2
3.5
VI = 13.5 V, RL = 25 5.1
VQ, OUTPUT VOLAGE (V)
VQ, OUTPUT VOLAGE (V)
200
5.0
4.9
VI = 13.5 V, RL = 16.5 3.4
3.3
3.2
VQ(nom) = 5.0 V
4.8
−40
0
40
80
120
VQ(nom) = 3.3 V
3.1
−40
160
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Output Voltage VQ vs. Temperature TJ
Figure 7. Output Voltage VQ vs. Temperature TJ
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NCV4275A
TYPICAL PERFORMANCE CHARACTERISTICS
5.0 V Version
3.3 V Version
6.0
6.0
RL = 16.5 TJ = 25°C
VQ, OUTPUT VOLTAGE (V)
VQ, OUTPUT VOLTAGE (V)
RL = 25 TJ = 25°C
5.0
4.0
3.0
2.0
1.0
5.0
4.0
3.0
2.0
1.0
VQ(nom) = 5.0 V
0.0
0
2
4
6
VI, INPUT VOLTAGE (V)
8
VQ(nom) = 3.3 V
0.0
0
10
1.2
VI = 13.5 V
1.0
0.8
0.6
0.4
0.2
VQ(nom) = 5.0 V
0.0
−40
0
40
80
120
160
VI = 13.5 V
1.0
0.8
0.6
0.4
0.2
VQ(nom) = 3.3 V
0.0
−40
IQ, OUTPUT CURRENT LIMITATION (A)
IQ, OUTPUT CURRENT LIMITATION (A)
TJ = 25°C
0.8
TJ = 125°C
0.6
0.4
0.2
VQ(nom) = 5.0 V
20
30
40
0
40
80
120
160
Figure 11. Output Current IQ vs. Temperature TJ
1.2
10
10
TJ, JUNCTION TEMPERATURE (°C)
Figure 10. Output Current IQ vs. Temperature TJ
0.0
0
8
1.2
TJ, JUNCTION TEMPERATURE (°C)
1.0
4
6
VI, INPUT VOLTAGE (V)
Figure 9. Output Voltage VQ vs. Input Voltage VI
IQ, OUTPUT CURRENT LIMITATION (A)
IQ, OUTPUT CURRENT LIMITATION (A)
Figure 8. Output Voltage VQ vs. Input Voltage VI
2
50
1.2
1.0
TJ = 25°C
0.8
TJ = 125°C
0.6
0.4
0.2
VQ(nom) = 3.3 V
0.0
0
VI, INPUT VOLTAGE (V)
10
20
30
40
VI, INPUT VOLTAGE (V)
Figure 13. Output Current IQ vs. Input Voltage VI
Figure 12. Output Current IQ vs. Input Voltage VI
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6
50
NCV4275A
TYPICAL PERFORMANCE CHARACTERISTICS
5.0 V Version
3.3 V Version
3.5
Iq, CURRENT CONSUMPTION (mA)
Iq, CURRENT CONSUMPTION (mA)
3.5
VI = 13.5 V, TJ = 25°C
3.0
2.5
2.0
1.5
1.0
0.5
VQ(nom) = 5.0 V
0.0
0
20
40
80
60
100
2.5
2.0
1.5
1.0
0.5
VQ(nom) = 3.3 V
0.0
120
VI = 13.5 V, TJ = 25°C
3.0
0
20
IQ, OUTPUT CURRENT (mA)
100
120
80
Iq, CURRENT CONSUMPTION (mA)
Iq, CURRENT CONSUMPTION (mA)
80
Figure 15. Current Consumption Iq vs.
Output Current IQ
80
VI = 13.5 V, TJ = 25°C
70
60
50
40
30
20
10
VQ(nom) = 5.0 V
0
100
200
300
400
500
60
50
40
30
20
10
VQ(nom) = 3.3 V
0
600
VI = 13.5 V, TJ = 25°C
70
0
100
IQ, OUTPUT CURRENT (mA)
400
500
600
Figure 17. Current Consumption Iq vs.
Output Current IQ
6
8
IDC, CHARGE CURRENT (A)
7
6
VI = 13.5 V, VD = 1.0 V
5
4
3
2
1
0
−40
300
200
IQ, OUTPUT CURRENT (mA)
Figure 16. Current Consumption Iq vs.
Output Current IQ
IDC, CHARGE CURRENT (A)
60
IQ, OUTPUT CURRENT (mA)
Figure 14. Current Consumption Iq vs.
Output Current IQ
0
40
VQ(nom) = 5.0 V
0
40
80
120
5
4
2
1
0
−40
160
VI = 13.5 V, VD = 1.0 V
3
TJ, JUNCTION TEMPERATURE (°C)
VQ(nom) = 3.3 V
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. Charge Current ID,C vs. Temperature TJ
Figure 19. Charge Current ID,C vs. Temperature TJ
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7
NCV4275A
TYPICAL PERFORMANCE CHARACTERISTICS
5.0 V Version
3.3 V Version
1.4
1.8
VDU/VDL, UPPER/LOWER TIMING
THRESHOLD (V)
VDU/VDL, UPPER/LOWER TIMING
THRESHOLD (V)
2.0
VDU
1.6
1.4
VI = 13.5 V
1.2
1.0
0.8
0.6
0.4
VDL
0.2
VQ(nom) = 5.0 V
0.0
−40
0
80
40
160
120
1.0
VI = 13.5 V
0.8
0.6
0.4
0.0
−40
Vdr, DROPOUT VOLTAGE (mV)
VQ(nom) = 3.3 V
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 20. Delay Switching Threshold VDU, VDL vs.
Temperature TJ
Figure 21. Delay Switching Threshold VDU, VDL vs.
Temperature TJ
600
500
TJ = 125°C
400
300
TJ = 25°C
200
100
VQ(nom) = 5.0 V
0
VDL
0.2
700
0
VDU
1.2
100
200
300
400
500
600
700
IQ, OUTPUT CURRENT (mA)
Figure 22. Drop Voltage Vdr vs. Output Current IQ
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NCV4275A
APPLICATION INFORMATION
VI
II
CI1
1000 μF
I
1
CI2
100 nF
ID
5
IQ
Q
CQ
22 μF
NCV4275A
D
4
CD
47 nF
2
3
RO
IRO
VQ
Rext
5.0 k
VRO
GND
Iq
Figure 23. Test Circuit
Circuit Description
The NCV4275A is an integrated low dropout regulator that
provides 5.0 V or 3.3 V, 450 mA protected output and a signal
for power on reset. The regulation is provided by a PNP pass
transistor controlled by an error amplifier with a bandgap
reference, which gives it the lowest possible drop out voltage
and best possible temperature stability. The output current
capability is 450 mA, and the base drive quiescent current is
controlled to prevent over saturation when the input voltage
is low or when the output is overloaded. The regulator is
protected by both current limit and thermal shutdown.
Thermal shutdown occurs above 150°C to protect the IC
during overloads and extreme ambient temperatures. The
delay time for the reset output is adjustable by selection of the
timing capacitor. See Figure 23, Test Circuit, for circuit
element nomenclature illustration.
ESR of ceramic capacitors. The aluminum electrolytic
capacitor is the least expensive solution, but, if the circuit
operates at low temperatures (−25°C to −40°C), both the
capacitance and ESR of the capacitor will vary considerably.
The capacitor manufacturer’s data sheet usually provides this
information.
The value for the output capacitor CQ shown in
Figure 23, Test Circuit, should work for most applications;
however, it is not necessarily the optimized solution.
Stability is guaranteed for CQ ≥ 22 F and an ESR ≤ 4.5 (5.0 V Version), 3.5 (3.3 V Version).
ESR characteristics were measured with ceramic
capacitors and additional resistors to emulate ESR. Murata
ceramic capacitors were used, GRM32ER71A226ME20
(22 F, 10 V, X7R, 1210), GRM31MR71E105KA01 (1 F,
25 V, X7R, 1206).
Regulator
The error amplifier compares the reference voltage to a
sample of the output voltage (VQ) and drives the base of a
PNP series pass transistor by a buffer. The reference is a
bandgap design to give it a temperature−stable output.
Saturation control of the PNP is a function of the load
current and input voltage. Over saturation of the output
power device is prevented, and quiescent current in the
ground pin is minimized.
Reset Output
The reset output is used as the power on indicator to the
microcontroller. This signal indicates when the output
voltage is suitable for reliable operation of the controller.
It pulls low when the output is not considered to be ready.
RO is pulled up to VQ by an external resistor, typically
5.0 k in value. The input and output conditions that
control the Reset Output and the relative timing are
illustrated in Figure 24, Reset Timing.
Output voltage regulation must be maintained for the delay
time before the reset output signals a valid condition. The
delay for the reset output is defined as the amount of time it
takes the timing capacitor on the delay pin to charge from a
residual voltage of 0.0 V to the upper timing threshold voltage
VDU. The charging current for this is ID,C and D pin voltage
in steady state is typically 3.2 V for 5.0 V regulator and
typically 2.4 V for 3.3 V regulator. By using typical IC
parameters with a 47 nF capacitor on the D pin, the following
time delay for 5.0 V regulator is derived:
tRD = CDVDU / ID,C
tRD = 47 nF (1.8 V) / 5.5 A = 15.4 ms
Other time delays can be obtained by changing the
capacitor value.
Regulator Stability Considerations
The input capacitors (CI1 and CI2) are necessary to
stabilize the input impedance to avoid voltage line
influences. Using a resistor of approximately 1.0 in
series with CI2 can stop potential oscillations caused by
stray inductance and capacitance.
The output capacitor helps determine three main
characteristics of a linear regulator: startup delay, load
transient response and loop stability. The capacitor value
and type should be based on cost, availability, size and
temperature constraints. A tantalum, aluminum or ceramic
capacitors can be used. The range of stability versus
capacitance, load current and capacitive ESR is illustrated
in Figures 2 to 5. Minimum ESR for CQ = 22 F is native
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9
NCV4275A
VI
t
< Reset Reaction Time
VQ
VQ,rt
t
Reset Charge Current
dVD
+
CD
dt
VD
Upper Timing Threshold VDU
Lower Timing Threshold VDL
t
Reset
Delay Time
Reset
Reaction Time
VRO
t
Power−on−Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Figure 24. Reset Timing
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10
Overload
at Output
NCV4275A
Calculating Power Dissipation
in a Single Output Linear Regulator
The maximum power dissipation for a single output
regulator (Figure 25) is:
PD(max) + [VI(max) * VQ(min)] IQ(max)
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and
the outside environment will have a thermal resistance.
Like series electrical resistances, these resistances are
summed to determine the value of RJA:
(1)
) VI(max)Iq
where
VI(max)
is the maximum input
voltage,
is the minimum output
VQ(min)
voltage,
IQ(max)
is the maximum output
current for the application,
Iq
is the quiescent current the regulator consumes
at IQ(max).
Once the value of PD(max) is known, the maximum
permissible value of RJA can be calculated:
T
RJA + 150° C * A
PD
RJA + RJC ) RCS ) RSA
where
RJC is the junction−to−case thermal resistance,
RCS is the case−to−heatsink thermal resistance,
RSA is the heatsink−to−ambient thermal resistance.
RJC appears in the package section of the data sheet.
Like RJA, it too is a function of package type. RCS and
RSA are functions of the package type, heatsink and the
interface between them. These values appear in heatsink
data sheets of heatsink manufacturers.
Thermal, mounting, and heatsinking considerations are
discussed in the ON Semiconductor application note
AN1040/D.
(2)
The value of RJA can then be compared with those in the
package section of the data sheet. Those packages with
RJA’s less than the calculated value in Equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external
heatsink will be required.
Thermal Model
IQ
II
SMART
REGULATOR®
VI
(3)
VQ
} Control
Features
Iq
Figure 25. Single Output Regulator with Key
Performance Parameters Labeled
A discussion of thermal modeling is in the ON Semiconductor web site: http://www.onsemi.com/pub/collateral/BR1487−D.PDF.
Table 1. DPAK 5−Lead Thermal RC Network Models
Drain Copper Area (1 oz thick)
168 mm2
(SPICE Deck Format)
736 mm2
168 mm2
Cauer Network
168
mm2
736
736 mm2
Foster Network
mm2
Units
Tau
Tau
Units
C_C1
Junction
Gnd
1.00E−06
1.00E−06
W−s/C
1.36E−08
1.361E−08
sec
C_C2
node1
Gnd
1.00E−05
1.00E−05
W−s/C
7.41E−07
7.411E−07
sec
C_C3
node2
Gnd
6.00E−05
6.00E−05
W−s/C
1.04E−05
1.029E−05
sec
C_C4
node3
Gnd
1.00E−04
1.00E−04
W−s/C
3.91E−05
3.737E−05
sec
C_C5
node4
Gnd
4.36E−04
3.64E−04
W−s/C
1.80E−03
1.376E−03
sec
C_C6
node5
Gnd
6.77E−02
1.92E−02
W−s/C
3.77E−01
2.851E−02
sec
C_C7
node6
Gnd
1.51E−01
1.27E−01
W−s/C
3.79E+00
9.475E−01
sec
C_C8
node7
Gnd
4.80E−01
1.018
W−s/C
2.65E+01
1.173E+01
sec
C_C9
node8
Gnd
3.740
2.955
W−s/C
8.71E+01
8.59E+01
sec
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11
NCV4275A
(SPICE Deck Format)
C_C10
node9
Cauer Network
Gnd
10.322
168
Foster Network
0.438
mm2
736
W−s/C
mm2
sec
R’s
R’s
R_R1
Junction
node1
0.015
0.015
C/W
0.0123
0.0123
C/W
R_R2
node1
node2
0.08
0.08
C/W
0.0585
0.0585
C/W
R_R3
node2
node3
0.4
0.4
C/W
0.0304
0.0287
C/W
R_R4
node3
node4
0.2
0.2
C/W
0.3997
0.3772
C/W
R_R5
node4
node5
2.97519
2.6171
C/W
3.115
2.68
C/W
R_R6
node5
node6
8.2971
1.6778
C/W
3.571
1.38
C/W
R_R7
node6
node7
25.9805
7.4246
C/W
12.851
5.92
C/W
R_R8
node7
node8
46.5192
14.9320
C/W
35.471
7.39
C/W
R_R9
node8
node9
17.7808
19.2560
C/W
46.741
28.94
C/W
R_R10
node9
Gnd
0.1
0.1758
C/W
NOTE:
C/W
Bold face items represent the package without the external thermal system.
R1
Junction
C1
R2
C2
R3
C3
Rn
Cn
Time constants are not simple RC products. Amplitudes
of mathematical solution are not the resistance values.
Ambient
(thermal ground)
Figure 26. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R1
C1
R2
C2
R3
C3
Rn
Cn
Each rung is exactly characterized by its RC−product
time constant; amplitudes are the resistances.
Ambient
(thermal ground)
Figure 27. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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12
NCV4275A
Table 2. D2PAK 5−Lead Thermal RC Network Models
Drain Copper Area (1 oz thick)
241 mm2
(SPICE Deck Format)
788 mm2
241 mm2
Cauer Network
241
mm2
788 mm2
Foster Network
653
mm2
Units
Tau
Tau
Units
C_C1
Junction
Gnd
1.00E−06
1.00E−06
W−s/C
1.361E−08
1.361E−08
sec
C_C2
node1
Gnd
1.00E−05
1.00E−05
W−s/C
7.411E−07
7.411E−07
sec
C_C3
node2
Gnd
6.00E−05
6.00E−05
W−s/C
1.005E−05
1.007E−05
sec
C_C4
node3
Gnd
1.00E−04
1.00E−04
W−s/C
3.460E−05
3.480E−05
sec
C_C5
node4
Gnd
2.82E−04
2.87E−04
W−s/C
7.868E−04
8.107E−04
sec
C_C6
node5
Gnd
5.58E−03
5.95E−03
W−s/C
7.431E−03
7.830E−03
sec
C_C7
node6
Gnd
4.25E−01
4.61E−01
W−s/C
2.786E+00
2.012E+00
sec
C_C8
node7
Gnd
9.22E−01
2.05
W−s/C
2.014E+01
2.601E+01
sec
C_C9
node8
Gnd
1.73
4.88
W−s/C
1.134E+02
1.218E+02
sec
C_C10
node9
Gnd
7.12
1.31
W−s/C
241
mm2
653
mm2
sec
R’s
R’s
R_R1
Junction
node1
0.015
0.0150
C/W
0.0123
0.0123
C/W
R_R2
node1
node2
0.08
0.0800
C/W
0.0585
0.0585
C/W
R_R3
node2
node3
0.4
0.4000
C/W
0.0257
0.0260
C/W
R_R4
node3
node4
0.2
0.2000
C/W
0.3413
0.3438
C/W
R_R5
node4
node5
1.85638
1.8839
C/W
1.77
1.81
C/W
R_R6
node5
node6
1.23672
1.2272
C/W
1.54
1.52
C/W
R_R7
node6
node7
9.81541
5.3383
C/W
4.13
3.46
C/W
R_R8
node7
node8
33.1868
18.9591
C/W
6.27
5.03
C/W
R_R9
node8
node9
27.0263
13.3369
C/W
60.80
29.30
C/W
R_R10
node9
gnd
1.13944
0.1191
C/W
NOTE:
C/W
Bold face items represent the package without the external thermal system.
The Cauer networks generally have physical significance and may be divided between nodes to separate thermal behavior
due to one portion of the network from another. The Foster networks, though when sorted by time constant (as above) bear
a rough correlation with the Cauer networks, are really only convenient mathematical models. Cauer networks can be easily
implemented using circuit simulating tools, whereas Foster networks may be more easily implemented using mathematical
tools (for instance, in a spreadsheet program), according to the following formula:
n
R(t) +
Ri ǒ1−e−tńtaui Ǔ
i+1
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13
110
110
100
100
90
90
80
80
70
JA (C°/W)
JA (C°/W)
NCV4275A
1 oz
60
2 oz
70
60
1 oz
2 oz
50
50
40
40
30
150 200 250 300 350 400 450 500 550 600 650 700 750
30
150 200 250 300 350 400 450 500 550 600 650 700 750
COPPER AREA (mm2)
COPPER AREA (mm2)
Figure 28. qJA vs. Copper Spreader Area,
DPAK 5−Lead
Figure 29. qJA vs. Copper Spreader Area,
D2PAK 5−Lead
100
Cu Area 167 mm2
Cu Area 736 mm2
R(t) C°/W
10
1.0
sqrt(t)
0.1
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
TIME (sec)
Figure 30. Single−Pulse Heating Curves, DPAK 5−Lead
100
Cu Area 167 mm2
Cu Area 736 mm2
R(t) C°/W
10
1.0
0.1
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
TIME (sec)
Figure 31. Single−Pulse Heating Curves, D2PAK 5−Lead
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14
10
100
1000
NCV4275A
100
50% Duty Cycle
RJA 736 mm2 C°/W
20%
10
1.0
10%
5%
2%
1%
0.1
Non−normalized Response
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
10
100
1000
10
100
1000
PULSE WIDTH (sec)
Figure 32. Duty Cycle for 1” Spreader Boards, DPAK 5−Lead
100
RJA 788 mm2 C°/W
50% Duty Cycle
10
20%
10%
5%
1.0
2%
1%
0.1
Non−normalized Response
0.01
0.0000001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1.0
PULSE WIDTH (sec)
Figure 33. Duty Cycle for 1” Spreader Boards, D2PAK 5−Lead
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15
NCV4275A
EMC−Characteristics: Conducted Susceptibility
Acceptance Criteria
All EMC−Characteristics are based on limited samples
and no part of production test according to 47A/658/CD
IEC62132−4 (direct Power Injection).
Amplitude Dev. max 4% of Output Voltage
Reset outputs remain in correct state ±1 V
1. dBm means dB mili−Watts, P(dBm) = 10 log
(P(mW)).
2. A global pin carries a signal or power which
enters or leaves the application board.
3. A local pin carries a signal or power which does
not leave the application board. It remains on the
application board as a signal between two
components.
Test Conditions
Supply Voltage Vin = 12 V
Temperature TA = 23°C ±5°C
Load
RL = 100 Direct Power Injection
33 dBm (Note 1) forward power CW for global pin (Note 2)
17 dBm (Note 1) forward power CW for local pin (Note 3)
X1
VIN_DC
X2
VIN_HF
L1
L3
FERRITE
FERRITE
C2
10 F
C1
100 nF
C4
47 nF
NCV4275A
1 I
GND
U1
VOUT
D
4
L4
3
FERRITE
FERRITE
X3
RO_DC
X4
RO_HF
X6
VOUT_HF
C5
22 F
Q 5
2 RO
L2
X5
VOUT_DC
R1
4.99k
C6
47 nF
VOUT
Figure 34. Test Circuit
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16
X7
D_DC
X8
D_HF
NCV4275A
40
40
30
Vin Pass 33 dBm
(dBm)
(dBm)
30
20
10
Vout Pass 33 dBm
20
10
0
0
1
10
100
1000
1
10
FREQUENCY (MHz)
1000
Figure 36. Typical Vout Pin Susceptibility
25
25
20
20
RO Pass 17 dBm
(dBm)
(dBm)
Figure 35. Typical Vin Pin Susceptibility
15
100
FREQUENCY (MHz)
15
10
10
5
5
0
Delay Pass 17 dBm
0
10
1
100
1000
1
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Figure 37. Typical RO Pin Susceptibility
Figure 38. Typical Delay Pin Susceptibility
ORDERING INFORMATION
Device
NCV4275ADS50G
Output Voltage
Package
Shipping†
5.0 V
D2PAK
(Pb−Free)
50 Units/Rail
NCV4275ADS50R4G
NCV4275ADT50RKG
NCV4275ADS33G
DPAK
(Pb−Free)
3.3 V
D2PAK
(Pb−Free)
NCV4275ADS33R4G
NCV4275ADT33RKG
DPAK
(Pb−Free)
800 Tape & Reel
2500 Tape & Reel
50 Units/Rail
800 Tape & Reel
2500 Tape & Reel
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
NCV4275A
PACKAGE DIMENSIONS
DPAK 5, CENTER LEAD CROP
DT SUFFIX
CASE 175AA−01
ISSUE A
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
R1
Z
A
S
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
1 2 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
SOLDERING FOOTPRINT*
6.4
0.252
2.2
0.086
0.34 5.36
0.013 0.217
5.8
0.228
10.6
0.417
0.8
0.031
SCALE 4:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
18
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
NCV4275A
PACKAGE DIMENSIONS
D2PAK, 5 LEAD
DS SUFFIX
CASE 936A−02
ISSUE C
−T−
OPTIONAL
CHAMFER
A
E
U
S
K
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A
AND K.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 6.
5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASH
AND GATE PROTRUSIONS NOT TO EXCEED 0.025
(0.635) MAXIMUM.
TERMINAL 6
V
H
1 2 3 4 5
M
D
0.010 (0.254)
M
T
DIM
A
B
C
D
E
G
H
K
L
M
N
P
R
S
U
V
P
N
G
L
R
C
SOLDERING FOOTPRINT*
8.38
0.33
INCHES
MIN
MAX
0.386
0.403
0.356
0.368
0.170
0.180
0.026
0.036
0.045
0.055
0.067 BSC
0.539
0.579
0.050 REF
0.000
0.010
0.088
0.102
0.018
0.026
0.058
0.078
5 _ REF
0.116 REF
0.200 MIN
0.250 MIN
MILLIMETERS
MIN
MAX
9.804
10.236
9.042
9.347
4.318
4.572
0.660
0.914
1.143
1.397
1.702 BSC
13.691
14.707
1.270 REF
0.000
0.254
2.235
2.591
0.457
0.660
1.473
1.981
5 _ REF
2.946 REF
5.080 MIN
6.350 MIN
1.702
0.067
10.66
0.42
3.05
0.12
16.02
0.63
SCALE 3:1
1.016
0.04
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
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representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product
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19
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For additional information, please contact your local
Sales Representative
NCV4275A/D