Comparing Micron N25Q00A with Macronix MX66L1G45G

APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
1. Introduction
This application note serves as a guide to compare Micron N25Q00A with Macronix MX66L1G45G 3V
1Gb serial NOR flash. The document does not provide detailed information on each individual device, but
highlights the similarities and differences between them. The comparison covers the general features,
performance, command codes, and other differences.
If common features are used in standard traditional modes, they may need only minimal software
modification. Minor pinout and timing differences are reviewed as well.
The information provided in this document is based on datasheets listed in Section 9. Newer versions of
the datasheets may override the contents of this document.
2. Features
Both flash device families have similar features and functions as shown in Table 2-1 and 2-2.
Table 2-1: Feature Comparison
Type / Function
Macronix MX66L1G45G
Micron N25Q00A
VCC Voltage Range
2.7V-3.6V
2.7V-3.6V
Normal Read Clock Frequency
66MHz
54MHz
(1)
Maximum STR Clock Frequency
166MHz
108MHz
Maximum DTR Clock Frequency
83MHz
54MHz
Configurable Dummy Cycles
YES
YES
Sector Size
4KB/32KB/64KB
4KB/64KB
Program Buffer Size
256Byte
256Byte
Security OTP
512Byte
64Byte
(3)
XIP / Performance Enhanced Mode
YES
YES
(3)
XIP / Performance Enhanced Mode Set at Power-on
YES
YES
Program/Erase Suspend & Resume
YES
YES
Wrap Around Read Mode
YES
YES
Adjustable Output Driver
YES
YES
Deep Power Down
YES
S/W Reset Command
YES
YES
High Voltage Accelerated Programming Option
YES
HOLD#/RESET# Pin
Reset#
Hold#/Reset#
Block Protection Mode (BP bits)
Top/Bottom
Top/Bottom
(2)
Individual Sector Protection (Volatile)
YES
YES
Program/Erase Cycles
100K
100K
Notes:
1. Maximum clock frequency with default dummy cycles shown in Table 2-2.
2. Please see App Note section 4-4 for detailed comparison of Individual Sector Protection.
3. Macronix supports 1-4-4 and 4-4-4 mode XIP; Micron supports XIP in all fast read modes.
P/N: AN0309
1
Ver.1,Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
Both devices support Double Transfer Rate (DTR) mode. While the Micron device supports DTR use with
all Read modes, Macronix only supports DTR use in the Fast DTR Read (1-1-1), Dual I/O DTR Read
( 2DTRD = 1-2-2), and Quad I/O DTR Read (4DTRD SPI = 1-4-4) modes (Table 2-2).
Table 2-2: Read Performance
Macronix MX66L1G45G
(1)
Read Mode
Default
Dummy
Cycles
Max Speed
@ Default
(2)
Dummy Cycles
Micron N25Q00A
Default
Dummy
Cycles
Max Speed
@ Default
Dummy Cycles
Fast Read
8
133MHz
8
108MHz
(1-1-1)
Dual Output Read
8
133MHz
8
108MHz
(DREAD = 1-1-2)
Dual I/O Read
4
84MHz
8
108MHz
(2READ = 1-2-2)
Dual Peripheral Interface
8
108MHz
(2-2-2)
Quad Output Read
8
133MHz
10
108MHz
(QREAD = 1-1-4)
Quad I/O SPI Read
6
84MHz
10
108MHz
(4READ SPI = 1-4-4)
Quad I/O QPI Read
6
84MHz
10
108MHz
(4READ QPI= 4-4-4)
Fast DTR Read
8
66MHz
6
54MHz
(1-1-1)
Dual Output DTR Read
6
54MHz
(1-1-2)
Dual I/O DTR Read
4
52MHz
6
53MHz
( 2DTRD = 1-2-2)
Quad Output DTR Read
6
53MHz
(1-1-4)
Quad I/O SPI DTR Read
6
52MHz
8
48MHz
( 4DTRD SPI = 1-4-4)
Quad I/O QPI DTR Read
6
52MHz
8
48MHz
( 4DTRD QPI = 4-4-4)
Notes:
1. In the x-y-z notation used in this applications note, x specifies the number of channels for the command, y
specifies the number of channels for the address, and z is the number of channels for data.
2. Higher clock rates can be achieved with increased number of dummy cycles (see Macronix datasheet).
P/N: AN0309
2
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
3. Package and Pinout
Both devices are available in 16-pin SOP and 24-BGA packages with similar footprints. Pinout definitions
are identical with the two exceptions shown in Table 3-2. Where Macronix has a NC/SIO3 pin, Micron
has either a HOLD#/DQ3 or a RESET#/DQ3 pin. If the Micron device has a HOLD# pin, but the HOLD#
function is not used, then the devices are pin compatible. Macronix does not support the VPP (10V Fast
Programming Voltage) function available on Micron’s W#/VPP/DQ2 pin. This function is normally only
used on external programmers to accelerate Program/Erase operations and is generally not used for
“in-circuit” programming.
Table 3-1: Packages
Packages
16-SOP (300mil)
24-Ball BGA (6mmx8mm with 5x5 ball array)
Macronix MX66L1G45G
YES
YES
Micron N25Q00A
YES
YES
Figure 3-1: 16- PIN SOP Pinout Comparison
16-PIN SOP (300mil)
Macronix
MX66L1G45GMI
Micron
N25Q00AAx3GSF
Macronix
MX66L1G45GMI
Micron
N25Q00AAx3GSF
NC/SIO3
VCC
RESET#
NC
DNU
DNU
CS#
SO/SIO1
HOLD#/DQ3
VCC
DNU
DNU
DNU
DNU
S#
DQ1
SCLK
SI/SIO0
NC
NC
DNU
DNU
GND
WP#/SIO2
C
DQ0
DNU
DNU
DNU
DNU
VSS
W#/ VPP /DQ2
Table 3-2: 16-SOP Pin Definition Comparison
Package
Pin
Macronix
MX66L1G45G
Pin #1
NC/SIO3
HOLD#/DQ3
HOLD# not supported by Macronix. Dedicated Micron part numbers
offer RESET# instead of HOLD#. NC means “No Connect”
Pin #3
RESET#
DNU
Macronix RESET# pin has internal pull up.
NC
DNU
WP#/SIO2
W#/ VPP
/DQ2
Pin #5,
13, & 14
Pin #9
P/N: AN0309
Micron
N25Q00A
Comments
NC means “No Connect”
DNU means “Do Not Use”
Macronix does not support VPP
3
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
Figure 3-2: 24-BGA (6x8mm with 5x5 Ball Array)
MX66L1G45GXD
N25Q00AAx3G12
5
NC
NC
NC
NC
NC
5
NC
NC
NC
NC
NC
4
RESET#
VCC
WP#
SIO2
NC
SIO3
NC
4
NC
VCC
WP#/
VPP/
DQ2
HLD#
DQ3
NC
3
NC
GND
NC
SI
SIO0
NC
3
NC
VSS
NC
DQ0
NC
2
NC
SCLK
CS#
SO
SIO1
NC
2
NC
C
S#
DQ1
NC
NC
NC
NC
NC
1
NC
NC
NC
NC
B
C
D
E
B
C
D
E
1
A
A
Table 3-3: 24-BGA Pin Definition Comparison
Package
Ball
Macronix
MX66L1G45G
Ball D4
NC/SIO3
HOLD#/DQ
3
Ball A4
RESET#
NC
Ball C4
WP#/SIO2
W#/
/DQ2
P/N: AN0309
Micron
N25Q00A
VPP
Comments
HOLD# not supported by Macronix. Dedicated Micron part numbers
offer RESET# instead of HOLD#. NC means “No Connect”
Macronix RESET# pin has internal pull up.
NC means “No Connect”
Macronix does not support VPP
4
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
4. Key Feature and Operational Differences
4-1 Status Register and Configuration Register Differences
Both devices use status and configuration registers to control device behavior and report status. The
registers and bits used are similar but not identical. Micron also has Non-Volatile registers not shown.
Both the Micron and Macronix devices use BP[3:0] bits to select the same memory areas for protection.
The N25Q00A Block Protection bits BP[3:0] are located in Status Register (bits 6 and [4:2]). The
Top/Bottom bit is located in Status Register bit 5 and selects whether block protection starts at the top or
bottom of memory. The BP[3:0] and Top/Bottom bits are nonvolatile and reprogrammable.
The MX66L1G45G Block Protection bits BP[3:0] are located in Status Register bits [5:2]. The top/bottom
starting point is controlled by the TB bit, which is located in Configuration Register bit 3. The default
setting of the TB bit starts block protection at the top of memory. If the ‘bottom’ starting point is selected,
it can never be returned to the ‘top’ starting point. The BP[3:0] bits are all nonvolatile and
reprogrammable. The TB bit is nonvolatile and one-time-programmable.
Table 4-1: Status Register Bits
Register Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Macronix MX66L1G45G
WIP; 1=write operation
WEL; 1=write enable
BP0; BP protection
BP1; BP protection
BP2; BP protection
BP3; BP protection
QE; 1=Quad mode enable
SRWD; 1=SR write disable
Micron N25Q00A
WIP; 1=write operation
WEL; 1=write enable
BP0; BP protection
BP1; BP protection
BP2; BP protection
T/B; Top/Bottom Protect
BP3; BP protection
SRWD; 1=SR write disable
Table 4-2: Configuration Register/ Enhanced Volatile Configuration Register
Register Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
P/N: AN0309
Macronix MX66L1G45G
ODS0 (Output Driver Strength)
ODS1 (Output Driver Strength)
ODS2 (Output Driver Strength)
T/B; Top/Bottom Protect
PBE; 1=Enable Preamble bit
4-BYTE; 1=4Byte address
DC0 (Dummy Cycle 0)
DC1 (Dummy Cycle 1)
5
Micron N25Q00A
ODS0 (Output Driver Strength)
ODS1 (Output Driver Strength)
ODS2 (Output Driver Strength)
Vpp accelerator; 1=disabled
Reset/Hold; 1=Enable
Reserved
DPI protocol; 1=disable
QPI protocol; 1=disable
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
Table 4-3: Macronix Security Register vs. Micron Flag Status Register
Register Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
Macronix MX66L1G45G
Secured OTP Indicator;
1=factory lock
LDSO; 1=OTP lock down
PSB (Program/Suspend bit)
ESB (Erase/Suspend bit)
Reserved
P_FAIL; 1=Program fail
E_FAIL; 1=Erase fail
WPSEL; 1=Individual WP
Micron N25Q00A
Address; 1=4-Byte address
Protection
PSB (Program/Suspend bit)
Vpp Error; 1=disabled (default)
P_FAIL; 1=Program fail
E_FAIL; 1=Erase fail
Erase Suspend; 1=suspend
PGM/ERS controller;1=ready
4-2 QPI Differences
Micron’s Quad I/O mode is entered by setting a bit in the Nonvolatile Configuration Register, which
remembers this mode after power cycles, or by setting a bit in the Enhanced Volatile Configuration
Register and is reset after a power cycle.
The MX66L1G45G requires an EQIO (35h) command to enter the equivalent QPI mode. This mode can
be terminated by a RSTQIO (F5h) command or by a power cycle or software reset.
4-3 XIP Differences
The XIP (eXecute In Place) feature (Macronix refers to this as Performance Enhance Mode) is only used
during Fast Read operations and eliminates the need to input read commands prior to entering an
address and reading data. This is an overhead reduction feature that increases data throughput. Both
devices offer this feature, but entry and exit methods are different. The MX66L1G45G enters XIP mode
whenever all four bits of the first and second dummy cycles of a FREAD instruction are not equal and will
exit XIP mode if any of the bits of the first and second dummy cycles are equal. Macronix only supports
XIP in Quad I/O (1-4-4) and QPI (4-4-4) modes. Micron supports XIP in all Fast Read I/O modes.
4-4 Individual Sector/Block Protection Differences
Both devices have the ability to protect individual 64KB sectors/blocks of memory. The methods used are
independent of the nonvolatile BP bit configuration in the Status Register. With the Micron flash, it is
possible to use both methods of write protection (BP bits and Individual Sector Protection) simultaneously,
and the protected area is the combination of the two. When using the Macronix flash, either BP bit
Protection or Individual Block Protection can be selected exclusively, with the default being the use of the
BP bits.
The N25Q00A has one Lock Register for each 64KB sector to control the sector’s program/erase
protection status. The protection can be turned on or off at any time unless the sector’s Lock Register
has been locked by the application. Once locked, its associated sector will remain in the protected or
unprotected state until the next power cycle or reset. All sectors not protected by the Status Register BP
configuration will be unprotected after power up and all Lock Registers will be unlocked.
P/N: AN0309
6
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
The MX66L1G45G has one volatile protection register for each of the top sixteen 4KB sectors, bottom
sixteen 4KB sectors, and 2046 middle 64KB blocks of memory. These protection registers can only be
used after permanently disabling the Status Register BP protection bits. This is done by executing the
WPSEL instruction once. Please note that this irreversible and the individual sector/block protection
method will be permanently selected.
After permanently selecting the individual sector/block protection method for the MX66L1G45G, all
sectors and blocks will be locked by default on power up. Sectors/blocks must be unlocked before they
can be programmed or erased. Unlocking sectors/blocks can be done on an individual basis with the
SBULK (Single Block Unlock) command or on all sectors/blocks with the GBULK (Global Block Unlock)
command. Sectors and blocks can be relocked as necessary with the SBLK (Single Block Lock)
command or GBLK (Global Block Lock) command.
Since the smallest individual sector protection size in the N25Q00A is 64KB, if an application is currently
locking/unlocking the top and/or bottom 64KB sector(s), it will need to lock/unlock each of the 16 top
and/or bottom 4KB sectors in the MX66L1G45G for equivalent results.
4-5. Chip Read and Erase Differences
The Micron N25Q00A only supports the Die Erase function, which means users have to execute four Die
Erase Commands (once in each die) to finish a chip erase operation. In the meantime, The Macronix
MX66L1G45G device looks and works like a monolithic 1Gb die and only needs one CE command with
no address required.
Similarly, because Micron treats its four die solution as four independently addressable arrays, extra
steps may be required when using the Micron flash during Reads which are not required for the Macronix
flash. For example, per the Micron datasheet "After any READ command is executed, the device will
output data from the selected address in the die. After a die boundary is reached, the device will start
reading again from the beginning of the same 256Mb die. A complete device reading is completed by
executing READ four times.." Macronix has no such requirement: “the whole memory can be read out
with a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached."
P/N: AN0309
7
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
5. Performance
Tables 5-1 and 5-2 show that the two devices have similar AC and DC performance.
Table 5-1: AC Parameter Comparison
Symbol
Macronix
Micron
tCH
tCH
tCL
tCL
tCLQV
Tclqv
Parameter
Clock High Time
Clock Low Time
Clock Low to Output Valid
(STR mode)
Output Hold Time
Data In Setup Time
Data In Hold Time
VCC(min) to CS# low
tCLQX
tDVCH
tCHDX
tVSL
tCLQX
tDVCH
tCHDX
tVTW
Page Program Time
(256 Bytes)
tPP
tPP
Erase 4KB Subsector/Sector
tSE
Condition
min
min
max @10pF
max @15pF
max @30pF
min.
min
min
min
max
typ
max
typ
max
Erase 32KB Sector
tBE32
typ
max
Erase 64KB Sector/Block
tBE
tSE
typ
max
Bulk Erase / Chip Erase
tCE
tBE
typ
max
Notes: 1. Calculated with Single Die Erase cycle time (32MB) x4.
tSSE
Macronix
MX66L1G45G
45% fTSCLK
45% fTSCLK
6ns
8ns
1ns
2ns
4ns
1500us
0.6ms
Micron
N25Q00A
4ns
4ns
6ns
8ns
1ns
2ns
3ns
150us
0.5ms
3ms
85ms
400ms
380ms
2s
680ms
4s
480s
1200s
5ms
250ms
800ms
700ms
3s
(1)
960s
(1)
1920s
Table 5-2: DC Parameter Comparison
Parameter
Leakage Current
Standby Current
VCC Read Current
(Fast Read)
Symbol
Macronix
Micron
ILI/ILO
ILI/ILO
ISB1
ICC1
ICC1
ICC3
Condition
max
typ
max
max @ 108MHz
(Quad I/O)
max @ 104MHz
(Quad I/O)
max @ 84MHz
max @ 54MHz
VCC Program Current
VCC Write Status
Register Current
VCC Erase Current
P/N: AN0309
ICC2
ICC3
ICC4
ICC5
max
max
ICC4
ICC6
max
8
Macronix
MX66L1G45G
+/- 4uA
60uA
200uA
Micron
N25Q00A
+/- 2uA
200uA
-
15mA
40mA
-
30mA
-
25mA
6mA
20mA
40mA
20mA
25mA
20mA
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
6. Command Code
Both devices use the same basic command set, but there are a few minor differences highlighted in
Table 6-1.
Table 6-1: Command Code Comparison
Instruction
Type
Read ID
Read
(STR)
Read
(DTR)
Write
Register
P/N: AN0309
Instruction
RDID
RDSFDP
READ
FAST_READ
DOFR
DIOFR
QOFR
QIOFR
FAST_READ
DOFR
DIOFR
QOFR
QIOFR
WREN
WRDI
PP
4PP
SE
BE 32K
SE 64K
CE
RDSR
RDEAR
WREAR
WRSR
RDSCUR
WRSCUR
RDLR
WRLR
RFSR
CLFSR
RDCR
-
Description
Read Identification
Read Serial Flash Discoverable P. Table
Read Data Bytes (3B/4B)
Read Data Bytes at Higher Speed (3B/4B)
Dual Output Fast Read (3B/4B)
Dual Input/Output Fast Read (3B/4B)
Quad Output Fast Read (3B/4B)
Quad Input/Output Fast Read (3B/4B)
Read Data Bytes at Higher Speed
Dual Output Fast Read
Dual Input/Output Fast Read
Quad Output Fast Read
Quad Input/Output Fast Read
Write Enable
Write Disable
Page Program (3B/4B)
Dual Input Fast Program (1-1-2)
Dual I/O Fast Program (1-2-2)
Quad Page Program (1-4-4)
Sector Erase 4KK
Block Erase 32KB
Block Erase 64KB
Single Die Erase (32MB)
Chip Erase (1Gb)
Read Status Register
Read Extended Address Register
Write Extended Address Register
Write Status Register
Read Security Register
Write Security Register
Read Lock Register
Write to Lock Register
Read Flag Status Register
Clear Flag Status Register
Read Non-volatile Configuration Register
Write Non-volatile Configuration Register
Read Volatile Configuration Register
Write Volatile Configuration Register
Read Enhance Volatile Configuration Register
Write Enhance Volatile Configuration Register
9
Macronix
MX66L1G45G
9Fh
5Ah
03h / 13h
0Bh / 0Ch
3Bh / 3Ch
BBh / BCh
6Bh / 6Ch
EBh /ECh
0Dh
BDh
EDh
06h
04h
02h / 12h
38h
20h
52h
D8h
60 / C7h
05h
C8h
C5h
01h
2Bh
2Fh
2Dh
2Ch
15h
-
Micron
N25Q00A
9Eh/9Fh
5Ah
03h / 13h
0Bh / 0Ch
3Bh / 3Ch
BBh / BCh
6Bh / 6Ch
EBh /ECh
0Dh
3Dh
BDh
6Dh
EDh
06h
04h
02h / 12h
A2h
D2h
32h
20h
D8h
C4h
05h
C8h
C5h
01h
E8h
E5h
70h
50h
B5h
B1h
85h
81h
65h
61h
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
Table 6-1: Command Code Comparison - Continued
Instruction
Type
QPI
OTP
Others
Instruction
EQIO
RSTQIO
QPIID
ENSO
EXSO
ROTP
POTP
PGM/ERS
Suspend
PGM/ERS
Resume
RSTEN
RST
EN4B
EX4B
DP
RDP
Description
Enable QPI
Reset (Exit) QPI
QPI ID Read
Enter Secured OTP
Exit Secured OTP
Read OTP Area
Program OTP Area
Program or Erase Suspend
Program or Erase Resume
Reset Enable
Reset Memory
Enter 4-Byte Mode
Exit 4-Byte Mode
Deep Power Down
Release from Deep Power Down
Macronix
MX66L1G45G
35h
F5h
AFh
B1h
C1h
B0h
30h
66h
99h
B7h
E9h
B9h
ABh
C0h
SBL
Set Burst Length
Note 1: Micron uses their Volatile Configuration Register to control this function.
Micron
N25Q00A
AFh
4Bh
42h
75h
7Ah
66h
99h
B7h
E9h
Note 1
7. Manufacturer and Device ID
Table 7-1: Manufacturer and Device ID Comparison
Command Type
Manufacture ID
Device ID
Macronix MX66L1G45G
C2h
Micron N25Q00A
20h
Memory Type
20h
BAh
Memory Capacity
1Bh
N/A
21h
17 Bytes
Unique ID
8. Summary
The Macronix MX66L1G45G and Micron N25Q00A have similar commands, functions, and features. The
devices are command compatible for basic read, program, and erase (4KB and 64KB) operations. The
devices are essentially pin compatible if the HOLD# function is not used. A more detailed analysis should
be done if “special” functions such as: XIP or Individual Sector Write Protection is used. If common
features are used in standard traditional modes, they may need only minimal software modification
primarily due to differences in register bit settings.
P/N: AN0309
10
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
9. References
Table 9-1 shows the datasheet versions used for comparison in this application note. For the most
current, detailed Macronix specification, please refer to the Macronix Website at
http://www.macronix.com/.
Table 9-1: Datasheet Version
Datasheet
MX66L1G45G, 3V, 1Gb, v0.0.pdf
n25q_1gb_3V_65nm.pdf
Location
Macronix Website
Micron Website
Date Issued
Dec. 2013
Sept. 2013
Version
0.0
K
10. Appendix
Table 10-1 shows the basic part number and package information cross reference between Macronix
MX66L1G45G and Micron N25Q128 parts.
Table 10-1: Part Number Cross Reference
Macronix Part No.
MX66L1G45GMI-10G
MX66L1G45GMI-10G
MX66L1G45GMI-10G
MX66L1G45GMI-10G
MX66L1G45GXDI-10G
MX66L1G45GXDI-10G
MX66L1G45GXDI-10G
MX66L1G45GXDI-10G
Micron Part No.
N25Q00AA13GSF40
N25Q00AA23GSF40
N25Q00AA33GSF40
N25Q00AA43GSF40
N25Q00AA13G1240
N25Q00AA23G1240
N25Q00AA33G1240
N25Q00AA43G1240
Package
16-SOP
16-SOP
16-SOP
16-SOP
24-BGA
24-BGA
24-BGA
24-BGA
Dimension
300 mil
300 mil
300 mil
300 mil
8 x 6 mm
8 x 6 mm
8 x 6 mm
8 x 6 mm
Note
Hold# pin, Micron XIP
Hold# pin, Basic XIP
Reset# pin, Micron XIP
Reset# pin, Basic XIP
Hold# pin, Micron XIP
Hold# pin, basic XIP
Reset# pin, Micron XIP
Reset# pin, basic XIP
11. Revision History
Revision
1.0
P/N: AN0309
Description
Initial Release
Date
January 20, 2014
11
Ver.1, Jan.20, 2014
Macronix Proprietary
APPLICATION NOTE
Comparing Micron N25Q00A with Macronix MX66L1G45G
Except for customized products which have been expressly identified in the applicable agreement,
Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial,
personal, and/or household applications only, and not for use in any applications which may, directly or
indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are
used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said
Macronix's product qualified for its actual use in accordance with the applicable laws and regulations;
and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen
therefrom.
Copyright© Macronix International Co., Ltd. 2014. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit,
Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo,
BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Au-dio, Rich Book, Rich TV,
and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes
only
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
P/N: AN0309
12
Ver.1, Jan.20, 2014
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