SC1116 Datasheet

SC1116
Linear FET Controller
For DDR Supplies
POWER MANAGEMENT
Description
Features
The SC1116 is a low cost controller for low power
linear DDR power supplies.
‹ User can select FETs to optimize system current
‹
The SC1116 comes in a space saving SOT-23 6 pin
‹
package.
‹
‹
The SC1116 provides a dual gate drive for the top serial
‹
and bottom parallel MOSFETs with internal shoot through
‹
protection.
‹
The wide range of input voltages (3V to 15V) allows the
chip to work in many various applications.
rating/dropout/cost
Low VDDQ, 0.5V to 2.5V
-40°C to +85°C operating temperature
External compensation capable for low ESR loads
Minimum external components
0.6 mA Quiescent current
Guaranteed no shoot through
SOT-23 6L small package. Fully WEEE and RoHS
compliant
Applications
‹
‹
‹
‹
The variable output voltage is programmable from the
outside with an input divider or an external reference.
Wide range of VDDQ, down to 0.5V
DDR supplies
SCSI
Line termination
Source / Sink LDOs
Typical Application Circuit
Q1
MOS FET N
VDDQ=2.5Vtyp
R1
1k 0.5%
VTT=1.25Vtyp
4 7uF
typ
U1
SC1116
Vcc=3 to 15V
1
VCC
DRVH
6
2
GND
FB
5
3
REF
DRVL
4
GND
0 .1 uF
R2
1k 0.5%
Q2
MOS FET N
1k
typ
0 .1 uF
4 .7 nF
typ
1k
typ
4 .7 nF
typ
Notes:
(1) Values used for optional compensation are 1K and 4.7nF typical.
(2) When using 3V as Vcc, use of low threshold FETs is a must.
Revision: March 28, 2007
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SC1116
POWER MANAGEMENT
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
Parameter
Symbol
Maximum
Units
Input Supply Voltage
VCC
-0.3 to +16.5
V
Operating Ambient Temperature Range
TA
-40 to +85
°C
Operating Junction Temperature Range
TJ
-40 to +125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Thermal Impedance Junction to Ambient
θJ A
95.7
°C/W
Thermal Impedance Junction to Case
θJ C
61.7
°C/W
Power Dissipation at TA = 25°C
PD
250
mW
Lead Temperature (Soldering) 10 seconds
TLEAD
300
°C
ESD Rating (Human Body Model)
ESD
2
kV
Electricial Characteristics
Unless otherwise specified, VCC = 5V, 0.5V ≤ VDDQ ≤ 2.5V, R1 = R2 = 1kΩ +/- 0.1%.
Specifications with standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range
(TA = -40°C to +85°C).
Parameter
Test Conditions
Supply Voltage
Load Regulation (1)
Quiescent Current/Standby Current
FB & REF Input Current
Min
Typ
3
IL: 0 + 3A
IL: 0 - 3A
-1
+1
VCC = 15V, no load = 0A
600
V C C = 15V
Max
Units
15
V
%
800
µA
100
nA
0.25
V
Gate Drive
Output Low
ISINK = 2.5mA
Output High
ISOURCE = 2.5mA
0.15
Vcc -0.25
Vcc -0.15
V
Note:
(1) For Load Regulation testing use a low duty cycle current pulse, when measuring VTT.
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SC1116
POWER MANAGEMENT
Pin Configuration
Ordering Information
Part Number
TOP VIEW
Top Mark
P ackag e
AH00
SOT-23 6L
SC1116ISKTR (1)
SC1116ISKTRT (1)(2)
VCC
1
6
DRVH
GND
2
5
FB
REF
3
4
DRVL
Notes:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
(2) Lead free option. Fully WEEE and RoHS compliant.
(SOT-23 6L)
Pin Descriptions
Pin #
Pin Name Pin Function
1
VC C
Supply pin, connect a 3V to 15V supply and decouple to ground with a 0.1µF ceramic capacitor.
2
GND
Power and signal ground.
3
REF
Reference input. Output voltage will be regulated to this voltage.
4
DRVL
5
FB
6
DRVH
Low side FET drive output.
Feedback pin.
High side FET drive output.
Block Diagram
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SC1116
POWER MANAGEMENT
Application Information
Overview
The SC1116 linear controller is designed to meet the
JEDEC specifications for termination of DDR-SDRAM.
Double Data Rate (DDR) memory is clocked at the same
speed as older SDRAM (synchronous dynamic random
access memory), yet handles twice the amount of data
by using the rising and falling edge of the clock signal for
data transfers. Another difference is that DDR memory
requires 2.5V instead of 3.3V used by standard SDRAM.
The other feature that separates DDR memory from a
conventional type is employment of the VTT – termination
voltage. Main requirements for the VTT are that it must
track variations of VDDQ and be able to supply (source)
current, and absorb (sink) current.
The SC1116 controller offers a low cost solution for DDR
termination voltage regulation by using external pass elements (MOSFETs). Having the flexibility of choosing the
MOSFETs allows for optimization on the basis of cost/
size/performance of the specific application.
Test Circuit & Waveforms
The test circuit is shown below in Figure 1.
Note that VREF voltage is supplied externally to eliminate
inaccuracy caused by resistor divider.
V TT =1.25V typ
Q1
IR37 14
V DDQ=2.5V
+/-3A
Iso urce/ Isink
Isin k
3A Isource
Po wer
Su pp ly
C1
1 00 uF
3 2m
U1
SC1116
1
V cc=5V
C2
1 uF
V ref=1.25V
C3
0 .1uF
VCC
2
G ND
3
R EF
C6
2 70 uF
DRVH
2 2m
6
2xIsin k
0A to 6A Step
FB
5
DRVL
4
Pu lse loa d, dc=50%
Q2
IR37 14
R3
1k
R4
1k
C4
4.7nF
Cu rrent
Pro be
E lectronic
Loa d
C5
4 .7nF
Figure 1.
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SC1116
POWER MANAGEMENT
Typical Characteristics
Regulation Vtt vs. Vref @ Is/s=5A; Vcc=5V
2.0%
2.0%
1.0%
1.0%
0.0%
0.0%
-1.0%
-1.0%
dVtt / Vtt
dVtt / Vtt
Regulation Vtt vs. Vref @ Is/s=1A; Vcc=5V
-2.0%
-2.0%
-3.0%
-3.0%
-4.0%
-4.0%
-5.0%
-5.0%
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.2
1.3
0.3
0.4
0.5
0.6
2.0%
1.0%
1.0%
0.0%
0.0%
-1.0%
-1.0%
dVtt / Vtt
dVtt / Vtt
2.0%
-2.0%
-3.0%
-4.0%
-4.0%
-5.0%
-5.0%
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.1
1.2
1.3
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Vref (Vddq/2), V
Vref (Vddq/2), V
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1.0
-2.0%
-3.0%
0.4
0.9
Regulation Vtt vs. Vref @ Is/s=5A; Vcc=12V
Regulation Vtt vs. Vref @ Is/s=1A; Vcc=12V
0.3
0.8
Vref (Vddq/2), V
Vref (Vddq/2), V
0.2
0.7
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SC1116
POWER MANAGEMENT
Typical Characteristics (Cont.)
Max. Sourcing Current
vs. V CC
6
V DDQ = 2.5V
V REF = 1.25V
V TT = 1.237V
OUTPUT CURRENT (A)
5
4
3
2
1
0
3
3.5
4
4.5
5
5.5
SUPPLY VOLTAGE, V CC (V)
6
6.5
Max. Sinking Current
vs. V CC
4.4
V DDQ = 2.5V
V REF = 1.25V
V TT = 1.263V
4.3
OUTPUT CURRENT (A)
4.2
4.1
4
3.9
3.8
3.7
3.6
3
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3.5
4
4.5
5
5.5
SUPPLY VOLTAGE, V CC (V)
6
6
6.5
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SC1116
POWER MANAGEMENT
Typical Characteristics (Cont.)
Quie s ce nt Current
vs . Te m pe rature
520
V CC = 5V
V DDQ = 2.5V
V REF = 1.25V
V TT = 1.25V
ILOAD = 0A
QUIESCENT CURRENT (uA
510
500
490
480
470
460
450
-40
-25
-10
5
20
35
50
65
TEMPERATURE °C
80
110
125
Quiescent Current
vs. V CC
800
V DDQ = 2.5V
V REF = 1.25V
V TT = 1.25V
ILOAD = 0A
700
600
QUIESCENT CURRENT (uA)
95
125 oC
500
400
25 oC
0 oC
300
200
100
0
3
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3.5
4
4.5
5
5.5
SUPPLY VOLTAGE, V CC(V)
7
6
6.5
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SC1116
POWER MANAGEMENT
Test Waveforms
VTT Transient Response
VCC = 5V
VDDQ = 2.5V
VREF = 1.25V
VTT
100mV/div
ISOURCE / ISINK
ISOURCE / ISINK
VTT
100mV/div
VCC = 5V
VDDQ = 2.5V
VREF = 1.25V
I STEP :
+2.3A
to - 2.2A
I STEP :
+1.75A
to –1.75A
Slew Rate:
2.5 A/uS
Slew Rate:
2.5 A/uS
Time (50us/div)
Time (50us/div)
Slew Rate:
2.5 A/uS
I STEP :
- 0.75A
to + 0.75A
ISOURCE / ISINK
VTT
100mV/div
ISOURCE / ISINK
I STEP :
+1.25A
to –1.25A
Slew Rate:
2.5 A/uS
Time (50us/div)
Time (50us/div)
 2007 Semtech Corp.
VCC = 5V
VDDQ = 2.5V
VREF = 1.25V
VTT
100mV/div
VCC = 5V
VDDQ = 2.5V
VREF = 1.25V
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SC1116
POWER MANAGEMENT
Test Waveforms (Cont.)
VTT Transient Response
I STEP :
- 0.5A
to + 0.53A
ISOURCE / ISINK
I STEP :
- 0.53A
to + 0.53A
ISOURCE / ISINK
VCC = 5V
VDDQ = 2.5V
VREF = 1.25V
COUT = 47uF
ceramic
VTT
100mV/div
VTT
100mV/div
VCC = 5V
VDDQ = 2.5V
VREF = 1.25V
Slew Rate:
2.5 A/uS
Slew Rate:
2.5 A/uS
Time (50us/div)
Time (50us/div)
VCC = 5V
VDDQ = 2.5V
VREF = 1.25V
VTT
50mV/div
VTT
20mV/div
VCC = 5V
VDDQ = 2.5V
VREF = 1.25V
I STEP :
+ 0.03A
to - 2.25A
ISOURCE / ISINK
ISOURCE / ISINK
I STEP :
+ 0.03A
to + 2.25A
Slew Rate:
2.5 A/uS
Time (20us/div)
Time (20us/div)
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Slew Rate:
2.5 A/uS
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SC1116
POWER MANAGEMENT
Evaluation Board
Top View
Top Layer
Evaluation Board Schematic
Q1
IR3714
VDDQ=2.5Vtyp
C1
22uF
R1
1k 0.5%
C6
47uF
U1
SC1116
Vcc=3 to 15V
C2
0.1
R2
1k 0.5%
VTT=1.25Vtyp
1
VCC
DRVH
6
2
GND
FB
5
3
REF
DRVL
4
Q2
IR3714
R3
1k
C3
0.1
GND
C4
4.7nF
R4
1k
C5
4.7nF
Notes:
(1) Values used for optional compensation are 1K and 4.7nF typical.
(2) When using 3V as Vcc, use of low threshold FETs is a must.
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SC1116
POWER MANAGEMENT
Outline Drawing - SOT-23-6
DIM
A
e1
2X E/2
A
A1
A2
b
c
D
E1
E
e
e1
L
L1
N
01
aaa
bbb
ccc
D
N
EI
1
E
2
ccc C
2X N/2 TIPS
e
B
D
aaa C
A2
SEATING
PLANE
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
.057
.035
.000
.006
.035 .045 .051
.010
.020
.003
.009
.110 .114 .122
.060 .063 .069
.110 BSC
.037 BSC
.075 BSC
.012 .018 .024
(.024)
6
0°
10°
.004
.008
.008
A
H
A1
C
bxN
bbb
1.45
0.90
0.15
0.00
.90 1.15 1.30
0.25
0.50
0.08
0.22
2.80 2.90 3.10
1.50 1.60 1.75
2.80 BSC
0.95 BSC
1.90 BSC
0.30 0.45 0.60
(0.60)
6
0°
10°
0.10
0.20
0.20
c
GAGE
PLANE
C A-B D
0.25
L
01
(L1)
SEE DETAIL
A
DETAIL
A
SIDE VIEW
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
Minimum Land Pattern - SOT-23-6
X
DIM
(C)
G
Z
Y
P
C
G
P
X
Y
Z
DIMENSIONS
MILLIMETERS
INCHES
(.098)
.055
.037
.024
.043
.141
(2.50)
1.40
0.95
0.60
1.10
3.60
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
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