AND8332/D Calculating External Components Prepared by: Stef Servaes ON Semiconductor http://onsemi.com APPLICATION NOTE Scope Additional proprietary handshaking is implemented as a fifth class to program with an external resistor. The ON Semiconductor vertical N−channel DMOS device is inherently robust for fast transients. This results in cable ESD levels of 2 kV (on the RJ45 connector) and HBM ESD levels of 2 kV. The PWM controller facilitates single−ended SMPS power supply topologies such as fly−back and forward converters. The control scheme is based on peak current control. This control allows line feed−forward, cycle−by−cycle current limitation and simple feedback compensation. The inrush current limit, operational current limit, operating frequency and soft start time are programmable, depending on the requirements of the application. This application note attempts to give a step−by−step approach to the implementation of a stable power supply. All aspects of the process from converter architecture to the PCB layout guidelines are explained, while trying to minimize the mathematics necessary to perform the steps. Converter transfer functions are not deduced as literature on these topics is widely available. An isolated fly−back topology is described in this document. Other topologies are discussed in separate application notes. Although the document mostly references the NCP1081, the discussed principles and calculations for the external components are equally valid for the NCP1080, NCP1082 and NCP1083. This document describes how to calculate external component values for the NCP1080, NCP1081, NCP1082 and NCP1083 integrated PoE−PD and DC−DC converter controller and elaborates on implementation details, without delving into theoretical details. Examples are illustrated with the use of the supplied calculation scripts. Introduction The NCP108x are robust, flexible and highly integrated solutions targeting demanding medium− and high−power Ethernet terminals. The combination of an enhanced PoE−PD fully compliant with the IEEE 802.3af and IEEE 802.3at specifications for the NCP1081 with a highly efficient SMPS, in a single device, offer new opportunities for the design of products directly supplied over Ethernet lines. Elimination of the need for any local power adaptor or power supply drastically reduces the overall installation and maintenance cost. ON Semiconductor’s unique process and design enhancements allow the NCP1081 to power PoE systems with up to 40 W. The NCP1080 is designed to support power levels up to 15.4 W, according to the IEEE 802.3af specification. The hot swap PD switch and programmable current limit are designed for high power applications. The handshaking for power requirements for the IEEE 802.3at standard supports Type 1 and Type 2 classification with Layer 1 single and dual events as well as Layer 2 classification. © Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 0 1 Publication Order Number: AND8332/D AND8332/D CURRENT MODE CONTROL, ISOLATED FLY−BACK CONVERTER 0.1uF VPORTP Bridge1 Magnetics1 0.1uF 1-TX+/BI_DA+ 2-TX-/BI_DA3-RX+/BI_DB+ 4-NC/BI_DC+ 5-NC/BI_DC6-RX-/BI_DB7-NC/BI_DD+ 8-NC/BI_DD- Cline Zline 0.1uF Bridge2 RJ45 Magnetics2 VPORTN 0.1uF Optional ground coupling capacity. Do not equip. Cpd, multiple footprints to allow precise adjustment and ESR tuning Cpd1 Cpd2 Cgnd Cpd3 Csn2 Rbw T1 Dbw VPORTP Cf1 VDDH CLASS Rinrush Rled Led Rfb3 VDDL INRUSH Rbias1 Rilim1 Cvddl ILIM1 Cfb2 NCP1081 Csn1 nClassAT UVLO U2 Rbias2 Q1 Rgate Rfb1 GATE Rdet2 TEST2 CS TEST1 FB OSC COMP SS VPORTN1 VPORTN2 1 Cout1 Cout2 Rclass Rdet1 Vout L1 Dsec Cvddh VPORTP Cout, multiple footprints to allow precise adjustment and ESR tuning. Rsn2 Rsn1 Rsl ARTN RTN Rcs Cfb1 TL431 Rfb2 VPORTN Css Rosc Figure 1. Isolated Fly−back Converter with Bias Winding and Diode Bridge http://onsemi.com 2 Cf2 2 AND8332/D Figure 2. Primary Circuitry of the Flyback Converter Using Active Rectification for Better Overall Efficiency http://onsemi.com 3 AND8332/D PoE−PD SIDE DESIGN The Isolated Fly−back Converter with Bias Winding and diode bridge is shown in Figure 1. The primary circuitry can use also the active rectification bridge for better overall converter efficiency(Figure 2). We will calculate or decide on the values for the components listed in Table 1. Detection and UVLO Setting During the detection phase the input impedance of the PD device is measured by the PSE and should, according to IEEE 802.3af/at, be included between 23.75 kW and 26.25 kW. The NCP108x can either use its internal under voltage lockout setting of 37.5 V, or an external resistor divider can be used to tune the UVLO. The NCP108x will not allow operation of the power converter unless the sensed line voltage is above the UVLO pin limit (internal or external). Rdet or the sum of Rdet1 and Rdet2 should hence be 25.5 kW. The UVLO limit, Vuvlo_on, should be configured to the low−line design parameter of the converter. In most cases this will be 36 V. Use Equation 1 to calculate Rdet1 and Rdet2. Table 1. LIST OF COMPONENTS Name Description Cout1,2 DC−DC output capacitor Cpd1,2,3 DC−DC input capacitor Rcs Resistor for current sensing Rsl Resistor for extra slope compensation (optional) Rclass Resistor setting the classification current level Rinrush Resistor setting the inrush current limitation level Rilim1 Resistor setting the operational current limit level Cline Input line capacitor Zline Tranzorb (transient voltage suppression diode) Rdet1 Detection signature and external UVLO programmable resistor 1 where Vuvlo_ref = 1.2 V Rdet2 Detection signature and external UVLO programmable resistor 2 Classification Csn1 Snubber capacitor for the switching transistor Rsn1 Snubber resistor for the switching transistor Csn2 Snubber capacitor for the power diode Rsn2 Snubber resistor for the power diode Rfb1 Resistor for the voltage feedback system Rfb2 Resistor for the voltage feedback system Rfb3 Resistor for the voltage feedback system R det2 + V uvlo_ref V uvlo_on + 25.5 kW (eq. 1) and R det2 ) R det1 + 25.5 kW IEEE 802.3af/at specifies five power classes (0 − 4). During classification the PSE equipment will sense the current that flows through Rclass to determine what power consumption class the PD equipment belongs to. Table 2 indicates what resistor value to use for Rclass for the different classes. Note that a fifth non−standard high−power class is defined to enable the NCP1081 high power capabilities. Table 2. IEEE 802.3AF/AT POWER CLASSES Rclass (W) Rbias1 Resistor for extra biasing current in the opto− coupler (optional) Rbias2 Resistor for extra biasing current in the TL431 shunt regulator (optional) 10k Class 0: 15.4 W 130 Class 1: 4 W Cfb1 Capacitor for the voltage feedback system 69.8 Class 2: 7 W Cfb2 Capacitor for the voltage feedback system 44.2 Class 3: 15.4 W Rbw Current limiting resistor for bias winding usage 30.9 Class 4: IEEE 802.3at device class Rled Current limiting resistor for nCLASS_AT LED 22.1 C1..4 Capacitors for noise reduction on the Ethernet magnetics Class 5: NCP1081 class, power levels exceeding IEEE 802.3at levels Cvddl Decoupling capacitor for VDDL low voltage regulator Cvddh Decoupling capacitor for VDDH high voltage regulator Rosc Resistor setting the PWM switching frequency Power Class The IEEE 802.3at specification describes a second classification event to let the application know if higher power (higher than IEEE 802.3af power levels) can be switched on. This second classification is either supported by hardware (NCP1081, not NCP1080) or by software on a network processor, powered by the NCP1081. The PSE http://onsemi.com 4 AND8332/D Power Stage Design decides which classification will be executed. When the hardware classification is complete the nClassAT pin is low. When the hardware classification is not executed, meaning that either the PSE is IEEE 802.3af compliant or that the high power capabilities will be exchanged by the network protocols, the nClassAT will remain high. The LED connected to nClassAT will only light when the second event hardware classification has completed. Decide on the System Parameters and Transformer to Use Table 5. INPUT PARAMETERS Programmable Current Limitation Inrush Current Limit Table 3 lists the typical values for Rinrush. Table 3. PROGRAMMABLE INRUSH CURRENT Rinrush (kW) Min Typ Max Unit 150 95 125 155 mA 57.6 260 310 360 mA Table 4. USEFUL VALUES FOR Rilim1 Typ Max Unit 84.5 450 510 570 mA 66.5 600 645 690 mA 56.0 720 770 820 mA 36.5 970 1100 1230 mA Vin Ethernet input voltage. Take into account the drop over the diode bridge. Vout The desired output voltage Lprim The inductance of the primary of the transformer N The transformer turns ratio Pout The desired output power Vripple The desired output ripple The desired PWM switching frequency The switching frequency (fs) supported by the NCP108x ranges up to 500 kHz. Higher frequencies reduce the size of the transformer but may have adverse effects on other parameters such as switching loss. The designer will have to find an optimum between power consumption and material cost. Note that this entire design guideline is focused on the implementation of a current measurement feedback loop on top of voltage feedback. Table 4 lists the typical values for Rilim1. Min Description fs Operational Current Limit Rilim1 (kW) Parameter Configure the Switching Frequency The PWM switching frequency is configured by an external resistor Rosc. Rosc is calculated using Equation 2, below. Note that non−standard compliant current can be achieved by lowering Rilim1. Keep in mind that the absolute maximum rating for the current through the NCP1081 is 1.23 A. Note that the board layout should allow proper thermal conductivity to avoid exceeding the maximum junction temperature. R osc + 38600 fs kW (eq. 2) Where fs (kHz) the desired switching frequency Continuos Conduction Mode (CCM) or Discontinuos Conduction Mode (DCM) Diode Bridge and Cline Note that the NCP108x is designed to operate in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Pros and cons exist for both modes of operation. In CCM, the ripple current is smaller and possibly a smaller output capacitance can be used. In DCM, the conduction losses are higher (because the currents are higher) but the switching loss is smaller (due to current being zero when switch opens). Also in DCM, a smaller inductor or transformer can be used, leading to lower leakage inductance. On the other hand, the AC losses in the DCM transformer may become dominant. Due to the higher currents in DCM, the DCM converter creates more EMI. Cline should be a 100nF ceramic with low ESR (< 0.1 W) and 20% tolerance. The diode bridge should be dimensioned to allow the maximum current that is chosen for the design. http://onsemi.com 5 AND8332/D Iprim Iprim Iprim t t Also take into account the forward voltage drop of the diode (typically 0.5 V). V inT onN 1 + V outT offN 2 D/fs Critical Conduction Mode t å D/fs D/fs Dead time Discontinuous Conduction Mode Continuous Conduction Mod N1 N2 + N å D max + Switching frequency, transformer induction and load are parameters that make the converter run in one or the other mode. The transition from one to the other mode depends on these three values. The point where the system transitions from DCM to CCM is called the critical conduction mode. Correspondingly, we can define the critical load, frequency and induction. 2 @ Lc @ fs @ n2 (1 * D ) LC + 2 N N 1 N 2 ) 1 2 V (eq. 6) in_min V out Calculate the Various Currents Ipeak_pri Iavg_pri R c @ ǒ1 * D) 2 2 @ fs @ n2 R C(1 * D) FC + (eq. 5) 1 * D max V out Figure 3. CCM/DCM RC + V in_min D max 2 t (eq. 3) Ton 2 @ LC @ n The design procedure described in the following sections focuses on CCM operation. Equation 3 can be used to find out how far the design is from running in one or the other mode. Ipeak_sec Toff t Figure 5. Primary and Secondary Currents (ccm) Calculate the Duty Cycle First calculate the converter duty−cycle D from the assumption that in one full cycle the secondary voltage should be zero and thus equal the shaded areas of Figure 4 where T is the period. Average currents, during Ton: I avg_pri + P out V in @ D @ h transformer I avg_sec + V Vin.n P out (eq. 7) V out @ (1 * D) Magnetizing currents: (1-D)T I mag_pri + DT V in @ D L pri @ f s (eq. 8) Vout I mag_sec + Figure 4. Determining the Duty−Cycle V out V in D +n 1*D ǒVout ) VdiodeǓ @ (1 * D) L sec @ f s Peak currents: (eq. 4) I peak_pri + I avg_pri ) I mag_pri or D+ V out I peak_sec + I avg_sec ) V out ) nV in The NCP108x supports duty cycles up to 0.80. Use Equations 5 and 6 and the data of the chosen transformer to calculate whether or not the maximum duty cycle can be met. Note that the duty cycle is at a maximum when the input voltage is at its lowest (low line), therefore we use Vin_min . http://onsemi.com 6 2 I mag_pri 2 (eq. 9) AND8332/D RMS currents: and I rms_pri + P out Z L + 2pf sL V in @ ǸD @ h transformer I avg_sec + or (eq. 10) P out LC + V out @ Ǹ(1 * D) Use the duty−cycle D to obtain a value for Cout. P out 2D f sV ripple V out (eq. 11) f LC + Cout1 s ǒ1 ) wzesr Ǔ @ ǒ1 * w s V ripple_esr ZC ) ZL 1) Ǔ (eq. 16) s wp where w zesr + 1 R esr @ C out (eq. 17) wzesr is a zero originating from the output capacitor and its equivalent series resistor. w zrhp + R load @ (1 * D) DL prin 2 2 (eq. 18) wzrhp is a right half plane zero can be explained by the phenomenon that when there’s a sudden load increase, the duty cycle will increase instantaneously, building up higher current but the voltage will drop temporarily until the required current is present. Since this zero is located in the (eq. 12) with ZC + zrhp T power_ccm(s) + K An additional L−C filter should be added to meet the ripple specification. A large capacitor should remain at the side of the load to cope with load changes and to make sure no stability issues arise from capacitive loading (due to shift of the filter resonance frequency). Therefore, split the output capacitance in two, or take an additional one (depending on the ESR which should not increase) and place an inductor in between to create an L−C filter. The damping of the L−C filter is given by Equation 12. This equation can be rewritten into Equation 13 which gives the product of L and C. ZC (eq. 15) Equation 16 shows the transfer function of the fly−back converter in current controlled mode of operation. Note that adding current measurement in the feedback loop has advantages on top of implementing only voltage measurement feedback: − The feedback is immediate, current can be limited in the same cycle, − The order of the transfer function is reduced, leading to a system that is easier to stabilize, − The phase margin is better. Figure 6. Adding an Additional Ripple Filter + 1 Ǹ p L2C Stability Analysis of the Converter in CCM Lsec V ripple (eq. 14) Choose a value for L and calculate the value for C. Next, make sure the resonance frequency (Equation 15) is at least two or three times higher than the cross−over frequency of the closed loop converter (to make sure the resonant peak stays well below 0 dB), but still lower than the switching frequency of the regulator (to make sure switching noise is filtered). Cout Cf1 Cf2 (eq. 13) 2 V ripple + I peak_sec R esr The parasitic effective series resistance (Resr) of the capacitor Cout affects the output voltage ripple the most. The ripple caused by Resr is an order of magnitude larger than the ripple caused by having a small output capacitance. The required output ripple specification will not be met by using an output capacitor only. Take the closest standard value for the capacitor with the lowest Resr. It is better to deviate from the calculated capacitance value when there’s another capacitor value with lower ESR. Equally important is to measure the chosen capacitor or parallel capacitors on an impedance analyzer to make sure the ESR is correct. Cout1 V ripple(2pf s) Vripple is the desired output voltage ripple and Vripple_esr is the voltage ripple that is generated over the ESR of the output capacitor. The approximate current that flows through the ESR resistor is the secondary peak current of the converter, leading to Equation 14. Output Capacitance and Filter C out + V ripple_esr * V ripple 1 2pf sC http://onsemi.com 7 AND8332/D right half plane, this leads to a gain boost and a phase lag (which is not desirable and can lead to an unstable system). wp + 1)D R loadC out A bigger phase margin lowers the peaking on transitions and a higher system bandwidth increases the speed of the system. The DC error (or static, or steady state error) is reduced when the low frequency gain is increased. Use Equation 16 to plot a Bode diagram and inspect where stability issues may arise. (eq. 19) wp , a dominant pole originates from the load and output capacitor. K+ R load(1 * D) (eq. 20) nR csA V(1 ) D) where Av = 2 for NCP108x To investigate and improve the stability of the DC−DC converter, the technique of frequency response compensation is used. This technique is based on the fact that any linear system in steady state will show at its output a sine wave with amplitude and phase when it is excited at its input with a sine wave of given frequency, amplitude and phase. The amplitude and phase of the output signal may be different than those of the input signal, however the input and output frequency will be the same. This technique uses a Bode plot to assess the stability criteria. A Bode plot consists of two drawings. One drawing plots the magnitude of the output signal over the input signal, using logarithmic scale. The other drawing plots the phase of the output minus the phase of the input, using logarithmic scale. Figure 8. Bode Plot of the Power Sate of a 30 W 3.3 V Fly−back Converter (note the poor gain at DC) DC Gain Boosting and Phase Margin Insurance When we translate the stability requirements to our fly−back converter design, we should have a system with high phase margin (around 60°), high bandwidth (unity gain or cross−over frequency as high as possible but still far enough from the switching frequency), a high gain at DC, and a high attenuation at high frequency. This is achieved by adding a control and compensation network which uses an opto−coupler for isolation, introduces an extra zero, two poles (one at DC) and has following transfer function: M(dB ) 0 Gain margin Frequency (log ) Phase (degrees ) −180 Phase margin Frequency (log ) T comp(s) + Figure 7. Phase and Gain Margin CTR @ ǒ5KńńR bias1Ǔ R fb3 (eq. 21) ǒ1 ) wszǓ ǒ A closed loop system is stable if the open loop frequency response shows a gain of less than 0 dB at the frequency where the phase shift is 180°. Gain margin is the value by which the gain of the system can be increased, while keeping the phase at −180° (Note 1), before the system becomes unstable. Phase margin is the value by which the phase of the system can be increased, keeping the gain at 1, before the system becomes unstable. R fb1 @ C fb1 @ s @ 1 ) ws Ǔ p The goal of the compensation network is to set the gain criteria while affecting the phase margin as least as possible. (Proportional−integral (PI) plus high−frequency pole compensation) 1. Note that the systems discussed here, all have negative feedback like most feedback systems, hence the −180° of the negative feedback together with an additional 180° shift would yield 360° overall shift, a positive feedback, unstable system. http://onsemi.com 8 AND8332/D Step 1: Define the Compensation Circuit Cross−Over Frequency plot of the open loop system to find the phase margin at the cross−over frequency. The pole of the compensation network needs to be K times larger and its zero needs to be K times smaller than the cross−over frequency. With K given by: Rule of thumb: The converter should have a cross−over frequency ǒ f cross t min f zrhp f s , , f zesr, f optocoupler 3 5 Ǔ ǒboost ) 45Ǔ 2 (eq. 22) K + tan where: − fzrhp is the frequency of the right hand plan zero of the open loop fly−back converter derived from Equation 18 − fs is the converter’s switching frequency − fzesr is the frequency of the zero introduced by the output capacitor’s series resistance, given by Equation 17 − foptocoupler is the frequency indicating the bandwidth of the chosen opto−coupler boost = desired phase margin − actual phase margin + 90 Now, choose a value for Rfb1 and use Equations 24 and 25 to calculate Cfb1 and Cfb2. fz + fp + Step 2: Phase Margin Insurance, Define the Pole and Zero Frequency of the Compensation Circuit 1 å C fb1 + 2p @ R fb1 @ C fb1 1 2pR fb1 f z (eq. 24) 1 2p @ ǒ5KńńR bias1Ǔ @ C fb2 å C fb2 + Instead of using a Type II or Type III compensation network with operational amplifier, often an equivalent but cheaper network with TL431 voltage reference is used as an error amplifier in combination with an opto−coupler for isolation. 1 (eq. 25) 2pǒ5KńńR bias1Ǔ f p Step 3: Gain Adjustment First we need to find out, using the Bode plot, what the gain (A0) is of the open loop system at fcross . The gain of the compensation network is given by: Integrator gain, 1st pole at DC CTR @ 2nd pole where opto−coupler rolls off Opto−coupler gain (eq. 23) 5KńńR bias1 R fb3 (eq. 26) where CTR is equal to the current transfer ratio of the opto−coupler. The Rbias2 and Rfb3 resistors connected to the opto−coupler and the TL431 shunt regulator should be carefully tuned to guarantee a sufficient operating current for the TL431 (typical TL431 require minimum 1 mA as bias current). The gain of this network needs to be sufficiently high to react abruptly on reaching the output voltage. It is good practice to measure the performance of this network prior to switching on the NCP1081. Now equalize the compensation network gain to the inverse of the open loop gain at cross−over frequency and calculate Rfb3. Overall gain(thick line) 0dB Zero where integrator has unity gain Figure 9. Compensation Network Gain Approximation At low frequencies Cfb1 and Rfb1 act like an integrator. The overall gain of the integrator is the product of the integrator gain and the opto−coupler gain. The compensation zero is located at the point where the integrator crosses over. At mid−range frequencies, the opto−coupler becomes dominant because the integrator with the TL431 has crossed unity gain. The gain is determined by the opto−coupler gain, Rfb3 and the NCP108x 5 kW internal pull−up in parallel with Rbias1. At high frequencies the pole of the opto−coupler becomes dominant. Make sure that the bandwidth of the opto−coupler is as high as possible. Rbias1 in parallel with the 5 kW internal resistor should be tuned such that the opto−coupler is sufficiently biased. We want to configure a known compensation pole by inserting Cfb2. We make sure that between the zero and the pole of the compensation network we have a unity gain of the closed loop system with the desired phase margin. Use the Bode CTR @ 5 kWńńR bias1 R fb3 + 1 + A comp A0 (eq. 27) Step 4: Set the TL431 DC Regulation Voltage The shunt regulator compares the output voltage divider to an internal Vtl431 reference and generates an error voltage which is applied to the cathode of the opto−coupler. The output resistor divider made of Rfb1 and Rfb2 should be calculated to provide exactly Vtl431 to the reference pin of the TL431 when the power converter output voltage equals the desired regulated Vout1 voltage. Since Rfb1 was already chosen before, Rfb2 can be calculated easily. R fb2 + http://onsemi.com 9 V tl431 @ R fb1 V out * V tl431 (eq. 28) AND8332/D Step 5: Check the Compensation Network Performance The theoretically derived component values need to be checked on the real design. Two separate measurement techniques are proposed to measure the frequency response of the entire loop and that of the converter without the compensation network. Most probably, more than one iteration will be required to get it right. Figure 10. Bode Plot for a 30 W 3.3 V Converter Compensation Network Measure the Full Loop Frequency Response, Including the Compensation Network Rbw Dbw Csn3 Rsn3 VPORTP Rclass VDDH CLASS Out Cout3 Dsec Rinrush Cline Cout4 Rled VDDL INRUSH Zline Frequency response analyser L2 Cvddh ChA ChB 1 2 J3 Cpd Rdet1 Rilim1 Led Cvddl ILIM1 20 … 100 NCP1081 nClassAT UVLO Rgate Rdet2 Cfb2 GATE TEST2 CS TEST1 FB COMP SS OSC VPORTN1 VPORTN2 Rfb3 Csn1 Q1 Rsn1 Rfb1 U2 Cfb1 Rsl ARTN RTN Rcs TL431 Rfb2 Css Rosc Figure 11. Closed Loop Measurement The proposed technique measures the entire loop frequency response without breaking the loop. The standard way of measuring this would be to break the loop and inject and measure the signal at impedance matched cutting points. http://onsemi.com 10 AND8332/D Measure the Frequency Response of the Power Converter Only, Without the Compensation Network Rbw Dbw Csn3 Rsn3 VPORTP Rclass L2 VDDH CLASS Cvddh Dsec Cline Zline Cout3 Cpd VDDL INRUSH Rdet1 1 2 Cout4 Rled Rinrush J3 Led Rilim1 Frequency response analyser Cvddl ILIM1 Out NCP1081 nClassAT UVLO Q1 Cfb2 GATE Cfb1 FB TEST1 COMP SS OSC VPORTN1 VPORTN2 Rfb1 U2 Rsn1 CS TEST2 ChB Rfb3 Rgate Rdet2 ChA Csn1 Rsl ARTN RTN Rcs TL431 Rfb2 Css Rosc Figure 12. Open Loop Measurement This measurement technique measures the loop without having to break it, but at the same time, the network between measurement point A and B is eliminated. In this case we measure the frequency response of the power converter, without the compensation network. These possible oscillations are modeled by another transfer function which will be multiplied with the transfer function of the power stage, listed in Equation 16. T h(s) + Slope Compensation To overcome sub−harmonic oscillations and instability problems that exist with constant frequency current mode control converters running in continuous conduction mode (CCM) and when the duty cycle is close or above 50%, the NCP108x integrates a current slope compensation circuit. This sub−harmonic oscillation phenomenon can be understood by looking at Figure 13. The current in the primary transformer is illustrated for two different duty cycle cases, assuming a current mode PWM controller without slope compensation. When D > 0.5, a small disturbance on the primary current causes a duty cycle asymmetry between consecutive pulse cycles. This error increases with every cycle (due to the fixed frequency operation) and will lead to oscillation in the regulation loop at fs / 2. When D < 0.5 this disturbance diminishes cycle by cycle. On Ts On On 1) ) (eq. 29) s2 wn 2 where Qp + wn + p @ fs mc + 1 ) se sn se + 1 p(m c(1 * D) * 0.5) V slope*pp sn + Ts V on L A sense Se is the compensation ramp slope, given by the compensation voltage over the switching period. Sn is the slope of the sensed current waveform, given by the voltage over the coil when the switch is on, times the current measurement gain, divided by the inductance. When only the current sense resistor is used, Asense = Rcs. The transfer function shows a peak at fs/2. This peaking could cause the gain to go above 0 dB again, even after we’ve done all the compensation (setting the cross−over frequency and phase margin improvement), rendering the system unstable once more. The height of the peak is determined by Qp. The lower Qp, the bigger the damping is and the lower the peak is. This damping is achieved by adding a slope to the comparator trip level. Figure 15 shows that, now even with D > 0.5, the error reduces every cycle. The necessary Slope compensation can be calculated using the following formula: Fixed fs, Ts constant On 1 s w nQ p Trip level D>0.5 Trip Level D<0.5 dV slope + nR cs Figure 13. Current Control Instability at D > 0.5, for PWM Controller not using Slope Compensation http://onsemi.com 11 V out 2L prin 2 dt (eq. 30) AND8332/D overall Bode plot needs to be drawn. The closed loop transfer function is given by Equation 33, product of Equations 16, 21 and 29. T closedLoop + T power_ccm(s) @ T comp @ (s)T h(s) (eq. 33) Stability Analysis in Discontinuous Conduction Mode (DCM) We use the values of the components as they were designed for CCM operation in the equation of the transfer function of the converter running in DCM mode. We check by drawing a Bode diagram if the stability requirements are met for the closed loop system, including the compensation network and the high frequency effect of the current mode control. Note that if one started the design procedure for a power converter in DCM mode, a similar approach can be used to check the stability in CCM mode. Figure 14. Same Converter as in Figure 7, but Now Including the High Frequency Effect of Current Control Step 1: Calculate the Duty Cycle, D, Based on the Voltage Transformation Ratio Fixed fs, Ts constant On On On Ts V out On S1 V in Slope Trip level S2 +D Ǹ V out R åD+ V in 2L prif s Ǹ 2L prif s R (eq. 34) Step 2: Frequency Response Analysis The transfer function of the power stage in DCM is given by Equation 35. Figure 15. How Slope Compensation Helps T power_dem(s) + K 1)w s zesr 1 ) ws p where dt + 1 fs where (eq. 31) K + nD and R cs + 0.36 w zesr + I PriPeak1.2 where R sl + 10 mA 2L secf sw + V out V in (eq. 35) 2 2 å fp + R loadC out 2pR loadC out (eq. 37) Plot the total closed loop frequency response (Equation 38) and check the stability requirements. 0.36 V Is the threshold voltage of the current comparator, factor 1.2 adds margin to the measurable current. This margin is required because there’s an additional voltage drop over Rsl. Since the NCP1081 integrated a slope compensation of 110 mV over 1 period, the remaining necessary slope can be obtained by adding an external Rsl resistor between the CS pin and Rcs resistor. dV slope * 110 mV R load (eq. 36) 1 1 å f zesr + R esr @ C out 2pR esr @ C out wp + V in D I PriPeak + L pri f s Ǹ T closedLoop + T power_dcm(s) @ T comp @ (s)T h(s) (eq. 38) Switch Drain−Source Voltage Considerations Special attention to the switch drain−source reverse voltage is required since in fly−back design, this voltage will be the sum of the input voltage and the weighted output voltage, as indicated in Equation 39. V DS + V in ) (eq. 32) N1 N2 V out (eq. 39) Note the forward diode drop needs to be taken into account. Also note the leakage inductance will add a voltage spike. Sufficient margin needs to be built in when choosing the switch transistor. (10 mA corresponds to the internal sawtooth current amplitude) To make sure the damping of the peak at fs / 2 in the frequency response is not an issue (gain at fs / 2 < 0), the http://onsemi.com 12 AND8332/D Snubber Design which increases progressively the duty cycle limit during the soft start time. This soft start is programmable by Css and defined by Equation 42. To avoid destruction of the switching transistor due to the voltage spikes originating from the leakage inductance, these transient spikes at the drain of the power switch need to be reduced. To size the snubber, measure the ringing frequency and calculate Rsn and Csn. R sn1 + 2pf ringL leak C sn1 + T softstart[ms] + 0.23C ss[nF] VDDL and VDDH Cvvdl and Cvddh are noise decoupling capacitors (20%) with low ESR (< 0.1 W). Cvddl may range from 330 to 470 nF. Cvddh may range from 1 to 2.2 mF. For application using the auxiliary bias winding to supply the VDDH regulator, the designer has to make sure that the bias winding does not force VDDH above 16 V for the maximum load condition. Use 50 W for Rbw as initial value. (eq. 40) 1 (eq. 41) 2pf ringR sn1 (eq. 42) The snubber design for the diode at the secondary side of the transformer is handled in the same way. To measure the oscillation frequency in a safe way, use a low Vin and do not apply any load to the converter to make sure that the peak voltage is not exceeding the switching transistor VDS rating. Converter Efficiency The overall efficiency of the flyback power converter is given by Equation 43. Soft Start To eliminate possible voltage overshoots on the output during start up, the NCP1081 provides a soft start function h+ P out P out ) P MOSdynamic ) P MOSstatic ) P diode ) P esr ) P MagConductive ) P core ) P NCP108x Static Power Switch Losses Each of the power losses in Equation 43 are calculated in following sections. Static losses are the conductive losses of the power switch and calculated using the Rdson resistance coming from the data sheet and the RMS current. Dynamic Power Switch Losses Dynamic switch losses are created during the toggling of the switch. Parasitic capacitances in the switch are charged and discharged. P MOSstatic + ǒR DS(on) ) R CSǓ @ I rms_pri 2 @ D ) 2 (eq. 44) Secondary Diode Losses ) f s @ Q gtot @ V gatedrive where V dsmax + 1.15 @ ǒ V in ) The secondary diode has a forward voltage drop, affecting the overall efficiency. Ǔ ǒVout ) VdiodeǓ 2 P diode + (eq. 45) Q gd @ R gatedrive V gatedrive @ V GSth , the switch−on time P out V out @ V diode (eq. 48) Capacitor Losses One of the biggest loss contributors is the parasitic equivalent series resistor of the output smoothing and the input bulk capacitors. the maximum drain−source voltage. t sw + (eq. 47) With RDS(on) the on resistance of the switch, from the data sheet and Rcs is the calculated current sense resistance. P MOSdynamic + V dsmax @ I peak_pri @ f s @ t sw C swout @ V dsmax @ f s (eq. 43) (eq. 46) P esr + R esr_cout @ I 2rms_sec ) R esr_cpd @ I 2 VGSth is the gate to source threshold voltage from the data sheet Qgd is the gate to drain Miller charge from the data sheet Qgtot is the total gate charge from the switch data sheet Ipeakpri is the peak current at the primary Vgatedrive is the gate drive voltage of the NCP1081, or 9 V Vdiode is the forward voltage drop of the diode at secondary side Cswout is the switching transistor output capacitance rms_pri (eq. 49) It is important to use low ESR capacitors. Conductive Losses in Magnetics Conductive losses are those originating from the DC and AC resistance of the transformer wire. DC resistance of primary and secondary windings are listed by the transformer manufacturer. When the switching frequency http://onsemi.com 13 AND8332/D increases, additional phenomena such as skin effect and proximity effect increase the losses even further. P MagConductive + R dc_pri @ I2 rms_pri ) R dc_sec @ I2 With rms_sec (eq. 50) P PortDriver(mW) + I PortDriver(mA) V portP(V) P PWM(mW) + I PWM(mA) (eq. 56) (eq. 57) R on_PassSwitch V portP(V) (eq. 58) if the auxiliary winding of transformer is not used, or P PWM(mW) + I PWM(mA) V DDH(V) (eq. 59) if VDDH is supplied by the auxiliary winding of transformer NCP1081 Losses The internal junction temperature can be evaluated. First calculate the current consumed on the VPORTP pin in Power Mode: ) I PortDriver (mA) ) I PWM (mA) V portP(V) ) I PortDriver 2(mA) To make calculations simpler, we discard the AC resistance of the copper wire. But note that the AC losses become substantial with high switching frequencies. Core losses originate from the energy that is dissipated in the core of the transformer and can be found from graphs for the specific core material used and the physical dimensions of the core. I VportP (mA) + I Quiescent (mA) P Quiescent(mW) + I Quiescent(mA) T J(degC) + T ambient(degC) ) P DissTotal(mW) R th(Wń deg C) (eq. 51) (eq. 60) 1000 With Rth the junction to ambient thermal resistance With I Quiescent (mA) + 1.4 (eq. 52) Secondary Diode Maximum Rating A rule of thumb for the maximum reverse voltage of the secondary rectifying diode is Core Losses V reverse + V in_max * N s Np (eq. 61) The maximum current through the diode is given by Equation 9. Design Example 1: 30 W Single Output 12 V Supply A Microsoft Excel® file (NCP108X DESIGN TOOL FLYBACK CCM.xls) with calculation sheets is provided by ON Semiconductor, with the presented expressions incorporated to design a stable and reliable flyback converter. In Figure 17 all the input data needed for the design is shown. As a result, the output calculated data is shown in Figure 18. The frequency and phase response of the system as well as the poles and zeroes are calculated by the Excel VBA macros and shown in logarithmic charts for the power stage, compensation and close loop networks in Figure 20. The Excel VBA script calculates also the efficiency for various output power, gives the final summary of all the designed components, according to a certain scematics(shown in Figure 1). In addition there is a convenient tool to calculate the output divider resistor values, when the output voltage and the reference voltage of the shunt feedback regulator are given. Figure 16. Core Losses 1 1 ƪ385 ƫ ) 2300 I PortDriver(mA) + 0.1 ) I PassSwitch (mA) (eq. 53) I PWM(mA) + 1.175 ) ƪ f s(kHz) 250 0.725 ) 4.35 C gate(nF) 2 ƫ (eq. 54) With Cgate the equivalent input capacitance of the external switching MOSFET Then calculate the internal power dissipation. P NCP108x(mW) + P Quiescent(mW) ) P PortDriver(mW) ) P PWM(mW) (eq. 55) http://onsemi.com 14 AND8332/D Figure 18. Output Data Calculated by the Flyback Design Excel Calculation Sheet − Values of the Detection Signature Resistors and the Maximum Power Estimated Efficiency Figure 19. Output Data Calculated by the Flyback Design Excel Calculation Sheet − Parameter Extraction of the External Components Values According to Figure 1 Figure 17. Input Data for the Flyback Design Excel Calculation Sheet http://onsemi.com 15 AND8332/D The output of the Scilab script summarizes the design parameters and the closest standard values of the calculated component values for the feedback loop. The Bode plot of the converter without compensator network and with compensator network is plotted in Figure 21. Magnitude vs Frequency, (dB) 60 40 Fp Fcz Magnitude (dB) 20 0 Fzrhp Fcross Fcp −20 −40 −60 −80 −100 100 1000 10000 100000 1000000 Frequency (Hz) T_power_stage T_compensation T_closed_loop Phase vs Frequency, (°) 0 −50 −100 Phase (°) −150 −200 −250 −300 −350 −400 100 1000 T_power_stage 10000 Frequency (Hz) 100000 T_compensation Figure 21. Gain and Phase Plot of the Compensated Converter 1000000 T_closed_loop Figure 20. Output Data Calculated by the Flyback Design Excel Calculation Sheet − Frequency and Phase Response of the Designed Flyback Converter Note: If Scilab or Excel software is not available, using asymptotic approximation to generate a Bode plot and computing the values manually will lead to similar results. Company or Product Inquiries Design Example 2: 20W Single Output 3.3V Supply For more information about ON Semiconductor’s Power over Ethernet products visit our Web site at http://www.onsemi.com Scilab scripts are also provided to aid the design calculation. Scilab is an open−source numeric computation program that is available free of charge at www.scilab.org. The input data is shown in Table 6. Table 6. DESIGN PARAMETERS Parameter Value Vin 36 V (minimal PD input voltage) Vout 3.3 V Lprim 42 mH, according to Coilcraft POE300F−33L data sheet N Pout Vripple fs 0.09, according to Coilcraft POE300F−33L data sheet 20W 33 mV 250 kHz http://onsemi.com 16 AND8332/D Microsoft Excel is a registered trademark of Microsoft Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 17 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative AND8332/D

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