POWERINT DPA426

DPA422-426
DPA-Switch Family
®
Highly Integrated DC-DC Converter ICs for
Power over Ethernet & Telecom Applications
Product Highlights
Highly Integrated Solution
• Eliminates up to 50 external components–saves space, cost
• Integrates 220 V high frequency MOSFET, PWM control
• Lower cost plastic DIP surface mount (G package) and
through-hole (P package) options for designs ≤35 W
• Thermally efficient TO-263-7C (R package) option for high
power applications
Superior Performance and Flexibility
• Eliminates all external current sensing circuitry
• Built-in auto-restart for output overload/open loop protection
• Pin selectable 300/400 kHz fixed frequency
• Wide input (line) voltage range: 16-75 VDC
• Externally programmable current limit
• Source connected tab reduces EMI
• Line under-voltage (UV) detection: meets ETSI standards
• Line overvoltage (OV) shutdown protection
• UV/OV limits gate drive voltage for synchronous rectification
• Fully integrated soft-start for minimum stress/overshoot
• Supports forward or flyback topology
• Cycle skipping: regulation to zero load without pre-load
• Hysteretic thermal shutdown for automatic fault recovery
• RoHS compliant P and G package options
®
EcoSmart – Energy Efficient
• Extremely low consumption at no load
• Cycle skipping at light load for high standby efficiency
Applications
• PoE applications, VoIP phones, WLAN, security cameras
• Telco central office equipment: xDSL, ISDN, PABX
• Distributed power architectures (24 V/48 V bus)
• Industrial controls
VO
SENSE
CIRCUIT
DPA-Switch
VIN
D
L
CONTROL
RESET/
CLAMP
CIRCUIT
S
X
C
F
PI-2770-032002
Figure 1.
Typical Forward Converter Application.
Output Power Table
36-75 VDC Input Range (Forward)2
Total Device
Dissipation3
0.5 W
1W
2.5 W
4W
6W
Max
Power
Output1
DPA4227
7.5 W
10 W
-
-
-
10 W
DPA423
12 W
16 W
-
-
-
18 W
DPA424
16 W
23 W
35 W
-
-
35 W
DPA425
23 W
32 W
50 W
62 W
-
70 W
DPA4265
25 W
35 W
55 W
70 W
83 W
100 W
Product4
36-75 VDC Input Range (Flyback)2
Total Device
Dissipation3
0.5 W
0.75 W
1W
1.5 W
Max
Power
Output1
6.5 W
9.0 W
-
-
9.0 W
Product4
DPA422
Description
DPA423
9W
13 W
-
-
13 W
The DPA-Switch IC family is a highly integrated solution for
DC-DC conversion applications with 16-75 VDC input.
DPA424
10 W
14.5 W
18 W
24 W
26 W
DPA425
-6
-6
-6
25.5 W
52 W
DPA-Switch uses the same proven topology as TOPSwitch®,
cost effectively integrating a power MOSFET, PWM control, fault
protection and other control circuitry onto a single CMOS chip.
High performance features are enabled with three user
configurable pins. Hysteretic thermal shutdown is also provided.
In addition, all critical parameters (i.e. current limit, frequency,
PWM gain) have tight temperature and absolute tolerance, to
simplify design and reduce system cost.
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Table 1. Output Power Table.
Notes:
1. Maximum output power is limited by device internal current limit.
2. See Applications Considerations section for complete description of assumptions
and for output powers with other input voltage ranges.
3. For device dissipation of 1.5 W or below, use P or G packages. Device
dissipation
above 1.5 W is possible with R package.
4. Packages: P: DIP-8, G: SMD-8, R: TO-263-7C. For lead-free package options,
see Part Ordering Information.
5. Available in R package only.
6. Due to higher switching losses, the DPA425 may not deliver additional power
compared to a smaller device.
7. Available in P and G package only.
December 2007
DPA422-426
Section List
Functional Block Diagram ....................................................................................................................................... 3
Pin Functional Description ...................................................................................................................................... 3
DPA-Switch Family Functional Description ............................................................................................................ 4
CONTROL (C) Pin Operation .................................................................................................................................... 4
Oscillator and Switching Frequency.......................................................................................................................... 5
Pulse Width Modulator & Maximum Duty Cycle ........................................................................................................ 5
Minimum Duty Cycle and Cycle Skipping ................................................................................................................. 6
Error Amplifier .......................................................................................................................................................... 6
On-chip Current Limit with External Programmability ................................................................................................ 6
Line Under-Voltage Detection (UV)............................................................................................................................ 6
Line Overvoltage Shutdown (OV) .............................................................................................................................. 6
Line Feed-Forward with DCMAX Reduction ................................................................................................................ 6
Remote ON/OFF ...................................................................................................................................................... 7
Synchronization........................................................................................................................................................ 7
Soft-Start ................................................................................................................................................................. 8
Shutdown/Auto-Restart ........................................................................................................................................... 8
Hysteretic Over-Temperature Protection ................................................................................................................... 8
Bandgap Reference ................................................................................................................................................. 8
High-Voltage Bias Current Source ............................................................................................................................ 8
Using Feature Pins ..................................................................................................................................................... 8
FREQUENCY (F) Pin Operation ................................................................................................................................ 8
LINE-SENSE (L) Pin Operation ................................................................................................................................. 9
EXTERNAL CURRENT LIMIT (X) Pin Operation ......................................................................................................... 9
Typical Uses of FREQUENCY (F) Pin ...................................................................................................................... 11
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins ....................................................... 11
Application Examples .............................................................................................................................................. 14
Key Application Considerations .............................................................................................................................. 16
DPA-Switch Design Considerations ........................................................................................................................ 16
DPA-Switch Layout Considerations ........................................................................................................................ 18
Quick Design Checklist .......................................................................................................................................... 19
Design Tools .......................................................................................................................................................... 20
Product Specifications and Test Conditions .......................................................................................................... 21
Typical Performance Characteristics .................................................................................................................. 27
Part Ordering Information ....................................................................................................................................... 30
Package Outlines .................................................................................................................................................... 31
2
Rev. S 12/07
www.powerint.com
DPA422-426
VC
0
DRAIN (D)
CONTROL (C)
ZC
INTERNAL
SUPPLY
1
SHUNT REGULATOR/
ERROR AMPLIFIER
+
SOFT START
5.8 V
4.8 V
-
-
5.8 V
+
INTERNAL UV
COMPARATOR
IFB
VI (LIMIT)
CURRENT
LIMIT
ADJUST
SOFT
START
+
VBG + VT
SHUTDOWN/
AUTO-RESTART
EXTERNAL
CURRENT LIMIT (X)
1V
VBG
OV/UV
LINE
SENSE
DCMAX
CONTROLLED
TURN-ON
GATE DRIVER
STOP SOFTSTART
DMAX
DCMAX
CLOCK
300/400 kHz
FREQUENCY (F)
CURRENT LIMIT
COMPARATOR
HYSTERETIC
THERMAL
SHUTDOWN
STOP LOGIC
LINE-SENSE (L)
-
÷8
ON/OFF
SAW
+
OSCILLATOR
S
Q
LEADING
EDGE
BLANKING
R
PWM
COMPARATOR
RE
CYCLE
SKIPPING
SOURCE (S)
PI-2760-070501
Figure 2.
Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
High voltage power MOSFET drain output. The internal startup
bias current is drawn from this pin through a switched highvoltage current source. Internal current limit sense point for
drain current.
SOURCE (S) Pin:
Output MOSFET source connection for the power return.
Primary side control circuit common and reference point.
Tab internally connected
to SOURCE pin
(See layout considerations)
CONTROL (C) Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/
compensation capacitor.
R Package
(TO-263-7C)
LINE-SENSE (L) Pin:
Input pin for overvoltage (OV), under-voltage (UV) lock out, line
feed-forward with the maximum duty cycle (DCMAX) reduction,
remote ON/OFF and synchronization. A connection to
SOURCE pin disables all functions on this pin.
EXTERNAL CURRENT LIMIT (X) Pin:
Input pin for external current limit adjustment and remote
ON/OFF. A connection to SOURCE pin disables all functions
on this pin.
FREQUENCY (F) Pin:
Input pin for selecting switching frequency: 400 kHz if
connected to SOURCE pin and 300 kHz if connected to
CONTROL pin.
123 4 5
CLX S F
P Package (DIP-8)
G Package (SMD-8)
C
1
8
S
L
2
7
S
X
3
6
D
F
4
5
S
7
D
PI-4030-110507
Figure 2.
Pin Configuration (Top View).
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Rev. S 12/07
DPA422-426
DPA-Switch Family Functional
Description
In addition to the standard TOPSwitch features, such as the
high-voltage start-up, the cycle-by-cycle current limiting, loop
compensation circuitry, auto-restart and thermal shutdown,
DPA-Switch also offers many advanced features that reduce
system cost and increase power supply performance and
design flexibility. Following is a summary of the advanced
features:
1. A fully integrated 5 ms soft-start limits peak currents and
voltages during start-up and reduces or eliminates output
overshoot in most applications.
2. A 75% maximum duty cycle (DCMAX) together with the line
feed-forward with DCMAX reduction feature makes
DPA-Switch well suited for both flyback and forward
topologies.
3. High switching frequency (400 kHz/300 kHz, pin selectable)
allows the use of smaller size transformers and offers high
bandwidth for power supply control loop.
4. Cycle skipping operation at light load minimizes standby
power consumption (typically <10 mA input current).
5. Line under-voltage ensures glitch free operations at both
power-up and power-down and is tightly toleranced over
process and temperature to meet system level requirements
common in DC to DC converters (e.g. ETSI).
6. Line overvoltage protects DPA-Switch against excessive
input voltage and line surge.
7. External current limit adjustment allows the setting of the
current limit externally to a lower level near the operating
peak current and, if desired, further adjusts the level gradually as line voltage rises. This makes possible an ideal
implementation of overload power limiting.
8. Synchronization function allows the synchronization of
DPA-Switch operation to an external lower frequency.
9. Remote ON/OFF feature permits DPA-Switch based power
supplies to be easily switched on/off using logic signals.
Maximum input current consumption is 2 mA in remote OFF.
10. Hysteretic over-temperature shutdown provides automatic
recovery from thermal fault.
11. Tight absolute tolerances and small temperature variations
on switching frequency, current limit, and undervoltage lock
out threshold (UV).
Three pins, LINE-SENSE (L), EXTERNAL CURRENT LIMIT (X)
and FREQUENCY (F), are used to implement all the pin controllable features. A resistor from the LINE-SENSE pin to DC
input bus implements line UV, line OV and line feed-forward with
DCMAX reduction. A resistor from the EXTERNAL CURRENT
LIMIT pin to the SOURCE pin sets current limit externally. In
Auto-restart
ICD1
IB
75
Duty Cycle (%)
DPA-Switch is an integrated switched mode power supply chip
that converts a current at the control input to a duty cycle at the
open drain output of a high voltage power MOSFET. During
normal operation the duty cycle of the power MOSFET
decreases linearly with increasing CONTROL pin current as
shown in Figure 4. A patented high-voltage CMOS technology
allows both the high-voltage power MOSFET and all the low
voltage control circuitry to be cost effectively integrated onto a
single monolithic chip.
Slope = PWM Gain
42
I <I
L
L(DC)
4
IC (SKIP)
IL = 115 μA
IC (mA)
PI-2761-112102
Figure 4.
Relationship of Duty Cycle to CONTROL Pin Current.
addition, remote ON/OFF may be implemented through either
the LINE-SENSE pin or the EXTERNAL CURRENT LIMIT pin
depending on the polarity of the logic signal available as well as
other system specific considerations. Shorting both the LINESENSE and the EXTERNAL CURRENT LIMIT pins to the
SOURCE pin disables line OV, line UV, line feed-forward with
DCMAX reduction, external current limit, remote ON/OFF and
synchronization. The FREQUENCY pin sets the switching
frequency to 400 kHz if connected to the SOURCE pin, or
300 kHz if connected to the CONTROL pin. This pin should not
be left open. Please refer to “Using Feature Pins” section for
detailed information regarding the proper use of those pins.
CONTROL (C) Pin Operation
The CONTROL pin is a low impedance node that is capable of
receiving a combined supply and feedback current. During
normal operation, a shunt regulator is used to separate the
feedback signal from the supply current. CONTROL pin voltage
VC is the supply voltage for the control circuitry including the
MOSFET gate driver. An external bypass capacitor closely
connected between the CONTROL and SOURCE pins is
required to supply the instantaneous gate drive current. The
total amount of capacitance connected to this pin also sets the
auto-restart timing as well as control loop compensation.
When the DC input voltage is applied to the DRAIN pin during
start-up, the MOSFET is initially off, and the CONTROL pin
capacitor is charged through the switched high voltage current
source connected internally between the DRAIN and
CONTROL pins. When the CONTROL pin voltage VC reaches
approximately 5.8 V, the control circuitry is activated and the
soft-start begins. The soft-start circuit gradually increases the
duty cycle of the MOSFET from zero to the maximum value
over approximately 5 ms. The high voltage current source is
turned off at the end of the soft-start. If no external feedback/
supply current is fed into the CONTROL pin by the end of the
soft-start, the CONTROL pin will start discharging in response
to the supply current drawn by the control circuitry and the gate
current of the switching MOSFET driver. If the power supply is
designed properly, and no fault condition such as open loop or
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Rev. S 12/07
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DPA422-426
overloaded output exists, the feedback loop will close, providing
external CONTROL pin current, before the CONTROL pin
voltage has had a chance to discharge to the lower threshold
voltage of approximately 4.8 V (internal supply undervoltage
lockout threshold). When the externally fed current charges the
CONTROL pin to the shunt regulator voltage of 5.8 V, current in
excess of the consumption of the chip is shunted to SOURCE
through resistor RE as shown in Figure 2. This current flowing
through RE controls the duty cycle of the power MOSFET to
provide closed loop regulation. The shunt regulator has a finite
low output impedance ZC that sets the gain of the error amplifier
when used in a primary feedback configuration. The dynamic
impedance ZC of the CONTROL pin together with the external
CONTROL pin capacitance sets the dominant pole for the
control loop.
Oscillator and Switching Frequency
The internal oscillator linearly charges and discharges an
internal capacitance between two voltage levels to create a
sawtooth waveform for the pulse width modulator. The
oscillator sets both the pulse width modulator latch and the
current limit latch at the beginning of each cycle.
When a fault condition such as an open loop or overloaded
output prevents the flow of an external current into the
CONTROL pin, the capacitor on the CONTROL pin discharges
towards 4.8 V. At 4.8 V auto-restart is activated which turns the
output MOSFET off and puts the control circuitry in a low
current standby mode. The high-voltage current source turns
on and charges the external capacitance again. A hysteretic
internal supply under-voltage comparator keeps VC within a
window of typically 4.8 V to 5.8 V by turning the high-voltage
current source on and off as shown in Figure 5. The autorestart circuit has a divide-by-8 counter that prevents the output
MOSFET from turning on again until eight discharge/charge
cycles have elapsed. This is accomplished by enabling the
output MOSFET only when the divide-by-8 counter reaches full
count (S7). The counter effectively limits DPA-Switch power
dissipation as well as the maximum power delivered to the
power supply output by reducing the auto-restart duty cycle to
typically 4%. Auto-restart mode continues until output voltage
regulation is again achieved through closure of the feedback
loop.
Pulse Width Modulator and Maximum Duty Cycle
The pulse width modulator implements voltage mode control by
driving the output MOSFET with a duty cycle inversely
proportional to the current into the CONTROL pin that is in
excess of the internal supply current of the chip (see Figure 4).
The excess current is the feedback error signal that appears
across RE (see Figure 2). This signal is filtered by an RC network
with a typical corner frequency of 30 kHz to reduce the effect of
switching noise in the chip supply current generated by the
MOSFET gate driver. The filtered error signal is compared with
the internal oscillator sawtooth waveform to generate the duty
cycle waveform. As the control current increases, the duty cycle
decreases. A clock signal from the oscillator sets a latch that
turns on the output MOSFET. The pulse width modulator resets
the latch, turning off the output MOSFET. Note that a minimum
current must be driven into the CONTROL pin before the duty
cycle begins to change.
The nominal switching frequency of 400 kHz was chosen to
minimize the transformer size and to allow faster power supply
loop response. The FREQUENCY pin, when shorted to the
CONTROL pin, lowers the switching frequency to 300 kHz,
which may be preferable in some applications such as those
employing secondary synchronous rectification. Otherwise, the
FREQUENCY pin should be connected to the SOURCE pin for
the default 400 kHz.
~
~
~
~
VUV
~
~
VLINE
0V
S6
S7
S0
S1
S2
S6
S0
S7
S1
S2
~
~
S2
S6
S7
S7
5.8 V
4.8 V
~
~
~
~
0V
S1
~
~
S0
~
~
S7
VC
~
~
VDRAIN
0V
VOUT
1
2
~
~
~
~
~
~
0V
3
2
Note: S0 through S7 are the output states of the auto-restart counter
Figure 5.
4
PI-3867-050602
Typical Waveforms for (1) Power Up, (2) Normal Operation, (3) Auto-restart and (4) Power Down.
5
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Rev. S 12/07
DPA422-426
The maximum duty cycle, DCMAX is set at a default maximum
value of 75% (typical). However, by connecting the LINE-SENSE
to the DC input bus through a resistor with appropriate value,
the maximum duty cycle can be made to decrease from 75% to
33% (typical) as shown in Figure 7 when input line voltage
increases (see Line Feed-Forward with DCMAX Reduction).
Minimum Duty Cycle and Cycle Skipping
To maintain power supply output regulation, the pulse width
modulator reduces duty cycle as the load at the power supply
output decreases. This reduction in duty cycle is proportional to
the current flowing into the CONTROL pin. As the CONTROL
pin current increases, the duty cycle reduces linearly towards a
minimum value specified as minimum duty cycle, DCMIN. After
reaching DCMIN, if CONTROL pin current is increased further by
approximately 2 mA, the pulse width modulator will force the
duty cycle from DCMIN to zero in a discrete step (refer to Figure
4). This feature allows a power supply to operate in a cycle
skipping mode when the load consumes less power than the
DPA-Switch delivers at minimum duty cycle, DCMIN. No
additional control is needed for the transition between normal
operation and cycle skipping. As the load increases or
decreases, the power supply automatically switches between
normal and cycle skipping mode as necessary.
Cycle skipping may be avoided, if so desired, by connecting a
minimum load at the power supply output such that the duty
cycle remains at a level higher than DCMIN at all times.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifier in primary side feedback applications. The shunt
regulator voltage is accurately derived from a temperaturecompensated bandgap reference. The gain of the error amplifier
is set by the CONTROL pin dynamic impedance. The
CONTROL pin clamps external circuit signals to the VC voltage
level. The CONTROL pin current in excess of the supply current
is separated by the shunt regulator and flows through RE as a
voltage error signal.
On-chip Current Limit with External Programmability
The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET on-state drain
to source voltage, VDS(ON) with a threshold voltage. At the current
limit, VDS(ON) exceeds the threshold voltage and the MOSFET is
turned off until the start of the next clock cycle. The current limit
comparator threshold voltage is temperature compensated to
minimize the variation of the current limit due to temperature
related changes in RDS(ON) of the output MOSFET. The default
current limit of DPA-Switch is preset internally. However, with a
resistor connected between EXTERNAL CURRENT LIMIT pin
and SOURCE pin, the current limit can be programmed
externally to a lower level between 25% and 100% of the default
current limit. Please refer to the graphs in the Typical
Performance Characteristics section for the selection of the
resistor value. By setting current limit low, a larger DPA-Switch
than necessary for the power required can be used to take
advantage of the lower RDS(ON) for higher efficiency/smaller heat
sinking requirements. With a second resistor connected
between the EXTERNAL CURRENT LIMIT pin and the DC input
bus, the current limit is reduced with increasing line voltage,
allowing a true power limiting operation against line variation to
be implemented in a flyback configuration.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that, if a
power supply is designed properly, current spikes caused by
primary-side capacitance and secondary-side rectifier reverse
recovery time should not cause premature termination of the
switching pulse.
The current limit after the leading edge blanking time is as
shown in Figure 31. To avoid triggering the current limit in
normal operation, the drain current waveform should stay within
the envelope shown.
Line Under-Voltage Detection (UV)
At power up, UV keeps DPA-Switch off until the input line
voltage reaches the under voltage upper threshold. At power
down, UV holds DPA-Switch on until the input voltage falls
below the under voltage lower threshold. A single resistor
connected from the LINE-SENSE pin to the DC input bus sets
UV upper and lower thresholds. To avoid false triggering by
noise, a hysteresis is implemented which sets the UV lower
threshold typically at 94% of the UV upper threshold. If the UV
lower threshold is reached during operation without the power
supply losing regulation and the condition stays longer than
10 μs (typical), the device will turn off and stay off until the UV
upper threshold has been reached again. Then, a soft-start will
be initiated the next time CONTROL pin voltage reaches 5.8.V. If
the power supply loses regulation before reaching the UV lower
threshold, the device will enter auto-restart. At the end of each
auto-restart cycle (S7), the UV comparator is enabled. If the UV
upper threshold is not exceeded, the MOSFET will be disabled
during the next cycle (see Figure 5). The UV feature can be
disabled independent of OV feature.
Line Overvoltage Shutdown (OV)
The same resistor used for UV also sets an overvoltage
threshold which, once exceeded, will force the DPA-Switch
output into the off-state within one switching cycle. The ratio of
OV and UV thresholds is preset at 2.7 as can be seen in
Figure 7. When the MOSFET is off, the input voltage surge
capability is increased to the voltage rating of the MOSFET
(220 V), due to the absence of the reflected voltage and leakage
spikes on the drain. A small amount of hysteresis is provided on
the OV threshold to prevent noise triggering. The OV feature
can be disabled independent of the UV feature as shown in
Figure 13.
Line Feed-Forward with DCMAX Reduction
The same resistor used for UV and OV also implements line
voltage feed-forward that minimizes output line ripple and
reduces power supply output sensitivity to line transients. This
feed-forward operation is illustrated in Figure 4 by the different
values of IL. Note that for the same CONTROL pin current,
higher line voltage results in smaller operating duty cycle. As an
added feature, the maximum duty cycle DCMAX is also reduced
from 75% (typical) at a voltage slightly higher than the UV
threshold to 33% (typical) at the OV threshold
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Rev. S 12/07
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DPA422-426
(see Figures 4, 7). Limiting DCMAX at higher line voltages helps
prevent transformer saturation due to large load transients in
forward converter applications. DCMAX of 33% at the OV
threshold was chosen to ensure that the power capability of the
DPA-Switch is not restricted by this feature under normal
operation.
Remote ON/OFF
Remote ON/OFF control describes operation where the IC is
turned on or off for long periods as opposed to the cycle-bycycle on/off control, which is described in the Synchronization
section below.
DPA-Switch can be turned on or off by controlling the current
into the LINE-SENSE pin or out from the EXTERNAL CURRENT
LIMIT pin (see Figure 7). This allows easy implementation of
remote ON/OFF control of DPA-Switch in several different ways.
A transistor or an optocoupler output connected between the
EXTERNAL CURRENT LIMIT pin and the SOURCE pin
implements this function with “active-on” (Figures 17, 19 and 21)
while a transistor or an optocoupler output connected between
the LINE-SENSE pin and the CONTROL pin implements the
function with “active-off” (Figures 18, 20 and 22).
When a signal is received at the LINE-SENSE pin or the
EXTERNAL CURRENT LIMIT pin to disable the output through
any of the pin functions such as OV, UV and remote ON/OFF,
DPA-Switch always completes its current switching cycle before
the output is forced off. The internal oscillator is stopped at the
end of the current cycle and stays there as long as the disable
signal exists. When the signal at the above pins changes state
from disable to enable, the internal oscillator starts the next
switching cycle.
The remote ON/OFF feature can be used as a standby or power
switch to turn off the DPA-Switch and keep it in a very low
power consumption state for indefinitely long periods. If the
DPA-Switch is held in remote-off state for longer than 10 μs
(typical), the CONTROL pin goes into the hysteretic mode of
operation. In this mode, the CONTROL pin goes through
alternate charge and discharge cycles between 4.8 V and 5.8 V
(see CONTROL Pin Operation section above) and the IC runs
entirely off the high voltage DC input, but with very low power
consumption (30 mW typical at 48 V with LINE-SENSE and
EXTERNAL CURRENT LIMIT pins open). When the DPA-Switch
is remotely turned on after entering this mode, it will initiate a
normal start-up sequence with soft-start the next time the
CONTROL pin reaches 5.8 V. In the worst case, the delay from
remote on to start-up can be equal to the full discharge/charge
cycle time of the CONTROL pin, which is approximately 36 ms
for a 22 μF CONTROL pin capacitor. This reducedconsumption remote-off mode can eliminate expensive and
unreliable in-line mechanical switches. It also allows for
microprocessor-controlled turn-on and turn-off sequences that
may be required in certain applications.
Synchronization
In addition to sensing incoming current for OV, UV and remote
ON/OFF, the LINE-SENSE pin also monitors its pin voltage
through a 1 V threshold comparator. A pin voltage below 1 V
turns on DPA-Switch. When the voltage at LINE-SENSE pin
rises beyond 1 V to disable the output, DPA-Switch completes
its current switching cycle before the output is forced off (similar
to remote ON/OFF operation). The internal oscillator is stopped
at the end of the current cycle awaiting the LINE-SENSE pin
voltage to go low to start the next cycle. This allows the use of
the 1 V threshold to synchronize DPA-Switch to an external
signal with a frequency lower than its internal switching
frequency. A transistor or an optocoupler output connected
between the LINE-SENSE pin and the SOURCE pin implements
this function (see Figure 24). Please refer to Figure 6 for the
timing waveforms of synchronization operation.
fSYNC ≥ 128 kHz; tOFF ≤ 7.7 μs; 120 ns ≤ tON ≤ 2250 ns for fOSC = 400 kHz
≤ 3080 ns for fOSC = 300 kHz
Oscillator
(SAW)
DMAX
VL
2V
Time
0V
tON
tOFF
ON
OFF
SYNC
PI-2762-070501
Figure 6.
Synchronization Timing Diagram.
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Rev. S 12/07
DPA422-426
In order to be recognized as a synchronization pulse, the
LINE-SENSE pin needs to stay low (on-time) for at least
120 ns but no more than 2250 ns for 400 kHz (or 3080 ns for
300 kHz) internal switching frequency. In addition, the off-time
must be kept below 7.7 μs, which is a limitation set by the
lowest synchronization frequency of 128 kHz allowed by the
chip. The effective DCMAX for synchronization operation can be
calculated as 0.75 × fSYNC/fOSC. An off-time longer than
7.7 μs may force the CONTROL pin to go into the hysteretic
mode and initiate a soft-start cycle at next turn-on.
Soft-Start
Two on-chip soft-start functions are activated at start-up with a
duration of 5 ms (typical). Maximum duty cycle starts from 0%
and linearly increases to the default maximum of 75% at the
end of the 5 ms duration and the current limit starts from about
85% and linearly increases to 100% at the end of the
5 ms duration. In addition to start-up, soft-start is also activated
at each restart attempt during auto-restart and when restarting
after being in hysteretic regulation of CONTROL pin voltage (VC),
due to remote off or thermal shutdown conditions. This
effectively minimizes current and voltage stresses on the output
MOSFET, the clamp circuit and the output rectifier during startup. This feature also helps minimize output overshoot and
prevents saturation of the transformer during start-up.
Shutdown/Auto-Restart
To minimize DPA-Switch power dissipation under fault
conditions, the shutdown/auto-restart circuit turns the power
supply on and off at an auto-restart duty cycle of typically 4% if
an out of regulation condition persists. Loss of regulation
interrupts the external current into the CONTROL pin. VC
regulation changes from shunt mode to the hysteretic autorestart mode as described in CONTROL pin operation section.
When the fault condition is removed, the power supply output
becomes regulated, VC regulation returns to shunt mode, and
normal operation of the power supply resumes.
Hysteretic Over-Temperature Protection
Over temperature protection is provided by a precision analog
circuit that turns the output MOSFET off when the junction
temperature exceeds the thermal shutdown temperature
(137 °C typical). When the junction temperature cools to below
the hysteretic temperature (110 °C typical), normal operation
resumes providing automatic recovery. VC is regulated in
hysteretic mode and a 4.8 V to 5.8 V (typical) sawtooth
waveform is present on the CONTROL pin while in thermal
shutdown.
Bandgap Reference
All critical DPA-Switch internal voltages are derived from a
temperature-compensated bandgap reference. This reference
is also used to generate a temperature-compensated current
reference that is trimmed to accurately set the switching
frequency, current limit, and the line OV/UV thresholds.
DPA-Switch has improved circuitry to maintain all of the above
critical parameters within very tight absolute and temperature
tolerances.
High-Voltage Bias Current Source
This current source biases DPA-Switch from the DRAIN pin and
charges the CONTROL pin external capacitance during start-up
or hysteretic operation. Hysteretic operation occurs during
auto-restart, remote off and over-temperature shutdown. In this
mode of operation, the current source is switched on and off
with an effective duty cycle of approximately 20%. This duty
cycle is determined by the ratio of CONTROL pin charge (IC(CH))
and discharge currents (ICD1 and ICD2). This current source is
turned off during normal operation when the output MOSFET is
switching. The effect of the current source switching may be
seen on the DRAIN voltage waveform as small disturbances,
which is normal.
Using Feature Pins
FREQUENCY (F) Pin Operation
The FREQUENCY pin is a digital input pin. Shorting the
FREQUENCY pin to SOURCE pin selects the nominal switching
frequency of 400 kHz (Figure 9) which is suited for most
applications. For other applications that may benefit from lower
switching frequency, a 300 kHz switching frequency can be
selected by shorting the FREQUENCY pin to the CONTROL pin
(Figure 10). This pin should not be left open.
Line-Sense and External Current Limit Pin Table*
Figure Number ➧
11
Three Terminal Operation
✓
12
13
✓
Undervoltage
✓
Overvoltage
✓
Line Feed-Forward (DCMAX)
✓
14
15
17
18
19
20
✓
21
22
23
✓
✓
✓
✓
✓
✓
✓
✓
✓
24
✓
Overload Power Limiting
External Current Limit
16
✓
Remote ON/OFF
✓
✓
✓
✓
✓
✓
✓
✓
✓
Synchronization
✓
✓
✓
*This table is only a partial list of many LINE-SENSE and EXTERNAL CURRENT LIMIT Pin Configurations that are possible.
Table 2.
Typical LINE-SENSE and EXTERNAL CURRENT LIMIT Pin Configurations.
8
Rev. S 12/07
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DPA422-426
LINE-SENSE (L) Pin Operation
When current is fed into the LINE-SENSE pin, it works as a
voltage source of approximately 2.6 V up to a maximum current
of +240 μA (typical). At +240 μA, this pin turns into a constant
current sink. Refer to Figure 8. In addition, a comparator with a
threshold of 1 V is connected at the pin and is used to detect
when the pin is shorted to the SOURCE pin.
There are a total of five functions available through the use of
the LINE-SENSE pin: OV, UV, line feed-forward with DCMAX
reduction, remote ON/OFF and synchronization. Shorting the
LINE-SENSE pin to the SOURCE pin disables all five functions.
The LINE-SENSE pin is typically used for line sensing by
connecting a resistor from this pin to the positive input DC
voltage bus to implement OV, UV and line feed-forward with
DCMAX reduction over line voltage. In this mode, the value of the
resistor determines the line OV/UV thresholds, and the DCMAX is
reduced linearly with input DC high voltage starting from just
above the UV threshold. This pin can also be used as the input
pin for remote ON/OFF and synchronization. An external
transistor placed between the LINE-SENSE pin and the
CONTROL pin realizes remote ON/OFF via UV or OV threshold.
Synchronization is available by connecting an open drain
external MOSFET between the LINE-SENSE pin and the
SOURCE pin to generate synchronization pulse. Each time the
MOSFET turns on, the falling edge of the LINE-SENSE pin
voltage initiates a new switching cycle. The lowest
synchronization frequency guaranteed by DPA-Switch is
128 kHz. Refer to Table 2 for possible combinations of the
functions with example circuits shown in Figure 11 through
Figure 24. A description of specific functions in terms of the
LINE-SENSE pin I/V characteristic is shown in Figure 7 (right
hand side). The horizontal axis represents LINE-SENSE pin
current with positive polarity indicating currents flowing into the
pin. The meaning of the vertical axes varies with functions. For
those that control the on/off states of the output such as UV,
OV and remote ON/OFF, the vertical axis represents the enable/
disable states of the output. UV triggers at IUV
(+50 μA typical with 4 μA hysteresis) and OV triggers at IOV (+135
μA typical with 4 μA hysteresis). Between the UV and OV
thresholds, the output is enabled. For line feed-forward with
DCMAX reduction, the vertical axis represents the magnitude of
the DCMAX Line feed-forward with DCMAX reduction lowers
maximum duty cycle from 75% at IL(DC) (+55 μA typical) to 33%
at IOV (+135 μA).
EXTERNAL CURRENT LIMIT (X) Pin Operation
When current is drawn out of the EXTERNAL CURRENT LIMIT pin,
it works as a voltage source of approximately
1.3 V up to a maximum current of -230 μA (typical). At
-230 μA, it turns into a constant current source (refer to Figure 8).
There are two functions available through the use of the
EXTERNAL CURRENT LIMIT pin: external current limit and
remote ON/OFF. Shorting the EXTERNAL CURRENT LIMIT pin
and SOURCE pin disables both functions. In high efficiency
applications, this pin can be used to reduce the current limit
externally to a value close to the operating peak current, by
connecting the pin to the SOURCE pin through a resistor. The
pin can also be used as a remote ON/OFF control input.
Table 2 shows several different ways of using this pin. See
Figure 7 for a description of the functions where the horizontal
axis (left hand side) represents the EXTERNAL CURRENT LIMIT
pin current. The meaning of the vertical axes varies with
function. For those that control the on/off states of the output
such as remote ON/OFF, the vertical axis represents the enable/
disable states of the output. For external current limit, the
vertical axis represents the magnitude of the ILIMIT. Please see
graphs in the Typical Performance Characteristics section for
the current limit programming range and the selection of the
appropriate resistor value.
9
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Rev. S 12/07
DPA422-426
IUV(U)
IREM(U)
(Enabled)
IOV(U)
(Enabled)
Output
MOSFET
Switching
Output
MOSFET
Switching
(Disabled)
(Disabled)
ILIMIT (Default)
DCMAX (75%)
Current
Limit
Maximum
Duty Cycle
-21.5 μA
VBG + VTP
-25.5 μA
VBG
X Pin Voltage
-250
L Pin Voltage
-200
-150
-100
-50
0
0
X Pin Current (μA)
131 μA
135 μA
47 μA
50
100
150
200
250
L Pin Current (μA)
Note: These figures provide idealized functional characteristics with typical performance values. Please refer to the
parametric table and typical performance characteristics sections of the data sheet for measured data.
PI-2778-080801
Figure 7.
LINE-SENSE and EXTERNAL CURRENT LIMIT Pin Characteristics.
CONTROL (C)
DPA-Switch
230 μA
(Negative Current Sense - ON/OFF,
Current Limit Adjustment)
VBG + VT
EXTERNAL CURRENT LIMIT (X)
(Voltage Sense)
LINE-SENSE (L)
VBG
1V
(Positive Current Sense - Under-Voltage,
Overvoltage, ON/OFF Maximum Duty
Cycle Reduction)
240 μA
PI-2765-061704
Figure 8.
LINE-SENSE (L), and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic
10
Rev. S 12/07
www.powerint.com
DPA422-426
Typical Uses of FREQUENCY (F) Pin
+
+
DC
Input
Voltage
DC
Input
Voltage
D
CONTROL
C
S
D
CONTROL
C
S
F
F
-
-
PI-2655-071700
PI-2654-071700
Figure 9.
Figure 10. 300 kHz Frequency Operation.
400 kHz Frequency Operation.
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins
+
+
VUV = IUV x RLS + VL (I = I )
L
UV
VOV = IOV x RLS + VL (I = I )
L
C L X S F
RLS
D
DC
Input
Voltage
619 kΩ
1%
DC
Input
Voltage
L
D
C
S
For RLS = 619 kΩ
VUV = 33.3 V
VOV = 86.0 V
D
D
CONTROL
S
X
L
CONTROL
C
-
C
F
-
S
PI-2766-070901
Figure 11. Three Terminal Operation (LINE-SENSE and EXTERNAL CURRENT
LIMIT Features Disabled. FREQUENCY Pin can be tied to SOURCE or
CONTROL Pin).
+
VUV = RLS x IUV +
VL (I = I )
464 kΩ
1%
L
RLS
DC
Input
Voltage
PI-2767-091302
Figure 12. Line-Sensing for Under-Voltage, Overvoltage and Line Feed-forward.
+
590 kΩ
1%
UV
For Values Shown
VUV = 33.1 V
150 kΩ
1%
D
DC
Input
Voltage
-
OV
For Values Shown
VOV = 86.2 V
30 kΩ
1%
D
L
VOV = IOV x RLS +
VL (I = I )
L
RLS
1N4148
L
CONTROL
CONTROL
C
C
15 V
OV
-
S
PI-2852-121504
Figure 13. Line-Sensing for Under-Voltage Only (Overvoltage Disabled).
S
PI-2853-091302
Figure 14. Line-Sensing for Overvoltage Only (Under-Voltage Disabled).
Maximum Duty Cycle will be reduced at Low Line.
11
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Rev. S 12/07
DPA422-426
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)
+
For RIL = 12 kΩ
ILIMIT = 64%
+
ILIMIT = 100% @ 36 VDC
ILIMIT = 64% @ 72 VDC
RLS
363 kΩ
For RIL = 25 kΩ
ILIMIT = 34%
DC
Input
Voltage
See Figure 34 for other
resistor values (RIL)
D
CONTROL
C
S
DC
Input
Voltage
D
CONTROL
C
S
X
X
RIL
RIL
4.2 kΩ
-
-
PI-2854-050602
PI-2836-011904
Figure 15. Externally Set Current Limit.
Figure 16. Current Limit Reduction with Line Voltage.
+
QR can be an optocoupler
output or can be replaced by
a manual switch.
QR can be an
optocoupler output or
can be replaced
by a manual switch.
+
QR
ON/OFF
RMC
47 kΩ
DC
Input
Voltage
DC
Input
Voltage
D
CONTROL
C
37.4 kΩ
L
D
CONTROL
S
C
X
ON/OFF
QR
47 KΩ
-
S
PI-2625-040501
Figure 18. Active-off Remote ON/OFF. Maximum Duty Cycle Will Be Reduced.
Figure 17. Active-on (Fail Safe) Remote ON/OFF.
+
DC
Input
Voltage
QR can be an optocoupler
output or can be replaced
by a MOSFET or manual
switch.
For RIL = 12 kΩ
ILIMIT = 64%
D
CONTROL
C
S
For RIL = 25 kΩ
ILIMIT = 34%
+
ON/OFF
47 kΩ
PI-2856-072602
Figure 19. Active-on Remote ON/OFF with Externally Set Current Limit.
RMC
47 kΩ
37.4 kΩ
DC
Input
Voltage
L
D
CONTROL
C
S
QR
QR can be an
optocoupler output
or can be replaced
by a manual switch.
QR
ON/OFF
X
RIL
-
PI-2855-050602
For RIL = 12 kΩ
ILIMIT = 64%
For RIL = 25 kΩ
ILIMIT = 34%
X
RIL
PI-2857-050602
Figure 20. Active-off Remote ON/OFF with Externally Set Current Limit.
12
Rev. S 12/07
www.powerint.com
DPA422-426
Typical Uses of LINE-SENSE (L) and EXTERNAL CURRENT LIMIT (X) Pins (cont.)
+
[email protected] V = 75%
[email protected] V = 42%
CONTROL
C
S
switch.
QR
For RIL = 12 kΩ
ILIMIT = 64%
For RLS = 619 kΩ
ON/OFF
QR can be an optocoupler
output or can be replaced
by a manual switch.
L
D
619 kΩ output or can be replaced
1%
by a MOSFET or manual
RLS
619 kΩ
1%
RLS
DC
Input
Voltage
QR can be an optocoupler
+
47 kΩ
DC
Input
Voltage
VUV = 33.3 V
VOV = 86.0 V
L
D
CONTROL
C
X
QR
RIL
ON/OFF
-
47 kΩ
-
S
PI-2859-050602
Figure 21. Active-on Remote ON/OFF with LINE-SENSE and
EXTERNAL CURRENT LIMIT.
For timing requirements,
see Figure 6.
1%
L
D
[email protected] V = 75%
[email protected] V = 42%
CONTROL
C
S
QR can be an optocoupler
output.
For RLS = 619 kΩ
VUV = 33.3 V
619 KΩ
VOV = 86.0 V
RLS
-
Figure 22. Active-off Remote ON/OFF with LINE-SENSE.
+
+
DC
Input
Voltage
PI-2858-072602
X
RIL
12 kΩ
DC
Input
Voltage
For RIL = 12 kΩ
ILIMIT = 64%
See Figure 34 for other
resistor values (RIL)
to select different ILIMIT
values
PI-2837-011904
Figure 23. Line-Sensing and Externally Set Current Limit.
D
L
CONTROL
C
S
QR
-
ON/OFF
47 kΩ
PI-3868-050602
Figure 24. Synchronization.
13
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Rev. S 12/07
DPA422-426
Application Examples
+ VIN
36-75 VDC
C7
1 nF
1.5 kV
L1
1 μH
2.5 A
R14
10 Ω
C10
100 μF
10 V
L2
R1
619 kΩ
1%
R15
10 Ω
R17
10 Ω
T1
R16
10 kΩ
C9*
CONTROL
S
VR1
SMBJ
150
X
U2
PC357N1T
C
F
R3
18.2 kΩ
1%
R4
1.0 Ω
C5
220 nF
VIN
C4
4.7 μF
20 V
D1
BAV
19WS
RTN
U2
R7
10 kΩ
R10
10.0 kΩ
1%
R5*
U1
DPA425R
L
D2
Q1
Si4888
DY
D4
BAV19WS
DPA-Switch
D
5 V, 6 A
C17
3300 pF
Q2
Si4888
DY
C1, C2 & C3
1 μF
100 V
C12
1 μF
10 V
C11
100 μF
10 V
C6
68 μF
10 V
*Optional components
D3
BAV19WS
R6
150 Ω
C13
10 μF
10 V
U3
LM431AIM3
C16
100 nF
R12
5.1 Ω
R9
220 Ω
C14
1 μF
R11
10.0 kΩ
1%
PI-3472-061704
Figure 25. A High Efficiency 30 W, 5 V, Telecom Input DC-DC Converter.
High Efficiency 30 W Forward Converter
The circuit shown in Figure 25 is a typical implementation of a
single output DC-DC converter using DPA-Switch in a forward
configuration with synchronous rectification. This design
delivers 30 W at 5 V, from a 36 VDC to 75 VDC input with a
nominal efficiency at 48 VDC of 90% using the DPA425R.
By taking advantage of many of the built-in features of the
DPA-Switch, the design is greatly simplified compared to a
discrete implementation. Resistor R1 programs the input undervoltage and overvoltage thresholds to typically 33 V and 86 V
respectively. This resistor also linearly reduces the maximum
duty from the internal maximum of 75% at 36 V to 42% at
72 V to prevent core saturation during load transients at high
input voltages. The DPA-Switch internal thresholds are
toleranced and characterized so the designer can guarantee
the converter will begin operation at 36 V, necessary to meet
ETSI standards, without the cost of an external reference IC.
The current limit is externally set by resistor R3 to just above the
drain current level needed for maximum load regulation to limit
the maximum overload power of the converter. The externally
programmable current limit feature also allows a larger
DPA-Switch family member to be selected. Using the X pin, the
current limit can be adjusted to the same level. A large device
reduces conduction losses and improves efficiency without
requiring any other circuit changes. This has been used here to
replace the DPA424R with a DPA425R.
The selectable 300/400 kHz switching frequency is set to
300 kHz by connecting the FREQUENCY (F) pin to CONTROL (C).
DRAIN voltage clamping is provided by VR1, which keeps the
peak DRAIN voltage within acceptable limits. Transformer core
reset is provided by the gate capacitance of Q1 with R17 in
series. Optional reset capacitance C9 with R5 can be added if
necessary to supplement the gate capacitance of Q1.
The output of the transformer is rectified using MOSFETs to
provide synchronous rectification. The UV/OV function, together
with the turns ratio of the transformer, defines the maximum
MOSFET gate voltage, allowing the very simple gate drive
arrangement, without the need for drive windings or a drive IC.
During primary on-time, capacitor C17 couples charge through
resistor R15 to drive the gate of the forward MOSFET, Q2.
Capacitor C17 provides a DC isolated drive for Q2, preventing
gate overstress on Q1 during power down. The time constant
formed by R16 and C17 is selected to be much longer than one
switching cycle. Diode D4 resets the voltage on capacitor C17
before the next switching cycle. During the primary off-time, the
diode D2 provides a conduction path for the energy in inductor
L2 while Q1 is still off. The transformer reset voltage on the
secondary winding directly drives a positive voltage on the gate
of catch MOSFET, Q1. MOSFET Q1 provides a low loss
conduction path for a substantial portion of the primary off-time.
An isolated auxiliary winding on L2, rectified and filtered by D1
and C4, provides the bias supply for the optocoupler transistor.
14
Rev. S 12/07
www.powerint.com
DPA422-426
+VIN
36 - 57 VDC
1
T1
J1-1
R1
1 MΩ
1%
L1
1 μH, 2A
9, 10
J2-1
D2
SL43
R2
619 kΩ
1%
3.3 V, 2 A
C5
330 μF
6V
2
C7
330 μF
6V
C6
330 μF
6V
C9
1 μF
10 V
RTN
6, 7
4
C2
47 pF
200 V
J2-2
R5
100 Ω
3
D3
BAV19, SOD323
R6
51 Ω
5
C1
1 μF
100 V
VR1
SMAJ
150A
L
D
CONTROL
-VIN
X
F
C3
0.1 μF
50 V
R3
8.66 kΩ
1%
R8
34 kΩ
1%
C8
1 μF
50 V
DPA-Switch
U1
DPA423G
U2
PC357
C
S
R7
1 kΩ
C11
0.1 μF
R4
5.1 Ω
C4
22 μF
10 V
J1-2
C10
0.33 μF
U3
CAT431L,
SOT23
R9
20 kΩ
1%
PI-3806-061704
Figure 26. A Cost Effective 6.6 W, 3.3 V Flyback DC-DC Converter.
Output regulation is achieved by using secondary side voltage
reference, U3. The resistor divider formed by R10 and R11,
together with the reference voltage, determines the output
voltage. Diode D3 and C13 form a soft-finish network that,
together with the internal duty cycle and current limit soft-start
of the DPA-Switch, prevent output overshoot at start-up.
Resistor R7 ensures that the soft-finish capacitor is discharged
quickly when the output falls out of regulation. Control loop
response is shaped by R6, C16, R12, C14, R9, R4 and C5,
providing a wide bandwidth and good phase margin at gain
crossover. Since the PWM control in DPA-Switch is voltage mode,
no slope compensation is required for duty cycles above 50%.
Cost Effective 6.6 W Flyback Converter
The DPA-Switch flyback power supply provides a cost effective
solution for high density PoE and VoIP DC-DC applications.
Figure 26 shows a typical implementation of a single output
flyback converter using the DPA423G. For applications that
require input to output isolation, this simple, low component
count design delivers 6.6 W at 3.3 V from a 36 VDC to 57 VDC
input with a nominal efficiency at 48 VDC of 80%.
Resistor R2 programs the input under-voltage and overvoltage
thresholds to 33 V and 86 V respectively. Resistors R1 and R3
program the internal device current limit. The addition of line
sense resistor R1 reduces the current limit with increasing input
voltage, preventing excessive overload output current. In this
design the overload output current varies less than ±2.5%
across the entire input voltage range. Controlling the current
limit also reduces secondary component stress and leakage
inductance spikes, allowing the use of a lower VRRM (30 V rather
than 40 V) Schottky output diode, D2.
The primary side Zener clamp VR1 ensures the peak drain
voltage is kept below the 220 V BVDSS rating of U1 under input
surge and overvoltage events. During normal operation, VR1
does not conduct and C2 is sufficient to limit the peak drain
voltage.
The primary bias winding provides CONTROL pin current after
start-up. Diode D3 rectifies the bias winding, while components
R5 and C8 reduce high frequency switching noise and prevent
peak charging of the bias voltage. Capacitor C3 provides local
decoupling of U1 and should be physically close to the
CONTROL and SOURCE pins. Energy storage for start-up and
auto-restart timing is provided by C4.
The secondary is rectified by D2 and the Low ESR tantalum
output capacitors, C5-C7, minimizing switching ripple and
maximizing efficiency. A small footprint secondary output choke
L1 and ceramic output capacitor C9 are adequate to reduce
high frequency noise and ripple to below 35 mV peak-peak
under full load conditions.
The output voltage is sensed by the voltage divider formed by
resistors R8 and R9 and is fed to the low voltage 1.24 V
reference U3. Feedback compensation is provided by R6, R7
and C11 together with C4 and R4. Capacitor C10 provides a
soft-finish characteristic, preventing output overshoot during
start-up.
Low Cost PoE VoIP Phone Converter
The basic circuitry to support IEEE standard 802.3af Power
over Ethernet (PoE) is straightforward. Class 0 signature and
classification circuits can be implemented with a single resistor
and the required under-voltage lockout function is a voltage
15
www.powerint.com
Rev. S 12/07
DPA422-426
D41
BAV19WS
Ethernet
(RJ-45)
D101
Connector DL4002
PoE Interface
L1
1 μH 2.5 A
1
(1,2)
DL4002
D102
D103
DL4002
R1
649 kΩ
1%
R52
20 kΩ
4
5
C1
1 μF
100 V
R51
24.9 kΩ
1% 1/4 W
Q21 VR21
Si4804
R23
174 k
1%
D21
SL13
15 V
R23
10 kΩ
(3,6)
DPA-Switch
U1
L DPA424P
D
(7,8)
DL4002
D108
RTN
C6
4.7 μF
20 V
U2
R16
10 kΩ
1%
U2
PC357
N1T
R11
10 kΩ
C12
100 nF
R13
11 Ω
CONTROL
D52
BAV19
R53
20 kΩ
R54
20 Ω
VR1
SMAJ
150
S
X
Q51
TIP29C (100 V/1 A)
or MMBTA06
F
C4
220 nF
R2
13.3 kΩ
1%
5 V, 2.4 A
5
2
R12
150 Ω
C
D107
DL4002
C25
R4 1 μF
160 Ω 10 V
R21
10 k
R22
10 kΩ
D51
BAV19
7.5 V, 0.4 A
C31
100 μF
10 V
C22-C24
100 μF 5 V
D6
BAV
19WS
D105
DL4002
DL4002
D106
6
8
7
Q20
MMBTS3906
C51
1 nF
50 V
7
L2
16 μH 4 A
C21
2.2 nF
R21
10 Ω
R22
10 Ω
T1
C2
1 μF
100 V
3
Q22
Si4804
7
6
(4,5)
DL4002
D104
8
3
VR51
28 V
4
D31
20CJQ060
20 V, 10 mA
C41
4.7 μF, 35 V
VR41
D42
6.8 V IN4148
D11
BAV19WS
R3
1.0 Ω
C5
47 μF
10 V
C11
2.2 μF
10 V
U3
LM431AIM3
C13
68 nF
R14
1 kΩ
R15
10 kΩ
1%
PI-3824-040706
Figure 27. PoE Interface Circuit Using a Bipolar Transistor Pass-Switch and DPA424P.
controlled pass-switch. By adding this circuitry to the front end
of a DPA converter, a low cost and low component count PoE
powered device (PD) power supply can be implemented.
Figure 27 shows a typical PD solution.
power from the power supply bias winding.
Once the three start up phases have been successfully
completed, the DPA-Switch is allowed to function as a forward
converter (described in Figure 25 and accompanying text).
The PoE specification requires the PD to provide three
fundamental functions: discovery, classification, and passswitch connection.
Key Application Considerations
When input voltage is applied to the PD, it must present the
correct discovery signature impedance in the voltage range of
2.5 VDC to 10 VDC. This impedance is provided by R51 in
Figure 27.
The second “classification” phase occurs at input voltages
15 VDC to 20 VDC. The PD must draw a specified current to
identify the device class (Class 0 specifies 0.5 mA to 4 mA).
This is again accomplished by resistor R51.
In the third phase, the bipolar pass-switch (Q51 in Figure 27)
connects the input voltage to the power supply at voltages
above approximately 30 VDC (28 V+VR52). Zener diode VR51
conducts, driving the current through resistor R52 to the base
of Q51. Resistor R53 prevents turn-on under other conditions.
Once the Power supply has started, components D51, D52,
C51 and R54 enhance the base-current drive by coupling
DPA-Switch Design Considerations
Power Table
This section provides a description of the assumptions used to
generate the power tables (Tables 1 and 3 through 6) and
explains how to use the information provided by them.
All Power tables: Tables 1 and 3 through 6
• Maximum output power is limited by the device internal
current limit. This is the peak output power which could
become the continuous output power, provided adequate
heat sinking is used.
• Data assumes adequate heat sinking to keep the junction
temperature at or below 100 °C and worst case RDS(ON) at
TJ = 100 °C.
• The use of P and G packages are recommended for device
dissipation equal to or less than 1.5 W only due to package
thermal limitation. For device dissipation above 1.5 W, use
R package.
16
Rev. S 12/07
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DPA422-426
Forward power tables: Tables 1 (upper half), 3 and 4
• Output power figures are based on forward topology using
Schottky diode rectification. Up to 5% higher output power is
possible using synchronous rectification.
• Dissipation data assumes a diode loss representing 6% of the
total output power and combined loss in magnetic components representing 6% of the total output power.
DPA-Switch losses are based on a ratio between conduction
and switching losses of approximately 3:1. These assumptions are typical for a single 5 V output forward converter
design using Schottky rectification and adequately designed
magnetic components.
Flyback power tables: Tables 1 (lower half), 5 and 6
• Output power and dissipation figures are based on a 5 V
output using Schottky diode rectification with an efficiency of
85%. Values are generated by calculation based on
I2 × RDS(ON) losses and characterization of switching losses,
correlated to bench measurement of each DPA-Switch device.
• Device dissipations above 1.5 W are possible using the
R package. However the forward converter topology is
recommended for such higher power designs.
Output Power Table
16-32 VDC Range (Forward)2
Total Device
Dissipation
0.5 W
1W
2.5 W
4W
6W
Max
Power
Output1
3.5 W
5W
7W
10 W
12 W
4.5 W
7W
10 W
14 W
16.5 W
15 W
22 W
25 W
27 W
31 W
37 W
5.0 W
7.5 W
15.5 W
31 W
43 W
Product3
DPA422
DPA423
DPA424
DPA425
DPA426
Table 3. Output Power Table for 16-32 VDC Input Voltage.
Notes:
1. Limited by device internal current limit.
2. See text in this section for a complete description of assumptions.
3. See Part Ordering Information.
Output Power Table
24-48 VDC Range (Forward)2
Total Device
Dissipation
0.5 W
1W
2.5 W
4W
6W
Max
Power
Output1
5.5 W
8W
11 W
16 W
18 W
7W
11 W
16 W
22 W
25 W
23.5 W
35 W
39 W
43 W
48 W
58 W
8W
11.5 W
25 W
47 W
65 W
Product3
The power tables provide two types of information. The first is
the expected device dissipation for a given output power. The
second is the maximum power output. Each table specifies the
input voltage range and assumes a single 5 V output using
Schottky diode rectification.
DPA422
DPA423
DPA424
DPA425
DPA426
For example, referring to Table 1, for 36 VDC to 75 VDC input
range, DPA424 would typically dissipate 1 W in a 23 W forward
converter and has a maximum power capacity of 35 W. In the
same converter, DPA425 would dissipate 0.5 W. Selecting
DPA425 with associated reduced dissipation would increase
overall converter efficiency by approximately 2%.
Table 4.
Issues Affecting Dissipation:
1. Using synchronous rectification will tend to reduce device
dissipation.
2. Designs with lower output voltages and higher currents will
tend to increase the device dissipation listed in the power
table.
3. Reduced input voltage decreases the available output power
for the same device dissipation. Tables 3 to 6 are the power
tables for 16 VDC and 24 VDC input voltages. Input voltages
below 16 V are possible, but since the internal start-up
current source is not specified at voltages below 16 V, an
external chip supply current should be fed into the
CONTROL pin approximately equal to but less than ICD1.
DPA-Switch Selection
Use Tables 1 and 3 through 6 to select the DPA-Switch based
on device dissipation. Selecting the optimum DPA-Switch
depends upon required maximum output power, efficiency,
heat sinking constraints and cost goals. With the option to
externally reduce current limit, a larger DPA-Switch may be
used for lower power applications where higher efficiency is
needed or minimal heat sinking is available. Generally, selecting
the next larger device, than is required for power delivery will
give the highest efficiency. Selecting even larger devices may
Output Power Table for 24-48 VDC Input Voltage
(See Table 3 for Notes).
Output Power Table
16-32 VDC Input Range (Flyback)2
Total Device
Dissipation
0.5 W
0.75 W
1W
1.5 W
Max
Power
Output1
3W
5W
6.5 W
7W
8.5 W
10 W
10 W
12 W
15 W
4.5 W
6W
11 W
22 W
Product3
DPA422
DPA423
DPA424
DPA425
Table 5.
Flyback Output Power Table for 16-32 VDC Input Voltage
(See Table 3 for Notes).
Output Power Table
24-48 VDC Input Range (Flyback)2
Total Device
Dissipation
0.5 W
0.75 W
1W
1.5 W
Max
Power
Output1
3W
7W
8.5 W
11.5 W
14 W
-
7W
8.5 W
17 W
Product3,4
DPA422
DPA423
DPA424
Table 6. Flyback Output Power Table for 24-48 VDC Input Voltage.
Notes:
1. Maximum output power is limited by device internal current limit.
2. See text in this section for a complete description of assumptions.
3. See Part Ordering Information.
4. Higher switching losses may prevent DPA425 from delivering more power than a
smaller device.
17
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DPA422-426
give little or no improvement in efficiency due to the
improvement in conduction losses being negated by larger
device switching losses. Figure 50 provides information on
switching losses. This together with conduction loss
calculations give an estimate of device dissipation.
Primary Clamp
A primary clamp network is recommended to keep the peak
DRAIN voltage due to primary leakage inductance to below the
BVDSS specification. A Zener diode combined with a small value
capacitor connected across the primary winding is a low cost
and low part count implementation.
Output Rectification
Rectification of the secondary is typically performed using
Schottky diodes or synchronous rectification. Schottky diodes
are selected for peak inverse voltage, output current, forward
drop and thermal conditions. Synchronous rectification
requires the additional complication of providing gate drive. The
specified line under-voltage and line overvoltage thresholds of
DPA-Switch simplifies deriving gate drive directly from the
transformer secondary winding for many applications. The
turns ratio of the transformer together with the under/
overvoltage thresholds defines the minimum and maximum
gate voltages, removing the need for Zeners to clamp the gate
voltage.
Soft-Start
Generally a power supply experiences maximum stress at startup before the feedback loop achieves regulation. For a period
of 5 ms the on-chip soft-start linearly increases the duty cycle
from zero to the default DCMAX at turn-on. In addition, the
primary current limit increases from 85% to 100% over the
same period. This causes the output voltage to rise in an
orderly manner allowing time for the feedback loop to take
control of the duty cycle. This integrated soft-start reduces the
stress on the DPA-Switch MOSFET, clamp circuit and output
diode(s), and helps prevent transformer saturation during startup. Also, soft-start limits the amount of output voltage
overshoot, and in many applications eliminates the need for a
soft-finish capacitor. If necessary, to remove output overshoot,
a soft-finish capacitor may be added to the secondary
reference.
Switching Frequency
The FREQUENCY pin of DPA-Switch offers a switching
frequency option of 400 kHz or 300 kHz. Operating at 300 kHz
will increase the amount of magnetization energy stored in the
transformer. This is ideal for applications using synchronous
rectification driven directly from the transformer secondary
where this energy can be used to drive the catch MOSFET gate.
Transformer Design
It is recommended that the forward converter transformer be
designed for maximum operating flux swing of 1500 Gauss and
a peak flux density of 3500 Gauss. When operating at the
maximum current limit of the selected DPA-Switch (during
overload conditions), neither magnetic component (transformer
and output inductor) should be allowed to saturate. When a
larger device than necessary has been selected, reducing the
internal current limit close to the operating peak current limits
overload power and minimizes the size of the secondary
components.
No-load and Standby Consumption
Cycle skipping operation at light or no load can significantly
reduce power loss. In addition this operating mode ensures
that the output maintains regulation even without an external
minimum load. However, if cycle skipping is undesirable in a
particular application, it can be avoided by adding sufficient
pre-load.
DPA-Switch Layout Considerations
The DPA-Switch can operate with large DRAIN current, the
following guidelines should be carefully followed.
Primary Side Connections
The tab of DPA-Switch R package is the intended return path
for the high switching currents. Therefore, the tab should be
connected by wide, low impedance traces back to the input
decoupling capacitor. The SOURCE pin should not be used to
return the power currents; incorrect operation of the device may
result. The SOURCE is only intended as a signal ground. The
device tab (SOURCE) is the correct connection for high current
with the R package.
The CONTROL pin bypass capacitor should be located as
close as possible to the SOURCE and CONTROL pins and its
SOURCE connection trace should not be shared by the main
MOSFET switching currents. All SOURCE pin referenced
components connected to the LINE-SENSE or EXTERNAL
CURRENT LIMIT pins should also be located closely between
their respective pin and SOURCE. Once again, the SOURCE
connection trace of these components should not be shared by
the main MOSFET switching currents. It is critical that the tab
(SOURCE) power switching currents are returned to the input
capacitor through a separate trace that is not shared by the
components connected to CONTROL, LINE-SENSE or
EXTERNAL CURRENT LIMIT pins.
Any traces to the L or X pins should be kept as short as
possible and away from the DRAIN trace to prevent noise
coupling. LINE-SENSE resistor (R1 in Figure 25) should be
located close to the L pin to minimize the trace length on the
L pin side.
In addition to the CONTROL pin capacitor (C6 in Figure 25), a
high frequency bypass capacitor in parallel is recommended as
close as possible between SOURCE and CONTROL pins for
better noise immunity. The feedback optocoupler output
should also be located close to the CONTROL and SOURCE
pins of DPA-Switch.
Heat Sinking
To maximize heat sinking of the DPA-Switch R or G package
and the other power components, special thermally conductive
PC board material (aluminum clad PC board) is recommended.
This has an aluminum sheet bonded to the PC board during the
manufacturing process to provide heat sinking directly and
allow the attachment of an external heat sink. If normal PC
board material is used (such as FR4), providing copper areas on
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DPA422-426
both sides of the board and using thicker copper will improve
heat sinking.
If an aluminum clad board is used then shielding of switching
nodes is recommended. This consists of an area of copper
placed directly underneath switching nodes such as the drain
node, and output diode to provide an electrostatic shield to
prevent coupling to the aluminum substrate. These areas are
connected to input negative in the case of the primary and
output return for secondary. This reduces the amount of
capacitive coupling into the insulated aluminum substrate that
can then appear on the output as ripple and high frequency
noise.
Quick Design Checklist
As with any power supply design, all DPA-Switch designs
should be verified on the bench to make sure that component
specifications limits are not exceeded under worst case
conditions. The following minimum set of tests for DPA-Switch
forward converters is strongly recommended:
1. Maximum drain voltage – Verify that peak VDS does not
exceed minimum BVDSS at highest input voltage and maximum overload output power. It is normal, however, to have
additional margin of approximately 25 V below BVDSS to allow
for other power supply component unit-to-unit variations.
Maximum overload output power occurs when the output is
loaded to a level just before the power supply goes into autorestart (loss of regulation).
2. Transformer reset margin – Drain voltage should also be
checked at highest input voltage with a severe load step
(50-100%) to verify adequate transformer reset margin. This
test shows the duty cycle at high input voltage, placing the
most demand on the transformer reset circuit.
3. Maximum drain current – At maximum ambient temperature,
maximum input voltage and maximum output load, verify
drain current waveforms at start-up for any signs of transformer or output inductor saturation and excessive leading
edge current spikes. DPA-Switch has a leading edge
blanking time of 100 ns to prevent premature termination of
the on cycle. Verify that the leading edge current spike does
not extend beyond the blanking period.
4. Thermal check – At maximum output power, minimum input
voltage and maximum ambient temperature, verify that
temperature specifications are not exceeded for the
transformer, output diodes, output choke(s) and output
capacitors. The DPA-Switch is fully protected against overtemperature conditions by its thermal shutdown feature. It is
recommended that sufficient heat sinking is provided to keep
the tab temperature at or below 115 °C (R package),
SOURCE pins at or below 100 °C (P/G packages) under
worst case continuous load conditions (at low input voltage,
maximum ambient and full load). This provides adequate
margin to minimum thermal shutdown temperature
(130 °C) to account for part-to-part RDS(ON) variation. When
monitoring device temperatures, note that the junction-tocase thermal resistance should be accounted for when
estimating die temperature.
Design Tools
Up-to-date information on design tools is available at the Power
Integrations website: www.powerint.com.
19
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Rev. S 12/07
DPA422-426
Solder Side
Component Side
TOP VIEW
Output
Diode
V
Transformer
+
D
Inductor
(Coupled)
V
DC
In
DPA-Switch
S
X
L
C
V
+
DC
Out
Optocoupler
-
-
V
Maximize hatched copper area for optimum heat sinking
V
Via between board layers
PI-2883-060602
Figure 28. Layout Considerations for DPA-Switch Using R Package.
Top Side PCB
Bottom Side PCB
TOP VIEW
Bottom Diode
Heatsink
(Two sided printed circuit board)
V
V
+
V
DC
In
V
-
-
S
S
D
S
V
DPA-Switch
C
L
X
F
T
r
a
n
s
f
o
r
m
e
r
V
V
V
+
DC
Out
V
V
V
PI-3805-012904
DPA-Switch Heatsink
V
Optocoupler
Maximize hatched copper area for optimum heat sinking
V
Via between board layers
Figure 29. Layout Considerations for DPA-Switch Using G Package.
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Rev. S 12/07
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DPA422-426
Absolute Maximum Ratings(1,5)
DRAIN Voltage .....................................................-0.3 V to 220 V
DRAIN Peak Current:
DPA422......................................1.31 A
DPA423......................................1.75 A
DPA424....................................... 3.5 A
DPA425...........................................7 A
DPA426....................................... 9.6 A
CONTROL Voltage ................................................ -0.3 V to 9 V
CONTROL Current .........................................................100 mA
LINE SENSE Pin Voltage ...................................... -0.3 V to 9 V
EXTERNAL CURRENT LIMIT Pin Voltage ........ -0.3 V to 9 V
FREQUENCY Pin Voltage ....................................... -0.3 V to 9 V
Storage Temperature-65 °C to 150 °C
Operating Junction Temperature(2).................... -40 °C to 150 °C
Lead Temperature(3) ....................................................... 260 °C
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
2. Normally limited by internal circuitry.
3. 1/16” from case for 5 seconds.
4. Maximum ratings specified may be applied, one at a time,
without causing permanent damage to the product.
Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect product reliability.
Theraml Impedance
Thermal Impedance: P or G Package:
(θJA) ........................... 70 °C/W(1); 60 °C/W(2)
(θJC)(3) ............................................11 °C/W
R Package:
(θJA) .................................................40 °C/W(4)
(θJA) .................................................30 °C/W(5)
(θJC)(6) ................................................2 °C/W
Parameter
Symbol
Notes:
1. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
2. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
3. Measured on pin 7 (SOURCE) close to plastic interface.
4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
5. Soldered to 3 sq. in. (1935 mm2), 2 oz. (610 g/m2) copper clad.
6. Measured at the back surface of tab.
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 33
(Unless Otherwise Specified)
Min
Typ
Max
FREQUENCY Pin
Connected to SOURCE
375
400
425
FREQUENCY Pin
Connected to CONTROL
282
300
317
4
6
Units
Control Functions
Switching
Frequency
fOSC
Duty Cycle (Prior to
Cycle Skipping)
DCMIN
Maximum Duty Cycle
DCMAX
Control Current at Start
of Cycle Skipping
External Bias
Current
IC(skip)
IB
TJ = 25 °C
IC = ICD1
kHz
VL = 0 V
71
75
79
IL = 80 μA
52
62
71
IL = 115 μA
32
42
57
DPA422
6.3
8.0
DPA423
7.2
9.0
DPA424
8.2
10.0
DPA425
10.0
12.0
DPA426
11.5
14.0
TJ = 25 °C; fOSC = 400 kHz
TJ = 25 °C; fOSC = 400 kHz
DPA422
1.8
2.5
3.1
DPA423
2
2.8
3.5
DPA424
2.5
3.5
4.4
DPA425
3.6
4.8
6.0
DPA426
4.4
5.7
7.1
%
%
mA
mA
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Rev. S 12/07
DPA422-426
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 33
(Unless Otherwise Specified)
Min
Typ
Max
Units
5
7.2
ms
-22
-18
%/mA
Control Functions (cont.)
Softstart Time
tSOFT
TJ = 25 °C; DCMIN to DCMAX
PWM Gain
DCreg
TJ = 25 °C; IC = IC(skip) + IB)/2
PWM Gain
Temperature Drift
Dynamic Impedance
-28
See Note A
ZC
TJ = 25 °C; IC = IC(skip) + IB)/2
-0.01
10
Dynamic Impedance
Temperature Drift
CONTROL Pin Internal
Filter Pole
15
%/mA/°C
22
Ω
0.18
%/°C
30
kHz
Shutdown/Auto-Restart
CONTROL Pin
Charging Current
During Startup and Auto-Restart:
VC = 5.0 V; VD = 16 V & 40 V; TJ = 25 °C
IC(CH))
-5.2
-4
mA
Average Current at the Beginning of
Softstart: VC = 5.0 V; VD = 16 V & 40 V;
TJ = 25 °C
-19
See Note A
-0.6
%/ °C
5.8
V
Charging Current
Temperature Drift
Auto-Restart Upper
Threshold Voltage
VC(AR)U
Auto-Restart Lower
Threshold Voltage
VC(AR)L
4.5
4.8
Auto-Restart
Hysteresis Voltage
VC(AR)Hyst
0.8
1
Auto-Restart Duty
Cycle
DC(AR)
CControl = 22 μF; fOSC = 400 kHz;
VX = 0 V
f(AR)
CControl = 22 μF; fOSC = 400 kHz;
VX = 0 V
Auto-Restart
Frequency
-3
5.1
V
V
10
3.8
%
Hz
Line-Sense (L) and External Current Limit (X) Inputs
Line Undervoltage
Threshold Current and
Hysteresis (L Pin)
Line Overvoltage or
Remote ON/OFF
Threshold Current and
Hysteresis (L Pin)
Remote ON/OFF
Negative Threshold
Current and
Hysteresis (X Pin)
IUV
TJ = 25 °C
Threshold from Off to On
48
50
52
Threshold from On to Off
44.5
47
49.5
Hysteresis
2
3
Threshold from On to Off
IOV
TJ = 25 °C
Threshold from Off to On
135
117
Hysteresis
Threshold from On to Off
IREM
TJ = 25 °C
μA
149
μA
131
4
-27
-21.5
Threshold from Off to On
-25.5
Hysteresis
4.5
-16
μA
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DPA422-426
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 33
(Unless Otherwise Specified)
Min
Typ
Max
VL = VC
175
240
380
VL = 0 V
-230
-170
Normal Mode
-270
-230
-185
Remote OFF Using L Pin
-105
-85
-65
IL = IUV
2.05
2.35
2.6
IL = IOV
2.1
2.5
2.9
Units
Line-Sense (L) and External Current Limit (X) Inputs (cont.)
L Pin Short Circuit
Current
IL(SC)
X Pin Short Circuit
Current
IX(SC)
Line Pin Voltage
(Positive Current)
VL
X Pin Voltage
(Negative Current)
Maximum Duty Cycle
Reduction Onset
Threshold Current
Remote OFF DRAIN
Supply Current
L Pin Voltage Turn-On
Threshold in
Synchronous Mode
On-Time Pulse Width
for Synchronization
VX = 0 V
VX
IL(DC)
ID(RMT)
IX = -50 μA
1.35
IX = -150 μA
1.25
TJ = 25 °C
55
VD = 40 V
VX = 0 V
0.6
1.1
VL = VC
0.9
1.5
1
1.4
0.6
ton(sync)
Off-Time Pulse Width
for Synchronization
toff(sync)
Synchronous Turn-On
Delay
tdelay(sync)
μA
V
μA
VL = Floating
VL(TH)
μA
mA
V
fOSC = 400 kHz
120
2250
fOSC = 300 kHz
120
3080
0.25
7.7
μs
250
ns
4
V
ns
From Synchronous On to Drain Turn-On
Frequency (F) Input
FREQUENCY Pin
Threshold Voltage
VF
FREQUENCY Pin Input
Current
IF
FREQUENCY Pin
Delay Time
1.1
VF = 0 V
-0.38
VF = VC
17
tdelay(VF)
120
2
μA
μs
Circuit Protection
Self Protection
Current Limit
(See Note B)
ILIMIT
TJ = 25 °C
DPA422 di/dt = 225 mA/μs
0.86
0.935
1.0
DPA423 di/dt = 300 mA/μs
1.16
1.25
1.34
DPA424 di/dt = 600 mA/μs
2.32
2.50
2.68
DPA425 di/dt = 1.25 A/μs
4.65
5.00
5.35
DPA426 di/dt = 1.75 A/μs
6.50
7.00
7.50
A
23
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Rev. S 12/07
DPA422-426
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 33
(Unless Otherwise Specified)
Min
Initial Current Limit
IINIT
VD = 35 V
0.9 ×
Leading Edge
Blanking Time
tLEB
TJ = 25 °C
Current Limit Delay
TIL(D)
IC = (IC(skip) + IB)/2
Thermal Shutdown
Temperature
TJ(SD)
Thermal Shutdown
Hysteresis
TJ(SD)hyst
Power-Up Reset
Threshold Voltage
VC(RESET)
Parameter
Typ
Max
Units
Circuit Protection (cont.)
A
100
100
130
137
ns
145
27
1.5
ns
°C
°C
2.75
4
V
Output
ON-State Resistance
RDS(ON)
DPA422
ID = 150 mA
TJ = 25 °C
2.60
3.00
TJ = 100 °C
4.00
4.60
DPA423
ID = 300 mA
TJ = 25 °C
1.30
1.50
TJ = 100 °C
2.00
2.30
TJ = 25 °C
0.65
0.75
TJ = 100 °C
1.00
1.15
TJ = 25 °C
0.33
0.38
TJ = 100 °C
0.50
0.58
TJ = 25 °C
0.24
0.28
TJ = 100 °C
0.37
0.43
DPA424
ID = 600 mA
DPA425
ID = 1.25 A
DPA426
ID = 1.75 A
OFF-State Drain
Leakage Current
IDSS
VX, VL = Floating;
VD = 150 V;
TJ = 125 °C;
IC = (IC(skip) + IB)/2
DPA422
33
DPA423
65
DPA424
130
DPA425
260
DPA426
360
Ω
μA
BVDSS
VX, VL = Floating; TJ = 25 °C;
IC = (IC(skip) + IB)/2; See Note C
Rise Time
tR
Measured in a Typical Application
10
ns
Fall Time
tF
Measured in a Typical Application
10
ns
Breakdown Voltage
220
V
24
Rev. S 12/07
www.powerint.com
DPA422-426
Parameter
Symbol
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
See Figure 33
(Unless Otherwise Specified)
Min
See Note D
16
IC = (IC(skip) + IB)/2; TJ = 25 °C
5.6
Typ
Max
Units
Supply Voltage Characteristics
DRAIN Supply Voltage
Shunt Regulator
Voltage
VC(SHUNT)
Shunt Regulator
Temperature Drift
CONTROL Supply/
Discharge Current
IC = (IC(skip) + IB)/2
ICD1
ICD2
Output
MOSFET Enabled
VL = 0 V;
fOSC = 400 kHz
V
5.85
6.0
±50
PPM/°C
DPA422
1.6
2.0
2.4
DPA423
1.9
2.3
2.7
DPA424
2.6
3.0
3.4
DPA425
3.7
4.3
4.8
DPA426
4.8
5.4
6
0.4
0.73
1.2
Output MOSFET Disabled
VL = 0 V; fOSC = 400 kHz
V
mA
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature.
B. For externally adjusted current limit values, please refer to Figure 35 (Current Limit vs. External Current Limit Resistance) in the
Typical Performance Characteristics section.
C. Breakdown voltage may be checked against minimum BVDSS specification by ramping the DRAIN pin voltage up to but not
exceeding minimum BVDSS.
D. It is possible to start up and operate DPA-Switch at DRAIN voltages well below 16 V. However, the CONTROL pin charging
current is reduced, which affects start-up time, auto-restart frequency, and auto-restart duty cycle. Refer to Figure 45, the
characteristic graph on CONTROL pin charge current (IC) vs. DRAIN voltage for low voltage operation characteristics.
25
www.powerint.com
Rev. S 12/07
DPA422-426
t2
t1
HV
90%
90%
DRAIN
VOLTAGE
t
D= 1
t2
10%
0V
PI-2039-033001
1.4
100
DRAIN Current (Normalized)
PI-2880-060302
CONTROL Pin Current (mA)
120
80
60
40
Dynamic
1
=
Impedance Slope
20
PI-2889-061302
Figure 30. Duty Cycle Measurement.
tLEB (Blanking Time) +
tIL(D) (Current Limit Delay)
1.2
1
0.8
0.6
0.4
Temperature Range:
-40 °C to 125 °C
0.2
0
0
0
2
4
6
8
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
10
Time (μs)
CONTROL Pin Voltage (V)
Figure 32. Typical Drain Operation Current Envelope.
Figure 31. CONTROL Pin I-V Characteristic.
S1
470 Ω
5W
0-200 kΩ
5-50 V
40 V
L
470 Ω
D
CONTROL
C
C
DPA-Switch
S2
S4
0-15 V
47 μF
0.1 μF
F
X
S
S3
0-70 kΩ
NOTE: This test circuit is not applicable for current limit or output characteristic measurements.
PI-2860-050602
Figure 33. DPA-Switch General Test Circuit.
26
Rev. S 12/07
www.powerint.com
DPA422-426
BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS
The following precautions should be followed when testing
DPA-Switch by itself outside of a power supply. The schematic
shown in Figure 33 is suggested for laboratory testing of
DPA-Switch.
When the DRAIN pin supply is turned on, the part will be in the
auto-restart mode. The CONTROL pin voltage will be
oscillating at a low frequency between 4.8 V and 5.8 V and the
drain is turned on every eighth cycle of the CONTROL pin
oscillation. If the CONTROL pin power supply is turned on
while in this auto-restart mode, there is only a 12.5% chance
that the CONTROL pin oscillation will be in the correct state
(drain active state) so that the continuous drain voltage
waveform may be observed. It is recommended that the VC
power supply be turned on first and the DRAIN pin power
supply second if continuous drain voltage waveforms are to be
observed. The 12.5% chance of being in the correct state is
due to the divide-by-8 counter. Temporarily shorting the
CONTROL pin to the SOURCE pin will reset DPA-Switch, which
then will come up in the correct state.
1.1
PI-2838-032202
Current Limit
(Normalized to Internal Current Limit)
Typical Performance Characteristics
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-230
-180
-130
-80
-30
0
IX (μA)
1.1
PI-2839-032202
Current Limit
(Normalized to Internal Current Limit)
Figure 34. Current Limit vs. EXTERNAL CURRENT LIMIT Pin Current.
1.0
0.9
Maximum
0.8
0.7
Minimum
0.6
0.5
Typical
0.4
0.3
0.2
0.1
0
5
10
15
20
25
30
35
External Current Limit Resistor RIL (kΩ)
Figure 35. Current Limit vs. External Current Limit Resistance.
27
www.powerint.com
Rev. S 12/07
DPA422-426
Typical Performance Characteristics (cont.)
0.8
0.6
0.4
0.2
PI-2866-051702
1.0
1.2
Current Limit
(Normalized to 25 °C)
PI-2868-051502
Output Frequency
(Normalized to 25 °C)
1.2
1.0
0.8
0.6
0.4
0.2
0
-50 -25
0
25
50
0
75 100 125 150
-50 -25
Junction Temperature (°C)
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 36. Frequency vs. Temperature.
Figure 37. Internal Current Limit vs. Temperature.
0.8
0.6
0.4
0.2
PI-2865-051702
Current Limit
(Normalized to 25 °C)
1.0
1.2
Overvoltage Threshold
(Normalized to 25 °C)
PI-2872-051602
1.2
1.0
0.8
0.6
0.4
0.2
0
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
0.8
0.6
0.4
0.2
0
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 40. Under-Voltage Threshold vs. Temperature.
50
75 100 125 150
7.0
LINE-SENSE Pin Voltage (V)
PI-2867-051502
Under-Voltage Threshold
(Normalized to 25 °C)
1.0
25
Figure 39. Overvoltage Threshold vs. Temperature.
Figure 38. External Current Limit vs. Temperature with
RIL = 12 kΩ.
1.2
0
Junction Temperature (°C)
PI-2871-051502
0
-50 -25
6.0
5.0
4.0
3.0
2.0
1.0
0.0
-200 -150 -100 -50
0
50 100 150 200 250
LINE-SENSE Pin Current (μA)
Figure 41. LINE-SENSE Pin Voltage vs. Current.
28
Rev. S 12/07
www.powerint.com
DPA422-426
Typical Performance Characteristics (cont.)
-200 μA ≤ IX ≤ -25 μA
1.2
1.0
0.8
0.6
0.4
1.2
PI-2863-011904
VX = 1.375 - ⏐IX⏐x 843 kΩ
CONTROL Pin Current
(Normalized to 25 °C)
1.4
PI-2869-051502
1.0
0.8
0.6
0.4
0.2
0.2
0
0
-225 -175
-125
-75
-25
-250
-200
-150
-100
-50
0
-50 -25
PI-2864-051702
Onset Threshold Current
(Normalized to 25 °C)
1.2
1.0
0.8
0.6
0.4
0.2
25
50
75 100 125 150
Figure 43. CONTROL Pin Current at Minimum Duty
Cycle vs. Temperature.
5.0
VC = 5 V
4.5
CONTROL Pin
Charging Current (mA)
Figure 42. EXTERNAL CURRENT LIMIT Pin Voltage vs. Current
0
Junction Temperature (°C)
EXTERNAL CURRENT LIMIT Pin Current (μA)
PI-2841-051502
EXTERNAL CURRENT LIMIT
Pin Voltage (V)
1.6
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
-50 -25
0
25
50
0
75 100 125 150
10
20
0.8
0.6
0.4
0.2
0
-50 -20
50
60
PI-176B-033001
1.1
Breakdown Voltage
(Normalized to 25 °C)
1.0
40
Figure 45. IC vs. DRAIN Voltage.
PI-2870-051502
Remote OFF DRAIN Supply Current
(Normalized to 25 °C)
Figure 44. Max. Duty Cycle Reduction Onset Threshold
Current vs. Temperature.
1.2
30
DRAIN Voltage (V)
Junction Temperature (°C)
1.0
0.9
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 46. Remote OFF DRAIN Supply Current vs. Temperature.
-50 -25
0
25
50
75 100 125 150
Junction Temperature (°C)
Figure 47. Breakdown Voltage vs. Temperature.
29
www.powerint.com
Rev. S 12/07
DPA422-426
Typical Performance Characteristics (cont.)
Drain Current (A)
16
14
TCASE = 25 °C
12
10
8
TCASE = 100 °C
6
4
2.5
PI-2850-011904
Scaling Factors:
DPA423 = 0.18
DPA424 = 0.36
DPA425 = 0.72
DPA426 = 1.00
On-resistance
(Normalized to 25 °C)
18
PI-2849-050302
20
2
1.5
1
0.5
2
0
0
1
2
3
4
5
-50 -25
Drain Voltage (V)
25
50
75 100 125 150
Temperature (°C)
Figure 49. On-Resistance vs. Temperature.
Scaling Factors:
DPA423 = 0.18
DPA424 = 0.36
DPA425 = 0.72
DPA426 = 1.00
1000
100
2.5
Switching Loss (W) at 400 kHz
10000
PI-2851-011904
Figure 48. Output Characteristics.
Capacitance (pF)
0
10
PI-2877-061704
0
Data taken from a typical
forward converter design.
2
1.5
Scaling Factors:
DPA423 = 0.08
DPA424 = 0.20
DPA425 = 0.55
DPA426 = 1.00
1
0.5
0
0
20
40
60
80 100 120 140 160
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
In-Circuit Peak Drain Current Normalized to
Nominal Device Internal Current Limit
DRAIN Voltage (V)
Figure 50. COSS vs. DRAIN Voltage.
Figure 51. Typical Switching Loss.
Part Ordering Information
• DPA-Switch Product Family
• Series Number
• Package Identifier
G
Plastic Surface Mount DIP
P
Plastic DIP
R
Plastic TO-263-7C (available only with TL option)
(422, 423, 424 & 425 only)
• Lead Finish
Blank
N
Standard (Sn Pb)
Pure Matte Tin (Pb-Free) (P & G)
• Tape & Reel and Other Options
Blank
DPA 423 G N - TL
TL
Standard Configurations
Tape & Reel, (G package: 1000 min./mult., R package: 750 min./mult.)
30
Rev. S 12/07
www.powerint.com
DPA422-426
DIP-8
DIM
inches
D S .004 (.10)
mm
8
A
B
C
G
H
J1
J2
K
L
M
N
P
Q
0.367-0.387
0.240-0.260
0.125-0.145
0.015-0.040
0.120-0.140
0.057-0.068
0.014-0.022
0.008-0.015
0.100 BSC
0.030 (MIN)
0.300-0.320
0.300-0.390
0.300 BSC
5
-E-
9.32-9.83
6.10-6.60
3.18-3.68
0.38-1.02
3.05-3.56
1.45-1.73
0.36-0.56
0.20-0.38
2.54 BSC
0.76 (MIN)
7.62-8.13
7.62-9.91
7.62 BSC
B
1
4
-D-
A
M
J1
Notes:
1. Package dimensions conform to JEDEC
specification MS-001-AB for standard dual in-line
(DIP) package .300 inch row spacing
(PLASTIC) 8 leads (issue B, 7/85).
2. Controlling dimensions are inches.
3. Dimensions shown do not include mold flash
G
or other protrusions. Mold flash or
protrusions shall not exceed .006 (.15) on any
side.
L
4. D, E and F are reference datums on the molded
body.
N
C
-FH
K
Q
J2
P08A
P
PI-2076-101102
SMD-8
D S .004 (.10)
-E-
8
DIM
inches
mm
A
B
C
G
H
J1
J2
J3
J4
K
L
M
P
a
0.367-0.387
0.240-0.260
0.125-0.145
0.004-0.012
0.036-0.044
0.057-0.068
0.048-0.053
0.032-0.037
0.007-0.011
0.010-0.012
0.100 BSC
0.030 (MIN)
0.372-0.388
0-8°
9.32-9.83
6.10-6.60
3.18-3.68
0.10-0.30
0.91-1.12
1.45-1.73
1.22-1.35
0.81-0.94
0.18-0.28
0.25-0.30
2.54 BSC
0.76 (MIN)
9.45-9.86
0-8°
5
1
E S .010 (.25)
P
B
.420
.046 .060
.080
Pin 1
4
L
.086
.186
.286
-D-
A
M
.060 .046
Solder Pad Dimensions
J1
C
K
-F.004 (.10)
J3
G08A
J4
J2
.010 (.25) M A S
a
G
H
Notes:
1. Package dimensions conform to JEDEC
specification MS-001-AB (issue B, 7/85)
except for lead shape and size.
2. Controlling dimensions are inches.
3. Dimensions shown do not include mold
flash or other protrusions. Mold flash
or protrusions shall not exceed .006 (.15)
on any side.
4. D, E and F are reference datums on the
molded body.
PI-2077-041003
31
www.powerint.com
Rev. S 12/07
DPA422-426
TO-263-7C
.390 (9.91)
.420 (10.67)
.045 (1.14)
.055 (1.40)
.245 (6.22)
MIN
.055 (1.40)
.066 (1.68)
.326 (8.28)
.336 (8.53)
.225 (5.72)
MIN
.580 (14.73)
.620 (15.75)
.208 (5.28)
Ref.
-A0.68 (1.73)
MIN
LD #1
.024 (0.61)
.034 (0.86)
.100 (2.54)
REF
.050 (1.27)
.000 (0.00)
.010 (0.25)
.090 (2.29)
.110 (2.79)
.010 (0.25)
.012 (0.30)
.024 (0.61)
0°- 8°
.315 (8.00)
.380 (9.65)
Solder Pad
Dimensions
.638 (16.21)
.128 (3.25)
.050 (1.27)
.038 (0.97)
.165 (4.19)
.185 (4.70)
.004 (0.10)
Notes:
1. Package Outline Exclusive of Mold Flash & Metal Burr.
2. Package Outline Inclusive of Plating Thickness.
3. Foot Length Measured at Intercept Point Between
Datum A Lead Surface.
4. Controlling Dimensions are in Inches. Millimeter
Dimensions are shown in Parentheses.
R07C
5. Minimum metal to metal spacing at the package body
for the omitted pin locations is .068 in. (1.73 mm).
PI-2664-122004
32
Rev. S 12/07
www.powerint.com
DPA422-426
Notes
33
www.powerint.com
Rev. S 12/07
DPA422-426
Notes
34
Rev. S 12/07
www.powerint.com
DPA422-426
Revision
Notes
Date
F
Final release data sheet.
6/02
G
Updated Figure 25 and text description.
9/02
H
Corrected missing text on page 9 and corrected Table 4.
Updated R package description.
Revised thermal impedances (qJA), DCMIN, VF, IF, and BVDSS.
Updated Figure 25 and description in text.
4/03
I
Corrected text errors on pp. 1, 7 and 20.
5/03
J
Figure 25 and description in text updated.
5/03
K
Added P and G packages.
1/04
L
Corrected Figure 3.
4/04
M
Added package information to Table 1.
Revised Figure 13.
Added lead-free ordering information.
12/04
N
Minor error corrections.
2/05
O
Added S-PAK.
7/05
P
Added notes to Table 6.
7/05
Q
Updated Figure 27 to best reflect current requirements for PoE.
5/06
R
Added DPA422.
2/07
S
Removed S-Pack.
12/07
35
www.powerint.com
Rev. S 12/07
For the latest updates, visit our website: www.powerint.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES
NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by
one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A
complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under
certain patent rights as set forth at http://www.powerint.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii)
whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant
injury or death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert
and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©2007, Power Integrations, Inc.
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