1/13-Inch System-On-A-Chip (SOC) CMOS Digital Image Sensor

‡
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Features
1/13-Inch System-On-A-Chip (SOC) CMOS Digital
Image Sensor
MT9V124 Datasheet, Rev. C
For the latest datasheet, please visit www.onsemi.com
Features
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Table 1:
Superior low-light performance
Ultra-low-power
VGA video at 30fps
Internal master clock generated by on-chip phase
locked loop (PLL) oscillator
Electronic rolling shutter (ERS), progressive scan
Integrated image flow processor (IFP) for single-die
camera module
One-time programmable memory (OTPM)
Automatic image correction and enhancement,
including four-channel lens shading correction
Image scaling with anti-aliasing
Supports ITU-R BT.656 format with Odd Timing
code
Two-wire serial interface providing access to
registers and microcontroller memory
Selectable output data format: YCbCr, 565RGB, and
RAW8+2-bit, BT656
High Speed serial data output in 12-bit packet
Independently configurable gamma correction
Direct XDMA access (reducing serial commands)
Integrated hue rotation ±22°
Key Parameters
Parameter
Typical Value
Optical format
1/13-inch
Active pixels
648 x 488 = 0.3 Mp (VGA)
Pixel size
1.75m
Color filter array
RGB Bayer
Shutter type
Electronic rolling shutter (ERS)
Input clock range
18 – 44 MHz
Output
12-bit packet
LVDS
Frame rate, full
resolution
30 fps
Responsivity
1.65 V/lux*sec
SNRMAX
33.4 dB
Dynamic range
Supply
voltage
Analog
58 dB
2.5–3.1V
Digital
1.7–1.95V
Digital I/O
1.7–1.95V or 2.5–3.1V
Power consumption
55 mW
Operating temperature
–30 °C to +70 °C
(ambient) -TA
Applications
• Medical tools, device
• Biometrics
• Industrial application
Chief ray angle
24°
Package options
Bare die, CSP
General Description
ON Semiconductor's MT9V124 is a 1/13-inch CMOS
digital image sensor with an active-pixel array of 648H
x 488V. It includes sophisticated camera functions
such as auto exposure control, auto white balance,
black level control, flicker detection and avoidance,
and defect correction. It is designed for low light performance. It is programmable through a simple twowire serial interface. The MT9V124 produces extraordinarily clear, sharp digital pictures that make it the perfect choice for a wide range of medical and industrial
applications.
MT9V124_DS Rev.C Pub. 5/15 EN
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©Semiconductor Components Industries, LLC 2015,
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Ordering Information
Ordering Information
Table 2:
Available Part Numbers
Part Number
Product Description
Orderable Product Attribute Description
MT9V124D00STCK22DC1-200
RGB color die
Die Sales, 200 m Thickness
MT9V124EBKSTC-CR
CSP with 400 m coverglass
Chip Tray without Protective Film
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©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Register and Variable Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Serial Low Voltage Differential Signaling (LVDS) Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
One-Time Programming Memory (OTPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Spectral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
List of Figures
List of Figures
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Figure 30:
MT9V124 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Typical Configuration (Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
25-ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Pixel Color Pattern Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Six Pixels in Normal and Column Mirror Readout Mode (Internal Data Format before Serializer).14
Eight Pixels in Normal and Column Skip 2X Readout Mode (Internal Data Format before Serializer)15
Pixel Readout (no skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Pixel Readout (x_odd_inc = 3, y_odd_inc = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Image Flow Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Color Bar Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Gamma Correction Curve. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
0° Hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
–22° Hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
+22° Hue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
BT656 Image Data with Only Odd Field SAV/EAV Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
LVDS Typical Serial Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
LVDS Serial Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Single READ from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Single Read from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Sequential READ, Start from Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Sequential READ, Start from Current Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Single WRITE to Random Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Sequential WRITE, Start at Random Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Chief Ray Angle (CRA) vs. Image Height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Quantum Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Two-Wire Serial Bus Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
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©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Key Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Available Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Status of Output Signals During Reset and Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
RGB Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2-Byte Bayer Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Summary of MT9V124 Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
LVDS Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
LVDS Serial Output Data Timing (for EXTCLK = 22MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
EXTCLK Input Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Operating/Standby Current Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
LVDS Output Port DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
LVDS Output Port DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Two-Wire Serial Interface Timing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Power Up Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
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©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Functional Description
ON Semiconductor’s MT9V124 is a 1/13-inch VGA CMOS digital image sensor with an
integrated advanced camera system. This camera system features a microcontroller
(MCU), a sophisticated image flow processor (IFP), and a serial port (using LVDS
signaling). The microcontroller manages all functions of the camera system and sets key
operation parameters for the sensor core to optimize the quality of raw image data
entering the IFP. The sensor core consists of an active pixel array of 648 x 488 pixels with
programmable timing and control circuitry. It also includes an analog signal chain with
automatic offset correction, programmable gain, and a 10-bit analog-to-digital
converter (ADC).
The entire system-on-a-chip (SOC) has an ultra-low power operational mode and a
superior low-light performance that is particularly suitable for medical applications.
The MT9V124 features ON Semiconductor’s breakthrough low-noise CMOS imaging
technology that achieves near-CCD image quality (based on signal-to-noise ratio and
low-light sensitivity) while maintaining the inherent size, cost, and integration advantages of CMOS.
Architecture Overview
The MT9V124 combines a VGA sensor core with an IFP to form a stand-alone solution
for both image acquisition and processing. Both the sensor core and the IFP have
internal registers that can be controlled by the user. In normal operation, an integrated
microcontroller autonomously controls most aspects of operation. The processed image
data is transmitted to the external host system through an LVDS bus. Figure 1 shows the
major functional blocks of the MT9V124.
Figure 1:
MT9V124 Block Diagram
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©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Sensor Core
The MT9V124 has a color image sensor with a Bayer color filter arrangement and a VGA
active-pixel array with electronic rolling shutter (ERS). The sensor core readout is 10 bits.
The sensor core also supports separate analog and digital gain for all four color channels
(R, Gr, Gb, B).
Image Flow Processor (IFP)
The advanced IFP features and flexible programmability of the MT9V124 can enhance
and optimize the image sensor performance. Built-in optimization algorithms enable
the MT9V124 to operate with factory settings as a fully automatic and highly adaptable
system-on-a-chip (SOC) for most camera systems.
These algorithms include shading correction, defect correction, color interpolation,
edge detection, color correction, aperture correction, and image formatting with cropping and scaling.
Microcontroller Unit (MCU)
The MCU communicates with all functional blocks by way of an internal ON Semiconductor proprietary bus interface. The MCU firmware executes the automatic control
algorithms for exposure and white balance.
System Control
The MT9V124 has a phase-locked loop (PLL) oscillator that can generate the internal
sensor clock from the common system clock. The PLL adjusts the incoming clock
frequency up, allowing the MT9V124 to run at almost any desired resolution and frame
rate within the sensor’s capabilities.
Low-power consumption is a very important requirement for all components of medical
devices. The MT9V124 provides power-conserving features, including an internal soft
standby mode and a hard standby mode.
A two-wire serial interface bus enables read and write access to the MT9V124’s internal
registers and variables. The internal registers control the sensor core, the color pipeline
flow, the output interface, auto white balance (AWB) and auto exposure (AE).
Output Interface
Image data is provided to the host system by a serial LVDS interface. The Start bit, 8-bit
image data, Line_Valid, Frame_Valid and Stop bit are packetized in a 12-bit packet. The
output data format is available in either raw data or processed data. Processed data
format includes YCbCr, RGB-565, BT656 with odd SAV/EAV code. It also supports the
SOC Bypass 8+2 data format over the 12-bit packet.
System Interfaces
Figure 2 on page 8 shows typical MT9V124 device connections. For low-noise operation,
the MT9V124 requires separate power supplies for analog and digital sections. Both
power supply rails should be decoupled from ground using capacitors as close as
possible to the die.
The MT9V124 provides dedicated signals for digital core and I/O power domains that
can be at different voltages. The PLL and analog circuitry require clean power sources.
Table 3, “Pin Descriptions,” on page 9 provides the signal descriptions for the MT9V124.
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©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Typical Configuration (Connection)
Two-wire
serial interface
SDATA
SCLK
Active HIGH standby mode
Analog
power
VAA
VDD
VDD_IO
RPULL-UP2
Digital
core
power
OTPM
power
(optional)
I/O3
power
VPP
Figure 2:
LVDS_N
Rt
STANDBY
Serial
interface
140Ω
External clock in
(18–44 MHz)
EXTCLK
LVDS_P
GND, GND_PLL
VDD_IO3, 4
Notes:
MT9V124_DS Rev.C Pub. 5/15 EN
VDD4
AGND
VAA4
1. This typical configuration shows only one scenario out of multiple possible variations for this sensor.
2. ON Semiconductor recommends a 1.5kresistor value for the two-wire serial interface RPULL-UP;
however, greater values may be used for slower transmission speed.
3. All inputs must be configured with VDD_IO.
4. ON Semiconductor recommends that 0.1μF and 1μF decoupling capacitors for each power supply
are mounted as close as possible to the module (Low-Z path). Actual values and numbers may vary
depending on layout and design considerations, such as capacitor effective series resistance (ESR),
dielectric, or power supply source impedance.
5. LVDS output requires termination resistor (140) to be placed closely at the sensor side.
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©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Signal Descriptions
Table 3:
Pin Descriptions
MT9V124
Sensor Signal
Name
Module
Signal
Name
EXTCLK
Ball Number
Type
Description
EXTCLK
E2
Input
Input clock signal.
STBY
A2
Input
Controls sensor’s standby mode, active HIGH.
SCLK
SCLK
D4
Input
Two-wire serial interface clock.
SDATA
SDATA
E4
I/O
Two-wire serial interface data.
LVDS_P
LVDS_P
E1
Output
LVDS positive output.
LVDS_N
Output
LVDS negative output.
STANDBY
LVDS_N
D2
VDD
VDD
C2, D5
Supply
Digital power (TYP 1.8V).
VAA, VDD_PLL
VAA
C1
Supply
Analog and PLL power (TYP 2.8V).
I/O power supply (TYP 1.8V).
VDD_IO
VDD_IO
C3
Supply
DGND, GND_IO,
GND_PLL
DGND
B3, B5, D1
Supply
AGND
AGND
B1
Supply
Analog ground.
VPP
A1
Supply
OTPM power
DNU
A3,A4,A5,B2,B4,
C4,C5,D3,E3,E5
VPP
DNU
Figure 3:
Digital, I/O, and PLL ground.
25-ball Assignments (Top View)
1
2
3
4
5
STDBY
DNU
DNU
DNU
AGND
DNU
GND
DNU
GND
VAA
VDD
VDD_IO DNU
DNU
GND
LVDS_N
A
VPP
B
C
D
DNU
SCLK
VDD
DNU
SDATA
DNU
E
LVDS_P EXTCLK
Power-On Reset
The MT9V124 includes a power-on reset feature that initiates a reset upon power-up. A
soft reset is issued by writing commands through the two-wire serial interface.
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Functional Description
Standby
The MT9V124 supports two different standby modes:
• Hard standby mode
• Soft standby mode
The hard standby mode is invoked by asserting STANDBY pin. It then disables all the
digital logic within the image sensor, and only supports being awoken by de-asserting
the STANDBY pin. The soft standby mode is enabled by a single register access, which
then disables the sensor core and most of the digital logic. However, the two-wire serial
interface is kept alive, which allows the image sensor to be awoken via a serial register
access.
All output signal status during standby are shown in Table 4.
Table 4:
Status of Output Signals During Reset and Standby
Signal
Reset
Post-Reset
Standby
LVDS_P
LVDS_N
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Module ID
The MT9V124 provides 4 bits of module ID that can be read by the host processor from
register 0x001A[15:12]. The module ID is programmed through the OTPM.
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Image Data Output Interface
The High Speed LVDS output port on MT9V124 can transmit the sensor image data to
the host system over a lengthy differential twisted pair cable.
The MT9V124 provides a serial high-speed output port, which is able for driving standard IEEE 1596.3-1996 LVDS receiver/deserializers such as the DS92LV1212A LVDS
Deserializer by National Semiconductor.
Image data is provided to the host system by the serial LVDS interface. The Start bit, 8-bit
image data, LV, FV, and Stop bit are packetized in a 12-bit packet. The output interface
block can select either raw data or processed data. Processed data format includes
YCbCr, RGB-565, and BT656 with odd SAV/EAV code. It also supports the SOC Bypass
8+2 data format over the 12-bit packet.
The LVDS port is disabled when Hard Standby or Soft Standby is asserted.
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Sensor Control
The sensor core of the MT9V124 is a progressive-scan sensor that generates a stream of
pixel data at a constant frame rate. Figure 4 shows a block diagram of the sensor core. It
includes the VGA active-pixel array. The timing and control circuitry sequences through
the rows of the array, resetting and then reading each row in turn. In the time interval
between resetting a row and reading that row, the pixels in the row integrate incident
light. The exposure is controlled by varying the time interval between reset and readout.
Once a row has been selected, the data from each column is sequenced through an
analog signal chain, including offset correction, gain adjustment, and ADC. The final
stage of sensor core converts the output of the ADC into 10-bit data for each pixel in the
array.
The pixel array contains optically active and light-shielded (dark) pixels. The dark pixels
are used to provide data for the offset-correction algorithms (black level control).
The sensor core contains a set of control and status registers that can be used to control
many aspects of the sensor behavior including the frame size, exposure, and gain
setting. These registers are controlled by the MCU firmware and are also accessible by
the host processor through the two-wire serial interface.
The output from the sensor core is a Bayer pattern; alternate rows are a sequence of
either green and red pixels or blue and green pixels. The offset and gain stages of the
analog signal chain provide per-color control of the pixel data.
Figure 4:
Sensor Core Block Diagram
Control Registers
System Control
Timing
and
Control
Green1/Green2
Channel
VGA
Active-Pixel
Sensor (APS)
Array
Analog
Processing
G1/G2
R/B
ADC
G1/G2
R/B
Digital
Processing
10-Bit
Data Out
Red/Blue
Channel
Sensor Core
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Functional Description
The sensor core uses a Bayer color pattern, as shown in Figure 5. The even-numbered
rows contain green and red pixels; odd-numbered rows contain blue and green pixels.
Even-numbered columns contain green and blue pixels; odd-numbered columns
contain red and green pixels.
Figure 5:
Pixel Color Pattern Detail
Column readout direction
First clear
pixel
B Gb B Gb B Gb B Gb B Gb B
Gr R Gr R Gr R
Gr R
Gr R Gr
B Gb B Gb B Gb B Gb B Gb B
Gr R Gr R Gr R
Gr R
Gr R Gr
B Gb B Gb B Gb B Gb B Gb B
Gr R Gr R Gr R
Gr R
Gr R Gr
B Gb B Gb B Gb B Gb B Gb B
Gr R Gr R Gr R
Gr R
Row readout
direction
Gr R Gr
Black pixels
The MT9V124 sensor core pixel array is shown with pixel (0,0) in the bottom right corner,
which reflects the actual layout of the array on the die. Figure 6 on page 14 shows the
image shown in the sensor during normal operation.
When the image is read out of the sensor, it is read one row at a time, with the rows and
columns sequenced.
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Figure 6:
Imaging a Scene
Lens
Scene
Sensor (rear view)
Row
Readout
Order
Column Readout Order
Pixel (0,0)
The sensor core supports different readout options to modify the image before it is sent
to the IFP. The readout can be limited to a specific window size of the original pixel array.
By changing the readout order, the image can be mirrored in the horizontal direction.
The image output size is set by programming row and column start and end address
registers. The edge pixels in the 648 x 488 array are present to avoid edge effects and
should not be included in the visible window.
When the sensor is configured to mirror the image horizontally, the order of pixel
readout within a row is reversed, so that readout starts from the last column address and
ends at the first column address. Figure 7 shows a sequence of 6 pixels being read out
with normal readout and reverse readout. This change in sensor core output is corrected
by the IFP.
Figure 7:
Six Pixels in Normal and Column Mirror Readout Mode (Internal Data Format before Serializer)
LINE_VALID
Normal readout
DOUT[9:0]
G0
(9:0)
R0
(9:0)
G1
(9:0)
R1
(9:0)
G2
(9:0)
R2
(9:0)
R2
(9:0)
G2
(9:0)
R1
(9:0)
G1
(9:0)
R0
(9:0)
G0
(9:0)
Reverse readout
DOUT[9:0]
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Figure 8:
Eight Pixels in Normal and Column Skip 2X Readout Mode (Internal Data Format before
Serializer)
LINE_VALID
Normal readout
DOUT[9:0]
G0
(9:0)
R0
(9:0)
G1
(9:0)
R1
(9:0)
G0
(9:0)
R0
(9:0)
G2
(9:0)
R2
(9:0)
G2
(9:0)
R2
(9:0)
G3
(9:0)
R3
(9:0)
LINE_VALID
Column skip readout
DOUT[9:0]
Figure 9 on page 15 through Figure on page 17 show the different skipping modes
supported in MT9V124.
Figure 9:
Pixel Readout (no skipping)
X Incrementing
Y Incrementing
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Functional Description
Figure 10:
Pixel Readout (x_odd_inc = 3, y_odd_inc = 1)
X Incrementing
Y Incrementing
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Image Flow Processor
Image control processing in the MT9V124 is implemented in the IFP hardware logic. The
IFP registers can be programmed by the host processor. For normal operation, the
microcontroller automatically adjusts the operational parameters of the IFP. Figure 11
shows the image data processing flow within the IFP.
Figure 11:
Image Flow Processor
RAW 10
Test Pattern
VGA
Pixel Array
ADC
Raw Data
IFP
Digital
Gain
Control,
Shading
Correction
MUX
Defect Correction,
Nosie Reduction,
Color Interpolation,
Statistics
Engine
8-bit
RGB
RGB to YUV
10/12-Bit
RGB
8-bit
YUV
Color Correction
Color Kill
Scaler
Aperture
Correction
Hue Rotate
Output
Formatting
YUV to RGB
Gamma
Correction
(10-to-8 Lookup)
Output
Interface
TX
FIFO
Serializer
LVDS
Output
For normal operation of the MT9V124, streams of raw image data from the sensor core
are continuously fed into the color pipeline. The MT9V124 features an automatic color
bar test pattern generation function to emulate sensor images as shown in Figure 12 on
page 18.
Color bar test pattern generation can be selected by programming a register.
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Figure 12:
Color Bar Test Pattern
Test Pattern
Example
REG= 0x8400, 0x15 // SEQ_CMD
REG= 0x8400, 0x16 // SEQ_CMD
REG= 0x8400, 0x17 // SEQ_CMD
REG= 0x8400, 0x18 // SEQ_CMD
REG= 0x8400, 0x19 // SEQ_CMD
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Image Corrections
Image stream processing starts with multiplication of all pixel values by a programmable
digital gain. This can be independently set to separate values for each color channel (R,
Gr, Gb, B). Independent color channel digital gain can be adjusted with variables.
Lenses tend to produce images whose brightness is significantly attenuated near the
edges. There are also other factors causing fixed pattern signal gradients in images
captured by image sensors. The cumulative result of all these factors is known as image
shading. The MT9V124 has an embedded shading correction module that can be
programmed to counter the shading effects on each individual R, Gb, Gr, and B color
signal.
The IFP performs continuous defect correction that can mask pixel array defects such as
high dark-current (hot) pixels and pixels that are darker or brighter than their neighbors
due to photoresponse nonuniformity. The module is edge-aware with exposure that is
based on configurable thresholds. The thresholds are changed continuously based on
the brightness of the current scene. Enabling and disabling noise reduction, and setting
thresholds can be defined through variable settings.
Color Interpolation and Edge Detection
In the raw data stream fed by the sensor core to the IFP, each pixel is represented by a
10-bit integer, which can be considered proportional to the pixel’s response to a onecolor light stimulus, red, green, or blue, depending on the pixel’s position under the
color filter array. Initial data processing steps, up to and including the defect correction,
preserve the one-color-per-pixel nature of the data stream, but after the defect correction it must be converted to a three-colors-per-pixel stream appropriate for standard
color processing. The conversion is done by an edge-sensitive color interpolation
module. The module adds the incomplete color information available for each pixel
with information extracted from an appropriate set of neighboring pixels. The algorithm
used to select this set and extract the information seeks the best compromise between
preserving edges and filtering out high-frequency noise in flat field areas. The edge
threshold can be set through variable settings.
Color Correction and Aperture Correction
To achieve good color fidelity of the IFP output, interpolated RGB values of all pixels are
subjected to color correction. The IFP multiplies each vector of three pixel colors by a
3 x 3 color correction matrix. The color correction matrix can either be programmed by
the user or automatically selected by the AWB algorithm implemented in the IFP. Color
correction should ideally produce output colors that are independent of the spectral
sensitivity and color crosstalk characteristics of the image sensor. The optimal values of
the color correction matrix elements depend on those sensor characteristics. The color
correction variables can be adjusted through variable settings.
To increase image sharpness, a programmable 2D aperture correction (sharpening filter)
is applied to color-corrected image data. The gain and threshold for 2D correction can
be defined through variable settings.
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Gamma Correction
The gamma correction curve (as shown in Figure 13) is implemented as a piecewise
linear function with 19 knee points, taking 12-bit arguments and mapping them to 8-bit
output. The abscissas of the knee points are fixed at 0, 64, 128, 256, 512, 768, 1024, 1280,
1536, 1792, 2048, 2304, 2560, 2816, 3072, 3328, 3584, 3840, and 4096.
The MT9V124 IFP includes a block for gamma correction that has the capability to
adjust its shape, based on brightness, to enhance the performance under certain
lighting conditions. Two custom gamma correction tables may be uploaded, one corresponding to a brighter lighting condition, the other one corresponding to a darker
lighting condition. The final gamma correction table used depends on the brightness of
the scene and can take the form of either uploaded tables or an interpolated version of
the two tables. A single (non-adjusting) table for all conditions can also be used.
Figure 13:
Gamma Correction Curve
Gamma Correction
300
Output RGB, 8-bit
250
200
0.45
150
100
50
0
0
1000
2000
3000
4000
Input RGB, 12-bit
Special effects like negative image, sepia, or B/W can be applied to the data stream at
this point. These effects can be enabled and selected by registers.
To remove high- or low-light color artifacts, a color kill circuit is included. It affects only
pixels whose luminance exceeds a certain preprogrammed threshold. The U and V
values of those pixels are attenuated proportionally to the difference between their luminance and the threshold.
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Image Scaling and Cropping
To ensure that the size of images output by the MT9V124 can be tailored to the needs of
all users, the IFP includes a scaler module. When enabled, this module performs rescaling of incoming images—shrinks them to selected width and height without reducing
the field of view and without discarding any pixel values. The scaler ratios are computed
from image output size and the FOV. The scaled output must not be greater than 352.
Output widths greater than this must not use the scaler.
By configuring the cropped and output windows to various sizes, different zooming
levels for 4X, 2X, and 1X can be achieved. The height and width definitions for the output
window must be equal to or smaller than the cropped image. The image cropping and
scaler module can be used together to implement a digital zoom.
Hue Rotate
The MT9V124 has integrated hue rotate. This feature will help for improving the color
image quality and give customers the flexibility for fine color adjustment and special
color effects.
Figure 14:
0° Hue
REG= 0xA00F, 0x00 // CAM_HUE_ANGLE
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Figure 15:
–22° Hue
REG= 0xA00F, 0xEA // CAM_HUE_ANGLE
Figure 16:
+22° Hue
REG= 0xA00F, 0x16 // CAM_HUE_ANGLE
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Auto Exposure
The AE algorithm performs automatic adjustments of the image brightness by
controlling exposure time, and analog gains of the sensor core as well as digital gains
applied to the image.
The AE algorithm analyzes image statistics collected by the exposure measurement
engine, and then programs the sensor core and color pipeline to achieve the desired
exposure. AE uses 4 x 4 exposure statistics windows, which can be scaled in size to cover
any portion of the image.
The MT9V124 uses Average Brightness Tracking (Average Y), which uses a constant
average tracking algorithm where a target brightness value is compared to a current
brightness value, and the gain and integration time are adjusted accordingly to meet the
target requirement. The MT9V124 also has a weighted AE algorithm that allows the
sensor to be configured to respond to scene illuminance based on each of the weights in
the windows.
The auto exposure can be configured to respond to scene illuminance based on certain
criteria by adjusting gains and integration time based on scene brightness.
Auto White Balance
The MT9V124 has a built-in AWB algorithm designed to compensate for the effects of
changing spectra of the scene illumination on the quality of the color rendition. The
algorithm consists of two major parts: a measurement engine performing statistical
analysis of the image and a module performing the selection of the optimal color correction matrix, digital, and sensor core analog gains. While default settings of these algorithms are adequate in most situations, the user can reprogram base color correction
matrices and place limits on color channel gains.
The AWB algorithm estimates the dominant color temperature of a light source in a
scene and adjusts the B/G, R/G gain ratios accordingly to produce an image for sRGB
display in which grey and white surfaces are reproduced faithfully. This usually means
that R,G,B are roughly equal for these surfaces hence the word “balance”.
The AWB algorithm uses statistics collected from the last frame to calculate the required
B/G and R/G ratios and set the blue and red analog sensor gains and digital SOC gains to
reproduce the most accurate grey and white surfaces
Flicker Detection and Avoidance
Flicker occurs when the integration time is not an integer multiple of the period of the
light intensity. The automatic flicker detection module does not compensate for the
flicker, but rather avoids it by detecting the flicker frequency and adjusting the integration time. For integration times below the light intensity period (10ms for 50Hz environment, 8.33ms for 60Hz environment), flicker cannot be avoided.
While this fast flickering is marginally detectable by the human eye, it is very noticeable
in digital images because the flicker period of the light source is very close to the range of
digital images’ exposure times.
Many CMOS sensors use a “rolling shutter” readout mechanism that greatly improves
sensor data readout times. This allows pixel data to be read out much sooner than other
methods that wait until the entire exposure is complete before reading out the first pixel
data. The rolling shutter mechanism exposes a range of pixel rows at a time. This range
of exposed pixels starts at the top of the image and then “rolls” down to the bottom
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Functional Description
during the exposure period of the frame. As each pixel row completes its exposure, it is
ready to be read out. If the light source oscillates (flickers) during this rolling shutter
exposure period, the image appears to have alternating light and dark horizontal bands.
If the sensor uses the traditional snapshot readout mechanism, in which all pixels are
exposed at the same time and then the pixel data is read out, then the image may appear
overexposed or underexposed due to light fluctuations from the flickering light source.
Lights operating on AC electric systems produce light flickering at a frequency of 100Hz
or 120Hz, twice the frequency of the power line.
To avoid this flicker effect, the exposure times must be multiples of the light source
flicker periods. For example, in a scene lit by 120Hz lighting, the available exposure
times are 8.33ms, 16.67ms, 25ms, 33.33ms, and so on. (The need for an exposure time
less than 8.33ms under artificial light is extremely rare.)
In this case, the AE algorithm must limit the integration time to an integer multiple of
the light’s flicker period.
By default, the MT9V124 does all of this automatically, ensuring that all exposure times
avoid any noticeable light flicker in the scene. The MT9V124 AE algorithm is always
setting exposure times to be integer multipliers of either 100Hz or 120Hz. The flicker
detection module keeps monitoring the incoming frames to detect whether the scene's
lighting has changed to the other of the two light source frequencies. A 50Hz/60Hz Tungsten lamp can be used to calibrate the flicker detect settings.
Output Conversion and Formatting
The YUV data stream can either exit the color pipeline as is or be converted before exit to
an alternative YUV or RGB data format.
Color Conversion Formulas
Y'U'V'
This conversion is BT 601 scaled to make YUV range from 0 through 255. This setting is
recommended for JPEG encoding and is the most popular, although it is not well defined
and often misused in various operating systems.
Y  = 0.299  R  + 0.587  G  + 0.114  B 
(EQ 1)
U  = 0.564  (B  – Y   + 128
(EQ 2)
V  = 0.713  (R  – Y   + 128
(EQ 3)
There is an option where 128 is not added to U'V'.
Y'Cb'Cr' Using sRGB Formulas
The MT9V124 implements the sRGB standard. This option provides YCbCr coefficients
for a correct 4:2:2 transmission.
Note:
16 < Y601< 235; 16 < Cb < 240; 16 < Cr < 240; and 0 < = RGB < = 255
Y  = (0.2126  R  + 0.7152  G  + 0.0722  B    (219  256) + 16
MT9V124_DS Rev.C Pub. 5/15 EN
(EQ 4)
Cb  = 0.5389  (B  – Y    (224  256) + 128
(EQ 5)
Cr  = 0.635  (R  – Y    (224  256) + 128
(EQ 6)
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
Y'U'V' Using sRGB Formulas
These are similar to the previous set of formulas, but have YUV spanning a range of 0
through 255.
Y  = 0.2126  R  + 0.7152  G  + 0.0722  B  + 128
(EQ 7)
U  = 0.5389  (B  – Y  ) + 128 = – 0.1146  R ' – 0.3854  G' + 0.5  B' + 128
(EQ 8)
V  = 0.635  (R  – Y   + 128 = 0.5  R ' – 0.4542  G ' – 0.0458  B' + 128
(EQ 9)
There is an option to disable adding 128 to U'V'. The reverse transform is as follows:
R  = Y + 1.5748   V – 128 
(EQ 10)
G  = Y – 0.1873  (U – 128  – 0.4681  (V – 128)
(EQ 11)
B  = Y + 1.8556  (U – 128)
(EQ 12)
Uncompressed YUV/RGB Data Ordering
The MT9V124 supports swapping YCbCr mode, as illustrated in Table 5.
Table 5:
YCbCr Output Data Ordering
Mode
Data Sequence
Default (no swap)
Swapped CrCb
Swapped YC
Swapped CrCb, YC
Yi
Yi
Cbi
Cri
Cbi
Cri
Yi
Yi
Cri
Cbi
Yi+1
Yi+1
Yi+1
Yi+1
Cri
Cbi
The RGB output data ordering in default mode is shown in Table 6. The odd and even
bytes are swapped when luma/chroma swap is enabled. R and B channels are bitwise
swapped when chroma swap is enabled.
Table 6:
RGB Ordering in Default Mode
Mode (Swap Disabled)
Byte
D7D6D5D4D3D2D1D0
565RGB
Odd
Even
R7R6R5R4R3G7G6G5
G4G3G2B7B6B5B4B3
Uncompressed 10-Bit Bypass Output
Raw 10-bit Bayer data from the sensor core can be output in bypass mode by using
DOUT[7:0] with a special 8 + 2 data format, shown in Table 7.
Table 7:
2-Byte Bayer Format
MT9V124_DS Rev.C Pub. 5/15 EN
Byte
Bits Used
Bit Sequence
Odd bytes
8 data bits
D9D8D7D6D5D4D3D2
Even bytes
2 data bits + 6 unused bits
0 0 0 0 0 0 D1D0
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Functional Description
BT656
YUV data can also be output in BT656 format with only Odd field SAV/EAV codes. The
BT656 data output will be progressive data and not interlaced (R0x3C00[5] = 1). Figure 17
depicts the data format before the serializer internal to the device, or after the external
deserializer.
Figure 17:
% BUB <>
BT656 Image Data with Only Odd Field SAV/EAV Codes
# MBOL JOH
''
4"7
$C
:
$S
:
$C
* N BHF
:
$S
:
''
%
&"7
# MBOL JOH
) # MBOL
) # MBOL
''
4"7
$C
:
$S
:
$C
* N BHF
:
$S
:
''
&"7
#
# MBOL JOH
) # MBOL
"DUJWF7JEFP
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Register and Variable Description
Register and Variable Description
To change internal registers and RAM variables of MT9V124, use the two-wire serial
interface through the external host device.
The sequencer is responsible for coordinating all events triggered by the user.
The sequencer provides the high-level control of the MT9V124. Commands are written
to the command variable to start streaming, stop streaming, and to select test pattern
modes. Command execution is confirmed by reading back the command variable with a
value of zero. The sequencer state variable can also be checked for transition to the
desired state. All configuration of the sensor (start/stop row/column, mirror, skipping)
and the SOC (image size, format) and automatic algorithms for AE, AWB, low light, are
performed when the sequencer is in the stopped state.
When the sequencer is in the idle or test pattern state the algorithms and register
updates are not performed, allowing the host complete manual control
Table 8:
MT9V124_DS Rev.C Pub. 5/15 EN
Summary of MT9V124 Variables
Name
Info
Monitor Variables
General information
Sequencer Variables
Programming control interface
FD Variables
Flicker Detect
AE_Track Variables
Auto Exposure
AWB Variables
Auto White Balance
Stat Variables
Statistics
Low Light Variables
Low Light
Cam Variables
Sensor specific settings
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MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Serial Low Voltage Differential Signaling (LVDS) Output
Serial Low Voltage Differential Signaling (LVDS) Output
The MT9V124 provides a serial high-speed output port which supports all the data
formats. MT9V124 is intended to drive standard IEEE 1596.3-1996LVDS receiver/deserializers. The internal serializer transforms the parallel data into serial in a 12-bit packet,
allowing the data be transported via a lengthy (several meters) twisted pair cable.
The LVDS output requires a differential termination resistor (Rtx_term = 140±1%) that
must be provided off-chip and close to the LVDS pins.
Figure 18:
LVDS Typical Serial Interface
LVDS Data Packet Format
The LVDS output is the standard 12-bit package with start bit, 10-bit payload and stop
bit supported by many off the shelf deserializers.
Table 9 describes the LVDS packet format; Figure 19 shows the LVDS data timing.
Table 9:
MT9V124_DS Rev.C Pub. 5/15 EN
LVDS Packet Format
12-Bit Packet
Data Format
Bit[0]
Bit[1]
Bit[2]
Bit[3]
Bit[4]
Bit[5]
Bit[6]
Bit[7]
Bit[8]
Bit[9]
Bit[10]
Bit[11]
START BIT “1”
PixelData[0]
PixelData[1]
PixelData[2]
PixelData[3]
PixelData[4]
PixelData[5]
PixelData[6]
PixelData[7]
LINEVALID (LV)
FRAMEVALID (FV)
STOP BIT “0”
28
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Serial Low Voltage Differential Signaling (LVDS) Output
Figure 19:
LVDS Serial Output Timing
Internal Shift Clock
LVDS Serial Out
START(1)
D0
D1
D2
D3
D4
D5
D6
D7
LV
FV
STOP(0)
tDW
Table 10:
LVDS Serial Output Data Timing (for EXTCLK = 22MHz)
Name
Min
Typical
Max
Unit
tDW
1/tDW
3.78
216
3.78
264
4.629
264
nS
Mbps
Table 11:
EXTCLK Input Range
Name
Min
Typical
Max
Unit
EXTCLK
18
22
44
MHz
If EXTCLK is greater than 22 MHz, the PLL must be set to obtain an equivalent internal
pixel clock to 22 MHz. The internal pixel clock is multiplied by 12 to achieve the serializer output frequency of maximum 264 MHz.
MT9V124_DS Rev.C Pub. 5/15 EN
29
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Two-Wire Serial Interface
Two-Wire Serial Interface
The two-wire serial interface bus enables read and write access to control and status
registers within the MT9V124.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The MT9V124 always operates in slave mode. The host (master)
generates a clock (SCLK) that is an input to the MT9V124 and is used to synchronize
transfers. Data is transferred between the master and the slave on a bidirectional signal
(SDATA).
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of lowlevel protocol elements, as follows:
1. a (repeated) start condition
2. a slave address/data direction byte
3. a 16-bit register address (8-bit addresses are not supported)
4. an (a no) acknowledge bit
5. a 16-bit data transfer (8-bit data transfers are supported using XDMA byte access)
6. a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with
a start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a repeated start or restart condition.
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Data is transferred serially, 8 bits at a time, with the most significant bit (MSB) transmitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit.
This data transfer mechanism is used for the slave address/data direction byte and for
message bytes. One data bit is transferred during each SCLK clock period. SDATA can
change when SCLK is LOW and must be stable while SCLK is HIGH.
MT9V124 Slave Address
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The
slave address default is 0x7A.
Messages
Message bytes are used for sending MT9V124 internal register addresses and data. The
host should always use 16-bit address (two bytes) and 16-bit data to access internal
registers. Refer to READ and WRITE cycles in Figure 20 on page 31 through Figure 24 on
page 33.
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowledge bit by driving SDATA LOW. For data transfers, SDATA can change when SCLK is LOW
and must be stable while SCLK is HIGH.
MT9V124_DS Rev.C Pub. 5/15 EN
30
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Two-Wire Serial Interface
The no-acknowledge bit is generated when the receiver does not drive SDATA low during
the SCLK clock period following a data transfer. A no-acknowledge bit is used to terminate a read sequence.
Typical Operation
A typical READ or WRITE sequence begins by the master generating a start condition on
the bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a READ or a WRITE, where a “0”
indicates a WRITE and a “1” indicates a READ. If the address matches the address of the
slave device, the slave device acknowledges receipt of the address by generating an
acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the 16-bit register address to which
a WRITE will take place. This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master will then transfer the 16-bit data, as two 8-bit sequences and the
slave sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master stops writing by generating a (re)start or stop condition. If the
request was a READ, the master sends the 8-bit write slave address/data direction byte
and 16-bit register address, just as in the WRITE request. The master then generates a
(re)start condition and the 8-bit read slave address/data direction byte, and clocks out
the register data, 8 bits at a time. The master generates an acknowledge bit after each
8-bit transfer. The data transfer is stopped when the master sends a no-acknowledge bit.
Single READ from Random Location
Figure 20 shows the typical READ cycle of the host to MT9V124. The first 2 bytes sent by
the host are an internal 16-bit register address. The following 2-byte READ cycle sends
the contents of the registers to host.
Figure 20:
Single READ from Random Location
Previous Reg Address, N
S
Slave Address
S = start condition
P = stop condition
Sr = restart condition
A = acknowledge
A = no-acknowledge
MT9V124_DS Rev.C Pub. 5/15 EN
0 A Reg Address[15:8]
A
Reg Address, M
Reg Address[7:0]
A Sr
Slave Address
1 A
M+1
Read Data
A P
slave to master
master to slave
31
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Two-Wire Serial Interface
Single READ from Current Location
Figure 21 shows the single READ cycle without writing the address. The internal address
will use the previous address value written to the register.
Figure 21:
Single Read from Current Location
Previous
Reg Address,
N
Previous
Reg Address,
N
S
S
SlaveAddress
Address
Slave
1 1A
A
N+1
Read Data Read Data
A
Read Data
[7:0] A A
[15:8]
P
N+2
Reg Address, N+1
N+L-1
N+2
Read Data
S
Slave A
Address Read1Data
A [15:8] A
Read Data
A
Read Data
A PData
[7:0] Read
A
Sequential READ, Start from Random Location
This sequence (Figure 22) starts in the same way as the single READ from random location (Figure 20 on page 31). Instead of generating a no-acknowledge bit after the first
byte of data has been transferred, the master generates an acknowledge bit and
continues to perform byte READs until “L” bytes have been read.
Figure 22:
Sequential READ, Start from Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
M+2
Read Data
A
A
Reg Address, M
Reg Address[7:0]
Slave Address
M+L-2
M+3
Read Data
A Sr
Read Data
A
1 A
M+L-1
Read Data
A
M+1
Read Data
A
M+L
A S
Sequential READ, Start from Current Location
This sequence (Figure 23) starts in the same way as the single READ from current location (Figure 21). Instead of generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge bit and continues to
perform byte reads until “L” bytes have been read.
Figure 23:
Sequential READ, Start from Current Location
Previous Reg Address, N
S
Slave Address
MT9V124_DS Rev.C Pub. 5/15 EN
1 A
Read Data
N+1
A
N+2
Read Data
32
A
Read Data
N+L-1
A
Read Data
N+L
A S
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
One-Time Programming Memory (OTPM)
Single Write to Random Location
Figure 24 shows the typical WRITE cycle from the host to the MT9V124. The first 2 bytes
indicate a 16-bit address of the internal registers with most-significant byte first. The
following 2 bytes indicate the 16-bit data.
Figure 24:
Single WRITE to Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
A
Reg Address, M
Reg Address[7:0]
Write Data
A
M+1
A P
A
Sequential WRITE, Start at Random Location
This sequence (Figure 25) starts in the same way as the single WRITE to random location
(Figure 24). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit and continues to perform
byte writes until “L” bytes have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 25:
Sequential WRITE, Start at Random Location
Previous Reg Address, N
S
Slave Address
0 A Reg Address[15:8]
M+1
Write Data
M+2
A
Write Data
A
Reg Address, M
Reg Address[7:0]
M+3
A
A
Write Data
M+L-2
Write Data
M+1
A
M+L-1
A
Write Data
M+L
A
S
A
One-Time Programming Memory (OTPM)
The MT9V124 has one-time programmable memory (OTPM) for supporting defect
correction, module ID, and other customer-related information. There are 2784 bits of
OTPM available for features such as Lens Shading Correction, Color Correction Matrix,
White Balance Weight, and user-defined information. The OTPM programming requires
the data to be first placed in OTPM buffer and the presence of VPP. The proper procedure and timing must be followed.
MT9V124_DS Rev.C Pub. 5/15 EN
33
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Spectral Characteristics
Spectral Characteristics
Figure 26:
Chief Ray Angle (CRA) vs. Image Height
CRA vs. Image Height Plot
30
28
26
24
22
20
CRA (deg)
18
16
14
12
10
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
110
Image Height (%)
Figure 27:
Image Height
CRA
(%)
(mm)
(deg)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
0
0.035
0.070
0.105
0.140
0.175
0.210
0.245
0.280
0.315
0.350
0.385
0.420
0.455
0.490
0.525
0.560
0.595
0.630
0.665
0.700
0
1.23
2.46
3.70
4.94
6.18
7.43
8.67
9.90
11.13
12.36
13.57
14.77
15.97
17.14
18.31
19.45
20.58
21.69
22.77
23.83
Quantum Efficiency
Quantum Efficiency (%)
50
40
30
20
10
0
350
400
450
500
550
600
650
700
750
Wavelength (nm)
MT9V124_DS Rev.C Pub. 5/15 EN
34
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Electrical Specifications
Electrical Specifications
Caution
Table 12:
Stresses above those listed in Table 12 may cause permanent damage to the device.
Absolute Maximum Ratings
Rating
Symbol
Parameter
Min
Max
Unit
VDD
Core digital voltage
–0.3
2.4
V
VDD_IO
I/O digital voltage
–0.3
4.0
V
Analog voltage
–0.3
4.0
V
VAA_PIX
Pixel supply voltage
–0.3
4.0
V
VPP
OTPM power supply
8
9.5
V
VIN
Input voltage
–0.3
VDD_IO + 0.3
V
TOP
Operating temperature (measure at junction)
–30
70
°C
Storage temperature
–40
85
°C
VAA
TSTG
1
Note:
This is a stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the product specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Table 13:
Symbol
VDD
VDD_IO
Operating Conditions
Parameter
Min
Typ
Max
Units
Core digital voltage
1.7
1.8
1.95
V
2.5
2.8
3.1
V
I/O digital voltage
1.7
1.8
1.95
V
Analog voltage
2.5
2.8
3.1
V
VAA_PIX
Pixel supply voltage
2.5
2.8
3.1
V
VPP
OTPM power supply
8
8.5
9
V
–30
55
70
°C
VAA
TJ
Operating temperature (at junction)
MT9V124_DS Rev.C Pub. 5/15 EN
35
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Electrical Specifications
Table 14:
DC Electrical Characteristics
Symbol
Parameter
VIH
VIL
IIN
VOH
Input HIGH voltage
Input LOW voltage
Input leakage current
Output HIGH voltage
VOL
Output LOW voltage
Table 15:
Condition
Min
Max
Unit
0.7 * VDD_IO
–0.3
VDD_IO + 0.5
0.3 * VDD_IO
10
–
–
–
–
–
–
0.1
0.2
0.4
0.1
0.2
0.4
V
V
A
V
V
V
V
V
V
V
V
V
V
V
V
VIN = 0V or VIN = VDD_IO
VDD_IO = 1.8V, IOH = 2mA
VDD_IO = 1.8V, IOH = 4mA
VDD_IO = 1.8V, IOH = 8mA
VDD_IO = 2.8V, IOH = 2mA
VDD_IO = 2.8V, IOH = 4mA
VDD_IO = 2.8V, IOH = 8mA
VDD_IO = 1.8V, IOH = 2mA
VDD_IO = 1.8V, IOH = 4mA
VDD_IO = 1.8V, IOH = 8mA
VDD_IO = 2.8V, IOH = 2mA
VDD_IO = 2.8V, IOH = 4mA
VDD_IO = 2.8V, IOH = 8mA
1.7
1.6
1.4
2.7
2.6
2.5
–
–
–
–
–
–
Operating/Standby Current Consumption
fEXTCLK = 44 MHz; voltages = Typ or Max; T = Typ or Max; excludes VDD_IO current
J
Symbol
Parameter
IDD
IAA
IDD_PLL
Digital operating current
Analog operating current
PLL supply current
Total supply current
Total power consumption
Total standby current when asserting the
STANDBY signal
Hard standby
Soft standby
(clock on)
Soft standby
(clock off)
Standby power
Total standby current
Condition
fEXTCLK = 44 MHz, Soft standby
Unit
9.5
7
5
21.5
55
19
mA
mA
mA
mA
mW
μA
44
1.67
μW
mA
3.016
19
mW
μA
44.2
μW
mode
Standby power
Total standby current
Soft standby mode
Standby power
MT9V124_DS Rev.C Pub. 5/15 EN
Typ
36
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Electrical Specifications
Table 16:
LVDS Output Port DC Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
1650
Units
mV
Output voltage high
Voh
Output voltage low
Vol
850
Differential output voltage
Vod
280
360
460
mV
Output offset voltage
Vos
1000
1192
1400
mV
Single-ended output resistance
Ro
250

See text
mV
150
Output resistance mismatch
Ro
12
%
Reflection coefficient mismatch

8
%
Vod
6
mV
Differential output mismatch
Offset voltage mismatch
Vos
30
mV
Output short-circuit current
Isa, Isb
17
mA
Output short-circuit current
Isab
10
mA
Ivddio
8
mA
Max
Units
53
5
Standing power-supply current
Table 17:
See text
LVDS Output Port DC Specifications
Parameter
Symbol
Conditions
Min
48
Typ
clock
250 MHz; Cload = 6pF
Differential signal rise time
tr
Cload = 6pF
360
ps
Differential signal fall time
tf
Cload = 6pF
360
ps
Propagation delay
tp
Cload = 6pF
2.5
Differential skew
tskew
Cload = 6pF
Clock signal duty cycle
MT9V124_DS Rev.C Pub. 5/15 EN
37
ns

©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Electrical Specifications
Table 18:
Two-Wire Serial Interface Timing Data
f
EXTCLK = 22 MHz; VDD = 1.8V; VDD_IO = 1.8V; VAA = 2.8V; VAA_PIX = 2.8V;
VDD_PLL = 2.8V
Standard-Mode
Parameter
Symbol
Fast-Mode
Min
Max
Min
Max
Unit
SCL
0
100
0
400
KHz
HD;STA
4.0
-
0.6
-
S
f
SCLK Clock Frequency
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
t
LOW
4.7
-
1.3
-
S
HIGH
4.0
-
0.6
-
S
Set-up time for a repeated START
condition
tSU;STA
4.7
-
0.6
-
S
Data hold time:
tHD;DAT
04
3.455
06
0.95
S
Data set-up time
tSU;DAT
-
1006
-
nS
300
nS
300
nS
LOW period of the SCLK clock
t
HIGH period of the SCLK clock
t
250
Rise time of both SDATA and SCLK signals
tr
-
1000
20 + 0.1Cb7
Fall time of both SDATA and SCLK signals
tf
-
300
20 + 0.1Cb7
tSU;STO
4.0
-
0.6
-
S
tBUF
4.7
-
1.3
-
S
Cb
-
400
-
400
pF
CIN_SI
-
3.3
-
3.3
pF
Set-up time for STOP condition
Bus free time between a STOP and START
condition
Capacitive load for each bus line
Serial interface input pin capacitance
SDATA max load capacitance
SDATA pull-up resistor
Notes:
MT9V124_DS Rev.C Pub. 5/15 EN
CLOAD_SD
-
30
-
30
pF
RSD
1.5
4.7
1.5
4.7
K
This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
Two-wire control is I2C-compatible.
All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 22 MHz.
A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the
undefined region of the falling edge of SCLK.
5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of
the SCLK signal.
6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
t
SU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it
must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according
to the Standard-mode I2C-bus specification) before the SCLK line is released.
7. Cb = total capacitance of one bus line in pF.
1.
2.
3.
4.
38
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Electrical Specifications
Figure 28:
Two-Wire Serial Bus Timing Parameters
Write Sequence
tSRTS
tSDS
tSCLK
tSRTH
tSTPS
tSHAW
tAHSW
tSDH
tSTPH
SCLK
SDATA
Write Start
Write
Address
Bit 7
Write
Address
Bit 0
Read Sequence
Register
Value
Bit 0
Register
Value
Bit 7
Ack
Ack
Stop
tSDSR
tSHAR
tAHSR
tSDHR
SCLK
SDATA
Read Start
MT9V124_DS Rev.C Pub. 5/15 EN
Read
Address
Bit 7
Read
Address
Bit 0
Register
Value
Bit 7
Ack
39
Register
Value
Bit 0
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Power Sequence
Power Sequence
Powering up the sensor requires the supply rails to be applied in a particular order to
ensure sensor start up in a normal operation and prevent undesired condition such as
latch up from happening. Refer to Figure 29 and Table 19 for detailed timing requirement.
Figure 29:
Power-Up Sequence
VDD
VAA, VDD_IO
EXTCLK
t1
t2
t3
Internal POR
t4
SCLK
SDATA
Table 19:
Power Up Signal Timing
Symbol
Parameter
Min
Typ
Max
Unit
t1
t2
t3
t4
Delay from VDD to VAA and VDD_IO
EXTCLK activation
Internal POR Duration
First I2C Write
0
t1
70
50
100
-
500
-
ms
ms
EXTCLKs
EXTCLKs
MT9V124_DS Rev.C Pub. 5/15 EN
40
©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Package Dimensions
Package Dimensions
Table 20:
Package Dimensions
Nominal
Parameter
Symbol
Min
Max
Nominal
Millimeters
Min
Max
Inches
Package Body Dimension X
A
2.69355
2.66855
2.71855
0.10605
0.10506
0.10703
Package Body Dimension Y
B
2.69355
2.66855
2.71855
0.10605
0.10506
0.10703
Package Height
C
0.670
0.615
0.725
0.02638
0.02421
0.02854
Cavity height (glass to pixel distance)
C4
0.041
0.037
0.045
0.00161
0.00146
0.00177
Glass Thickness
C3
0.400
0.390
0.410
0.01575
0.01535
0.01614
Package Body Thickness
C2
0.570
0.535
0.605
0.02244
0.02106
0.02382
Ball Height
C1
0.100
0.070
0.130
0.00394
0.00276
0.00512
Ball Diameter
D
0.200
0.170
0.230
0.00787
0.00669
0.00906
Total Ball Count
N
25
Ball Count X axis
N1
5
Ball Count Y axis
N2
5
UBM
U
0.240
0.230
0.250
0.00945
0.00906
0.00984
Pins Pitch X axis
J1
0.500
0.490
0.510
0.01969
0.01929
0.02008
Pins Pitch Y axis
J2
0.500
0.490
0.510
0.01969
0.01929
0.02008
BGA ball center to package center
offset in X-direction
X
0
-0.025
0.025
0
-0.00098
0.00098
BGA ball center to package center
offset in Y-direction
Y
0
-0.025
0.025
0
-0.00098
0.00098
Edge to Ball Center Distance along X axis
S1
0.347
0.317
0.377
0.01365
0.01247
0.01483
Edge Ball Center Distance along Y axis
S2
0.347
0.317
0.377
0.01365
0.01247
0.01483
Figure 30:
Package Mechanical Drawing
1
2
3
4
E
5
A
B
BGA center(0,0)=
Package center
C
pixel center(0.13,0)
D
E
E
TOP VIEW
BOTTOM VIEW
CROSS-SECTION VIEW(E-E)
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©Semiconductor Components Industries, LLC, 2015.
MT9V124: 1/13-Inch VGA SOC Digital Image Sensor
Revision History
Revision History
Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/5/15
• Updated to ON Semiconductor template
• Removed Confidential marking
• Updated “Ordering Information” on page 2
Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/17/11
• Updated Table 20, “Package Dimensions,” on page 41
Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7/26/10
• Initial release
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©Semiconductor Components Industries, LLC, 2015 .
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