256 bit NV CMOS Static RAM

CAT22C10
256-Bit Nonvolatile CMOS Static RAM
FEATURES
■ Single 5V Supply
■ Low CMOS Power Consumption:
–Active: 40mA Max.
–Standby: 30µA Max.
■ Fast RAM Access Times:
–200ns
–300ns
■ JEDEC Standard Pinouts:
–18-lead DIP
–16-lead SOIC
■ Infinite EEPROM to RAM Recall
■ CMOS and TTL Compatible I/O
■ 10 Year Data Retention
■ Power Up/Down Protection
■ Commercial, Industrial and Automotive
■ 100,000 Program/Erase Cycles (E2PROM)
Temperature Ranges
DESCRIPTION
The CAT22C10 NVRAM is a 256-bit nonvolatile memory
organized as 64 words x 4 bits. The high speed Static
RAM array is bit for bit backed up by a nonvolatile
EEPROM array which allows for easy transfer of data
from RAM array to EEPROM (STORE) and from
EEPROM to RAM (RECALL). STORE operations are
completed in 10ms max. and RECALL operations typically within 1.5µs. The CAT22C10 features unlimited
RAM write operations either through external RAM
writes or internal recalls from EEPROM. Internal false
store protection circuitry prohibits STORE operations
when VCC is less than 3.0V.
The CAT22C10 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles (EEPROM)
and has a data retention of 10 years. The device is
available in JEDEC approved 18-lead plastic DIP and
16-lead SOIC packages.
PIN FUNCTIONS
PIN CONFIGURATION
DIP Package (L)
NC
A4
1
2
18
Vcc
17
A3
A2
3
4
16
15
NC
A5
I/O3
A1
A0
5
6
7
8
14
13
12
11
I/O2
I/O1
I/O0
9
10
RECALL
CS
Vss
STORE
WE
Pin Name
SOIC Package (W)
A4
A3
A2
A1
A0
CS
Vss
STORE
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Function
A0–A5
Address
Vcc
A5
I/O4
I/O3
I/O2
I/O1
I/O0–I/O3
Data In/Out
WE
Write Enable
CS
Chip Select
RECALL
Recall
WE
RECALL
STORE
Store
VCC
+5V
VSS
Ground
NC
No Connect
1
Doc. No. MD-1082, Rev. R
CAT22C10
BLOCK DIAGRAM
EEPROM ARRAY
A0
ROW
STATIC RAM
SELECT
ARRAY
STORE
A1
A2
A3
A4
A5
RECALL
COLUMN SELECT
CONTROL
LOGIC
STORE
RECALL
CS
READ/WRITE
CIRCUITS
I/O0 I/O1 I/O2 I/O3
WE
MODE SELECTION(1)(2)(3)
Input
CS
WE
RECALL
STORE
Standby
H
X
H
H
Output High-Z
RAM Read
L
H
H
H
Output Data
RAM Write
L
L
H
H
Input Data
(EEPROM→RAM)
X
H
L
H
Output High-Z RECALL
(EEPROM→RAM)
H
X
L
H
Output High-Z RECALL
(RAM→EEPROM)
X
H
H
L
Output High-Z STORE
(RAM→EEPROM)
H
X
H
L
Output High-Z STORE
Mode
I/O
POWER-UP TIMING(4)
Symbol
Parameter
Min.
Max.
Units
VCCSR
VCC Slew Rate
0.5
0.005
V/ms
Note:
(1) RECALL signal has priority over STORE signal when both are applied at the same time.
(2) STORE is inhibited when RECALL is active.
(3) The store operation is inhibited when VCC is below ≈ 3.0V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-1082, Rev. R
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
CAT22C10
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum
rating for extended periods may affect device performance and reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) .............. -2.0 to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
Units
Reference Test Method
100,000
Cycles/Byte
MIL-STD-883, Test Method 1033
10
Years
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
NEND(1)
Endurance
TDR(1)
Data Retention
VZAP(1)
ESD Susceptibility
2000
Volts
ILTH(1)(4)
Latch-Up
100
mA
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +5V ±10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
ICC
Current Consumption
(Operating)
40
mA
All Inputs = 5.5V
TA = 0°C
All I/O’s Open
ISB
Current Consumption
(Standby)
30
µA
CS = VCC
All I/O’s Open
ILI
Input Current
10
µA
0 ≤ VIN ≤ 5.5V
ILO
Output Leakage Current
10
µA
0 ≤ VOUT ≤ 5.5V
VIH
High Level Input Voltage
2
VCC
V
VIL
Low Level Input Voltage
0
0.8
V
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
VDH
RAM Data Holding Voltage
2.4
1.5
V
IOH = –2mA
0.4
V
IOL = 4.2mA
5.5
V
VCC
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Max.
Unit
Conditions
CI/O(1)
Input/Output Capacitance
10
pF
VI/O = 0V
CIN(1)
Input Capacitance
6
pF
VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
3
Doc No. MD-1082, Rev. R
CAT22C10
A.C. CHARACTERISTICS, Write Cycle
VCC = +5V ±10%, unless otherwise specified.
22C10-20
Symbol
Parameter
Min.
Max.
22C10-30
Min.
Max.
Unit
Conditions
tWC
Write Cycle Time
200
300
ns
tCW
CS Write Pulse Width
150
150
ns
tAS
Address Setup Time
50
50
ns
CL = 100pF
tWP
Write Pulse Width
150
150
ns
+1TTL gate
tWR
Write Recovery Time
25
25
ns
VOH = 2.2V
tDW
Data Valid Time
100
100
ns
VOL = 0.65V
tDH
Data Hold Time
0
0
ns
VIH = 2.2V
ns
VIL = 0.65V
tWZ(1)
Output Disable Time
tOW
Output Enable Time
100
100
0
0
ns
22C10-20
22C10-30
A.C. CHARACTERISTICS, Read Cycle
VCC = +5V ±10%, unless otherwise specified.
Symbol
Parameter
Min.
Max.
tRC
Read Cycle Time
200
tAA
Address Access Time
200
tCO
CS Access Time
200
tOH
Output Data Hold Time
0
tLZ(1)
CS Enable Time
0
tHZ(1)
CS Disable Time
Min.
Max.
Unit
Conditions
ns
CL = 100pF
300
ns
+1TTL gate
300
ns
VOH = 2.2V
0
ns
VOL = 0.65V
0
ns
VIH = 2.2V
ns
VIL = 0.65V
300
100
100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-1082, Rev. R
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
CAT22C10
A.C. CHARACTERISTICS, Store Cycle
VCC = +5V ±10%, unless otherwise specified.
Limits
Symbol
Parameter
tSTC
Store Time
tSTP
Store Pulse Width
tSTZ(1)
Store Disable Time
tOST(1)
Store Enable Time
Min.
Max.
Units
10
ms
200
100
0
Conditions
ns
CL = 100pF + 1TTL gate
ns
VOH = 2.2V, VOL = 0.65V
ns
VIH = 2.2V, VIL = 0.65V
Units
Conditions
A.C. CHARACTERISTICS, Recall Cycle
VCC = +5V ±10%, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Max.
tRCC
Recall Cycle Time
1.4
µs
tRCP
Recall Pulse Width
300
ns
CL = 100pF + 1TTL gate
tRCZ
Recall Disable Time
ns
VOH = 2.2V, VOL = 0.65V
tORC
Recall Enable Time
ns
VIH = 2.2V, VIL = 0.65V
tARC
Recall Data Access Time
100
0
1.1
µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
5
Doc No. MD-1082, Rev. R
CAT22C10
array into the Static RAM. When the STORE input is
taken low, it initiates a store operation which transfers
the entire Static RAM array contents into the EEPROM
array.
DEVICE OPERATION
The configuration of the CAT22C10 allows a common
address bus to be directly connected to the address
inputs. Additionally, the Input/Output (I/O) pins can be
directly connected to a common I/O bus if the bus has
less than 1 TTL load and 100pF capacitance. If not, the
I/O path should be buffered.
Standby Mode
The chip select (CS) input controls all of the functions of
the CAT22C10. When a high level is supplied to the CS
pin, the device goes into the standby mode where the
outputs are put into a high impendance state and the
power consumption is drastically reduced. With ISB less
than 100µA in standby mode, the designer has the
flexibility to use this part in battery operated systems.
When the chip select (CS) pin goes low, the device is
activated. When CS is forced high, the device goes into
the standby mode and consumes very little current. With
the nonvolatile functions inhibited, the device operates
like a Static RAM. The Write Enable (WE) pin selects a
write operation when WE is low and a read operation
when WE is high. In either of these modes, an array byte
(4 bits) can be addressed uniquely by using the address
lines (A0–A5), and that byte will be read or written to
through the Input/Output pins (I/O0–I/O3).
Read
When the chip is enabled (CS = low), the nonvolatile
functions are inhibited (STORE = high and RECALL =
high). With the Write Enable (WE) pin held high, the data
in the Static RAM array may be accessed by selecting an
address with input pins A0–A5. This will occur when the
outputs are connected to a bus which is loaded by no more
than 100pF and 1 TTL gate. If the loading is greater than
this, some additional buffering circuitry is recommended.
The nonvolatile functions are inhibited by holding the
STORE input and the RECALL input high. When the
RECALL input is taken low, it initiates a recall operation
which transfers the contents of the entire EEPROM
Figure 1. Read Cycle Timing
tRC
ADDRESS
tAA
tCO
CS
tLZ
tOH
HIGH-Z
DATA I/O
Doc. No. MD-1082, Rev. R
tHZ
DATA VALID
6
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
CAT22C10
Write
With the chip enabled and the nonvolatile functions
inhibited, the Write Enable (WE) pin will select the write
mode when driven to a low level. In this mode, the
address must be supplied for the byte being written.
After the set-up time (tAS), the input data must be
supplied to pins I/O0–I/O3. When these conditions, in-
cluding the write pulse width time (tWP) are met, the data
will be written to the specified location in the Static RAM.
A write function may also be initiated from the standby
mode by driving WE low, inhibiting the nonvolatile functions, supplying valid addresses, and then taking CS low
and supplying input data.
Figure 2. Write Cycle Timing
tWC
ADDRESS
tCW
CS
tAS
tWR
tWP
WE
tDW
tDH
DATA VALID
DATA IN
tWZ
tOW
HIGH-Z
DATA OUT
Figure 3. Early Write Cycle Timing
tWC
ADDRESS
tCW
CS
tAS
tWR
tWP
WE
tDW
DATA VALID
DATA IN
HIGH-Z
DATA OUT
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
tDH
7
Doc No. MD-1082, Rev. R
CAT22C10
place independent of the state of CS, WE or A0–A5. The
STORE pin must be held low for the duration of the Store
Pulse Width (tSTP) to ensure that a store operation is
initiated. Once initiated, the STORE pin becomes a
“Don’t Care”, and the store operation will complete its
transfer of the entire contents of the Static RAM array
into the EEPROM array within the Store Cycle time
(tSTC). If a store operation is initiated during a write cycle,
the contents of the addressed Static RAM byte and its
corresponding byte in the EEPROM array will be unknown.
Recall
At anytime, except during a store operation, taking the
RECALL pin low will initiate a recall operation. This is
independent of the state of CS, WE, or A0–A5. After the
RECALL pin has been held low for the duration of the
Recall Pulse Width (tRCP), the recall will continue independent of any other inputs. During the recall, the entire
contents of the EEPROM array is transferred to the
Static RAM array. The first byte of data may be externally
accessed after the recalled data access time from end of
recall (tARC) is met. After this, any other byte may be
accessed by using the normal read mode.
During the store operation, the outputs are in a high
impedance state. A minimum of 100,000 store operations can be performed reliably and the data written into
the EEPROM array has a minimum data retention time
of 10 years.
If the RECALL pin is held low for the entire Recall Cycle
time (tRCC), the contents of the Static RAM may be
immediately accessed by using the normal read mode.
A recall operation can be performed an unlimited number of times without affecting the integrity of the data.
DATA PROTECTION DURING POWER-UP AND
POWER-DOWN
The outputs I/O0–I/O3 will go into the high impedance
state as long as the RECALL signal is held low.
The CAT22C10 has on-chip circuitry which will prevent
a store operation from occurring when VCC falls below
3.0V typ. This function eliminates the potential hazard of
spurious signals initiating a store operation when the
system power is below 3.0V typ.
Store
At any time, except during a recall operation, taking the
STORE pin low will initiate a store operation. This takes
Figure 4. Recall Cycle Timing
tRCC
ADDRESS
tRCP
RECALL
tARC
CS
tORC
HIGH-Z
DATA UNDEFINED
DATA I/O
DATA VALID
tRCZ
Figure 5. Store Cycle Timing
tSTC
tSTP
STORE
tSTZ
HIGH-Z
DATA I/O
Doc. No. MD-1082, Rev. R
8
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
CAT22C10
EXAMPLE OF ORDERING INFORMATION(1)
Prefix
CAT
Company ID
Device #
Suffix
22C10
W
Product Number
22C10
I
–
20
Temperature Range
I = Industrial (-40°C to +85°C)
E = Extended (-40°C to +125°C)(3)
Package
L: PDIP
W: SOIC, JEDEC
– T1
T: Tape & Reel
1: 1,000/Reel
Speed
20: 200ns
30: 300ns
ORDERING INFORMATION
Orderable Part Numbers (for Pb-Free Devices)
CAT22C10LE20
CAT22C10WE-20-T1
CAT22C10LE30
CAT22C10WE-30-T1
CAT22C10LI20
CAT22C10WI-20-T1
CAT22C10LI30
CAT22C10WI-30-T1
Notes:
(1) The device used in the above example is a CAT22C10WI-20-T1 (SOIC, Industrial Temperature, 200ns, Tape & Reel, 1,000/Reel).
(2) For additional package option please contact your nearest Catalyst Semiconductor Sales office.
(3) Extended Temperature available upon request.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
9
Doc No. MD-1082, Rev. R
CAT22C10
REVISION HISTORY
Date
Revision Description
16-Apr-04
O
Add Lead free logo
Update Features
Update Pin Configuration
Update Ordering Information
Update Revision Number
24-Jun-08
P
Update Example of Ordering Information
17-Mar-09
Q
Change logo and fine print to ON Semiconductor
31-Jul-09
R
Update Example of Ordering Information
Update Ordering Information table
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Characteristics subject to change without notice.
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