XICOR X22C10DMB

X22C10
X22C10
256 Bit
64 x 4
Nonvolatile Static RAM
FEATURES
DESCRIPTION
•
The X22C10 is a 64 x 4 CMOS NOVRAM featuring a
high-speed static RAM overlaid bit-for-bit with a nonvolatile E2PROM. The NOVRAM design allows data to
be easily transferred from RAM to E2PROM (STORE)
and from E2PROM to RAM (RECALL). The STORE
operation is completed within 5ms or less and the
RECALL is completed within 1µs.
•
•
•
•
•
•
•
High Performance CMOS
—120ns RAM Access Time
High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
Low Power Consumption
—Active: 40mA Max.
—Standby: 100µA Max.
Infinite Array Recall, RAM Read and Write Cycles
Nonvolatile Store Inhibit: VCC = 3.5V Typical
Fully TTL and CMOS Compatible
JEDEC Standard 18-Pin 300-mil DIP
100% Compatible with X2210
—With Timing Enhancements
Xicor NOVRAMs are designed for unlimited write operations to the RAM, either RECALLs from E2PROM or
writes from the host. The X22C10 will reliably endure
1,000,000 STORE cycles. Inherent data retention is
greater than 100 years.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
PLASTIC DIP
CERDIP
2
NONVOLATILE E PROM
MEMORY ARRAY
STORE
A0
A1
ROW
SELECT
ARRAY
RECALL
STATIC RAM
MEMORY ARRAY
A2
STORE
RECALL
CONTROL
LOGIC
VCC
VSS
COLUMN
I/O CIRCUITS
NC
1
18
VCC
A4
2
17
NC
A3
3
16
A5
A2
4
15
A1
5
X22C10 14
I/O4
I/O3
A0
6
13
CS
VSS
STORE
7
12
I/O2
I/01
8
11
WE
9
10
RECALL
I/O1
I/O2
I/O3
3815 FHD F02
INPUT
DATA
CONTROL
I/O4
COLUMN SELECT
SOIC
A3
A4
A5
CS
WE
3815 FHD F01
A4
1
16
VCC
A3
2
15
A5
A2
3
14
A1
4
13
I/O4
I/O3
A0
5
CS
6
11
I/O2
I/O1
VSS
7
10
WE
STORE
8
9
X22C10
12
RECALL
3815 FHD F08.1
© Xicor, Inc. 1991,1995 Patents Pending
3815-2.4 7/26/96 T0/CO/D3 SH
1
Characteristics subject to change without notice
X22C10
PIN DESCRIPTIONS AND DEVICE OPERATION
RECALL
Addresses (A0–A5)
The RECALL input, when LOW, will initiate the transfer
of the entire contents of the E2PROM array to the RAM
array. The transfer of data will be completed in 1µs or
less.
The address inputs select a 4-bit memory location
during a read or write operation.
Chip Select (CS)
The Chip Select input must be LOW to enable read or
write operations with the RAM array. CS HIGH will place
the I/O pins in the high impedance state.
An array recall has priority over RAM read/write operations and will terminate both operations when RECALL
is asserted. RECALL LOW will also inhibit the STORE
input.
Write Enable (WE)
Automatic Recall
The Write Enable input controls the I/O buffers, determining whether a RAM read or write operation is enabled. When CS is LOW and WE is HIGH, the I/O pins
will output data from the selected RAM address locations. When both CS and WE are LOW, data presented
at the I/O pins will be written to the selected address
location.
Upon power-up the X22C10 will automatically recall
data from the E2PROM array into the RAM array.
Write Protection
The X22C10 has three write protect features that are
employed to protect the contents of the nonvolatile
memory.
Data In/Data Out (I/O1–I/O4)
• VCC Sense—All functions are inhibited when VCC is
<3.5V typical.
Data is written to or read from the X22C10 through the
I/O pins. The I/O pins are placed in the high impedance
state when either CS is HIGH or during either a store or
recall operation.
• Write Inhibit—Holding either STORE HIGH or
RECALL LOW during power-up or power-down will
prevent an inadvertent store operation and E2PROM
data integrity will be maintained.
STORE
• Noise Protection—A STORE pulse of typically less
than 20ns will not initiate a store cycle.
The STORE input, when LOW, will initiate the transfer of
the entire contents of the RAM array to the E2PROM
array. The WE and RECALL inputs are inhibited during
the store cycle. The store operation is completed in 5ms
or less.
PIN NAMES
Symbol
A0–A5
I/O1–I/O4
WE
CS
RECALL
STORE
VCC
VSS
NC
A store operation has priority over RAM read/write
operations. If STORE is asserted during a read operation, the read will be discontinued. If STORE is asserted
during a RAM write operation, the write will be immediately terminated and the store performed. The data at
the RAM address that was being written will be unknown
in both the RAM and E2PROM arrays.
Description
Address Inputs
Data Inputs/Outputs
Write Enable
Chip Select
Recall
Store
+5V
Ground
No Connect
3815 PGM T01
2
X22C10
ABSOLUTE MAXIMUM RATINGS
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS ....................................... –1V to +7V
D.C. Output Current ............................................ 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
–40°C
–55°C
+70°C
+85°C
+125°C
X22C10
5V ±10%
3815 PGM T13
3815 PGM T12.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
CS = VIL, I/Os = Open, All Others =
VIH, Addresses = 0.4V/2.4V Levels @
f = 8MHz
Store or Recall Functions Not Active,
I/Os = Open, All Other Inputs = VIH
Store or Recall functions Not Active,
I/Os = Open, All Other Inputs =
VCC –0.3V
VIN = VSS to VCC
VOUT = VSS to VCC
lCC
VCC Supply Current,
RAM Read/Write
40
mA
ISB1
VCC Standby Current
(TTL Inputs)
VCC Standby Current
(CMOS Inputs)
2
mA
100
µA
10
10
0.8
VCC + 1
0.4
µA
µA
V
V
V
V
ISB2
ILI
ILO
VlL(2)
VIH(2)
VOL
VOH
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
–1
2
2.4
IOL = 4.2mA
IOH = –2mA
3815 PGM T02.3
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
Parameter
Max.
Units
Test Conditions
CI/O(1)
CIN(1)
Input/Output Capacitance
Input Capacitance
8
6
pF
pF
VI/O = 0V
VIN = 0V
3815 PGM T03
Notes: (1) This parameter is periodically sampled and not 100% tested.
(2) VIL min. and VIH max. are for reference only and are not tested.
3
X22C10
MODE SELECTION
CE
WE
RECALL
STORE
I/O
Mode
H
L
L
L
X
H
X
H
X
H
L
L
H
X
H
X
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
L
Output High Z
Output Data
Input Data HIGH
Input Data LOW
Output High Z
Output High Z
Output High Z
Output High Z
Not Selected(3)
Read RAM
Write “1” RAM
Write “0” RAM
Array Recall
Array Recall
Nonvolatile Store(4)
Nonvolatile Store(4)
3815 PGM T05.1
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Store Cycles
Data Retention
Min.
Units
100,000
1,000,000
100
Data Changes Per Bit
Store Cycles
Years
3815 PGM T06
POWER-UP TIMING
Symbol
Parameter
Max.
Units
tPUR(5)
Power-up to Read Operation
Power-up to Write or Store Operation
100
5
µs
ms
tPUW(5)
3815 PGM T07
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
Input Rise and
Fall Times
Input and Output
Timing Levels
5V
919Ω
OUTPUT
0V to 3V
10ns
1.5V
3815 PGM T04.1
497Ω
100pF
3815 FHD F09.1
Notes: (3) Chip is deselected but may be automatically completing a store cycle.
(4) STORE = LOW is required only to initiate the store cycle, after which the store cycle will be automatically completed
(e.g. STORE = X).
(5) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These
parameters are periodically sampled and not 100% tested.
4
X22C10
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.
Read Cycle Limits
Symbol
Parameter
Min.
tRC
tAA
tCO
tOH
tLZ(6)
tHZ(6)
Read Cycle Time
Access Time
Chip Select to Output Valid
Output Hold from Address Change
Chip Select to Output in Low Z
Chip Deselect to Output in High Z
120
Max.
Units
ns
ns
ns
ns
ns
ns
120
120
0
0
50
3815 PGM T08
Read Cycle
tRC
ADDRESS
tA
tOH
tCO
tHZ
CS
tLZ
DATA I/O
DATA VALID
3815 FHD F03
Note:
(6) tLZ min. and tHZ min. are periodically sampled and not 100% tested.
5
X22C10
Write Cycle Limits
Symbol
Parameter
Min.
tWC
tCW
tAS
tWP
tWR
tDW
tDH
tWZ
tOW
Write Cycle Time
Chip Select to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
120
90
0
90
0
40
0
Max.
50
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
3815 PGM T09
Write Cycle
tWC
ADDRESS
tCW
CS
tAS
tWP
tWR
WE
tDW
DATA IN
tDH
DATA VALID
tWZ
tOW
DATA OUT
3815 FHD F04
Early Write Cycle
tWC
ADDRESS
tCW
tWR
CS
tAS
tWP
WE
tDW
tDH
DATA VALID
DATA IN
HIGH Z
DATA OUT
3815 FHD F05
6
X22C10
Recall Cycle Limits
Symbol
tRCC
tRCP(7)
tRCZ
tORC
tARC
Parameter
Min.
Array Recall Time
Recall Pulse Width
Recall to Output in High Z
Output Active from End of Recall
Recalled Data Access Time from End of Recall
Max.
Units
1
µs
ns
ns
ns
ns
90
50
0
150
3815 PGM T10
Recall Cycle
ADDRESS
tRCP
tRCC
RECALL
CS
tRCZ
tORC
DATA I/O
tARC
3815 FHD F06
Note:
(7) Recall rise time must be less than 1µs.
7
X22C10
Store Cycle Limits
Symbol
tSTC
tSTP
tSTZ
tOST
Parameter
Min.
Internal Store Time
Store Pulse Width
Store to Output in High Z
Output Active from End of Store
Max.
Units
5
ms
ns
ns
ns
90
50
0
3815 PGM T11
Store Cycle Limits
tSTC
tSTP
STORE
tSTZ
DATA I/O
tOST
HI Z
3815 FHD F07
SYMBOL TABLE
WAVEFORM
8
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
X22C10
FACKAGING INFORMATION
16-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.386 (9.80)
0.394 (10.01)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° – 8°
0.250"
0.0075 (0.19)
0.012 (0.30)
0.016 (0.410)
0.037 (0.937)
FOOTPRINT
0.030" Typical
16 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F26
9
X22C10
PACKAGING INFORMATION
18-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
0.960 (24.38)
––
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN.
0.800 (20.32)
REF.
0.098 (2.49)
––
SEATING
PLANE
0.150 (3.81) MIN.
0.200 (5.08)
––
0.070 (1.78)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
TYP. 0.100 (2.54)
0.065 (1.65)
0.038 (0.97)
TYP. 0.060 (1.52)
0.023 (0.58)
0.014 (0.36)
TYP. 0.018 (0.46)
0.320 (8.13)
0.290 (7.37)
TYP. 0.311 (7.90)
0°
15°
0.015 (0.38)
0.008 (0.20)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F06
10
X22C10
PACKAGING INFORMATION
18-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.915 (23.24)
0.894 (22.71)
0.270 (6.86)
0.250 (6.35)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.050 (1.27)
0.800 (20.32)
REF.
0.165 (4.19)
0.130 (3.30)
SEATING
PLANE
0.025 (0.51)
0.005 (0.13)
0.140 (3.56)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.070 (1.78)
0.050 (1.27)
0.020 (0.51)
0.016 (0.41)
0.325 (8.26)
0.300 (7.62)
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F02
11
X22C10
ORDERING INFORMATION
X22C10
X
X
Store Cycles
Blank = 1,000,000
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 18-Lead Plastic DIP
D = 18-Lead Cerdip
S = 16-Lead SOIC (150 mil)
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
12