Complementary Bias Resistor Transistors R1 = 1 k , R2 = 1 k

MUN5330DW1,
NSBC113EPDXV6
Complementary Bias
Resistor Transistors
R1 = 1 kW, R2 = 1 kW
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NPN and PNP Transistors with Monolithic
Bias Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
PIN CONNECTIONS
(3)
(2)
R1
Q2
R2
•
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
R2
Q1
R1
Features
•
•
•
•
(1)
(4)
(5)
(6)
MARKING DIAGRAMS
6
30 M G
G
SOT−363
CASE 419B
1
1
MAXIMUM RATINGS
(TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)
Rating
Symbol
Max
Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
IC
100
mAdc
Input Forward Voltage
VIN(fwd)
10
Vdc
Input Reverse Voltage
VIN(rev)
10
Vdc
Collector Current − Continuous
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
30 M G
G
SOT−563
CASE 463A
1
30
M
G
= Specific Device Code
= Date Code*
= Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
ORDERING INFORMATION
Package
Shipping†
MUN5330DW1T1G
SMUN5330DW1T1G
SOT−363
(Pb−Free)
3000 / Tape
& Reel
NSBC113EPDXV6T1G
SOT−563
(Pb−Free)
4000 / Tape
& Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 3
1
Publication Order Number:
DTC113EP/D
MUN5330DW1, NSBC113EPDXV6
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
187
256
1.5
2.0
mW
MUN5330DW1 (SOT−363) ONE JUNCTION HEATED
PD
Total Device Dissipation
(Note 1)
TA = 25°C
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)
Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)
RqJA
mW/°C
670
490
°C/W
250
385
2.0
3.0
mW
MUN5330DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3)
PD
Total Device Dissipation
(Note 1)
TA = 25°C
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)
Thermal Resistance,
Junction to Ambient
(Note 2)
RqJA
(Note 1)
Thermal Resistance,
Junction to Lead (Note 1)
(Note 2)
RqJL
Junction and Storage Temperature Range
TJ, Tstg
mW/°C
°C/W
493
325
°C/W
188
208
−55 to +150
°C
357
2.9
mW
mW/°C
NSBC113EPDXV6 (SOT−563) ONE JUNCTION HEATED
PD
Total Device Dissipation
(Note 1)
TA = 25°C
Derate above 25°C
(Note 1)
Thermal Resistance,
Junction to Ambient
RqJA
(Note 1)
°C/W
350
NSBC113EPDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3)
PD
Total Device Dissipation
(Note 1)
TA = 25°C
Derate above 25°C
(Note 1)
Thermal Resistance,
Junction to Ambient
500
4.0
RqJA
(Note 1)
Junction and Storage Temperature Range
TJ, Tstg
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 × 1.0 Inch Pad.
3. Both junction heated values assume total power is sum of two equally powered channels.
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2
mW
mW/°C
°C/W
250
−55 to +150
°C
MUN5330DW1, NSBC113EPDXV6
ELECTRICAL CHARACTERISTICS (TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
−
−
100
−
−
500
−
−
4.3
50
−
−
50
−
−
3.0
5.0
−
−
−
0.25
−
−
1.2
1.3
−
−
−
−
1.7
1.7
−
−
−
−
0.2
4.9
−
−
Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current
(VCB = 50 V, IE = 0)
ICBO
Collector-Emitter Cutoff Current
(VCE = 50 V, IB = 0)
ICEO
Emitter-Base Cutoff Current
(VEB = 6.0 V, IC = 0)
IEBO
Collector-Base Breakdown Voltage
(IC = 10 mA, IE = 0)
V(BR)CBO
Collector-Emitter Breakdown Voltage (Note 4)
(IC = 2.0 mA, IB = 0)
V(BR)CEO
nAdc
nAdc
mAdc
Vdc
Vdc
ON CHARACTERISTICS
hFE
DC Current Gain (Note 4)
(IC = 5.0 mA, VCE = 10 V)
Collector-Emitter Saturation Voltage (Note 4)
(IC = 10 mA, IB = 5.0 mA)
VCE(sat)
Input Voltage (Off)
(VCE = 5.0 V, IC = 100 mA) (NPN)
(VCE = 5.0 V, IC = 100 mA) (PNP)
Vi(off)
Input Voltage (On)
(VCE = 0.2 V, IC = 20 mA) (NPN)
(VCE = 0.2 V, IC = 20 mA) (PNP)
Vi(on)
Output Voltage (On)
(VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW)
VOL
Output Voltage (Off)
(VCC = 5.0 V, VB = 0.05 V, RL = 1.0 kW)
VOH
V
Vdc
Vdc
Vdc
Vdc
Input Resistor
R1
0.7
1.0
1.3
Resistor Ratio
R1/R2
0.8
1.0
1.2
kW
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤ 2%.
PD, POWER DISSIPATION (mW)
400
350
300
250
200
(1) SOT−363; 1.0 × 1.0 Inch Pad
(2) SOT−563; Minimum Pad
(1) (2)
150
100
50
0
−50
−25
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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3
MUN5330DW1, NSBC113EPDXV6
10
100
IC/IB = 10
1
25°C
150°C
0.1
−55°C
0.01
25°C
−55°C
10
1
0.1
0
30
10
40
20
IC, COLLECTOR CURRENT (mA)
0.1
50
1
10
IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) vs. IC
100
Figure 3. DC Current Gain
3.6
100
2.8
IC, COLLECTOR CURRENT (mA)
f = 10 kHz
IE = 0 A
TA = 25°C
3.2
2.4
2.0
1.6
1.2
0.8
0.4
0
0
10
20
30
40
VR, REVERSE VOLTAGE (V)
150°C
VO = 5 V
0.1
50
0
0.5
1.0
1.5
2.0
Vin, INPUT VOLTAGE (V)
−55°C
150°C
VO = 0.2 V
0.1
0
2.5
Figure 5. Output Current vs. Input Voltage
10
1
−55°C
1
100
25°C
25°C
10
Figure 4. Output Capacitance
Vin, INPUT VOLTAGE (V)
Cob, OUTPUT CAPACITANCE (pF)
150°C
VCE = 10 V
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)
TYPICAL CHARACTERISTICS − NPN TRANSISTOR
MUN5330DW1, NSBC113EPDXV6
10
20
30
40
IC, COLLECTOR CURRENT (mA)
Figure 6. Input Voltage vs. Output Current
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4
50
3.0
MUN5330DW1, NSBC113EPDXV6
TYPICAL CHARACTERISTICS − PNP TRANSISTOR
100
IC/IB = 10
VCE = 10 V
HFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER
VOLTAGE (V)
10
1
TA = 25°C
TA = 150°C
0.1
TA = −55°C
0.01
TA = 25°C
TA = −55°C
1
0.1
0
10
20
30
40
50
0.1
1
10
100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 7. VCE(sat) vs. IC
Figure 8. DC Current Gain
100
100
Vo = 0.2 V
10
Vin, INPUT VOLTAGE (V)
TA = 150°C
TA = −55°C
1
TA = 25°C
0.1
0
0.5
10
TA = 150°C
TA = 25°C
1
TA = −55°C
Vo = 5 V
1
1.5
2
2.5
0.1
0
10
20
30
40
Vin, INPUT VOLTAGE (V)
IC, COLLECTOR CURRENT (mA)
Figure 9. Output Current vs. Input Voltage
Figure 10. Input Voltage vs. Output Current
12
Cob, OUTPUT CAPACITANCE (PF)
IC, COLLECTOR CURRENT (mA)
TA = 150°C
10
f = 10 kHz
IE = 0 V
TA = 25°C
10
8
6
4
2
0
0
5
10
15
20
25
30
VR, REVERSE VOLTAGE (V)
Figure 11. Output Capacitance
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5
35
40
50
MUN5330DW1, NSBC113EPDXV6
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H D
D
A
D
6
5
GAGE
PLANE
4
2
L
L2
E1
E
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
H
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
ddd
TOP VIEW
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
b
A2
M
C A-B D
DETAIL A
A
6X
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
c
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
END VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
6X
6X
0.30
0.66
2.50
0.65
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
MUN5330DW1, NSBC113EPDXV6
PACKAGE DIMENSIONS
SOT−563, 6 LEAD
CASE 463A
ISSUE F
D
−X−
6
5
1
2
A
L
4
E
−Y−
3
b
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.
DIM
A
b
C
D
E
e
L
HE
HE
C
5 PL
6
0.08 (0.003)
M
X Y
MILLIMETERS
MIN
NOM MAX
0.50
0.55
0.60
0.17
0.22
0.27
0.08
0.12
0.18
1.50
1.60
1.70
1.10
1.20
1.30
0.5 BSC
0.10
0.20
0.30
1.50
1.60
1.70
INCHES
NOM MAX
0.021 0.023
0.009 0.011
0.005 0.007
0.062 0.066
0.047 0.051
0.02 BSC
0.004 0.008 0.012
0.059 0.062 0.066
MIN
0.020
0.007
0.003
0.059
0.043
SOLDERING FOOTPRINT*
0.3
0.0118
0.45
0.0177
1.35
0.0531
1.0
0.0394
0.5
0.5
0.0197 0.0197
SCALE 20:1
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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