NB7L1008 2.5V / 3.3V 1:8 LVPECL Fanout Buffer Multi−Level Inputs w/ Internal Termination http://onsemi.com Description MARKING The NB7L1008 is a high performance differential 1:8 Clock/Data fanout buffer. The NB7L1008 produces eight identical output copies of Clock or Data operating up to 7 GHz or 12 Gb/s, respectively. As such, the NB7L1008 is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB7L1008 to accept various logic standards, such as LVPECL, CML, LVDS logic levels. The VREFAC reference output can be used to rebias capacitor−coupled differential or single−ended input signals. The 1:8 fanout design was optimized for low output skew applications. The NB7L1008 is a member of the GigaComm™ family of high performance clock products. 32 DIAGRAM 1 32 1 QFN32 MN SUFFIX CASE 488AM A WL YY WW G NB7L 1008 AWLYYWWG G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) Features • • • • • • • • • • • • • • • Typical Maximum Input Data Rate > 12 Gb/s Typical Data Dependent Jitter < 15 ps Maximum Input Clock Frequency > 7 GHz Typical Random Clock Jitter < 0.8 ps RMS Low Skew 1:8 LVPECL Outputs, < 20 ps max Multi−Level Inputs, accepts LVPECL, CML, LVDS 160 ps Typical Propagation Delay 50 ps Typical Rise and Fall Times Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical Operating Range: VCC = 2.375 V to 3.6 V, GND = 0 V Internal Input Termination Resistors, 50 W VREFAC Reference Output QFN−32 Package, 5 mm x 5 mm −40°C to +85°C Ambient Operating Temperature These are Pb−Free and Halide−Free Devices SIMPLIFIED LOGIC DIAGRAM Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 IN VT 50W 50W IN Q4 Q4 VREFAC Q5 Q5 Q6 Q6 Q7 Q7 ORDERING INFORMATION See detailed ordering and shipping information on page 9 of this data sheet. © Semiconductor Components Industries, LLC, 2014 April, 2014 − Rev. 1 1 Publication Order Number: NB7L1008/D 29 28 27 26 VCC Q2 30 Q2 Q0 31 Q1 Q0 32 Q1 VCC NB7L1008 Exposed Pad (EP) 25 VCC 1 24 GND GND 2 23 VCC IN 3 22 Q3 VT 4 21 Q3 20 Q4 NB7L1008 VREFAC 5 IN 6 19 Q4 GND 7 18 VCC VCC 8 17 13 14 15 16 Q6 Q5 Q5 VCC 12 Q6 Q7 11 Q7 10 VCC GND 9 Figure 1. 32−Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 3, 6 IN, IN LVPECL, CML, LVDS Input 4 VT 2, 7 17,24 GND Negative Supply Voltage, Note 2 1, 8, 9, 16, 18, 23, 25, 32 VCC Positive Supply Voltage, Note 2 31, 30, 29, 28, 27, 26, 22, 21, 20, 19, 15, 14, 13, 12, 11, 10 Q0, Q0, Q1, Q1, Q2, Q2, Q3, Q3, Q4, Q4, Q5, Q5, Q6, Q6, Q7, Q7 5 VREFAC − EP Non−inverted / Inverted Differential Clock/Data Input. Note 1 Internal 50 W Termination Pin for IN and IN LVPECL Non−inverted / Inverted Differential Output. Output Voltage Reference for Capacitor−Coupled Inputs, only − The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to GND and is recommended to be electrically connected to GND on the PC board. 1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal is applied on IN/IN, then the device will be susceptible to self−oscillation. 2. All VCC and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation. http://onsemi.com 2 NB7L1008 Table 2. ATTRIBUTES Characteristics ESD Protection Value Human Body Model Machine Model > 2 kV > 200 V Moisture Sensitivity (Note 3) Indefinite Time of the Drypack QFN−32 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 263 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, refer to Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0 V 4.0 V VIN Input Voltage GND = 0 V −0.5 to VCC V VINPP Differential Input Voltage |IN − IN| 1.89 V IIN Input Current Through RT (50 W Resistor) $40 mA Iout Output Current 34 40 mA IVFREFAC VREFAC Sink/Source Current $1.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 4) TGSD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias 500 lfpm QFN−32 27 °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board QFN−32 12 °C/W Tsol Wave Solder 265 °C Continuous Surge Pb−Free Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7L1008 Table 4. DC CHARACTERISTICS − LVPECL OUTPUT VCC = 2.375 V to 3.6 V; GND = 0V TA = −40°C to 85°C (Note 6) Symbol Characteristic Min Typ Max Unit 165 215 mA POWER SUPPLY CURRENT ICC Power Supply Current, Inputs and Outputs Open LVPECL OUTPUTS (Note 5, Figure 11) VOH VOL Output HIGH Voltage VCC – 1025 2275 1475 VCC – 775 2525 1725 mV VCC = 3.3V VCC = 2.5V VCC – 2000 1300 500 VCC – 1500 1800 1000 mV VCC = 3.3V VCC = 2.5V Output LOW Voltage DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Notes 7 and 8) (Figures 7 and 9) VIH Single−Ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−Ended Input LOW Voltage GND Vth – 100 mV Vth Input Threshold Reference Voltage Range 1100 VCC – 100 mV VISE Single−Ended Input Voltage (VIH – VIL) 200 1200 mV VREFAC VREFAC Output Reference Voltage @ 100 mA for Capacitor − Coupled Inputs, Only VCC = 3.3 V VCC = 2.5 V mV VCC – 1150 VCC – 1150 VCC – 1050 VCC – 1050 VCC – 950 VCC – 950 DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (IN, IN) (Note 9) (Figures 5 and 8) VIHD Differential Input HIGH Voltage 1100 VCC mV VILD Differential Input LOW Voltage GND VIHD − 100 mV VID Differential Input Voltage (VIHD − VILD) 100 1200 mV IIH Input HIGH Current −150 40 +150 mA IIL Input LOW Current −150 0 +150 mA 45 50 55 W TERMINATION RESISTORS RTIN Internal Input Termination Resistor NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. LVPECL outputs loaded with 50 W to VCC − 2 V for proper operation. 6. Input and output parameters vary 1:1 with VCC. 7. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. http://onsemi.com 4 NB7L1008 Table 5. AC CHARACTERISTICS VCC = 2.375 V to 3.6 V; GND = 0V TA = −40°C to 85°C (Note 10) Symbol Min Typ fDATA Maximum Operating Input Data Rate (Note 17) Characteristic 10 12 Gb/s fINCLK Maximum Input Clock Frequency, VOUTPP w 400 mV (Note 17) 5 7 GHz VOUTPP Output Voltage Amplitude (see Figures 2 and 6, Notes 11, 17) fin v 5 GHz Max Unit mV 400 VCMR Input Common Mode Range (Differential Configuration, Note 12, Figure 10) 600 tPLH, tPHL Propagation Delay to Output Differential, IN/IN to Qn/Qn 100 tPLH TC Propagation Delay Temperature Coefficient −40°C to +85°C tDC Output Clock Duty Cycle fin v 5 GHz tSKEW Within Device Skew (Note 13) Device to Device Skew (Note 14) Tjitter Clock Jitter RMS, 1000 Cycles (Note 17) fin ≤ 6 GHz Data Dependent Jitter (DDJ) (Note 17) ≤ 10 Gb/s 0.2 3 Tjitter (additive) 622 MHz @ Integration Range of 12 kHz to 20 MHz 0.025 VINPP Input Voltage Swing (Differential Configuration) (Note 16) (Figure 6) 100 tr, tf Output Rise/Fall Times (20% − 80%) Qn, Qn 20 160 VCC − 50 mV 220 ps 25 45 fs/°C 49/51 55 % 20 100 ps 0.8 15 ps ps 50 1200 mV 80 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. All outputs must be loaded with external 50 W to VCC − 2 V. 11. Output voltage swing is a single−ended measurement operating in differential mode. 12. VIHDMIN ≥ 1100 mV. 13. Within device skew compares coincident edges. 14. Device to device skew is measured between outputs under identical transition 15. Additive CLOCK jitter with 50% duty cycle clock signal input. 16. Input voltage swing is a single−ended measurement operating in differential mode. 17. VCC of 2.5−3.3, input = 800 mvp−p . 1.0 VCC OUTPUT P−P (V) 0.9 0.8 IN 0.7 50 W 0.6 VT 50 W 0.5 Vout p−p IN 0.4 0.3 2 3 4 5 6 7 8 9 10 Figure 3. Input Structure FREQUENCY (GHz) Figure 2. Typical VOUT P−P vs. Frequency at 255C http://onsemi.com 5 NB7L1008 SQRT ((0.04663 ps out2)−(0.040.91 ps in2)) = 0.025 ps additive Figure 4. Additive Phase Jitter RMS from 12 kHz to 20 MHz @ 622 MHz, Typical 0.025 ps http://onsemi.com 6 NB7L1008 IN VINPP = VIH(IN) − VIL(IN) IN VID = |VIHD(IN) − VILD(IN)| IN Q VIHD IN VILD VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 5. Differential Inputs Driven Differentially VIH Figure 6. AC Reference Measurement IN IN IN IN Vth VIL Vth Figure 7. Differential Input Driven Single−Ended VCC VCC Vthmax Vth Figure 8. Differential Inputs Driven Differentially VIHmax VILmax VCMR VIHmin VILmin Vthmin GND VILDmax VID = VIHD − VILD VIHDtyp IN VIH Vth VIL IN VIHDmax VCMmax IN VILDtyp VIHDmin VILDmin VCMmin GND Figure 9. Vth Diagram Figure 10. VCMR Diagram VCC − 2 V 50 W Q Zo = 50 W 50 W D Receiver Device Driver Device Q Zo = 50 W D Figure 11. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8173/D) http://onsemi.com 7 NB7L1008 VCC VCC NB7L1008 ZO = 50 W LVPECL Driver VCC VCC ZO = 50 W IN 50 W VT = VCC − 2 V ZO = 50 W LVDS Driver 50 W IN 50 W VT = Open ZO = 50 W IN 50 W IN GND GND GND GND Figure 12. LVPECL Interface Figure 13. LVDS Interface VCC VCC VCC VCC NB7L1008 ZO = 50 W CML Driver NB7L1008 ZO = 50 W IN 50 W VT = VCC ZO = 50 W Differential Driver 50 W NB7L1008 IN 50 W VT = VREFAC* ZO = 50 W IN 50 W IN GND GND GND GND Figure 15. Capacitor−Coupled Differential Interface (VT Connected to VREFAC) Figure 14. Standard 50 W Load CML Interface *VREFAC bypassed to ground with a 0.01 mF capacitor VCC VCC ZO = 50 W Differential Driver NB7L1008 IN 50 W VT = VREFAC* 50 W IN GND GND Figure 16. Capacitor−Coupled Single−Ended Interface (VT Connected to VREFAC) http://onsemi.com 8 NB7L1008 Figure 17. Tape and Reel Pin 1 Quadrant Orientation ORDERING INFORMATION Package Shipping NB7L1008MNG Device QFN32 (Pb−Free/Halide−Free) 74 Units / Rail NB7L1008MNTXG QFN32 (Pb−Free/Halide−Free) 1000 / Tape & Reel (Pin 1 Orientation in Quadrant B, Figure 17) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NB7L1008 PACKAGE DIMENSIONS QFN32 5x5, 0.5P CASE 488AM ISSUE A A D PIN ONE LOCATION ÉÉ ÉÉ L L B L1 DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS E 0.15 C 0.15 C A DETAIL B 0.10 C ÉÉ ÉÉ ÇÇ EXPOSED Cu TOP VIEW (A3) A1 MOLD CMPD DETAIL B ALTERNATE CONSTRUCTION 0.08 C SEATING PLANE C SIDE VIEW NOTE 4 K D2 MILLIMETERS MAX MIN 1.00 0.80 −−− 0.05 0.20 REF 0.30 0.18 5.00 BSC 2.95 3.25 5.00 BSC 2.95 3.25 0.50 BSC 0.20 −−− 0.30 0.50 −−− 0.15 5.30 17 8 32X DIM A A1 A3 b D D2 E E2 e K L L1 RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 9 NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 3.35 L 32X 0.63 E2 1 32 3.35 5.30 25 e e/2 BOTTOM VIEW 32X b 0.10 M C A B 0.05 M C NOTE 3 0.50 PITCH 32X 0.30 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GigaComm is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 10 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB7L1008/D