5V ECL 3-Bit 4:1 Mux-Latch

MC100E256
5VECL 3-Bit 4:1 Mux-Latch
The MC100E256 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. Separate Select controls
are provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and
output data is controlled by the multiplexer select controls. A logic
HIGH on LEN latches the outputs. The Master Reset (MR) overrides
all other controls to set the Q outputs LOW.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
•
MARKING
DIAGRAM
950 ps Max. D to Output
850 ps Max. LEN to Output
Split Select
MC100E256FN
Differential Outputs
AWLYYWW
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input Pulldown Resistors
PLCC−28
FN SUFFIX
CASE 776
•
• ESD Protection: > 1 KV HBM, > 75 V MM
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
•
http://onsemi.com
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 code V−0 @ 1/8″,
Oxygen Index 28 to 34
Transistor Count = 280 devices
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 1
A
Location
WL
YY
WW
= Assembly
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
1
28 1
Package
Shipping
MC100E256FN
PLCC−28
37 Units/Rail
MC100E256FNR2
PLCC−28
500 Units/Reel
Publication Order Number:
MC100E256/D
MC100E256
D1b D1a D2d D2c D2b D2a VCCO
19
18
Q2
27
17
Q2
28
16
VCC
SEL1A
26
SEL1B
SEL2
VEE
1
LEN
2
MR
D1c
25
24
23
22
21
20
Pinout: 28-Lead PLCC
15
(Top View)
Q1
14
Q1
3
13
VCCO
4
12
Q0
5
6
7
8
9
10
11
D1d D0a D0b D0c D0d VCCO Q0
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Pin Assignment
PIN DESCRIPTION
PIN
FUNCTION
D0x − D2x
ECL Data Inputs
SEL1A, SEL1B
ECL First-stage Select Inputs
SEL2
ECL Second-stage Select Input
LEN
ECL Latch Enable
MR
ECL Master Reset
Q0, Q0 − Q2, Q2
ECL Data Outputs
VCC, VCCO
Positive Supply
VEE
Negative Supply
SEL2
SEL1A
SEL1B
State
H
H
H
1
D0b
0
D0c
1
D0d
0
D1a
1
D1b
0
D1c
1
D1d
0
D2a
1
D2b
0
D2c
1
D2d
0
1
0
1
0
1
0
SEL1A
SEL1B
SEL2
LEN
MR
Figure 2. Logic Diagram
FUNCTION TABLE
Pin
D0a
Operation
Output c/d Data
Input d Data
Input b Data
http://onsemi.com
2
D
Q0
EN
R
Q0
D
Q1
EN
R
Q1
D
Q2
EN
R
Q2
MC100E256
MAXIMUM RATINGS (Note 1)
Rating
Units
VCC
PECL Mode Power Supply
Parameter
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8
V
VI
PECL Mode Input Voltage
VEE = 0 V
VI ≤ VCC
6
V
NECL Mode Input Voltage
VCC = 0 V
VI ≥ VEE
−6
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
0 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
θJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
28 PLCC
28 PLCC
63.5
43.5
°C/W
°C/W
θJC
Thermal Resistance (Junction−to−Case)
std bd
28 PLCC
22 to 26
°C/W
VEE
PECL Operating Range
4.2 to 5.7
V
NECL Operating Range
−5.7 to −4.2
V
265
°C
Symbol
Tsol
Wave Solder
Condition 1
Condition 2
< 2 to 3 sec @ 248°C
1. Maximum Ratings are those values beyond which device damage may occur.
100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 2)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
69
83
69
83
79
96
mA
VOH
Output HIGH Voltage (Note 3)
3975
4050
4120
3975
4050
4120
3975
4050
4120
mV
VOL
Output LOW Voltage (Note 3)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
4050
4120
3835
4120
4120
3835
4120
4120
mV
VIL
Input LOW Voltage
3190
3300
3525
3190
3525
3525
3190
3525
3525
mV
IIH
Input HIGH Current
150
μA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
μA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / −0.8 V.
3. Outputs are terminated through a 50 Ω resistor to VCC − 2.0 V.
100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 4)
0°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
IEE
Power Supply Current
69
83
69
83
79
96
mA
VOH
Output HIGH Voltage (Note 5)
−1025
−950
−880
−1025
−950
−880
−1025
−950
−880
mV
VOL
Output LOW Voltage (Note 5)
−1810
−1705
−1620
−1810
−1745
−1620
−1810
−1740
−1620
mV
VIH
Input HIGH Voltage
−1165
−950
−880
−1165
−880
−880
−1165
−880
−880
mV
VIL
Input LOW Voltage
−1810
−1700
−1475
−1810
−1475
−1475
−1810
−1475
−1475
mV
IIH
Input HIGH Current
150
μA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
μA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained.
4. Input and output parameters vary 1:1 with VCC. VEE can vary +0.46 V / −0.8 V.
5. Outputs are terminated through a 50 Ω resistor to VCC − 2.0 V.
http://onsemi.com
3
MC100E256
AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 6)
0°C
Symbol
Characteristic
fMAX
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
ts
Setup Time
th
Min
Typ
25°C
Max
Min
TBD
Typ
85°C
Max
Min
TBD
Typ
Max
TBD
Unit
GHz
ps
D
SEL1
SEL2
LEN
MR
400
550
450
350
350
600
775
650
500
600
D
SEL1
SEL2
400
600
500
D
SEL1
SEL2
900
1050
900
800
825
400
550
450
350
350
600
775
650
500
600
275
300
250
400
600
500
300
100
200
−275
−300
−250
700
600
900
1050
900
800
825
400
550
450
350
350
600
775
650
500
600
275
300
250
400
600
500
275
300
250
300
100
200
−275
−300
−250
300
100
200
−275
−300
−250
700
600
700
600
900
1050
900
800
825
ps
Hold Time
ps
tRR
Reset Recovery Time
tPW
Minimum Pulse Width
ps
MR
tSKEW
Within-Device Skew (Note 7)
tJITTER
Cycle−to−Cycle Jitter
tr
tf
Rise/Fall Times
(20 - 80%)
ps
400
400
400
50
50
50
ps
TBD
TBD
TBD
ps
ps
275
475
700
275
475
700
275
6. 100 Series: VEE can vary +0.46 V / −0.8 V.
7. Within-device skew is defined as identical transitions on similar paths through a device.
Q
D
Driver
Device
Receiver
Device
Q
D
50 Ω
50 Ω
VTT
VTT = VCC − 2.0 V
Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
http://onsemi.com
4
475
700
MC100E256
Resource Reference of Application Notes
AN1404
− ECLinPS Circuit Performance at Non−Standard VIH Levels
AN1405
−
ECL Clock Distribution Techniques
AN1406
−
Designing with PECL (ECL at +5.0 V)
AN1503
−
ECLinPS I/O SPICE Modeling Kit
AN1504
−
Metastability and the ECLinPS Family
AN1568
−
Interfacing Between LVDS and ECL
AN1596
−
ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
−
Using Wire−OR Ties in ECLinPS Designs
AN1672
−
The ECL Translator Guide
AND8001
−
Odd Number Counters Design
AND8002
−
Marking and Date Codes
AND8020
−
Termination of ECL Logic Devices
http://onsemi.com
5
MC100E256
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
-N-
0.007 (0.180)
B
Y BRK
U
T L −M
M
0.007 (0.180)
M
S
N
T L −M
S
S
N
S
D
-L-
Z
-M-
D
W
X
V
28
1
G1
0.010 (0.250)
S
T L −M
S
N
S
VIEW D-D
Z
C
A
0.007 (0.180)
R
0.007 (0.180)
M
T L −M
S
N
S
M
T L −M
S
N
S
H
0.007 (0.180)
M
T L −M
N
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
-T-
T L −M
S
N
0.007 (0.180)
VIEW S
S
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIM G1, TRUE POSITION TO BE MEASURED
AT DATUM -T-, SEATING PLANE.
3. DIM R AND U DO NOT INCLUDE MOLD FLASH.
ALLOWABLE MOLD FLASH IS 0.010 (0.250)
PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
http://onsemi.com
6
INCHES
MIN
MAX
0.485 0.495
0.485 0.495
0.165 0.180
0.090 0.110
0.013 0.019
0.050 BSC
0.026 0.032
0.020
0.025
0.450 0.456
0.450 0.456
0.042 0.048
0.042 0.048
0.042 0.056
0.020
2°
10°
0.410 0.430
0.040
MILLIMETERS
MIN
MAX
12.32 12.57
12.32 12.57
4.20
4.57
2.79
2.29
0.33
0.48
1.27 BSC
0.81
0.66
0.51
0.64
11.58
11.43
11.58
11.43
1.07
1.21
1.07
1.21
1.42
1.07
0.50
2°
10°
10.42 10.92
1.02
M
T L −M
S
N
S
S
MC100E256
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
7
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC100E256/D
Similar pages