3-BIT 4:1 MUX-LATCH DESCRIPTION FEATURES ■ 950ps max. data to output ■ Extended 100E VEE range of –4.2V to –5.5V The SY10/100E256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ECL systems. Separate Select controls are provided for the leading 2:1 mux pairs (see block diagram). When the Latch Enable (LEN) is at a logic LOW, the latch is transparent and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW. ■ ■ ■ ■ 850ps max. latch enable to output Separate select controls Differential outputs Fully compatible with industry standard 10KH, 100K ECL levels ■ Internal 75KΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E256 ■ Available in 28-pin PLCC package E N R Q1 Q1 D Q2 E N R Q2 VCCO D2a 25 24 23 22 21 20 19 SEL1A SEL1B 26 18 27 17 SEL2 VEE 28 LEN MR 2 3 D1c 4 12 16 TOP VIEW PLCC J28-1 1 5 6 7 8 9 Q2 Q2 15 VCC Q1 14 Q1 13 VCCO Q0 10 11 D0d VCCO Q0 D D2c D2b Q0 D1b E N R D0a D0b D0c D2a D2b D2c D2d Q0 D1d D1a D1b D1c D1d D D1a D2d PIN CONFIGURATION BLOCK DIAGRAM D0a D0b D0c D0d SY10E256 SY100E256 SEL1A SEL1B PIN NAMES SEL2 LEN Pin MR Function D0x–D2x Parallel Data Inputs SEL1A, SEL1B First-stage Select Inputs SEL2 Second-stage Select Input LEN Latch Enable MR Master Reset Q0, Q0–Q2, Q2 Data Outputs VCCO VCC to Output Rev.: C 1 Amendment: /1 Issue Date: February, 1998 SY10E256 SY100E256 Micrel TRUTH TABLE Pin State Operation SEL2 H Output c/d Data SEL1A H Input d Data SEL1B H Input b Data DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — Unit Condition ps — ps — ps — — — 150 — — 150 — — 150 — — 69 69 83 83 — — 69 69 83 83 — — 69 79 83 96 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. tPLH tPHL Propagation Delay to Output D SEL1 SEL2 LEN MR 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 tS Set-up Time D SEL1 SEL2 400 600 500 275 300 250 — — — 400 600 500 275 300 250 — — — 400 600 500 275 300 250 — — — Hold Time D SEL1 SEL2 300 100 200 –275 –300 –250 — — — 300 100 200 –275 –300 –250 — — — 300 100 100 –275 –300 –250 — — — tRR Reset Recovery Time 700 600 — 700 600 — 700 600 — ps — tPW Minimum Pulse Width, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew tr tf Rise/Fall Time 20% to 80% tH — 50 — — 50 — — 50 — ps 1 275 475 700 275 475 700 275 475 700 ps — NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code 2 Package Type Operating Range SY10E256JC J28-1 Commercial SY10E256JCTR J28-1 Commercial SY100E256JC J28-1 Commercial SY100E256JCTR J28-1 Commercial SY10E256 SY100E256 Micrel 28 LEAD PLCC (J28-1) Rev. 03 3 SY10E256 SY100E256 Micrel MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4