SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994
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•
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DW OR NT PACKAGE
(TOP VIEW)
State-of-the-Art BiCMOS Design
Significantly Reduces ICCZ
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
High-Impedance State During Power Up
and Power Down
3-State B Outputs Sink 64 mA and Source
15 mA
Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
T/R
A1
A2
A3
A4
A5
VCC
A6
A7
A8
ODD/EVEN
ERR
description
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
OE
B1
B2
B3
B4
GND
GND
B5
B6
B7
B8
PARITY
The SN64BCT657 contains eight noninverting buffers with parity generator/checker circuits and control signals.
The transmit/receive (T/R) input determines the direction of data flow. When T/R is high, data flows from the
A port to the B port (transmit mode); when T/R is low, data flows from the B port to the A port (receive mode).
When the output-enable (OE) input is high, both the A and B ports are in the high-impedance state.
Odd or even parity is selected by a logic high or low level on the ODD/EVEN input. PARITY carries the parity
bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity
generator/checker in the receive mode.
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic
level that maintains the parity sense selected by the level at the ODD/EVEN input. For example, if ODD/EVEN
is low (even parity selected) and there are five high bits on the A bus, then PARITY is set to the logic high level
so that an even number of the nine total bits (eight A-bus bits plus parity bit) are high.
In the receive mode, after the B bus is polled to determine the number of high bits, the error (ERR) output logic
level indicates whether or not the data to be received exhibits the correct parity sense. For example, if
ODD/EVEN is high (odd parity selected), PARITY is high, and there are three high bits on the B bus, then ERR
is low, indicating a parity error.
The SN64BCT657 is characterized for operation from − 40°C to 85°C and 0°C to 70°C.
Copyright 1994, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
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• DALLAS, TEXAS 75265
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POST OFFICE BOX 655303
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3−1
SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994
FUNCTION TABLE
NUMBER OF A OR B
INPUTS THAT ARE HIGH
0, 2, 4, 6, 8
1, 3, 5, 7
Don’t care
INPUTS
OUTPUTS
OE
T/R
ODD/EVEN
INPUT/OUTPUT
PARITY
ERR
OUTPUT MODE
L
H
H
H
Z
Transmit
L
H
L
L
Z
Transmit
L
L
H
H
H
Receive
L
L
H
L
L
Receive
L
L
L
H
L
Receive
L
L
L
L
H
Receive
L
H
H
L
Z
Transmit
L
H
L
H
Z
Transmit
L
L
H
H
L
Receive
L
L
H
L
H
Receive
L
L
L
H
H
Receive
L
L
L
L
L
Receive
H
X
X
Z
Z
Z
logic symbol†
OE
T/R
ODD/EVEN
A1
A2
A3
A4
A5
A6
A7
A8
24
1
11
2
3
G3
3 EN1/3G5 [REC]
3 EN2 [XMIT]
N4
1
23
1
2
Z11
22
4
21
5
20
6
17
8
16
9
15
10
14
11
12
13
14
15
16
17
18
2k
13
4, 2
B2
B3
B4
B5
B6
B7
B8
PARITY
5
4, 1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
3−2
B1
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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12
ERR
SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994
logic diagram (positive logic)
T/R 1
OE 24
2
A1
A2
A3
A4
A5
A6
A7
A8
ODD/EVEN
23
3
22
4
21
5
20
6
17
8
16
9
15
10
14
B1
B2
B3
B4
B5
B6
B7
B8
13
11
12
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PARITY
ERR
3−3
SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the disabled or power-off state, VO . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
Voltage range applied to any output in the high state, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
VIH
Supply voltage
VIL
IIK
Low-level input voltage
0.8
V
Input clamp current
−18
mA
IOH
High-level output current
IOL
Low-level output current
∆t /∆VCC
Power-up ramp rate
High-level input voltage
2
A port
3−4
V
−3
B port, PARITY, ERR
−15
A port
24
B port, PARITY, ERR
64
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POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
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−40
mA
mA
µs / V
2
TA
Operating free-air temperature
NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
V
85
°C
SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VCC = 4.5 V,
VCC = 4.5 V,
II = −18 mA
IOH = − 3 mA
VCC = 4.5 V,
VCC = 4.75 V,
IOH = − 15 mA
IOH = − 3 mA
VCC = 4.5 V,
VCC = 4.5 V,
IOL = 24 mA
IOL = 64 mA
OE
VCC = 0,
VI = 7 V
ODD/EVEN
VCC = 0,
VI = 7 V
VCC = 0 to 5.5 V,
VI = 5.5 V
Any output
VOH
B port, PARITY, ERR
Any output
A port
VOL
TEST CONDITIONS
B port, PARITY, ERR
T/R
II
MIN
TYP†
2.4
3.3
2
3.1
T/R, OE
0.5
0.55
OE = 4.5 V
20
T/R = 4.5 V
20
20
200
VCC = 5.5 V,
20
VI = 2.7 V
IOZH
IOZL
ERR
ERR
ICCL
ICCH
ICCZ
Ci
Control inputs
−70
VCC = 5.5 V,
−20
VI = 0.5 V
B port, PARITY
µA
−20
−60
−200
−125
−300
VCC = 5.5 V,
VO = 0
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
−50
µA
VCC = 5.5 V,
VCC = 5.5 V,
Outputs open
90
mA
Outputs open
2
mA
VCC = 5.5 V,
VCC = 5 V,
Outputs open
1
mA
VCC = 5 V,
VO = 2.5 V or 0.5 V
VI = 2.5 V or 0.5 V
A port
Cio
µA
20
A port
B port, PARITY, ERR
µA
200
ODD/EVEN
IOS§
V
100
A or B port, PARITY
T/R, OE
V
0.42
ODD/EVEN
IIL‡
V
0.35
A or B port, PARITY
IIH‡
UNIT
−1.2
2.7
A port
B port, PARITY
MAX
50
6.5
mA
µA
pF
10
Co
ERR
VCC = 5 V,
VO = 2.5 V or 0.5 V
† All typical values are at VCC = 5 V, TA = 25°C.
‡ For I/O ports, the parameters IIH and IIL include the off-state output current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
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•
14
10
pF
pF
3−5
SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994
switching characteristics over recommended range of supply voltage, CL = 50 pF (unless
otherwise noted) (see Note 3)
TA = − 40°C
to 85°C
VCC = 5 V,
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
A
PARITY
tPLH
tPHL
ODD/EVEN
PARITY, ERR
tPLH
tPHL
B
ERR
tPLH
tPHL
PARITY
ERR
tPZH
tPZL
OE
A, B, PARITY, or ERR
tPHZ
tPLZ
OE
A, B, PARITY, or ERR
PARAMETER
TYP
MAX
MIN
MAX
MIN
MAX
1.1
3.1
6
1.1
6.9
1.1
6.6
2
5.3
8.5
2
9.3
2
9
3
7.4
12.7
3
16.4
3
15.4
4.6
8.6
14.1
4.6
16.9
4.6
15.9
1.1
4.1
6.4
1.1
7.7
1.1
7.1
2.6
5.5
8.3
2.6
9.3
2.6
9
3.1
7.4
12.6
3.1
16.4
3.1
15.3
4.4
6.5
13.3
4.4
16.6
4.4
15.5
3.4
7.7
10.7
3.4
14.4
3.4
13.2
5.5
8.8
12
5.5
14.9
5.5
13.9
1.8
5.1
7.7
1.8
9.5
1.8
9.1
3.2
6.7
14.2
3.2
17
3.2
16.3
2.6
5.7
8
2.6
9.5
2.6
9.1
2
5
7.4
2
8.8
2
8
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UNIT
MIN
NOTE 3: Load circuits and voltage waveforms are shown in Section 1.
3−6
TA = 0°C
to 70°C
ns
ns
ns
ns
ns
ns
ns
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