dm00067257

AN4182
Application note
LNBH26 dual supply and control IC with step-up and I²C
interface
Introduction
This application note provides additional information and suggestions about the correct use of the
LNBH26 device. All waveforms shown are based on the evaluation board STEVAL-CBL011V1 and
STEVAL-CBL012V1 described in Section 5: "Component selection guide" . The LNBH26 is a low-cost
integrated solution for supplying/interfacing dual satellite LNB modules. Its performance is very good
with the minimum quantity of external components. It includes all functions needed for tuner STB supply
and interface, in accordance with international standards. Moreover, it includes an I 2C bus interface and,
thanks to a fully integrated step-up DC-DC converter, it works with a single input voltage supply range
from 8 V to 16 V.
Figure 1: LNBH26 internal block diagram
DSQIN-A ADDR SCL SDA
DSQIN-B
DAC
Drop control
Tone ctrl
Diagnostics
Protections
Gate ctrl
VUP-A
Linear
Regulator
PGND
VUP-B
Linear
Regulator
Gate ctrl
PGND
VOUT-A
PWM CTRL
PWM CTRL
I²C Digital core
BPSW-A
VOUT-B
DETIN-B
DETIN-A
DSQOUT-A
Isense
LX-B
Isense
LX-A
Tone
detector
Tone
detector
Current
Limit
selection
Voltage
reference
DSQOUT-B
BPSW-B
FLT
ISEL GND BYP VCC
December 2015
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www.st.com
Contents
AN4182
Contents
1
2
Block diagram description.............................................................. 3
1.1
Step-up controller .............................................................................. 3
1.2
Voltage reference block .................................................................... 3
1.3
I2C interface digital core and diagnostic ............................................ 3
1.4
Tone detector .................................................................................... 4
1.5
Linear post regulator ......................................................................... 4
DiSEqC data encoding .................................................................... 5
2.1
22 kHz external source (EXTM=TEN=1) ........................................... 5
2.2
DiSEqC data envelope source (EXTM=0; TEN=1) ............................ 6
2.3
22 kHz tone in continuous mode (EXTM=0; TEN=1; DSQIN pin=H) . 8
3
DiSEqC data implementation .......................................................... 9
4
Pin description .............................................................................. 11
5
Component selection guide .......................................................... 13
6
7
2/24
5.1
Input capacitors ............................................................................... 15
5.2
DC-DC converter output capacitors ................................................ 15
5.3
DC-DC converter Schotty diode ...................................................... 15
5.4
DC-DC converter inductor ............................................................... 16
5.5
Output current limit selection ........................................................... 17
5.6
Undervoltage diode protection ........................................................ 17
5.7
DiSEq C2.0 implementation and inductor selection ........................ 18
5.8
TVS diode ....................................................................................... 18
Layout guidelines .......................................................................... 20
6.1
PCB layout ...................................................................................... 20
6.2
Start-up procedure .......................................................................... 22
Revision history ............................................................................ 23
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1
Block diagram description
Block diagram description
The LNBH26 internal blocks are described in the following sections. There are two
completely independent sections. Except for the VCC and I²C inputs, each circuit can be
separately controlled and has its own independent external components. All the
specifications below must be considered equal for both sections (A/B).
1.1
Step-up controller
The LNBH26 features a built-in step-up DC-DC converter that, from a single supply source
ranging from 8 V to 16 V, generates the voltages that allow the linear post-regulator to work
with minimum power dissipation. The external components of the DC-DC converter are
connected to the LX and VUP pins. No external power MOSFET is needed.
1.2
Voltage reference block
This block includes the undervoltage lockout circuit, which disables the whole circuit when
the supplied VCC pin drops below a fixed threshold (4.7 V typ.) and a power-on reset sets
all the I2C registers to zero when the VCC turns on and rises from zero above the threshold
(4.8 V typ.). If the input voltage is lower than LPD (low power diagnostic) minimum
thresholds (6.7 V typ.), the PNG I²C bit is set to “1” by the voltage reference block and the
FLT pin is set low.
1.3
I2C interface digital core and diagnostic
The device main functions are controlled by I 2C bus, the data communication protocol from
the main microprocessor to the LNBH26 and vice versa, which takes place through SDA
and SCL pins. By writing to 4 control registers, all the LNBH26 functions can be managed.
Moreover, 2 status registers can be read back and 8 diagnostic functions are received by
the IC. The LNBH26 I2C interface address can be selected between two different
addresses by setting the voltage level of the dedicated ADDR pin.
Eight bits report the diagnostic status of eight internal monitoring functions:
OLF: overload fault. If the output current required exceeds the current limit threshold or
short-circuit occurs, OLF I2C bit is set to "1".
VMON: output voltage monitoring. If the output voltage level is below the guaranteed limits,
the VMON I²C bit is set to "1".
PDO: pull-down overcurrent. If the device output is raised to a voltage level higher than
output nominal voltage selected, PDO I²C bit is set to "1". This may happen due to an
external voltage source present on the LNB output (VOUT pin).
OTF: overtemperature fault. If an overheating occurs, (junction temperature exceeds 150
°C typ.) the OTF I2C bit is set to "1".
PNG: power not good. If the input voltage (VCC pin) is lower than LPD minimum threshold
(6.7 V typ.) the PNG I2C bit is set to "1".
TDET: tone detection. 22 kHz tone presence is detected on the DETIN pin.
TMON: tone monitoring. If the 22 kHz tone amplitude and/or the tone frequency is out of
the guaranteed limits, the TMON I²C bit is set to "1".
IMON: minimum output current diagnostic to detect if no LNB is connected on the bus or
cable not connected to the IRD, the LNBH26 is provided with a minimum output current flag
by the IMON I²C bit, which is set to "1" if the output current is lower than 12 mA (typ.).
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Block diagram description
1.4
AN4182
Tone detector
This block provides a complete circuit to decode the 22 kHz burst code present on the
DETIN pin in a digital signal by the DSQOUT pin where an open drain MOSFET is
connected. The tone is also monitored and a dedicated bit (TMON) provides the diagnostic
function described in the Section 1.3: "I2C interface digital core and diagnostic" .
1.5
Linear post regulator
The output voltage selection and the current selection commands join this block, which
manages all the LNB output functions. This block gives feedback to the I2C interface
overcurrent protection and output settings. The linear post-regulator current limit threshold
can be set by an external resistor connected to the ISEL pin.
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2
DiSEqC data encoding
DiSEqC data encoding
The internal 22 kHz tone generator is factory-trimmed in accordance with current
DiSEqC™ standards and its waveform is internally controlled by the LNBH26 tone
generator in terms of rise/fall time and amplitude. The 22 kHz tone can be controlled in
different ways through DISQIN logic pin and two I²C bits (EXTM and TEN).
2.1
22 kHz external source (EXTM=TEN=1)
If an external 22 kHz source DiSEqC data is available, it can be connected to the DSQIN
logic pin (TTL compatible). The EXTM and TEN I²C bits must be set to "1". In this case the
frequency and the duty cycle of the output tone are defined by the external 22 kHz signal
on the DSQIN pin.
Figure 2: 22 kHz external source
Before sending the TTL signal to the DSQIN pin, the EXTM and TEN bits must be
previously set to "1". When the DSQIN internal circuit detects the 22 kHz TTL external
signal code, the LNBH26 activates the 22 kHz tone on the VOUT pin with about 1 μs delay
from TTL signal activation, and it stops with about 60 μs delay after the 22 kHz TTL signal
on DSQIN has expired, refer to Figure 3: "22 kHz external source activation delay" and
Figure 4: "22 kHz external source deactivation delay".
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DiSEqC data encoding
AN4182
Figure 3: 22 kHz external source activation delay
Figure 4: 22 kHz external source deactivation delay
2.2
DiSEqC data envelope source (EXTM=0; TEN=1)
Using an external DiSEqC data envelope source connected to the DSQIN logic pin, the I²C
tone control bits must be set: EXTM = 0 and TEN = 1. In this manner, the internal 22 kHz
signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz tone.
During the period in which the DSQIN is kept high, the internal control circuit activates the
22 kHz tone output.
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DiSEqC data encoding
Figure 5: DiSEqC data envelope source
22 kHz tone on the VOUT pin is active with about 6 μs delay from the DSQIN TTL signal
rising edge, and it stops with a delay time in the range from 15 μs to 60 μs after the 22 kHz
TTL signal on DSQIN has expired (refer to Figure 6: "DiSEqC data envelope source
activation delay" and Figure 7: "DiSEqC data envelope source deactivation delay").
Figure 6: DiSEqC data envelope source activation delay
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DiSEqC data encoding
AN4182
Figure 7: DiSEqC data envelope source deactivation delay
2.3
22 kHz tone in continuous mode (EXTM=0; TEN=1; DSQIN
pin=H)
If a 22 kHz presence is requested in continuous mode, the integrated tone generator can
be activated through the TEN I²C bit. In this case the DSQIN TTL pin must be pulled high
and the EXTM bit set to "0".
Figure 8: 22 kHz tone in continuous mode
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3
DiSEqC data implementation
DiSEqC data implementation
The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC 2.0 interfacing.
The input pin (DETIN) must be AC coupled to the DiSEqC bus, and the extracted PWK
data is available on the DSQOUT pin (refer to below figure).
Figure 9: DSQOUT output pin
To comply with the bi-directional DiSEqC 2.0 bus hardware requirements, an output RL
filter is needed. In order to avoid 22 kHz waveform distortion during tone transmission, the
LNBH26 is provided with the BPSW pin to be connected to an external transistor, which
allows bypassing the output RL filter in DiSEqC 2.x applications while in transmission mode
(refer to belo figure). Before starting tone transmission by DSQIN pin, the TEN bit has to be
set to "1" and after ending tone transmission, the TEN bit has to be set to "0".
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DiSEqC data implementation
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Figure 10: BPSW pin behavior during tone transmission
10/24
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4
Pin description
Pin description
The LNBH26 is available in QFN24L with exposed pad package for surface mount
assembly. The below figure shows the device pinout while Table 1 briefly summarizes the
pin functions.
Figure 11: LNBH26 pin configuration
24
24
DSQIN-B
1
23
23
22
22
DSQOUT
DSQINA
-A
21
21
VUP- A
20
20
19
19
VOUT-A DETIN -A
DSQOUT
--B
BPSW-A
18
18
2
FLT
VCC
17
17
3
LX-A
BYP
16
16
4
PGND
GND
15
15
5
LX-B
-
NC
14
14
6
ADDR
BPSW-B
SCL
SDA
ISEL
7
8
9
13
VUP-- B VOUT-B DETIN-B
10
11
12
Table 1: Pin description
Pin
Symbol
Name
Function
Open drain output for IC fault conditions. It is set low in
case of overload (OLF bit) or overheating status (OTF
bit) is detected. To be connected to pull-up resistor (5 V
max.)
2
FLT
FLT
5/3
LX-B/LX-A
NMOS drain
4
P-GND
Power ground
6
ADDR
Address
setting
7
SCL
Serial clock
Clock from/to I2C bus
8
SDA
Serial data
Bi-directional data from/to I²C bus
9
ISEL
Current
selection for
both channel
A and B
15
GND
Analog ground
16
BYP
Bypass
capacitor
17
VCC
Supply input
Integrated N-channel power MOSFET drain
DC-DC converter power ground to be connected
directly to the exposed pad
Two I2C bus addresses available by setting the address
pin level voltage
The resistor RSEL connected between ISEL and GND
defines the linear regulator current limit threshold. Refer
to output current limit selection in application
information section
Analog circuit ground. To be connected directly to the
exposed pad
Needed for internal pre-regulator filtering. The BYP pin
connects an external ceramic capacitor. Any connection
of this pin to external current or voltage sources may
cause permanent damage to the device
8 to 16 V IC DC-DC power supply
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Pin description
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Pin
Symbol
Name
Function
13/18
BPSW-B /
BPSW-A
Switch control
To be connected to an external transistor to bypass the
output RL filter needed in DiSEqC™ 2.x applications
during the DiSEqC™ transmitting mode (see typical
application circuits). Set to ground if it is not used
12/19
DETIN-B /
DETIN-A
Tone detector
input
22 kHz tone decoder input, must be AC coupled to the
DiSEqC 2.0 bus. Set to ground if it is not used
11/20
VOUT-B /
VOUT-A
LNB output
port
Output of the integrated very low drop linear regulator.
See truth table for voltage selections and description
10/21
VUP-B /
VUP-A
Step-up
voltage
Input of the linear post-regulator. The voltage on this
pin is monitored by the internal step-up controller to
keep a minimum dropout across the linear pass
transistor
DSQIN for
DiSEqC
envelope input
or external 22
kHz TTL input
It can be used as DiSEqC envelope input or external 22
kHz TTL input depending on the EXTM I²C bit setting
as follows: EXTM=0, TEN=1: it accepts the DiSEqC
envelope code from the main microcontroller. The
LNBH26 uses this code to modulate the internally
generated 22 kHz carrier. If EXTM=TEN=1: it accepts
external 22 kHz logic signals which activate the 22 kHz
tone output (refer to DATA ENCODING application
information). Pull up high if the tone output is activated
by TEN I²C bit only
24/22
DSQIN-B /
DSQIN-A
1/23
DSQOUT-B /
DSQOUT-A
DiSEqC
output
Open drain output of the tone detector to the main
microcontroller for DiSEqC 2.0 data decoding. It is low
when tone is detected to the DETIN input pin. Set to
ground if it is not used
Exposed
pad
Exposed pad
Exposed pad
To be connected with power ground and to the ground
layer through vias to dissipate heat
14
NC
Not internally
connected
Not internally connected pins. These pins can be
connected to GND to improve thermal performance
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5
Component selection guide
Component selection guide
The LNBH26 application schematic in the below figures shows the typical configurations for
a single LNB power supply for DiSEqC 1.x communication.
Figure 12: STEVAL-CBL011V1 evaluation board schematic for DiSEqC1.x communication
D2
to LNB
Vup
Vout
C3
D1
C2
C5
D3
TVS
LX
LNBH26
section A/B
L1
VIN
12 V
DiSEqC
22 kHz
C4
TTL
DSQIN
or
DiSEqC
envelope
DETIN
Vcc
C1
BPSW
ADDR
TTL
I2C Bus
{
DSQOUT
SDA
SCL
FLT
RSEL
ISEL
P-GND
A-GND
Byp
C7
TVS diode has to be used if surge protection is required.
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Component selection guide
AN4182
Figure 13: STEVAL-CBL012V1 evaluation board schematic for DiSEqC1.x communication
D2
L2
Vup
to LNB
Vout
C3
D1
R9
C2
C5
D3
TVS
LX
LNBH26
section A/B
L1
R3
TR1
C6
BPSW
R2
R5
Vin
12 V
C1
DiSEqC
22 kHz
C4
TTL
DSQIN
or
DiSEqC
envelope
DETIN
Vcc
ADDR
TTL
I2C Bus
{
DSQOUT
SDA
SCL
FLT
RSEL
ISEL
P-GND
A-GND
Byp
C7
Table 2: LNBH26 evaluation board BOM list
Component
IC1
LNBH26 (QFN24L) exposed pad
C1
10 μF, 25 V ceramic capacitor
C2A, C2B
100 μF, 50 V electrolytic capacitor
C3A, C3B
1 μF, 50 V ceramic capacitor
C6A, C6B
0.01 µF, 35 V ceramic capacitor
C4, C5A, C5B,
C7
0.22 μF, 50 V ceramic capacitor
D1A, D1B
STPS130A or any similar Schottky diode
D2A, D2B
S1A general purpose diode
D3A, D3B
BAT43 (or any Schottky diode with IF(AV) > 0.2 A, VRRM > 25 V) or BAT30,
BAT54, TMM BAT43, 1N5818
TVSA, TVSB
LNBTVS22-XX TVS protection diode is suggested. Any other solution can be
used depending on the requested surge protection level
L1A, L1B
10 μH inductor with ISAT>IPEAK
L2A , L2B
a
220 µH inductor with current rating higher than rated output current
TR1A and
TR1Ba
SI2003BDS 30 V PMOS
RSEL
16.2 kΩ 1/16 W resistor
R2A, R2B, R3A,
R3Ba
4.7 kΩ resistor
R5A, R5Ba
10 kΩ resistor
R9A, R9Aa
15 kΩ 1/4 W resistor
a
14/24
Notes
For the STEVAL-CBL012V1 only.
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5.1
Component selection guide
Input capacitors
A ceramic bypass capacitor (C1) between 10 µF and 47 µF placed near the LNBH26 is
needed for a stable operation. In any case, a ceramic capacitor in the range from 100 nF to
470 nF is recommended to reduce the switching noise on the input voltage pin (C4 in
Figure 12: "STEVAL-CBL011V1 evaluation board schematic for DiSEqC1.x
communication" and Figure 13: "STEVAL-CBL012V1 evaluation board schematic for
DiSEqC1.x communication").
5.2
DC-DC converter output capacitors
Low-cost electrolytic capacitors are needed on the DC-DC converter output stage (C2 in
Figure 12: "STEVAL-CBL011V1 evaluation board schematic for DiSEqC1.x
communication" and Figure 13: "STEVAL-CBL012V1 evaluation board schematic for
DiSEqC1.x communication"). Moreover, a ceramic capacitor between 1 μF and 4.7 μF is
recommended to reduce high frequency switching noise (C3 in Figure 12: "STEVALCBL011V1 evaluation board schematic for DiSEqC1.x communication" and Figure 13:
"STEVAL-CBL012V1 evaluation board schematic for DiSEqC1.x communication"). The
switching noise is due to the voltage spikes of the fast switching action of the output switch,
and to the parasitic inductance of the output capacitors. To further reduce switching noise,
a ferrite bead is recommended between the capacitors (refer to the below figure).
Figure 14: DC-DC converter output stage with ferrite bead
The capacitor voltage rating must be at least 25 V, but if the highest voltage selection
condition is used (VSEL1= VSEL2= VSEL3= VSEL4 = 1), 35 V or higher voltage capacitors are
suggested.
5.3
DC-DC converter Schotty diode
In typical application conditions, 1 A Schottky diode is suitable for the LNBH26 DC-DC
converter. Taking into consideration that the DC-DC converter Schottky diode must be
selected depending on the application conditions,(V RRM > 25 V) one N-channel Schottky
diode, such as the STPS130A is recommended. The average current flowing through the
Schottky diode is lower than Ipeak and can be calculated using the equation 1. In worst-case
conditions, such as low input voltage and higher output current, a Schottky diode,
supporting the Ipeak, should be selected. Ipeak can be calculated using equation 2.
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Component selection guide
Equation 1:
AN4182
Id = IOUT x VOUT/VIN
Table 3: Recommended Schottky diode
Vendor
Order code
IF(AV)
VF(max.)
1N5818
1A
0.50 V
1N5819
1A
0.55 V
STPS130A
1A
0.46 V
STPS1L30A
1A
0.30 V
STPS2L30A
2A
0.45 V
1N5822
3A
0.52 V
STPS340
3A
0.63 V
STPS3L40A
3A
0.5 V
STMicrolectronics
5.4
DC-DC converter inductor
The LNBH26 operates with a 10 µH inductor for the entire range of supply voltage and load
current. The inductor saturation current rating (where inductance is approximately 70% of
zero current inductance) must be greater than the switch peak current (Ipeak) calculated at:



maximum load (IOUTmax.)
minimum input voltage (VINmin.)
maximum DC-DC output voltage (VUPmax. = VOUTmax. + 1 V)
In this condition the switch peak current is calculated using the equation 2:
Equation 2:
Ipeak =
VUPmax.· IOUTmax. VINmin.
VIN min. )
+
1(
Eff · VI Nmin.
2LF
VUPmax.
where:
Eff: is the efficiency of the DC-DC converter (93% typ. at the highest load)
L: is the inductance (10 µH typ.)
F: is the PWM frequency (440 kHz typ.)
Here below an example by using 10 µH coil.
The application condition as follows:
VOUTmax. = 19.150 V (supposing VSEL1 = VSEL2 = VSEL4 = 1, VSEL2 = 0)
VINmin. = 11 V
VUPmax. = VOUTmax. +VDROP = 19.150 V+1 V = 20.150 V
IOUTmax. = 500 mA
Eff = 90%
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Component selection guide
By using equation 1, Ipeak is:
Equation 3:
20.150· 0.5
11
+
Ipeak =
2 ·10 ·10-6 · 440 ·103
0.9·11
11
)=1.23 A
(1- 20.150
Table 4: Recommended inductors
Supplier
Order code
ISAT(A)
DRC(mΩ)
Mounting type
Coilcraft
LPS6235-103MLB
2.3
100
SMT
TDK
SLF6045-100M1R6
1.6
39
SMT
EPCOS
B82472G6103M
1.9
53
SMT
Several inductors suitable for the LNBH26 are listed in the above table, although there are
many other manufacturers and devices that can be used. Consult each manufacturer for
more detailed information since many different shapes and sizes are available. Ferrite core
inductors should be used to obtain the best efficiency. Choose an inductor that can handle
at least the Ipeak current without saturating, and ensure that the inductor has a low DRC
(copper wire resistance) to minimize power losses and, therefore, to maximize total
efficiency.
5.5
Output current limit selection
The linear regulator current limit threshold can be set through an external resistor
connected to ISEL pin. The resistor value defines the output current limit using the below
equation:
Equation 4:
with ISET = 0
Equation 5:
Where RSEL is the resistor connected between the ISEL pin and GND. The highest
selectable current limit threshold is 1.0 A (typ.) with RSEL = 11.5 kΩ.
5.6
Undervoltage diode protection
During a short-circuit removal on the LNB output, negative voltage spikes may occur on the
VOUT pin. To prevent reliability problems, a low-cost Schottky diode (D3) is used between
this pin and GND (see D3 in Figure 12: "STEVAL-CBL011V1 evaluation board schematic
for DiSEqC1.x communication" and Figure 13: "STEVAL-CBL012V1 evaluation board
schematic for DiSEqC1.x communication").
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Component selection guide
5.7
AN4182
DiSEq C2.0 implementation and inductor selection
To comply with DiSEqC 2.x requirements, an output R-L filter is needed. The internal 22
kHz signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz
tone and the LNBH26 is provided with the BPSW connected to an external transistor (refer
to Figure 13: "STEVAL-CBL012V1 evaluation board schematic for DiSEqC1.x
communication"), which allows the output RL filter to be bypassed during the 22 kHz tone
transmission. This solution allows the 22 kHz tone to pass without any losses due to the RL filter impedance. With respect to the minimum DC voltage requirement, an inductor with a
current rating higher than the rated output current and a low DRC to minimize the voltage
drop should be used.
For example, supposing:
- IOUT = 500 mA
- DRC = 33 m (Coilcraft inductor DO3340P-224)
Equation 6:
Vdrop (V) = DCR (Ω) x IOUT (A) = 0.440 x 0.5 = 0.22 V
Several inductors suitable for the LNBH26 are listed in the below table.
Table 5: Recommended inductors
5.8
Supplier
Order code
ISAT(A)
DRC(mΩ)
Mounting type
Sumida
CD104-221MC
RHC110-221M
1.6
2.4
67
88
SMD
T.H.
Toko
822LY-221K
824LY-221K
A671HN-221L
A814LY-221M
1.3
1.72
2.44
2.0
70
76
21
75
T.H.
T.H.
T.H.
SMD
Panasonic
ELC08D221E ELC11D221E
1.8
3.2
51
40
T.H.
T.H.
Coilcraft
DO5010H-224
MSS1278-224
DO3340P-224
2.4
2.3
1.6
380
360
440
SMT
SMT
SMT
TVS diode
The LNBH26 device is directly connected to the antenna cable in a set-top box.
Atmospheric phenomenon can cause high voltage discharges on the antenna cable
causing damage to the attached devices. Surge pulses occur due to direct or indirect
lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic
fields causing high voltage or current transients. The LNBH26 device doesn't withstand
such high energy discharges, so transient voltage suppressor (TVS) devices are used to
protect the LNBH26 and other devices electrically connected to the antenna cable.
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Component selection guide
Figure 15: Recommended TVS diode connection
The LNBTVS, developed by STMicroelectronics, is a dedicated lightning and electrical
overstress surge protection for LNB voltage regulators. This protection complies with the
stringent IEC61000-4-5 standard with surges up to 500 A with a whole range of products
for a cost/performance optimization.
The correct choice of the TVS diode must be taken into account according to the maximum
peak power dissipation that the diode supports.
Table 6: Recommended ST LNBTVS
Order code
VBR typ. (V)
Ppp (W)
10/100 µs
LNBTVS4-220
23.1
1800
LNBTVS4-221
23.1
2000
LNBTVS4-222S
23.1
2000
LNBTVS6-221S
21.3
3000
Select the TVS diode, which is able to support the Ppp(W).
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Layout guidelines
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AN4182
Layout guidelines
Due to high current levels and fast switching waveforms, which radiate noise, a proper PC
board layout and a star ground configuration to protect sensitive analog ground are very
important. Besides, lead lengths should be minimized to reduce stray capacitances, trace
resistance, and radiated noise. Ground noise could be minimized by connecting GND, the
input bypass capacitor ground lead, and the output filter capacitor ground lead to a single
point (star ground configuration). Input bypass capacitors (C1 and C4) should be placed as
close as possible to VCC and GND and the DC-DC output capacitors (C2 and C3) as close
as possible to VUP. Excessive noise on the VCC input may falsely trigger the undervoltage
circuitry, resetting the I2C internal registers. If this occurs, the registers are set to zero and
the LNBH26 is in shutdown mode.
6.1
PCB layout
Any switch mode power supply requires a good design of the PCB (printed circuit board)
layout in order to achieve the top of performance in terms of system functionality.
Component placing, GND trace routing and their widths are usually the major issues. Basic
rules, commonly used for DC-DC converters for a good PCB layout, should be followed. All
traces, carrying current, should be drawn on the PCB as short and thick as possible. This
should minimize resistive and inductive parasitic effects, gaining system efficiency.
Figure 16: STEVAL-CBL011V1 top layer
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Layout guidelines
Figure 17: STEVAL-CBL011V1 bottom layer
Figure 18: STEVAL-CBL011V1 component layout
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Layout guidelines
6.2
AN4182
Start-up procedure
To test the board, you need:






PC with USB port
USB I2C BUS interface
LNBH25L/26 testing software
Dual output power supply (1 A clamp current or higher)
Voltmeter
Oscilloscope
Step 1: the LNBH25L/26 testing software
Step 2: plug the I2C connector in CN6
Step 3: supply the evaluation board with CN1
Step 4: test the evaluation board
Figure 19: PCB connector
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Revision history
Revision history
Table 7: Document revision history
Date
Revision
17-Dec-2015
1
DocID023774 Rev 1
Changes
First release.
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