1/2 Phase Controller for CPU and Chipset Applications

NCP5386, NCP5386A,
NCP5386B
1/2 Phase Controller for
CPU and Chipset
Applications
The NCP5386 is a one− or two−phase buck controller which
combines differential voltage and current sensing, and adaptive
voltage positioning to power both AMD and Intel processors and
chipsets. Dual−edge pulse−width modulation (PWM) combined with
inductor current sensing reduces system cost by providing the fastest
initial response to transient load events. Dual−edge multi−phase
modulation reduces total bulk and ceramic output capacitance
required to satisfy transient load−line regulation.
A high performance operational error amplifier is provided, which
allows easy compensation of the system. The proprietary method of
Dynamic Reference Injection makes the error amplifier
compensation virtually independent of the system response to VID
changes, eliminating tradeoffs between overshoot and dynamic VID
performance.
Features
• Meets Intel’s VR 10.0 and 11.0, and AMD Specifications
• No load Intel VR Offset of −19 mV (NCP5386), +20 mV
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(NCP5386A), and 0 mV (NCP5386B)
Dual−Edge PWM for Fastest Initial Response to Transient Loading
High Performance Operational Error Amplifier
Supports both VR11 and Legacy Soft−Start Modes
Dynamic Reference Injection (Patent# 7057381)
DAC Range from 0.5 V to 1.6 V
0.5% System Voltage Accuracy from 1.0 V to 1.6 V
True Differential Remote Voltage Sensing Amplifier
Phase−to−Phase Current Balancing
“Lossless” Differential Inductor Current Sensing
Differential Current Sense Amplifiers for each Phase
Adaptive Voltage Positioning (AVP)
Frequency Range: 100 kHz – 1.0 MHz
OVP with Resettable, 8 Event Delayed Latch
Threshold Sensitive Enable Pin for VTT Sensing
Power Good Output with Internal Delays
Programmable Soft−Start Time
This is a Pb−Free Device*
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MARKING
DIAGRAMS
1
1
NCP5386x
AWLYYWWG
32
QFN32, 5 x 5*
MN SUFFIX
CASE 485AF
*Pin 33 is the thermal pad on the bottom of the device.
NCP5386 = Specific Device Code
x
= Blank, A or B
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping†
NCP5386MNR2G*
QFN32
(Pb−Free)
2500 /
Tape & Reel
NCP5386AMNR2G*
QFN32
(Pb−Free)
2500 /
Tape & Reel
NCP5386BMNR2G*
QFN32
(Pb−Free)
2500 /
Tape & Reel
Device
*Temperature Range: 0°C to 85°C
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
• Desktop Processors and Chipsets
• Server Processors and Chipsets
• DDR
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 3
1
Publication Order Number:
NCP5386/D
27
26
25
12VMON
G2
28
29
NTC
VR_RDY
30
31
VCC
CS2N
NCP5386/A/B
1/2−Phase Buck Controller
(QFN32)
CS1N
VFB
COMP
DIFFOUT
VDRP
16
9
CS1
AGND Down−Bonded to
Exposed Flag
15
8
DACMODE
VS−
VID7
14
7
13
VID6
VS+
VID5
6
SS
5
NC
VID4
CS2
12
4
VR_FAN
VID3
ILIM
3
DRVON
ROSC
VID2
G1
11
VID1
2
10
1
EN
VID0
32
NCP5386, NCP5386A, NCP5386B
Figure 1. Pin Connections
(Top View)
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2
24
23
22
21
20
19
18
17
NCP5386, NCP5386A, NCP5386B
12 V_FILTER
+5 V
12 V_FILTER
VTT
680 PULLUPS
C4
+5 V
RVCC
CVCC1
NCP3418B
RNTC1
U1
VCC
VID0
VID0
VID1
VID1
VID2
VID2
VID3
VID3
VID4
VID4
VID5
VID5
VID6
VID6
VID7
VID7
RNTC2
GND
NTC
OD
IN
VR_RDY
VR_FAN
CS1
CS1N
12 V_FILTER
NCP3418
VS−
VCC
VS+
BST
DRVH
OD
SW
DRVL
NCP5386/A/B
IN
CFB1
12 V_FILTER
CS2
CS2N
RISO2
RS1
G2
VR_FAN
RT2
PGND
RT1
CS1
VR_RDY
RISO1
SW
G1
EN
VR_EN
BST
DRVH
DRVL
12VMON
DACMODE
VID_SEL
VCC
PGND
RS2
RFB1
DIFFOUT
CS2
RFB
VFB
RDRP
VDRP
CD1
RD1
CF
RF
DRVON
COMP
ILIM
ROSC SS
CH
RVFB
RLIM1
CSS
RLIM2
RT2 LOCATED NEAR OUTPUT INDUCTORS
VCCP
+
VSSP
CPU/MCH
GND
Figure 2. 2−Phase Application Schematic
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3
NCP5386, NCP5386A, NCP5386B
12 V_FILTER
+5 V
12 V_FILTER
VTT
680 PULLUPS
+5 V
RVCC
CVCC1
NCP3418B
RNTC1
U1
VCC
VID0
VID0
VID1
VID1
VID2
VID2
VID3
VID3
VID4
VID4
VID5
VID5
VID6
VID6
VID7
VID7
RNTC2
DGND
12VMON
NTC
BST
DRVH
OD
SW
DRVL
IN
PGND
RS1
RT1
CS1
G1
DACMODE
VID_SEL
VCC
CS1
CS1N
EN
VR_EN
VR_RDY
VR_RDY
CS2
VR_FAN
VR_FAN
CS2N
VS−
VS+
RISO1
RISO2
RT2
CFB1
NCP5386/A/B
RFB1
DIFFOUT
RFB
VFB
RDRP
VDRP
CD1
RD1
CF
RF
DRVON
COMP
ILIM
ROSC SS
CH
RVFB
RLIM1
CSS
RLIM2
RT2 LOCATED NEAR OUTPUT INDUCTORS
VCCP
+
VSSP
CPU/MCH
GND
Figure 3. 1−Phase Application Schematic
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4
NCP5386, NCP5386A, NCP5386B
DACMODE
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
NTC
NCP5386/A/B
VR_FAN
VR10/11/AMD
DAC
NTC
+
-
SS
DAC
VS−
-
VS+
+
Diff Amp
DIFFOUT
Fault
1.3 V
+
VFB
-
COMP
VDRP
GND
Error Amp
Droop
Amplifier
+−
1.3 V
CS1
CS1N
+
-
+
-
ENB
G1
+
-
ENB
G2
Gain = 6
CS2
CS2N
+
Gain = 6
OVER
Oscillator
Fault
ROSC
DIFFOUT
+
ILIM
EN
VCC
-
ILimit
+
VCC UVLO
12VMON
+
12VMON UVLO
Figure 4. Simplified Block Diagram
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5
Fault Logic
3 Phase
Detect
and
Monitor
Circuits
DRVON
VR_RDY
NCP5386, NCP5386A, NCP5386B
PIN DESCRIPTIONS
QFN32
Pin No.
Symbol
32, 1 – 7
VID0–VID7
Voltage ID DAC inputs
8
DACMODE
VRM select bit
9
SS
10
ROSC
11
ILIM
Overcurrent shutdown threshold. To program the shutdown threshold, connect this pin to the ROSC pin via a
resistor divider as shown in the Applications Schematics. To disable the over−current feature, connect this pin
directly to the ROSC pin. To guarantee correct operation, this pin should only be connected to the voltage
generated by the ROSC pin; do not connect this pin to any externally generated voltages.
12
NC
Do not connect anything to this pin.
13
VS+
Non−inverting input to the internal differential remote sense amplifier
14
VS−
Inverting input to the internal differential remote sense amplifier
15
DIFFOUT
16
COMP
17
VFB
Error amplifier inverting input. Connect a resistor from this pin to DIFFOUT. The value of this resistor and the
amount of current from the droop resistor (RDRP) will set the amount of output voltage droop (AVP) during
load.
18
VDRP
Current signal output for Adaptive Voltage Positioning (AVP). The voltage of this pin above the 1.3 V internal
offset voltage is proportional to the output current. Connect a resistor from this pin to VFB to set the amount of
AVP current into the feedback resistor (RFB) to produce an output voltage droop. Leave this pin open for no
AVP.
19, 21
CS1N,
CS2N
Inverting input to current sense amplifier.
20, 22
CS1, CS2
23
DRVON
Output to enable Gate Drivers
24, 25
G1, G2
PWM output pulses to gate drivers
26
12VMON
Description
A capacitor from this pin to ground programs the soft−start time.
A resistance from this pin to ground programs the oscillator frequency. Also, this pin supplies an output
voltage of 2 V which may be used to form a voltage divider to the ILIM pin to set the over−current shutdown
threshold as shown in the Applications Schematics.
Output of the differential remote sense amplifier
Output of the error amplifier, and the non−inverting input of the PWM comparators
Non−inverting input to current sense amplifier.
Second UVLO monitor for monitoring the power stage supply rail
27
VCC
28
VR_RDY
Power for the internal control circuits.
29
NTC
Remote temperature sense connection. Connect an NTC thermistor from this pin to GND and a resistor from
this pin to VREF. As the NTC’s temperature increases, the voltage on this pin will decrease.
30
VR_FAN
Open drain output that will be low impedance when the voltage at the NTC pin is above the specified
threshold. This pin will transition to a high impedance state when the voltage at the NTC pin decreases below
the specified threshold. This pin requires an external pull−up resistor.
31
EN
33
GND
Voltage Regulator Ready (Power Good) output. Open drain output that indicates the output is regulating.
Pull this pin high to enable controller. Pull this pin low to disable controller. Either an open−collector output
(with a pull−up resistor) or a logic gate (CMOS or totem−pole output) may be used to drive this pin. A
Low−to−High transition on this pin will initiate a soft start. Connect this pin directly to VREF if the Enable
function is not required. 20 MHz filtering at this pin is required.
Power supply return (QFN Flag)
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6
NCP5386, NCP5386A, NCP5386B
MAXIMUM RATINGS
Electrical Information
Pin Symbol
VMAX (V)
VMIN (V)
ISOURCE (mA)
ISINK (mA)
COMP
5.5
−0.3
10
10
VDRP
5.5
−0.3
5
5
VS+
2.0
GND − 300 mV
1
1
VS−
2.0
GND − 300 mV
1
1
DIFFOUT
5.5
−0.3
20
20
VR_RDY, VR_FAN
5.5
−0.3
N/A
20
VCC
7.0
−0.3
N/A
20
ROSC
5.5
−0.3
1
N/A
DACMODE, EN
3.5
−0.3
0
0
All Other Pins
5.5
−0.3
−
−
Symbol
Value
Unit
RJA
56
°C/W
Operating Junction Temperature Range (Note 2)
TJ
0 to 125
°C
Operating Ambient Temperature Range
TA
0 to 85
°C
Maximum Storage Temperature Range
TSTG
−55 to +150
°C
Moisture Sensitivity Level, QFN Package
MSL
1
*All signals reference to GND unless otherwise noted.
Thermal Information
Rating
Thermal Characteristic,
QFN Package (Note 1)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 Airflow.
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 Airflow.
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 F)
Parameter
Test Conditions
Min
Typ
Max
Units
−200
−
200
nA
Error Amplifier
Input Bias Current
Input Offset Voltage (Note 3)
−1.0
−
1.0
mV
Open Loop DC Gain (Note 3)
CL = 60 pF to GND,
RL = 10 k to GND
−
100
−
dB
Open Loop Unity Gain Bandwidth
(Note 3)
CL = 60 pF to GND,
RL = 10 k to GND
−
15
−
MHz
Open Loop Phase Margin (Note 3)
CL = 60 pF to GND,
RL = 10 k to GND
−
70
−
°
Slew Rate (Note 3)
VIN = 100 mV, G = −10 V/V,
1.5 V < COMP < 2.5 V,
CL = 60 pF, DC Load = ±125 A
−
5
−
V/s
Maximum Output Voltage
10 mV of Overdrive
ISOURCE = 2.0 mA
2.20
VCC −
20 mV
−
V
Minimum Output Voltage
10 mV of Overdrive
ISINK = 2.0 mA
−
0.01
0.5
V
3. Guaranteed by design. Not tested in production.
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NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 F)
Parameter
Test Conditions
Min
Typ
Max
Units
Error Amplifier
Output Source Current (Note 3)
10 mV Input Overdrive
COMP = 2.0 V
2.0
−
−
mA
Output Sink Current (Note 3)
10 mV Input Overdrive
COMP = 1.0 V
2.0
−
−
mA
Differential Summing Amplifier
VS+ Input Resistance
DRVON = Low
DRVON = High
−
−
1.5
17
−
−
k
VS+ Input Bias Voltage
DRVON = Low
DRVON = High
−
−
0.05
0.65
−
−
V
VS− Bias Current
VS− = 0 V
−
33
−
A
VS+ Input Voltage Range
0.95 DIFFOUT / VS− 1.05
0.5 V DIFFOUT 2.0 V
−0.3
−
2.0
V
VS− Input Voltage Range
0.95 DIFFOUT / VS− 1.05
0.5 V DIFFOUT 2.0 V
−0.3
−
0.3
V
DC Gain VS+ to DIFFOUT
0 V DAC − VS+ 0.3 V
0.99
−
1.01
V/V
DAC Accuracy (measured at VS+)
Closed loop measurement including error
amplifier. (See Figure 20)
1.0 DAC 1.6
0.8 DAC 1.0
0.5 DAC 0.8
−0.5
−5
−8
−
−
−
0.5
5
8
%
mV
mV
−3dB Bandwidth (Note 3)
CL = 80 pF to GND,
RL = 10 k to GND
−
10
−
MHz
Slew Rate (Note 3)
VIN = 100 mV,
DIFFOUT = 1.3 V to 1.2 V
−
5.0
−
V/s
Maximum Output Voltage
VS+ − DAC = 1.0 V
ISOURCE = 2.0 mA
2.0
3.0
−
V
Minimum Output Voltage
VS+ − DAC = −0.8 V
ISINK = 2.0 mA
−
0.01
0.5
V
Output Source Current (Note 3)
VS+ − DAC = 1.0 V
DIFFOUT = 1.0 V
2.0
−
−
mA
Output Sink Current
VS+ − DAC = −0.8 V
DIFFOUT = 1.0 V
2.0
−
−
mA
−
1.30
5.64
5.79
5.95
V/V
−
4
−
MHz
Internal Offset Voltage
VDRP pin offset voltage AND
Error Amp input voltage
V
VDRP Adaptive Voltage−Positioning Amplifier
Current Sense Input to VDRP Gain
−60 mV < (CSx−CSxN) < +60 mV
(Each CS Input Independently)
Current Sense Input to VDRP −3dB
Bandwidth (Note 3)
CL = 30 pF to GND,
RL = 10 k to GND
VDRP Output Slew Rate (Note 3)
VIN = 25 mV
1.3 V < VDRP < 1.9 V,
CL = 330 pF to GND,
RL = 1 k to 10 k connected to 1.3 V
2.5
−
−
V/s
VDRP Output Voltage Offset from
Internal Offset Voltage
CSx= CSxN = 1.3 V
−15
−
+15
mV
Maximum VDRP Output Voltage
CSx − CSxN = 0.1 V (all phases),
ISOURCE = 1.0 mA
2.6
3.0
−
V
3. Guaranteed by design. Not tested in production.
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8
NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 F)
Parameter
Test Conditions
Min
Typ
Max
Units
VDRP Adaptive Voltage−Positioning Amplifier
Minimum VDRP Output Voltage
CSx − CSxN = −0.033 V (all phases),
ISINK = 1.0 mA
−
0.1
0.5
V
Output Source Current (Note 3)
VDRP = 2.0 V
−
1.3
−
mA
Output Sink Current (Note 3)
VDRP = 1.0 V
−
25
−
mA
Current Sense Amplifiers
Input Bias Current
−200
−
200
nA
Common Mode Input Voltage Range
CSx = CSxN = 1.4 V
−0.3
−
2.0
V
Differential Mode Input Voltage Range
(Note 3)
−120
−
120
mV
−1.0
−
1.0
mV
−
6.0
−
V/V
100
−
1000
kHz
196
380
803
−
−
−
226
420
981
kHz
−
−
5
10
−
−
%
1.950
2.010
2.065
V
−
30
40
ns
Propagation Delay (Note 3)
−
20
−
ns
Magnitude of the PWM Ramp
−
1.0
−
V
Input Referred Offset Voltage (Note 3)
CSx = CSxN = 1.0 V
Current Sense Input to PWM Gain
0 V < (CSx − CSxN) < 0.1 V
Oscillator
Switching Frequency Range (Note 3)
Switching Frequency Accuracy
ROSC =
50 k
25 k
10 k
Switching Frequency Tolerance (Note 3)
200 kHz < FSW < 600 kHz
100 kHz < FSW <1 MHz
ROSC Output Voltage
10 A ≤ IROSC ≤ 200 A
Modulators (PWM Comparators)
Minimum Pulse Width (Note 3)
FS = 800 kHz
0% Duty Cycle
COMP voltage when the PWM outputs remain
LOW
−
1.3
−
V
100% Duty Cycle
COMP voltage when the PWM outputs remain
HIGH
−
2.3
−
V
−
90
−
%
−15
−
15
°
PWM Linear Duty Cycle (Note 3)
PWM Phase Angle Error
VR_RDY (Power Good) Output
VR_RDY Saturation Voltage
IVR_RDY = 10 mA
−
−
0.4
V
VR_RDY Rise Time
External pullup of 680 to 1.25 V, CL = 45 pF,
VO = 10% to 90%
−
−
150
ns
VR_RDY High – Output Leakage
Current
VR_RDY = 5.0 V
−
−
1.0
A
VR_RDY Upper Threshold Voltage
VCore increasing, DAC = 1.3 V
−
300
−
mV below
DAC
VR_RDY Lower Threshold Voltage
VCore decreasing, DAC = 1.3 V
−
350
−
mV below
DAC
VR_RDY Rising Delay
VCore increasing
−
−
3
ms
VR_RDY Falling Delay
VCore decreasing
−
−
250
ns
3.0
−
VCC
V
PWM Outputs
Output High Voltage
Sourcing 500 A
3. Guaranteed by design. Not tested in production.
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9
NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 F)
Parameter
Test Conditions
Min
Typ
Max
Units
PWM Outputs
Output Low Voltage
Sinking 500 A
−
−
0.15
V
Rise Time
CL = 20 pF, VO = 0.3 to 2.0 V
−
−
20
ns
Fall Time
CL = 20 pF, VO = Vmax to 0.7 V
−
−
20
ns
Tri−State Output Leakage
Gx = 2.5 V, x = 1 − 4
−
−
1.5
A
Output Impedance − Sourcing
Maximum Resistance to VCC
−
320
−
Output Impedance − Sinking
Maximum Resistance to GND
−
140
−
3.0
−
VCC
V
DRVON
Output High Voltage
Sourcing 500 A
Output Low Voltage
Sinking 500 A
−
−
0.7
mV
Rise Time
CL (PCB) = 20 pF, VO = 10% to 90%
−
24
30
ns
Fall Time
CL = 20 pF, VO = 10% to 90%
−
11
20
ns
−
70
−
k
3.75
5.0
6.25
A
Internal Pulldown Resistance
Soft−Start
Soft−Start Pin Source Current
Soft−Start Ramp Time
CSS = 0.01 F; Time to 1.05 V
−
2.2
−
ms
Soft−Start Pin Discharge Voltage
DRVON pin = LO (Fault)
−
−
25
mV
VR11 Dwell Time at VBOOT
CSS = 0.01 F
50
−
500
s
Input Range for AMD Operating Mode
2.3
−
3.5
V
Input Range for VR11 Operating Mode
0.9
−
1.7
V
Input Range for VR10 Operating Mode
0
−
0.5
V
−
−
1.0
A
DACMODE Input
Enable Input
Enable High Input Leakage Current
EN = 3.3 V
Rising Threshold
VUPPER
0.800
−
0.920
V
Falling Threshold
VLOWER
0.670
−
0.830
V
Hysteresis
VUPPER – VLOWER
−
130
−
mV
Enable Delay Time
Time from Enable transitioning HI to initiation
of Soft−Start
1.0
−
5.0
ms
Disable Delay Time
EN Low to DRVON Low
−
150
200
ns
5.7
5.95
6.2
V/V
−
−
1.0
A
Current Limit
Current Sense Amp to ILIM Gain
20 mV < (CSx − CSxN) < 60 mV
(Each CS Input Independently)
ILIM Pin Input Bias Current
VILIM = 2.0 V
ILIM Pin Working Voltage Range
ILIM Offset Voltage
Offset extrapolated to CSx − CSxN = 0,
referred to ILIM pin
Delay (Note 3)
3. Guaranteed by design. Not tested in production.
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10
0.2
−
2.0
V
−33
17
67
mV
−
300
−
ns
NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 F)
Parameter
Test Conditions
Min
Typ
Max
Units
DAC+
160
−
DAC+
200
mV
−
100
−
ns
4
−
4.5
V
Overvoltage Protection
Overvoltage Threshold
Delay (Note 3)
Undervoltage Protection
VCC UVLO Start Threshold
VCC UVLO Stop Threshold
3.8
−
4.3
V
VCC UVLO Hysteresis
100
215
−
mV
VID Inputs
Upper Threshold
VUPPER
−
−
800
mV
Lower Threshold
VLOWER
300
−
−
mV
−
−
500
nA
500
−
800
ns
Input Bias Current
Delay before Latching VID Change
(VID De−Skewing) (Note 3)
Measured from the edge of the first VID
change
Internal DAC Slew Rate Limiter
Positive Slew Rate Limit
VID Step of +500 mV
−
6.3
−
mV/s
Negative Slew Rate Limit
VID Step of −500 mV
−
−6.3
−
mV/s
EN = LOW, No PWM
−
−
20
mA
VR_FAN Upper Voltage Threshold
Fraction of VREF voltage above which
VR_FAN output pulls low
−
0.4 x
VREF
−
−
VR_FAN Lower Voltage Threshold
Fraction of VREF voltage below which
VR_FAN output is open
−
0.33 x
VREF
−
−
VR_FAN Output Saturation Voltage
ISINK = 4 mA
−
−
0.3
V
VR_FAN Output Leakage Current
High Impedance State
−
−
1
A
−
−
1
A
Input Supply Current
VCC Operating Current
Temperature Sensing
NTC Pin Bias Current
12VMON
12VMON (Rising Threshold)
Sufficient power stage supply voltage
0.728
−
0.821
V
12VMON (Falling Threshold)
Insufficient power stage supply voltage
0.643
−
0.725
V
3. Guaranteed by design. Not tested in production.
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11
NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 F)
Parameter
Test Conditions
Min
Typ
Max
Units
VRM11 DAC
System Voltage Accuracy
1.0 V < DAC < 1.6 V
0.8 V < DAC < 1.0 V
0.5 V < DAC < 0.8 V
−
−
±0.5
±5
±8
%
mV
mV
No Load Offset Voltage from Nominal
DAC Specification (NCP5386)
With CS Input
VIN = 0 V
−
−19
−
mV
No Load Offset Voltage from Nominal
DAC Specification (NCP5386A)
With CS Input
VIN = 0 V
−
+20
−
mV
No Load Offset Voltage from Nominal
DAC Specification (NCP5386B)
With CS Input
VIN = 0 V
−
50
−
mV
Table 1: VRM11 VID Codes
VID7
800 mV
VID6
400 mV
VID5
200 mV
VID4
100 mV
VID3
50 mV
VID2
25 mV
VID1
12.5 mV
VID0
6.25 mV
Voltage
(V)
HEX
0
0
0
0
0
0
0
0
OFF
00
0
0
0
0
0
0
0
1
OFF
01
0
0
0
0
0
0
1
0
1.60000
02
0
0
0
0
0
0
1
1
1.59375
03
0
0
0
0
0
1
0
0
1.58750
04
0
0
0
0
0
1
0
1
1.58125
05
0
0
0
0
0
1
1
0
1.57500
06
0
0
0
0
0
1
1
1
1.56875
07
0
0
0
0
1
0
0
0
1.56250
08
0
0
0
0
1
0
0
1
1.55625
09
0
0
0
0
1
0
1
0
1.55000
0A
0
0
0
0
1
0
1
1
1.54375
0B
0
0
0
0
1
1
0
0
1.53750
0C
0
0
0
0
1
1
0
1
1.53125
0D
0
0
0
0
1
1
1
0
1.52500
0E
0
0
0
0
1
1
1
1
1.51875
0F
0
0
0
1
0
0
0
0
1.51250
10
0
0
0
1
0
0
0
1
1.50625
11
0
0
0
1
0
0
1
0
1.50000
12
0
0
0
1
0
0
1
1
1.49375
13
0
0
0
1
0
1
0
0
1.48750
14
0
0
0
1
0
1
0
1
1.48125
15
0
0
0
1
0
1
1
0
1.47500
16
0
0
0
1
0
1
1
1
1.46875
17
0
0
0
1
1
0
0
0
1.46250
18
0
0
0
1
1
0
0
1
1.45625
19
0
0
0
1
1
0
1
0
1.45000
1A
0
0
0
1
1
0
1
1
1.44375
1B
0
0
0
1
1
1
0
0
1.43750
1C
0
0
0
1
1
1
0
1
1.43125
1D
0
0
0
1
1
1
1
0
1.42500
1E
0
0
0
1
1
1
1
1
1.41875
1F
0
0
1
0
0
0
0
0
1.41250
20
0
0
1
0
0
0
0
1
1.40625
21
0
0
1
0
0
0
1
0
1.40000
22
0
0
1
0
0
0
1
1
1.39375
23
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12
NCP5386, NCP5386A, NCP5386B
Table 1: VRM11 VID Codes
VID7
800 mV
VID6
400 mV
VID5
200 mV
VID4
100 mV
VID3
50 mV
VID2
25 mV
VID1
12.5 mV
VID0
6.25 mV
Voltage
(V)
HEX
0
0
1
0
0
1
0
0
1.38750
24
0
0
1
0
0
1
0
1
1.38125
25
0
0
1
0
0
1
1
0
1.37500
26
0
0
1
0
0
1
1
1
1.36875
27
0
0
1
0
1
0
0
0
1.36250
28
0
0
1
0
1
0
0
1
1.35625
29
0
0
1
0
1
0
1
0
1.35000
2A
0
0
1
0
1
0
1
1
1.34375
2B
0
0
1
0
1
1
0
0
1.33750
2C
0
0
1
0
1
1
0
1
1.33125
2D
0
0
1
0
1
1
1
0
1.32500
2E
0
0
1
0
1
1
1
1
1.31875
2F
0
0
1
1
0
0
0
0
1.31250
30
0
0
1
1
0
0
0
1
1.30625
31
0
0
1
1
0
0
1
0
1.30000
32
0
0
1
1
0
0
1
1
1.29375
33
0
0
1
1
0
1
0
0
1.28750
34
0
0
1
1
0
1
0
1
1.28125
35
0
0
1
1
0
1
1
0
1.27500
36
0
0
1
1
0
1
1
1
1.26875
37
0
0
1
1
1
0
0
0
1.26250
38
0
0
1
1
1
0
0
1
1.25625
39
0
0
1
1
1
0
1
0
1.25000
3A
0
0
1
1
1
0
1
1
1.24375
3B
0
0
1
1
1
1
0
0
1.23750
3C
0
0
1
1
1
1
0
1
1.23125
3D
0
0
1
1
1
1
1
0
1.22500
3E
0
0
1
1
1
1
1
1
1.21875
3F
0
1
0
0
0
0
0
0
1.21250
40
0
1
0
0
0
0
0
1
1.20625
41
0
1
0
0
0
0
1
0
1.20000
42
0
1
0
0
0
0
1
1
1.19375
43
0
1
0
0
0
1
0
0
1.18750
44
0
1
0
0
0
1
0
1
1.18125
45
0
1
0
0
0
1
1
0
1.17500
46
0
1
0
0
0
1
1
1
1.16875
47
0
1
0
0
1
0
0
0
1.16250
48
0
1
0
0
1
0
0
1
1.15625
49
0
1
0
0
1
0
1
0
1.15000
4A
0
1
0
0
1
0
1
1
1.14375
4B
0
1
0
0
1
1
0
0
1.13750
4C
0
1
0
0
1
1
0
1
1.13125
4D
0
1
0
0
1
1
1
0
1.12500
4E
0
1
0
0
1
1
1
1
1.11875
4F
0
1
0
1
0
0
0
0
1.11250
50
0
1
0
1
0
0
0
1
1.10625
51
0
1
0
1
0
0
1
0
1.10000
52
0
1
0
1
0
0
1
1
1.09375
53
0
1
0
1
0
1
0
0
1.08750
54
0
1
0
1
0
1
0
1
1.08125
55
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13
NCP5386, NCP5386A, NCP5386B
Table 1: VRM11 VID Codes
VID7
800 mV
VID6
400 mV
VID5
200 mV
VID4
100 mV
VID3
50 mV
VID2
25 mV
VID1
12.5 mV
VID0
6.25 mV
Voltage
(V)
HEX
0
1
0
1
0
1
1
0
1.07500
56
0
1
0
1
0
1
1
1
1.06875
57
0
1
0
1
1
0
0
0
1.06250
58
0
1
0
1
1
0
0
1
1.05625
59
0
1
0
1
1
0
1
0
1.05000
5A
0
1
0
1
1
0
1
1
1.04375
5B
0
1
0
1
1
1
0
0
1.03750
5C
0
1
0
1
1
1
0
1
1.03125
5D
0
1
0
1
1
1
1
0
1.02500
5E
0
1
0
1
1
1
1
1
1.01875
5F
0
1
1
0
0
0
0
0
1.01250
60
0
1
1
0
0
0
0
1
1.00625
61
0
1
1
0
0
0
1
0
1.00000
62
0
1
1
0
0
0
1
1
0.99375
63
0
1
1
0
0
1
0
0
0.98750
64
0
1
1
0
0
1
0
1
0.98125
65
0
1
1
0
0
1
1
0
0.97500
66
0
1
1
0
0
1
1
1
0.96875
67
0
1
1
0
1
0
0
0
0.96250
68
0
1
1
0
1
0
0
1
0.95625
69
0
1
1
0
1
0
1
0
0.95000
6A
0
1
1
0
1
0
1
1
0.94375
6B
0
1
1
0
1
1
0
0
0.93750
6C
0
1
1
0
1
1
0
1
0.93125
6D
0
1
1
0
1
1
1
0
0.92500
6E
0
1
1
0
1
1
1
1
0.91875
6F
0
1
1
1
0
0
0
0
0.91250
70
0
1
1
1
0
0
0
1
0.90625
71
0
1
1
1
0
0
1
0
0.90000
72
0
1
1
1
0
0
1
1
0.89375
73
0
1
1
1
0
1
0
0
0.88750
74
0
1
1
1
0
1
0
1
0.88125
75
0
1
1
1
0
1
1
0
0.87500
76
0
1
1
1
0
1
1
1
0.86875
77
0
1
1
1
1
0
0
0
0.86250
78
0
1
1
1
1
0
0
1
0.85625
79
0
1
1
1
1
0
1
0
0.85000
7A
0
1
1
1
1
0
1
1
0.84375
7B
0
1
1
1
1
1
0
0
0.83750
7C
0
1
1
1
1
1
0
1
0.83125
7D
0
1
1
1
1
1
1
0
0.82500
7E
0
1
1
1
1
1
1
1
0.81875
7F
1
0
0
0
0
0
0
0
0.81250
80
1
0
0
0
0
0
0
1
0.80625
81
1
0
0
0
0
0
1
0
0.80000
82
1
0
0
0
0
0
1
1
0.79375
83
1
0
0
0
0
1
0
0
0.78750
84
1
0
0
0
0
1
0
1
0.78125
85
1
0
0
0
0
1
1
0
0.77500
86
1
0
0
0
0
1
1
1
0.76875
87
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14
NCP5386, NCP5386A, NCP5386B
Table 1: VRM11 VID Codes
VID7
800 mV
VID6
400 mV
VID5
200 mV
VID4
100 mV
VID3
50 mV
VID2
25 mV
VID1
12.5 mV
VID0
6.25 mV
Voltage
(V)
HEX
1
0
0
0
1
0
0
0
0.76250
88
1
0
0
0
1
0
0
1
0.75625
89
1
0
0
0
1
0
1
0
0.75000
8A
1
0
0
0
1
0
1
1
0.74375
8B
1
0
0
0
1
1
0
0
0.73750
8C
1
0
0
0
1
1
0
1
0.73125
8D
1
0
0
0
1
1
1
0
0.72500
8E
1
0
0
0
1
1
1
1
0.71875
8F
1
0
0
1
0
0
0
0
0.71250
90
1
0
0
1
0
0
0
1
0.70625
91
1
0
0
1
0
0
1
0
0.70000
92
1
0
0
1
0
0
1
1
0.69375
93
1
0
0
1
0
1
0
0
0.68750
94
1
0
0
1
0
1
0
1
0.68125
95
1
0
0
1
0
1
1
0
0.67500
96
1
0
0
1
0
1
1
1
0.66875
97
1
0
0
1
1
0
0
0
0.66250
98
1
0
0
1
1
0
0
1
0.65625
99
1
0
0
1
1
0
1
0
0.65000
9A
1
0
0
1
1
0
1
1
0.64375
9B
1
0
0
1
1
1
0
0
0.63750
9C
1
0
0
1
1
1
0
1
0.63125
9D
1
0
0
1
1
1
1
0
0.62500
9E
1
0
0
1
1
1
1
1
0.61875
9F
1
0
1
0
0
0
0
0
0.61250
A0
1
0
1
0
0
0
0
1
0.60625
A1
1
0
1
0
0
0
1
0
0.60000
A2
1
0
1
0
0
0
1
1
0.59375
A3
1
0
1
0
0
1
0
0
0.58750
A4
1
0
1
0
0
1
0
1
0.58125
A5
1
0
1
0
0
1
1
0
0.57500
A6
1
0
1
0
0
1
1
1
0.56875
A7
1
0
1
0
1
0
0
0
0.56250
A8
1
0
1
0
1
0
0
1
0.55625
A9
1
0
1
0
1
0
1
0
0.55000
AA
1
0
1
0
1
0
1
1
0.54375
AB
1
0
1
0
1
1
0
0
0.53750
AC
1
0
1
0
1
1
0
1
0.53125
AD
1
0
1
0
1
1
1
0
0.52500
AE
1
0
1
0
1
1
1
1
0.51875
AF
1
0
1
1
0
0
0
0
0.51250
B0
1
0
1
1
0
0
0
1
0.50625
B1
1
0
1
1
0
0
1
0
0.50000
B2
1
1
1
1
1
1
1
0
OFF
FE
1
1
1
1
1
1
1
1
OFF
FF
OFF
B3 to FD
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15
NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 F)
Parameter
Test Conditions
Min
Typ
Max
Units
VRM10 DAC
System Voltage Accuracy
1.0 V < DAC < 1.6 V
0.83125 V < DAC < 1.0 V
−
−
±0.5
±5
%
mV
No Load Offset Voltage from Nominal
DAC Specification
With CS Input
VIN = 0 V
−
−19
−
mV
No Load Offset Voltage from Nominal
DAC Specification (NCP5386A)
With CS Input
VIN = 0 V
−
+20
−
mV
No Load Offset Voltage from Nominal
DAC Specification (NCP5386B)
With CS Input
VIN = 0 V
−
50
−
mV
Table 2: VRM10 VID Codes
VID4
400 mV
VID3
200 mV
VID2
100 mV
VID1
50 mV
VID0
25 mV
VID5
12.5 mV
VID6
6.25 mV
Nominal DAC
Voltage (V)
0
1
0
1
0
1
1
1.60000
0
1
0
1
0
1
0
1.59375
0
1
0
1
1
0
1
1.58750
0
1
0
1
1
0
0
1.58125
0
1
0
1
1
1
1
1.57500
0
1
0
1
1
1
0
1.56875
0
1
1
0
0
0
1
1.56250
0
1
1
0
0
0
0
1.55625
0
1
1
0
0
1
1
1.55000
0
1
1
0
0
1
0
1.54375
0
1
1
0
1
0
1
1.53750
0
1
1
0
1
0
0
1.53125
0
1
1
0
1
1
1
1.52500
0
1
1
0
1
1
0
1.51875
0
1
1
1
0
0
1
1.51250
0
1
1
1
0
0
0
1.50625
0
1
1
1
0
1
1
1.50000
0
1
1
1
0
1
0
1.49375
0
1
1
1
1
0
1
1.48750
0
1
1
1
1
0
0
1.48125
0
1
1
1
1
1
1
1.47500
0
1
1
1
1
1
0
1.46875
1
0
0
0
0
0
1
1.46250
1
0
0
0
0
0
0
1.45625
1
0
0
0
0
1
1
1.45000
1
0
0
0
0
1
0
1.44375
1
0
0
0
1
0
1
1.43750
1
0
0
0
1
0
0
1.43125
1
0
0
0
1
1
1
1.42500
1
0
0
0
1
1
0
1.41875
1
0
0
1
0
0
1
1.41250
1
0
0
1
0
0
0
1.40625
1
0
0
1
0
1
1
1.40000
1
0
0
1
0
1
0
1.39375
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16
NCP5386, NCP5386A, NCP5386B
Table 2: VRM10 VID Codes
VID4
400 mV
VID3
200 mV
VID2
100 mV
VID1
50 mV
VID0
25 mV
VID5
12.5 mV
VID6
6.25 mV
Nominal DAC
Voltage (V)
1
0
0
1
1
0
1
1.38750
1
0
0
1
1
0
0
1.38125
1
0
0
1
1
1
1
1.37500
1
0
0
1
1
1
0
1.36875
1
0
1
0
0
0
1
1.36250
1
0
1
0
0
0
0
1.35625
1
0
1
0
0
1
1
1.35000
1
0
1
0
0
1
0
1.34375
1
0
1
0
1
0
1
1.33750
1
0
1
0
1
0
0
1.33125
1
0
1
0
1
1
1
1.32500
1
0
1
0
1
1
0
1.31875
1
0
1
1
0
0
1
1.31250
1
0
1
1
0
0
0
1.30625
1
0
1
1
0
1
1
1.30000
1
0
1
1
0
1
0
1.29375
1
0
1
1
1
0
1
1.28750
1
0
1
1
1
0
0
1.28125
1
0
1
1
1
1
1
1.27500
1
0
1
1
1
1
0
1.26875
1
1
0
0
0
0
1
1.26250
1
1
0
0
0
0
0
1.25625
1
1
0
0
0
1
1
1.25000
1
1
0
0
0
1
0
1.24375
1
1
0
0
1
0
1
1.23750
1
1
0
0
1
0
0
1.23125
1
1
0
0
1
1
1
1.22500
1
1
0
0
1
1
0
1.21875
1
1
0
1
0
0
1
1.21250
1
1
0
1
0
0
0
1.20625
1
1
0
1
0
1
1
1.20000
1
1
0
1
0
1
0
1.19375
1
1
0
1
1
0
1
1.18750
1
1
0
1
1
0
0
1.18125
1
1
0
1
1
1
1
1.17500
1
1
0
1
1
1
0
1.16875
1
1
1
0
0
0
1
1.16250
1
1
1
0
0
0
0
1.15625
1
1
1
0
0
1
1
1.15000
1
1
1
0
0
1
0
1.14375
1
1
1
0
1
0
1
1.13750
1
1
1
0
1
0
0
1.13125
1
1
1
0
1
1
1
1.12500
1
1
1
0
1
1
0
1.11875
1
1
1
1
0
0
1
1.11250
1
1
1
1
0
0
0
1.10625
1
1
1
1
0
1
1
1.10000
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17
NCP5386, NCP5386A, NCP5386B
Table 2: VRM10 VID Codes
VID4
400 mV
VID3
200 mV
VID2
100 mV
VID1
50 mV
VID0
25 mV
VID5
12.5 mV
VID6
6.25 mV
Nominal DAC
Voltage (V)
1
1
1
1
0
1
0
1.09375
1
1
1
1
1
0
1
OFF
1
1
1
1
1
0
0
OFF
1
1
1
1
1
1
1
OFF
1
1
1
1
1
1
0
OFF
0
0
0
0
0
0
1
1.08750
0
0
0
0
0
0
0
1.08125
0
0
0
0
0
1
1
1.07500
0
0
0
0
0
1
0
1.06875
0
0
0
0
1
0
1
1.06250
0
0
0
0
1
0
0
1.05625
0
0
0
0
1
1
1
1.05000
0
0
0
0
1
1
0
1.04375
0
0
0
1
0
0
1
1.03750
0
0
0
1
0
0
0
1.03125
0
0
0
1
0
1
1
1.02500
0
0
0
1
0
1
0
1.01875
0
0
0
1
1
0
1
1.01250
0
0
0
1
1
0
0
1.00625
0
0
0
1
1
1
1
1.00000
0
0
0
1
1
1
0
0.99375
0
0
1
0
0
0
1
0.98750
0
0
1
0
0
0
0
0.98125
0
0
1
0
0
1
1
0.97500
0
0
1
0
0
1
0
0.96875
0
0
1
0
1
0
1
0.96250
0
0
1
0
1
0
0
0.95625
0
0
1
0
1
1
1
0.95000
0
0
1
0
1
1
0
0.94375
0
0
1
1
0
0
1
0.93750
0
0
1
1
0
0
0
0.93125
0
0
1
1
0
1
1
0.92500
0
0
1
1
0
1
0
0.91875
0
0
1
1
1
0
1
0.91250
0
0
1
1
1
0
0
0.90625
0
0
1
1
1
1
1
0.90000
0
0
1
1
1
1
0
0.89375
0
1
0
0
0
0
1
0.88750
0
1
0
0
0
0
0
0.88125
0
1
0
0
0
1
1
0.87500
0
1
0
0
0
1
0
0.86875
0
1
0
0
1
0
1
0.86250
0
1
0
0
1
0
0
0.85625
0
1
0
0
1
1
1
0.85000
0
1
0
0
1
1
0
0.84375
0
1
0
1
0
0
1
0.83750
0
1
0
1
0
0
0
0.83125
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18
NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 F)
Parameter
Test Conditions
Min
Typ
Max
Units
AMD DAC
System Voltage Accuracy
0.8 V < DAC < 1.55 V
−
−
±0.5
%
No Load Offset Voltage from Nominal
DAC Specification
With CS Input
VIN = 0 V
−
20
−
mV
Table 3: AMD VID Codes
VID4
VID3
VID2
VID1
VID0
Nominal VOUT (V)
Tolerance
0
0
0
0
0
1.550
±0.5 %
0
0
0
0
1
1.525
±0.5 %
0
0
0
1
0
1.500
±0.5 %
0
0
0
1
1
1.475
±0.5 %
0
0
1
0
0
1.450
±0.5 %
0
0
1
0
1
1.425
±0.5 %
0
0
1
1
0
1.400
±0.5 %
0
0
1
1
1
1.375
±0.5 %
0
1
0
0
0
1.350
±0.5 %
0
1
0
0
1
1.325
±0.5 %
0
1
0
1
0
1.300
±0.5 %
0
1
0
1
1
1.275
±0.5 %
0
1
1
0
0
1.250
±0.5 %
0
1
1
0
1
1.225
±0.5 %
0
1
1
1
0
1.200
±0.5 %
0
1
1
1
1
1.175
±0.5 %
1
0
0
0
0
1.150
±0.5 %
1
0
0
0
1
1.125
±0.5 %
1
0
0
1
0
1.100
±0.5 %
1
0
0
1
1
1.075
±0.5 %
1
0
1
0
0
1.050
±0.5 %
1
0
1
0
1
1.025
±0.5 %
1
0
1
1
0
1.000
±0.5 %
1
0
1
1
1
0.975
±5.0 mV
1
1
0
0
0
0.950
±5.0 mV
1
1
0
0
1
0.925
±5.0 mV
1
1
0
1
0
0.900
±5.0 mV
1
1
0
1
1
0.875
±5.0 mV
1
1
1
0
0
0.850
±5.0 mV
1
1
1
0
1
0.825
±5.0 mV
1
1
1
1
0
0.800
±5.0 mV
1
1
1
1
1
Shutdown
−
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19
NCP5386, NCP5386A, NCP5386B
1.60
2.017
1.58
2.016
ROSC VOLTAGE (V)
VR_RDY DELAY TIME (ms)
TYPICAL CHARACTERISTICS
1.56
1.54
1.52
2.015
2.014
2.013
1.50
0
10
20
30
40
50
60
70
80
2.012
90
20
30
40
50
60
70
TA, AMBIENT TEMPERATURE (°C)
Figure 5. PWM Output Resistance vs. Ambient
Temperature
Figure 6. ROSC Voltage vs. Ambient
Temperature
80
90
80
90
11.0
SUPPLY CURRENT (mA)
SOFT−START CURRENT (A)
10
TA, AMBIENT TEMPERATURE (°C)
4.90
4.85
4.80
4.75
4.70
10.5
10.0
9.5
9.0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 7. Soft−start Current vs. Ambient
Temperature
Figure 8. Supply Current vs. Ambient
Temperature
1.003
VCC, UVLO THRESHOLD (V)
RSA GAIN (V/V)
4.30
1.002
DAC = 1.6 V
DAC = 1.1 V
1.001
DAC = 0.5 V
1.000
0
0
10
20
30
40
50
60
70
80
Start
4.25
4.20
4.15
4.10
4.05
90
Stop
0
TA, AMBIENT TEMPERATURE (°C)
10
20
30
40
50
60
70
80
TA, AMBIENT TEMPERATURE (°C)
Figure 9. RSA Gain vs. Ambient Temperature
Figure 10. UVLO Threshold vs. Ambient
Temperature
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20
90
NCP5386, NCP5386A, NCP5386B
TYPICAL CHARACTERISTICS
0.90
0.80
0.76
0.74
0.72
0.70
0.68
Stop
0
10
20
30
40
0.86
0.84
0.82
0.80
0.78
0.76
50
60
70
80
0.72
90
0
10
20
30
40
50
60
70
80
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 11. 12VMON Threshold vs. Ambient
Temperature
Figure 12. Enable Threshold vs. Ambient
Temperature
90
VDRP SOURCE CURRENT (mA)
1.50
85°C
BIAS ERROR (mV)
Stop
0.74
2.0
1.0
70°C
50°C
0
25°C
−1.0
0°C
1.45
1.40
1.35
1.30
1.25
−2.0
2
22
42
62
82
102
122
142
0
162
10
20
30
40
50
60
70
80
DAC CODE
TA, AMBIENT TEMPERATURE (°C)
Figure 13. RSA Bias
Figure 14. VDRP Source Current vs. Ambient
Temperature
90
5.795
6.35
6.30
5.790
FALLING
6.25
VDRP GAIN (V/V)
DAC SLEW RATE (mV/s)
Start
0.88
ENABLE THRESHOLD (V)
12VMON THRESHOLD (V)
Start
0.78
6.20
6.15
RISING
6.10
5.785
5.780
6.05
5.770
6.00
5.765
0
10
20
30
40
50
60
70
80
90
CS2
5.775
CS1
0
10
20
30
40
50
60
70
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 15. DAC Slew Rate vs. Ambient
Temperature
Figure 16. VDRP Gain vs. Ambient
Temperature
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21
80
90
NCP5386, NCP5386A, NCP5386B
TYPICAL CHARACTERISTICS
360
3.0
Lower
THRESHOLD (mV)
2.0
1.0
0
340
330
320
310
−1.0
0
10
20
30
40
50
60
70
80
90
300
Upper
0
10
20
30
40
50
60
70
80
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 17. VDRP Offset vs. Ambient
Temperature
Figure 18. VR_RDY Thresholds vs. Ambient
Temperature
3.0
2.0
DEVIATION (%)
VDRP OFFSET (mV)
350
SINKING
1.0
SOURCING
0
−1.0
0
10
20
30
40
50
60
70
80
TA, AMBIENT TEMPERATURE (°C)
Figure 19. PWM Output Resistance vs.
Ambient Temperature
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22
90
90
NCP5386, NCP5386A, NCP5386B
FUNCTIONAL DESCRIPTION
Schematic. In 1−Phase mode, gate output G2 must be left
open as shown in the 1−phase Applications Schematic. The
CS2 and CS2N inputs should be connected to CS1N. The
following truth table summarizes the modes of operation:
General
The NCP5386/A/B dual edge modulated multiphase
PWM controller is specifically designed with the necessary
features for a high current VR10, VR11 or AMD CPU and
chipset power system. The IC consists of the following
blocks: Precision Programmable DAC, Differential
Remote Voltage Sense Amplifier, High Performance
Voltage Error Amplifier, Differential Current Feedback
Amplifiers, Precision Oscillator and Triangle Wave
Generators, and PWM Comparators. Protection features
include Undervoltage Lockout, Soft−Start, Overcurrent
Protection, Overvoltage Protection, and Power Good
Monitor.
Gate Output Connections
Mode
G1
G2
1−Phase
Normal
OPEN
2−Phase
Normal
Normal
These are the only allowable connection schemes to
program the modes of operation.
Differential Current Sense Amplifiers
Two differential amplifiers are provided to sense the
output current of each phase. The inputs of each current
sense amplifier must be connected across the current
sensing element of the phase controlled by the
corresponding gate output (G1 or G2). If a phase is
unused, the differential inputs to that phase’s current
sense amplifier must be shorted together and connected
to CS1N as shown in the 1−Phase Application
Schematics.
A voltage is generated across the current sense element
(such as an inductor or sense resistor) by the current
flowing in that phase. The output of the current sense
amplifiers are used to control three functions. First, the
output controls the adaptive voltage positioning, where the
output voltage is actively controlled according to the
output current. In this function, all of the current sense
outputs are summed so that the total output current is used
for output voltage positioning. Second, the output signal is
fed to the current limit circuit. This again is the summed
current of all phases in operation. Finally, the individual
phase current is connected to the PWM comparator. In this
way current balance is accomplished.
Remote Output Sensing Amplifier (RSA)
A true differential amplifier allows the NCP5386/A/B to
measure VCore voltage feedback with respect to the Vcore
ground reference point by connecting the Vcore reference
point to VS+, and the Vcore ground reference point to VS−.
This configuration keeps ground potential differences
between the local controller ground and the Vcore ground
reference point from affecting regulation of Vcore between
VCore and VCore ground reference points. The RSA also
subtracts the DAC (minus VID offset) voltage, thereby
producing an unamplified output error voltage at the
DIFFOUT pin. This output also has a 1.3 V bias voltage to
allow both positive and negative error voltages.
Precision Programmable DAC
A precision programmable DAC is provided. This DAC
has 0.5% accuracy over the entire operating temperature
range of the part. The DAC can be programmed to support
either Intel VR10 or VR11 or AMD K8 specifications. A
program selection pin is provided to accomplish this. This pin
also sets the startup mode of operation. Connect this pin to
1.25 V to select the VR11 DAC table and startup mode.
Connect this pin to ground to select the VR10 DAC table and
the VR11 startup mode. Connect this pin to VREF to select the
AMD DAC table and startup mode.
Oscillator and Triangle Wave Generator
A programmable precision oscillator is provided. The
oscillator ’s frequency is programmed by the resistance
connected from the ROSC pin to ground. The user will
usually form this resistance from two resistors in order to
create a voltage divider that uses the ROSC output voltage
as the reference for creating the current limit setpoint
voltage. The oscillator frequency range is 100 kHz/phase
to 1.0 MHz/phase. The oscillator generates up to 4 triangle
waveforms (symmetrical rising and falling slopes)
between 1.3 V and 2.3 V. The triangle waves have a phase
delay between them such that for 2−phase operation the
PWM outputs are separated by 180 angular degrees,
respectively.
High Performance Voltage Error Amplifier
The error amplifier is designed to provide high slew rate
and bandwidth. Although not required when operating as
the controller of a voltage regulator, a capacitor from
COMP to VFB is required for stable unity gain test
configurations.
Gate Driver Outputs and 1/2 Phase Operation
The part can be configured to run in 1− or 2−Phase mode.
In 2−phase mode, phases 1 and 2 should be used to drive the
external gate drivers as shown in the 2−phase Applications
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23
NCP5386, NCP5386A, NCP5386B
PWM Comparators with Hysteresis
amplifiers. The overcurrent latch is set when the current
information exceeds the voltage at the ILIM pin. The
outputs are immediately disabled, the VR_RDY and
DRVON pins are pulled low, and the soft−start is pulled
low. The outputs will remain disabled until the VCC voltage
is removed and re−applied, or the ENABLE input is
brought low and then high.
Four PWM comparators receive the error amplifier
output signal at their noninverting input. Each comparator
receives one of the triangle waves offset by 1.3 V at it’s
inverting input. The output of the comparator generates the
PWM outputs G1 and G2.
During steady state operation, the duty cycle will center
on the valley of the triangle waveform, with steady state
duty cycle calculated by VOUT/VIN. During a transient
event, both high and low comparator output transitions
shift phase to the points where the error amplifier output
intersects the down and up ramp of the triangle wave.
Overvoltage Protection and Power Good Monitor
An output voltage monitor is incorporated. During
normal operation, if the voltage at the DIFFOUT pin
exceeds 1.3 V, the VR_RDY pin goes low, the DRVON
signal remains high, the PWM outputs are set low. The
outputs will remain disabled until the VCC voltage is
removed and reapplied. During normal operation, if the
output voltage falls more than 300 mV below the DAC
setting, the VR_RDY pin will be set low until the output
rises.
PROTECTION FEATURES
Undervoltage Lockout
An undervoltage lockout (UVLO) senses the VCC input.
During powerup, the input voltage to the controller is
monitored, and the PWM outputs and the soft−start circuit
are disabled until the input voltage exceeds the threshold
voltage of the UVLO comparator. The UVLO comparator
incorporates hysteresis to avoid chattering, since VCC is
likely to decrease as soon as the converter initiates
soft−start.
Soft−Start
The NCP5386 incorporates an externally programmable
soft−start. The soft−start circuit works by controlling the
ramp−up of the DAC voltage during powerup. The initial
soft−start pin voltage is 0 V. The soft−start circuitry clamps
the DAC input of the Remote Sense Amplifier to the SS pin
voltage until the SS pin voltage exceeds the DAC setting
minus VID offset thereafter. The soft−start pin is pulled to
0 V.
There are two possible soft−start modes: AMD and
VR11. AMD mode simply ramps Vcore from 0 V
directly to the DAC setting at the rate set by the capacitor
connected to the SS pin. The VR11 mode ramps Vcore to
1.1 V at the SS capacitor charge rate, pauses at 1.1 V for
170 s, reads the VID pins to determine the DAC setting,
then ramps Vcore to the final DAC setting at the
Dynamic VID slew rate of 7.3 mV/s. Typical AMD and
VR11 soft−start sequences are shown in the following
graphs.
Overcurrent Shutdown
A programmable overcurrent function is incorporated
within the IC. A comparator and latch makeup this
function. The inverting input of the comparator is
connected to the ILIM pin. The voltage at this pin sets the
maximum output current the converter can produce. The
ROSC pin provides a convenient and accurate reference
voltage from which a resistor divider can create the
overcurrent setpoint voltage. Although not actually
disabled, tying the ILIM pin directly to the ROSC pin sets
the limit above useful levels – effectively disabling
overcurrent shutdown. The comparator noninverting input
is the summed current information from the current sense
−
1.3 V
REMOTE
SENSE
+ AMP
VS−
VS+
+
−
DIFFOUT
R1
ERROR
AMP
VFB
10 k
Figure 20. DAC Servo Evaluation Circuit
http://onsemi.com
24
C1
1 nF
COMP
NCP5386, NCP5386A, NCP5386B
2.4
2.2
2.0
VOLTAGE
1.8
VID Setting
1.6
1.4
1.2
1.0
0.8
0.6
Vcore Voltage
SS Pin Voltage
0.4
0.2
0
TIME
0
Figure 21. Typical AMD Soft−Start Sequence to Vcore = 1.3 V
2.4
2.2
2.0
VID Setting
VOLTAGE
1.8
Boot Voltage
1.6
1.4
1.2
1.0
Boot
Dwell Time
0.8
0.6
Vcore Voltage
SS Pin Voltage
0.4
0.2
0
NCP5386
Internal Dynamic
VID Rate Limit
TIME
0
Figure 22. Typical VR10 & VR11 Soft−Start Sequence to Vcore = 1.3 V
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25
NCP5386, NCP5386A, NCP5386B
APPLICATION INFORMATION
16. Start the second ATX supply by turning it on and
setting the PSON DIP switch low. The green VID
lights should light up to match the VTT tool VID
setting.
17. Set the VR_ENABLE DIP switch up to start the
NCP5386.
18. Check that the output voltage is about 19 mV
below the VID setting.
The NCP5386 is a high performance multiphase
controller optimized to meet the Intel VR11 Specifications.
The demo board for the NCP5386 is available by request.
It is configured as a four phase solution with decoupling
designed to provide a 1.0 m load line under a 100 A step
load. A schematic is available upon request from ON
Semiconductor.
Startup Procedure
The demo board comes with a Socket 775 and requires
an Intel dynamic load tool (VTT Tool) available through a
third party supplier, Cascade Systems. The web page is
http://www.cascadesystems.net/.
Start by installing the test tool software. It’s best to power
the test tool from a separate ATX power supply. The test
tool should be set to a valid VID code of 0.5 V or above
in−order for the controller to start. Consult the VTT help
manual for more detailed instructions.
Step Load Testing
The VTT tool is used to generate the high di/dt step load.
Select the dynamic loading option in the VTT test tool
software. Set the desired step load size, frequency, duty,
and slew rate. See Figures 23 and 24.
Startup Sequence
1. Make sure the VTT software is installed.
2. Powerup the PC or Laptop do not start the VTT
software.
3. Insert the VTT Test Tool adapter into the socket
and lock it down.
4. Insert the socket saver pin field into the bottom of
the VTT test tool.
5. Carefully line up the tool with the socket in the
board and press tool into the board.
6. Connect the scope probe, or DMM to the voltage
sense lines on the test tool. When using a scope
probe it is best to isolate the scope from the AC
ground. Make the ground connection on the scope
probe as short as possible.
7. Connect the first ATX supply to the VTT tool.
8. Powerup the first ATX supply to the VTT tool.
9. Start the VTT tool software in VR11 mode with
the current limit set to 150 A.
10. Using the VTT tool software, select a VID code
that is 0.5 V or above.
11. Connect the second ATX supply to the demo
board.
12. Set the VID DIP switches. All the VID switches
should be up or open.
13. Set the VR_ENABLE DIP switch down or
closed.
14. Set the VR10 DIP switch up or open.
15. Set the VID_SEL switch up or open.
Figure 23. Typical Step Load Response
Figure 24. Typical Load Release Event
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26
NCP5386, NCP5386A, NCP5386B
Dynamic VID Testing
The VTT tool provides for VID stepping based on the
Intel Requirements. Select the Dynamic VID option.
Before enabling the test set the lowest VID to 0.5 V or
greater and set the highest VID to a value that is greater than
the lowest VID selection, then enable the test. See
Figures 25 through 27.
Design Methodology
Decoupling the VCC Pin on the IC
An RC input filter is required as shown in the VCC pin to
minimize supply noise on the IC. The resistor should be
sized such that it does not generate a large voltage drop
between the 12 V supply and the IC. See the schematic
values.
Understanding Soft−Start
The controller supports two different startup routines. An
AMD ramp to the initial VID code, or a VR11 Ramp to the
1.1 V VID code, with a pause to capture the VID code then
resume ramping to target value based on an internal slew
rate limit. See Figures 28 and 29. The controller is designed
to regulate to the voltage on the SS pin until it reaches the
internal DAC voltage. The soft−start cap sets the initial
ramp rate using a typical 5.0 A current. The typical value
to use for the soft−start cap (SS), is typically set to 0.01 F.
This results in a ramp time to 1.1 V of 2.2 ms based on
Equation 1.
dt
Css iss ss
dvss
1.1 · V
dv
ss and iss 5 · A
dtss
2.2 · ms
Figure 25. 1.6 to 0.5 Dynamic VID Response
Css 0.01 · F
Figure 26. Dynamic VID Settling Time Rising
Figure 28. VR11 Startup
Figure 27. Dynamic VID Settling Time Falling
Figure 29. AMD Startup
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27
(eq. 1)
NCP5386, NCP5386A, NCP5386B
Programming the Current Limit and the
Oscillator Frequency
The demo board is set for an operating frequency of
approximately 330 kHz. The OSC pin provides a 2.0 V
reference voltage which is divided down with a resistor
divider and fed into the current limit pin ILIM. Calculate
the total series resistance to set the frequency and then
calculate the individual values for current limit divider.
The series resistors RLIM1 and RLIM2 sink current to
ground. This current is internally mirrored into a capacitor
to create an oscillator. The period is proportional to the
resistance and frequency is inversely proportional to the
resistance. The resistance may be estimated by equation 2.
RTOTAL 24686 FSW −1.1549
30.5 k (eq. 2)
24686 330 −1.1549
100
90
80
ROSC (k)
70
60
50
40
30
FOSC (2, Measured)
20
10
0
FOSC (2, Calculated)
0
200
400
600
800
1000
1200
FOSC (kHz)
Figure 30. ROSC vs. FOSC, 2 Phase
The current limit function is based on the total sensed
current of all phases multiplied by a gain of 6. DCR sensed
inductor current is function of the winding temperature.
The best approach is to set the maximum current limit
based on the expected average maximum temperature of
the inductor windings.
DCRTmax DCR25C ·
(1 0.00393 · C−1 (T max −25 · C))
Calculate the current limit voltage:
VILIMIT 6 ·
I MIN_OCP · DCRTmax DCRTmax · V out
2 · VIN · F s
·
VIN VOUT
L
(N−1) ·
V OUT
L
(eq. 3)
(eq. 4)
Solve for the individual resistors:
RLIM2 VILIMIT · RTOTAL
2·V
RLIM1 RTOTAL RLIM2
(eq. 5)
(eq. 6)
Final Equation for the Current Limit Threshold
ILIMIT(Tinductor) 2 · V · RLIM2
RLIM1RLIM2
5.84 · (DCR25C · (1 0.00393 · C−1(T Inductor−25 · C)))
V OUT
2 · V IN · Fs
·
V IN−VOUT
L
(N−1) ·
VOUT
L
(eq. 7)
Inductor Selection
The inductors on the demo board have a DCR at 25°C of
0.75 m. Selecting the closest available values of 16.9 k
for RLIM1 and 13.7 k for RLIM2 yield a nominal
operating frequency of 330 kHz and an approximate
current limit of 152 A at 100°C. The total sensed current
can be observed as a scaled voltage at the VDRP pin added
to a positive, no−load offset of approximately 1.3 V.
When using inductor current sensing it is recommended
that the inductor does not saturate by more than 10% at
maximum load. The inductor also must not go into hard
saturation before current limit trips. The demo board includes
a two phase output filter using the T50−8 core from
Micrometals with 4turns and a DCR target of 0.75 m @
25°C. Smaller DCR values can be used, however, current
sharing accuracy and droop accuracy decrease as DCR
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28
NCP5386, NCP5386A, NCP5386B
decreases. Use the excel spreadsheet for regulation accuracy
calculations for a specific value of DCR.
of the inductor and recover the voltage that is the result of
the current flowing through the inductor’s DCR. This is
done by matching the RC time constant of the current sense
filter to the L/DCR time constant. The first cut approach is
to use a 0.1 F capacitor for C and then solve for R.
Inductor Current Sense Compensation
The NCP5386 uses the inductor current sensing method.
This method uses an RC filter to cancel out the inductance
RSENSE(T) L
0.1 · F · DCR25C · (1 0.00393 · C−1 · (T−25 · C))
(eq. 8)
The demo board inductor measured 350 nH and
0.75 m at room temp. The actual value used for RSENSE
was 4.42 k which matches the equation for RSENSE at
approximately 50°C. Because the inductor value is a
function of load and inductor temperature final selection of
R is best done experimentally on the bench by monitoring
the VDROOP pin and performing a step load test on the
actual solution.
Simple Average PSPICE Model
A simple state average model shown in Figure 32 can be
used to determine a stable solution and provide insight into
the control system.
Figure 31.
E1
+
+
− −
E
0 GAIN = 6
12
−
+
−
+
VRamp_min
1.3 V
0
−
+
L
1
DCR
2
(250e−9/4)
VIN
12
1
4
RDRP
5.11 k
CCer
(22e−6*18)
1Aac
ESRCer
0Adc
(1.5e−3/18)
2
ESLBulk
(3.5e−9/10)
ESL Cer
(1.5e−9/18)
1
1
+
−
I1 = 10
I2 = 110
TD = 10u
TR = 50n
TF = 50n
PW = 40u
PER = 80u
I2
+
−
0
RF
CF
4.3 k
1.5 n
CFB1
680 p
1E3
CBulk
(560e−6*10)
RBRD
0.75 m
ESRBulk
(7e−3/10)
2
0
22 p
2
100 p
(0.85e−3/4)
Voff
CH
LBRD
Unity
Gain
BW = 15 MHz R6
RFB1
100
RFB
−+
Voff
VOUT
+
−
1k
+
1k
C3
10.6 n
1.3
Voffset
−
0
0
Figure 32.
http://onsemi.com
29
+
VDAC
−
1.25 V
0
NCP5386, NCP5386A, NCP5386B
bulk capacitors have an ESR of 7.0 m. Thus the bulk ESR
plus the board impedance is 0.7 m + 0.75 m or
1.45 m. The actual output filter impedance does not drop
to 1.0 m until the ceramic breaks in at over 375 kHz. The
controller must provide some loop gain slightly less than
one out to a frequency in excess 300 kHz. At frequencies
below where the bulk capacitance ESR breaks with the
bulk capacitance, the DC−DC converter must have
sufficiently high gain to control the output impedance
completely. Standard Type−3 compensation works well
with the NCP5386. RFB1 should be kept above 50 for
amplifier stability reasons.
The goal is to compensate the system such that the
resulting gain generates constant output impedance from
DC up to the frequency where the ceramic takes over
holding the impedance below 1.0 m. See the example of
the locations of the poles and zeros that were set to optimize
the model above.
A complex switching model is available by request
which includes a more detailed board parasitic for this
demo board.
Compensation and Output Filter Design
The values shown on the demo board are a good place to
start for any similar output filter solution. The dynamic
performance can then be adjusted by swapping out various
individual components.
If the required output filter and switching frequency are
significantly different, it’s best to use the available PSPICE
models to design the compensation and output filter from
scratch.
The design target for this demo board was 1.0 m out to
2.0 MHz. The phase switching frequency is currently set to
330 kHz. It can easily be seen that the board impedance of
0.75 m between the load and the bulk capacitance has a
large effect on the output filter. In this case the ten 560 F
Zout Open Loop
Zout Closed Loop
Open Loop Gain with Current loop Closed
80
Voltage Loop Compensation Gain
1/(2*PI*CFB1*(RFB1+RFB))
60
1/(2*PI*CF*RF)
40
20
1/(2*PI*RF*CH)
RF/RFB1
RF/RFB
Error Amp
Open Loop
Gain
dB
0
1/(2*PI*(RBRD+ESRBulk)*CBulk)
−20
−40
1/(2*PI*SQRT(ESL_Cer*CCer))
1mOhm
−60
−80
−100
100
1/(2*PI*CCer*(RBRD+ESRBulk))
1000
10000
100000
1000000
10000000
Frequency
Figure 33.
By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk
and ceramic capacitor type output filter.
1
1
2 · CF · RF
2 · (RBRD ESRBulk) · CBulk
1
1
2 · CFBI · (RFBI RFB)
2 · CCer * (RBRD ESRBulk)
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30
(eq. 9)
NCP5386, NCP5386A, NCP5386B
RFB is always set to 1.0 k and RFB1 is usually set to
100 for maximum phase boost. The value of RF is
typically set to 4.0 k.
RRDP determines the target output impedance by the
basic equation:
VOUT
RFB · DCR · 6
Z OUT IOUT
RDRP
RFB · DCR · 6
RDRP ZOUT
Droop Injection and Thermal Compensation
The VDRP signal is generated by summing the sensed
output currents for each phase and applying a gain of
approximately six. VDRP is externally summed into the
feedback network by the resistor RDRP. This induces an
offset which is proportional to the output current thereby
forcing the controlled resistive output impedance.
(eq.
10)
The value of the inductor’s DCR varies with temperature
according to the following equation 10:
DCRTmax DCR 25C · (1 0.00393 · C−1(T max 25 · C))
The system can be thermally compensated to cancel this
effect out to a great degree by adding an NTC (negative
temperature coefficient resistor) in parallel with RFB to
reduce the droop gain as the temperature increases. The
NTC device is nonlinear. Putting a resistor in series with the
(eq. 11)
NTC helps make the device appear more linear with
temperature. The series resistor is split and inserted on both
sides of the NTC to reduce noise injection into the feedback
loop. The recommended value for RISO1 and RISO2 is
approximately 1.0 k.
The output impedance varies with inductor temperature by the equation:
ZOUT(T) RFB · DCR25C · (1 0.00393 · C−1(T max −25C)) · 6
Rdroop
(eq. 12)
By including the NTC RT2 and the series isolation resistors the new equation becomes:
ZOUT(T) RFB · (RISO1RT2(T)RISO2)
RFBRISO1RT2(T)RISO2
· DCR25C · (1 0.00393 · C−1(T max −25C)) · 6
R droop
The typical equation of a NTC is based on a curve fit
equation 13.
1 2731 T
298
RT2(T) RT225C · e (eq. 13)
ON Semiconductor provides an excel spreadsheet to
help with the selection of the NTC. The actual selection of
the NTC will be effected by the location of the output
inductor with respect to the NTC and airflow, and should
be verified with an actual system thermal solution.
(eq. 14)
The demo board is populated with a 10 k NTC with a
Beta of 4300. Figure 34 shows the uncompensated and
compensated output impedance versus temperature.
VRFAN
Thermal monitoring provides one threshold sensitive
comparator for thermal monitoring. The circuit consists of
one comparator that compares the voltage on the NTC pin
to an internal resistor divider connected to VCC.
The following equations can be used to find the
temperature trip points.
1 2731 T
298
RT1(T) RT125C · e RatioNTC(T) :
RNTC2 RT1(T)
RNTC1 RNTC2 RT1(T)
(eq. 15)
(eq. 16)
The demo board contains a 68 K NTC for RT1 with a
Beta of 4750. RNTC1 is populated with 15 k and RNTC2
is populated with a zero ohm resistor. Figure 35 is a plot of
Equation 16. The horizontal trip thresholds intersect the
Figure 34. Uncompensated and Compensated Output
Impedance vs. Temperature
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31
NCP5386, NCP5386A, NCP5386B
Ratio NTC curve, at the respective activation and
deactivation temperature.
UVLO threshold. See the state diagram for further details.
The OVP circuit monitors the output of DIFFOUT. If the
DIFFOUT signal reaches 180 mV above the nominal 1.3 V
offset the OVP will trip. The DIFFOUT signal is the
difference between the output voltage and the DAC voltage
plus the 1.3 V internal offset. This results in the OVP
tracking the DAC voltage even during a dynamic change
in the VID setting during operation.
Gate Driver and MOSFET Selection
ON Semiconductor provides the companion gate driver
IC (NCP3418B). The NCP3418B driver is optimized to
work with a range of MOSFETs commonly used in CPU
applications.
The NCP3418B provides special
functionality and is required for the high performance
dynamic VID operation of the part. Contact your local
ON Semiconductor
applications
engineer
for
MOSFET recommendations.
Figure 35.
OVP
The overvoltage protection threshold is not adjustable.
OVP protection is enabled as soon as soft−start begins and
is disabled when the part is disabled. When OVP is tripped,
the controller commands all two gate drivers to enable their
low side MOSFETs, and VR_RDY transitions low. In order
to recover from an OVP condition, VCC must fall below the
Board Stackup
The demo board follows the recommended Intel Stackup
and copper thickness as shown.
Figure 36.
Board Layout
A complete Allegro ATX and BTX demo board layout
file and schematics are available by request at
www.onsemi.com and can be viewed using the Allegro
Free Physical Viewer 15.x from the Cadence website
http://www.cadence.com/.
Close attention should be paid to the routing of the sense
traces and control lines that propagate away from the
controller IC. Routing should follow the demo board
example. For further information or layout review contact
ON Semiconductor.
http://onsemi.com
32
NCP5386, NCP5386A, NCP5386B
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 485AF−01
ISSUE O
PIN ONE
LOCATION
2X
ÉÉ
ÉÉ
0.15 C
2X
A
B
D
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
TOP VIEW
0.15 C
(A3)
0.10 C
A
32 X
0.08 C
SIDE VIEW
SEATING
PLANE
A1
C
EXPOSED PAD
D2
L
32 X
9
MILLIMETERS
MIN
NOM MAX
0.800 0.900 1.000
0.000 0.025 0.050
0.200 REF
0.180 0.250 0.300
5.00 BSC
3.500 3.650 3.800
5.00 BSC
3.500 3.650 3.800
0.500 BSC
0.200
−−−
−−−
0.300 0.400 0.500
16
K
32 X
17
8
E2
1
24
32
25
32 X b
0.10 C A B
e
0.05 C
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent− Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products
for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components
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indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney
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negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws
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http://onsemi.com
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