SC1175 Datasheet

SC1175
Low Power Dual Synchronous DC/DC
Controller With Current Sharing Circuitry
POWER MANAGEMENT
Description
Features
The SC1175 is a versatile 2 phase, synchronous, voltage mode PWM controller that may be used in two distinct ways. First, the SC1175 is ideal for applications
where point of use output power exceeds any single input power budget. Alternatively, the SC1175 can be used
as a dual switcher. The SC1175 features a temperature
compensated voltage reference, over current protection
with 50% fold-back and internal level-shifted, high-side
drive circuitry.
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In current sharing configuration, the SC1175 can produce a single output voltage from two separate voltage
sources (which can be different voltage levels) while
maintaining current sharing between the channels. Current sharing is programmable to allow loading each input
supply as required by the application.
Two Phase, Current Sharing Controller
300kHz fixed frequency operation
Soft Start and Enable function
Power Good output provided
Over current protection with 50% fold-back
Phase-shifted switchers minimize ripple
High efficiency operation, >90%
Programmable output(s) as low as 1.25V
Industrial temperature range
20 pin SOIC or TSSOP package
‹ Flexible, same or separate VIN
‹ Programmable current sharing
‹ Combined current limit with fold-back
‹ 2 phases operating opposed for ripple reduction
‹ Thermal distribution via multi-phase output
In dual switcher configuration, two feedback paths are
provided for independent control of the separate outputs. The device will provide a regulated output from
flexibly configured inputs (3.3V, 5V, 12V), provided 5V is
present for VCC. The two switchers are 180° out of phase
to minimize input and output ripple.
Two Independent PWM Controllers
‹
‹
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‹
Flexible, same or separate VIN
Independent control for each channel
Independent and separate current limit
2 phases operating opposed for ripple reduction (if
same VIN used)
Applications
‹ Graphics cards
‹ DDR Memory
‹ Peripheral add-in card
‹ SSTL Termination
‹ Dual-Phase power supply
‹ Power supplies requiring two outputs
Revision: September 22, 2004
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SC1175
POWER MANAGEMENT
Typical Application Circuit
2 Channels with Current Sharing
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SC1175
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Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied.
Parameter
VCC to GND
Symbol
Limits
Units
VIN
-0.3 to 15
V
±1
V
-0.3 to 26
V
PGND to GND
BST to GND
Thermal Resistance Junction to Case
θJC
30
°C/W
Thermal Resistance Junction to Ambient
θJ A
90
°C/W
Operating Ambient Temperature Range
TA
0 to 85
°C
Operating Junction Temperature Range
TJ
0 to 125
°C
Storage Temperature Range
TSTG
-65 to +150
°C
Lead Temperature (Soldering) 10 sec
TLEAD
300
°C
Electrical Characteristics
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, 0mV < (CS(+) - CS(-)) < 60mV , TJ = 25°C
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage
IO = 2A(1), VOUT set to 2.75V
2.65
2.75
2.85
V
Supply Voltage
V CC
4.2
15
V
Supply Current
VCC = 5.0
Reference
Load Regulation
10
1.2375
IO = 0.3A to 15A (1)
1.25
mA
1.2625
1
V
%
Reference Line Regulation
5V < V C C < 15V
.5
%
Output Line Regulation
5V < VIN < 15V
.5
%
Gain (AOL)
VOSENSE to VO
35
dB
Current Limit Voltage
60
70
80
mV
Oscillator Frequency
270
300
330
kHz
Oscillator Max Duty Cycle
90
95
%
DH Sink Current
DH - PGND = 3.5V
1
A
DH Sink Current
DH - PGND = 1.75V
.5
A
DH Source Current
BSTH - DH = 5.0V
1
A
DH Source Current
BSTH - DH = 2.5V
.5
A
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SC1175
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Electrical Characteristics (Cont.)
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, 0mV < (CS(+) - CS(-)) < 60mV , TJ = 25°C
PARAMETER
CONDITIONS
MIN
DL Sink Current
DL - PGND = 3.5V
1
A
DL Sink Current
DL - PGND = 1.75V
.5
A
DL Source Current
BSTL - DL = 5V
1
A
DL Source Current
BSTL - DL = 2.5V
.5
A
Note 5
50
Dead Time
Soft Start Charge Current (2)
Soft Start Enable
Soft Start End
Soft Start Transition(2)
150
UNITS
ns
µA
0% duty cycle
1.4
V
100% duty cycle
2.5
V
Synchronous mode
3.3
V
+10
%VOUT
50%
I LIM
VOUT = 0V
Fold Back Voltage Knee
Input Bias Current
100
MAX
25
Power Good Window(3)
Fold Back Current
TYP
I = ILIM
-IN1, +IN2, -IN2
1.25
VOUT
V
1
µA
NOTES:
(1) Specification refers to application circuit.
(2) The soft start pin sources 25µA to an external capacitor. The converter operates in synchronous mode
above the soft start transition threshold and in asynchronous mode below it.
(3) Power good is an open collector pulled low when the output voltage is outside the ±10% window.
(4) This device is ESD sensitive. Use of standard ESD handling precautions is required.
(5) 200ns maximum at 70°.
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SC1175
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Pin Configuration
Ordering Information
Top View
Device(1)
SC1175CSW.TR
P ackag e
SOIC-20
SC1175CSWTRT(2)
SC1175TS.TR
TSSOP-20
SC1175TSTRT(2)
Pin Descriptions
Expanded Pin Description
 2004 Semtech Corp.
Current Share Version Evaluation
Board
SC1175EVB-2
Dual Channel Version Evaluation
Board
Notes:
(1) Only available in tape and reel packaging. A reel
contains 1000 (SOIC) and 2500 (TSSOP) devices.
(2) Lead free product. This product is fully WEEE and
RoHS compliant.
(SOIC-20 and TSSOP-20 Pin)
Pin 1: (VREF)
Internal 1.25V reference
Connected to the + input of the master channel error
amplifier.
Pin 2: (+IN)
+ Input of slave channel error amplifier.
Connected to 1.25V reference (Pin 1) for the two
independent channel configuration.
Pin 3, 18: (-IN2, -IN1)
- Inputs of close loop error amplifiers.
Works as a feedback inputs (For both modes).
Pin 4: (VCC)
VCC chip supply voltage.
15V maximum, 10mA typical.
Needs a 1µF ceramic multilayer decoupling capacitor
to GND (Pin 20).
Pin 5, 6,
15, 1
6: (CL2-, CL2+, CL1+, CL1-)
6,1
16:
Pins (-) and (+) of the current limit amplifiers for both
channels.
Connected to output current sense resistors. Compares that sense voltage to internal 75mV reference.
Needs RC filter for noise rejection.
Pin 7, 14: (BST2, BST1)
BST signal. Supply for high side driver.
Can be connected to a high enough voltage source.
Usually connected to bootstrap circuit.
Pin 8, 13: (DH2, DH1)
DH signal (Drive High).
Gate drive for top MOSFETs.
Requires a small series resistor.
SC1175EVB-1
Pin 9, 12: (DL2, DL1)
DL signal (Drive Low).
Gate drive for bottom MOSFETs.
Requires a small series resistor.
Pin 10: (PGND)
Power GND. Return of gate drive currents.
Pin 11: (BSTC)
Supply for bottom MOSFETs gate drive.
Pin 1
7: (SS/ENA)
17
Soft start pin. Internal current source connected to
external capacitor.
Inhibits the chip if pulled down.
Pin 19: (PWRGD)
Power good signal.
Open collector signal .
Turns to 0 if output voltage is outside the power good
window.
Pin 20: (GND)
Analog GND.
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Block Diagram
NOTES
(1) Block 1 (top) is the Master and Block 2 (bottom) is the Slave in current sharing configuration.
(2) For independant operation there is no Master or Slave.
Applications Information - Theory of Operation
Main Loop(s)
back path from their own output. In this mode, the
positive input of error amplifier 2 is connected externally to Vref. If the application uses a common input
voltage, the sawtooth phase shift between the channels provides some measure of input ripple current
cancellation.
The SC1175 is a dual, voltage mode synchronous Buck
controller, the two separate channels are identical and
share only IC supply pins (Vcc and GND), output driver
ground (PGND) and pre-driver supply voltage (BSTC). They
also share a common oscillator generating a sawtooth
waveform for channel 1 and an inverted sawtooth for
channel 2. Each channel has its own current limit comparator. Channel 1 has the positive input of the error
amplifier internally connected to Vref. Channel 2 has
both inputs of the error amplifier uncommitted and available externally. This allows the SC1175 to operate in two
distinct modes.
b) Two channels operating in current sharing mode
with common output voltage and either common input voltage or different input voltages. In this mode,
channel 1 operates as a voltage mode Buck controller, as before, but error amp 2 monitors and amplifies
the difference in voltage across the output current
sense resistors of channel 1 and channel 2 (Master
and Slave) and adjusts the Slave duty cycle to match
output currents. Because of finite gain and offsets in
the loop, the resistor ratio for perfect current matching is not 1:1. The Master and Slave channels still have
a) Two independent channels with either common or
different input voltages and different output voltages.
The two channels each have their own voltage feed 2004 Semtech Corp.
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SC1175
POWER MANAGEMENT
Applications Information - Theory of Operation
their own current limits, identical to the independent
channel case.
3. For high duty cycle on the slave channel (above 50%),
the pull up will be on pin 2.
Power Good
The formula is:
The controller provides a power good signal. This is an
open collector output, which is pulled low if the output
voltage is outside of the power good window.
R pull −up (KΩ ) = 2.1 X
5 − VOUT
+ .1
V
.5 − OUT
VSLAVE
100Ω being the value of the resistors connecting the
pins 2 and 3 to the two output sense resistors.
Soft Start/Enable
The Soft Start/Enable (SS/ENA) pin serves several functions. If held below the Soft Start Enable threshold, both
channels are inhibited. DH1 and DH2 will be low, turning
off the top FETs. Between the Soft Start Enable threshold and the Soft Start End threshold, the duty cycle is
allowed to increase. At the Soft Start End threshold,
maximum duty cycle is reached. In practical applications
the error amplifier will be controlling the duty cycle before the Soft Start End threshold is reached. To avoid
boost problems during startup in current share mode,
both channels start up in asynchronous mode, and the
bottom FET body diode is used for recirculating current
during the FET off time. When the SS/ENA pin reaches
the Soft Start Transition threshold, the channels begin
operating in synchronous mode for improved efficiency.
The soft start pin sources approximately 25uA and soft
start timing can be set by selection of an appropriate
soft start capacitor value.
.1 V is an estimated voltage drop across the MOSFETs.
Positive values go to pin 3, negative to pin 2.
A +20K will be a 20K on pin 3.
A -20K will be a 20K on pin 2.
Now that the offset resistor has been fixed, we need to
set up the maximum current for each channel.
Selection of RSENSE 1 for the master channel: (in m ohm)
RSENSE 1 = 72mV / I max master
Selection of RSENSE 2 for the slave channel: (in m ohm)
RSENSE 2 = 72mV / I max slave
The errors will be minimized if the power components
have been sized proportionately to the maximum
currents.
SENSE RESISTOR SELECTION
Current Sharing Mode
Independent Channels
Calculation of the three programming resistors to achieve
sharing. Three resistors will determine the current sharing load line. First the offset resistor will ensure that the
load line crosses the origin (0 Amp on each channel) for
sharing at light current. A pull up resistor from the 5V
bias (VCC of the chip) will be used. For low duty cycle on
the slave channel (below 50%), the pull up will be on pin
Calculation of the two current limiting resistors.
There is no need for an offset resistor in the independent channels mode, only the two sense resistors are
used:
Selection of RSENSE 1 for the channel 1: (mohms)
RSENSE 1 = 72mV / I max ch 1
Selection of RSENSE 2 for the channel 2: (mohms)
RSENSE 1 = 72mV / I max ch 2
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing
Figure 1: VOUT vs IIN(5V) and IIN(12V) with VCC applied and 4A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (1A/Div)
Ch4: IIN(12V) (1A/Div)
IOUT: 4.004 Amps
Figure 2: VOUT vs IIN(5V) and IIN(12V) with VCC removed and 4A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (1A/Div)
Ch4: IIN(12V) (1A/Div)
IOUT: 4.004 Amps
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing (Cont.)
Figure 3: VOUT vs IIN(5V) and IIN(12V) with VCC applied and 12A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (2A/Div)
Ch4: IIN(12V) (2A/Div)
IOUT: 12 Amps
Figure 4: VOUT vs IIN(5V) and IIN(12V) with VCC removed and 12A load. Soft start capacitor = 10nF.
Ch1: VOUT
Ch2: IIN(5V) (2A/Div)
Ch4: IIN(12V) (2A/Div)
IOUT: 12 Amps
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Channels with Current Sharing (Cont.)
Figure 5: Efficiency data - current sharing mode.
1.0
0.9
0.8
Efficiency (%)
0.7
0.6
0.5
0.4
0.3
VIN(MASTER) = 12V
VIN(SLAVE) = 5V
VOUT = 2.75V
0.2
0.1
0.0
0
2
4
6
8
10
12
14
Current (A)
The Current Sharing Evaluation Board is not intended for a specific application. The power components are not
optimized for minimum cost and size. This evaluation board should be used to understand the operation of the
SC1175. To design with SC1175 for specific current sharing applications,please refer to Application note AN00-3.
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SC1175
POWER MANAGEMENT
Evaluation Board Schematic - 2 Channel with Current Sharing
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SC1175
POWER MANAGEMENT
Evaluation Board Bill of Materials - 2 Channels with Current Sharing
Item
Quantity
1
2
C1,C7
.22uF, 50V
2
3
C2,C3,C4
1uF, 50V
3
3
C5,C15,C16
10nF, 50V
4
1
C8
1nF, 50V
5
3
C9,C10,C14
100uF, 6V
6
6
C11,C12,C13,C17,C18,C19
150uF, 16V
7
2
D1,D2
D L4148
8
1
L1
7.5uH, 8A
9
1
L2
4.7uH, 8A
10
2
M1,M3
IRF7809 or FDB7030
11
2
M2,M4
IRF7811 or FDB7030
12
1
R1
124
13
7
R2,R3,R4,R5,R6,R7,R8
2.2
14
2
R9,R10
100
15
1
R12
150
16
1
R13
.006
17
1
R14
.003
18
1
U1
SC1175
 2004 Semtech Corp.
Reference
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Part
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SC1175
POWER MANAGEMENT
Evaluation Board Gerber Plots - 2 Channels with Current Sharing
Top Side Traces
Bottom Side Traces
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels
Figure 6:
Figure 7
7:: Output Current
Input Voltage = 12V @ 5Amps. 2A/DIV.
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels (Cont.)
Figure 8: Peak - Peak Output Ripple @ 5A
IInput Voltage = 12V.
Output Voltage = 2.0V
Figure 9: Phase Node 12V Input @ 5A (without snubber and RC network.
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels (Cont.)
Figure 10: Start-up Power On
Chan. 1 = Output Current. 2A/DIV.
Chan. 2 = 5V Bias Voltage
Figure 11: Power Off
Chan. 1 = Output Current. 2A/DIV.
Chan. 2 = 5V Bias Voltage
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SC1175
POWER MANAGEMENT
Typical Characteristics - 2 Independent Channels Efficiency Test
Figure 12:
EFFICIENCY
100
95
Vin = 12V Vout =
2.0V
90
85
Vin = 5V
1.25V
80
75
Vout =
70
0
1
2
3
4
5
6
OUTPUT CURRENT
The Independent Channels Evaluation Board is not intended for a specific application. The power components
are not optimized for minimum cost and size. This evaluation board should be used to understand the operation
of the SC1175.
To design with the SC1175 for specific independent channels applications. Please refer to: Application note
AN00-4.
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SC1175
POWER MANAGEMENT
Evaluation Board Schematic - 2 Independent Channels
 2004 Semtech Corp.
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SC1175
POWER MANAGEMENT
Evaluation Board Bill of Materials - 2 Independent Channels
Item
Quantity
1
3
C1,C2,C3
1uF, 50V
2
3
C4,C6,C11
.22uF, 50V
3
1
C5
1nF, 50V
4
4
C7,C8,C9,C10
10nF, 50V
5
9
C12,C13,C14,C15,C16,C17,C18,C19,C20
150uF, 6V
6
3
C21,C22,C23
100uF, 16V
7
2
D1,D2
D L4148
8
1
L1
7.5uH, 8A
9
1
L2
4.7uH, 8A
10
2
M1,M3
IRF7809 or FDB7030
11
2
M2,M4
IRF7811 or FDB7030
12
7
R1,R2,R3,R4,R5,R6,R7
2.2
13
3
R8,R9,R13
100
14
1
R10
.006
15
1
R11
220
16
1
R12
.003
17
2
R14,R15
124
18
1
U1
SC1175
 2004 Semtech Corp.
Reference
19
Part
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SC1175
POWER MANAGEMENT
Evaluation Board Gerber Plots - 2 Independent Channels
Top Side Traces
Bottom Side Traces
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SC1175
POWER MANAGEMENT
Power and signal traces must be kept separated for
noise considerations. Feedback, current sense traces
and analog ground should not cross any traces or
planes carrying high switching currents, such as the
input loop or the phase node.
The input loop, consisting of the input capacitors and
both MOSFETs must be kept as small as possible. All of
the high switching currents occur in this loop. The
enclosed loop area must be kept small to minimize
inductance and radiated and conducted emissions.
Designing for minimum trace length is not always the
best approach, often a more optimum layout can be
achieved by keeping loop area constraints in mind.
It is important to keep gate lengths short, the IC must
be close to the power switches. This is more difficult in
a dual channel device than a single and requires that
the two power paths run on either side of a centrally
located controller.
Grounding requirements are always conflicting in a
buck converter, especially at high power, and the trick
is to achieve the best compromise. Power ground
(PGND) should be returned to the bottom MOSFET
source to provide the best gate current return path.
Analog ground (GND) should be returned to the ground
side of the output capacitors so that the analog
circuitry in the controller has an electrically quiet
reference and to provide the greatest feedback
accuracy. The problem is that the differential voltage
capability of the two IC grounds is limited to about 1V
for proper operation and so the physical separation
between the two grounds must also be minimized. If
the grounds are too far apart, fast current transitions
in the connection can generate voltage spikes exceeding the 1V capability, resulting in unstable and erratic
behavior.
The feedback divider must be close to the IC and be
returned to analog ground. Current sense traces must
be run parallel and close to each other and to analog
ground.
The IC must have a ceramic decoupling capacitor
across its supply pins, mounted as close to the device
as possible. The small ceramic, noise-filtering capacitors on the current sense lines should also be placed
as close to the IC as possible.
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SC1175
POWER MANAGEMENT
Outline Drawing - TSSOP-20
A
DIM
D
e
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
N
2X E/2
E1
E
PIN 1
INDICATOR
ccc C 1 2 3
2X N/2 TIPS
e/2
B
.047
.002
.006
.031
.042
.007
.012
.003
.007
.251 .255 .259
.169 .173 .177
.252 BSC
.026 BSC
.018 .024 .030
(.039)
20
0°
8°
.004
.004
.008
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
6.40 6.50 6.60
4.30 4.40 4.50
6.40 BSC
0.65 BSC
0.45 0.60 0.75
(1.0)
20
0°
8°
0.10
0.10
0.20
D
aaa C
SEATING
PLANE
DIMENSIONS
INCHES
MILLIMETERS
MIN NOM MAX MIN NOM MAX
A2 A
C
H
A1
bxN
bbb
C A-B D
c
GAGE
PLANE
0.25
SEE DETAIL
SIDE VIEW
L
(L1)
DETAIL
A
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B-
TO BE DETERMINED AT DATUM PLANE-H-
3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4. REFERENCE JEDEC STD MO-153, VARIATION AC.
Land Pattern - TSSOP-20
X
DIM
(C)
G
C
G
P
X
Y
Z
Z
Y
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
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SC1175
POWER MANAGEMENT
Outline Drawing - SO-20
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
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