APPLICATION NOTE Atmel AVR1021: Migration from ATxmega64A4/32A4/16A4 to ATxmega64A4U/32A4U/16A4U Atmel AVR XMEGA Features • • • • • • • Enhancement and added functions Memories System clock and clock options Reset source I/O ports DAC – digital to analog converter AC – analog comparator Introduction This application note is a guide to assist users of Atmel® ATxmega64A4/32A4/16A4 in converting designs to Atmel ATxmega64A4U/32A4U/16A4U. For complete device details, always refer to the most recent version of the ATxmega64A4U/32A4U/16A4U datasheet and the Atmel AVR®XMEGA®AU manual. Errata differences between ATxmega64A4/32A4/16A4 and ATxmega64A4U/32A4U/16A4U are not listed in this document, only in the device datasheet. In addition to the differences described in this document, other typical characteristics could be different. Check the latest datasheet for details. ATxmega64A4U/32A4U/16A4U also includes new configuration options and functions. As far as possible these are implemented as a superset of existing ATxmega64A4/32A4/16A4 functions, so existing code for these devices will work on the new devices without changing existing configuration or enabling new functions. The new options and functions are listed in the application note for customers who in addition to a pure migration also wish to see an overview to consider use of the new functions. 8417B−AVR−03/2013 Table of Contents 1. Enhancements and Added Functions .................................................. 3 1.1 USB ….. ........................................................................................................... 3 1.2 Clock system ..................................................................................................... 3 1.3 Two-wire interface ............................................................................................. 3 1.4 I/O ports ............................................................................................................ 3 1.5 Analog to digital converter ................................................................................. 3 1.6 Analog comparator ............................................................................................ 3 1.7 CRC16 / CRC32 generator ............................................................................... 3 1.8 High 16-bit timer/counter 0 ................................................................................ 3 1.9 High resolution extension .................................................................................. 3 1.10 Power management .......................................................................................... 4 2. Memories ............................................................................................. 4 2.1 NVM controller .................................................................................................. 4 2.2 Fuses and lock bits ........................................................................................... 4 3. System Clock and Clock Options ......................................................... 4 3.1 DFLL 2MHz and DFLL 32MHz .......................................................................... 4 4. Reset Source ....................................................................................... 5 4.1 Brown-out detection .......................................................................................... 5 5. I/O Ports ............................................................................................... 5 6. DAC – Digital to Analog Converter ...................................................... 5 7. AC – Analog Converter ........................................................................ 6 8. Registers .............................................................................................. 6 8.1 Removed registers and bits .............................................................................. 6 9. Revision History ................................................................................... 7 Atmel AVR1021: Migration from ATxmega64A4/32A4/16A4 to ATxmega64A4U/32A4U/16A4U [APPLICATION NOTE] 8417B−AVR−03/2013 2 1. Enhancements and Added Functions In this chapter, we summarize the enhancement or added features in Atmel ATxmega64A4U/32A4U/16A4U compared to Atmel ATxmega64A4/32A4/16A4. For pure migration, you can skip the chapter and start from the next chapter. 1.1 USB • 1.2 1.3 Clock system • • • • Alternate pin location for TOSC1 and TOSC2 pins for 32.768kHz crystal connection • • Higher drive option for external crystal oscillator to support crystals with higher load Alternate pin locations for Timer/Counter 0 Compare Channels, USART0 and SPI Alternate pin locations for the Peripheral Clock and Event output functions The Real Time Counter clock can be output to a port pin Any Event Channel can be output to a port pin Automatic input channel scan VCC/2 voltage reference option 1/2x (divide by two) gain stage setting Internal ground can be used as negative input in differential mode (with gain) Analog Comparator 1 can be output on a port pin A constant current source A CRC16/CRC32 Generator Module that supports CRC16 (RC-CCITT) and CRC-32 (IEEE 802.3) High 16-bit timer/counter 0 • 1.9 The SDA Hold time can be increased and configured in order to be SMBUS compliant CRC16 / CRC32 generator • 1.8 The 32MHz Internal Oscillator can be tuned to run at any frequency between 30MHz and 55MHz Analog comparator • • 1.7 Non-prescaled Real Time Counter clock source options: External clock from TOSC1, 32.768kHz from TOSC, and the 32.768kHz from the 32.768kHz Internal Oscillator Analog to digital converter • • • • 1.6 PLL lock failure detection with optionally Non Mask-able Interrupt (NMI), for improved safety and robustness I/O ports • • • • 1.5 A divide-by-two option for the PLL output that enables output frequency down to 10MHz Two-wire interface • 1.4 One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface is added Split mode that enable two 8-bit Timer/Counters with 4PWM channels each High resolution extension • Hi-Res+ option to allow PWM resolution to be increased with 8x (3-bit) Atmel AVR1021: Migration from ATxmega64A4/32A4/16A4 to ATxmega64A4U/32A4U/16A4U [APPLICATION NOTE] 8417B−AVR−03/2013 3 1.10 Power management • Possibility to enable sequential start of the components used for analog modules ADC and Analog Comparator in order to reduce start-up current 2. Memories 2.1 NVM controller For Atmel ATxmega64A4/32A4/16A4 devices, the chip erase time is about 40ms. The chip erase time of Atmel ATxmega64A4U/32A4U/16A4U devices is longer. The typical chip erase time of ATxmega64A4U/32A4U/16A4U devices is listed in Table 2-1. Table 2-1. ATxmega64A4U/32A4U/16A4U chip erase time. Product Flash and boot code size Chip erase time ATxmega16A4U 16KB + 4KB 45ms ATxmega32A4U 32KB + 4KB 50ms ATxmega64A4U 64KB + 4KB 55ms To ensure that the flash chip erase be finished correctly, no flash access should be done during the chip erase time. In the user code, it is always needed to check the FBUSY bit in Non-Volatile Memory Status Register to see when the chip erase is finished. 2.2 Fuses and lock bits BOD levels are different in ATxmega64A4U/32A4U/16A4U. See Section 4.1 Brown-out detection for the differences. 3. System Clock and Clock Options 3.1 DFLL 2MHz and DFLL 32MHz COMP0, the lowest byte of Oscillator Compare Register, does not exist from both DFLLs for 2MHz and 32MHz internal oscillator in Atmel ATxmega64A4U/32A4U/16A4U. For more details, refer to device datasheet. Atmel AVR1021: Migration from ATxmega64A4/32A4/16A4 to ATxmega64A4U/32A4U/16A4U [APPLICATION NOTE] 8417B−AVR−03/2013 4 4. Reset Source 4.1 Brown-out detection The programmable BODLEVEL settings are different in Atmel ATxmega64A4U/32A4U/16A4U. See Table 4-1 for details. Refer to the device datasheet regarding tolerance for the Brown-out levels. Table 4-1. 5. Brown-out levels. BODLEVEL VBOT – XMEGA AU VBOT – XMEGA A 111 1.6V 1.6V 110 1.8V 1.9V 101 2.0V 2.1V 100 2.2V 2.4V 011 2.4V 2.6V 010 2.6V 2.9V 001 2.8V 3.2V 000 3.0V 3.4V I/O Ports The I/O port pins are LVTTL and LVCMOS compatible for Atmel ATxmega64A4U/32A4U/16A4U devices. The minimum “Input High Voltage” is never higher than 2.0V for VCC > 2.7V. In Atmel ATxmega64A4/32A4/16A4, the minimum “Input High Voltage” is 0.7VCC, and could be higher than 2.0V for VCC > 2.86V. 6. DAC – Digital to Analog Converter The ATxmega64A4U/32A4U/16A4U DAC has two continuous output channels, and not a sample and hold circuit as ATxmega64A4/32A4/16A4 devices. This give continuous time output and higher sample rate for each channel. There is separate calibration (offset/gain) for each DAC channel in ATxmega64A4U/32A4U/16A4U. When DACA0OFFCAL (in Production Signature Row) is written to CH0OFFSETCAL in DACA, CH1OFFSETCAL is also written with this value. The details of this operation are shown below. The first step, • • read DACA0OFFCAL from production signature row write DACA0OFFCAL to DACA.CH0OFFSETCAL This will result in: • • DACA.CH0OFFSETCAL = DACA0OFFCAL DACA.CH1OFFSETCAL = DACA0OFFCAL The second step, • • read DACA1OFFCAL from production signature row write DACA1OFFCAL to DACA.CH1OFFSETCAL This will result in: • DACA.CH1OFFSETCAL = DACA1OFFCAL Atmel AVR1021: Migration from ATxmega64A4/32A4/16A4 to ATxmega64A4U/32A4U/16A4U [APPLICATION NOTE] 8417B−AVR−03/2013 5 After that, any further writing to DACA.CH0OFFSELCAL does not change DACA.CH1OFFSELCAL until the next reset. The same is implemented for both OFFSET and GAIN calibration registers in DACA and DACB. This ensure that customers using the ATxmega64A4/32A4/16A4 DAC can continue and use the same calibration sequence and still calibrate both channels. TIMCTRL register does not exist in ATxmega64A4U/32A4U/16A4U, so there are no timing constraints on DAC operation. 7. AC – Analog Converter In Atmel ATxmega64A4U/32A4U/16A4U, there is a two-cycle delay from writing a new MUX setting until it takes effect. 8. Registers 8.1 Removed registers and bits Table 8-1 lists register bits, which exist in Atmel ATxmega64A4/32A4/16A4 but not in Atmel ATxmega64A4U/32A4U/16A4U. Table 8-1. Register bits and functionality that does not exist in ATxmega64A4U/32A4U/16A4U. Register name TIMCTRL COMP0 Register bit Function CONINTVAL[2:0] DAC Conversion Interval REFRESH[3:0] DAC Channel Refresh Timing Control COMP[7:0] Oscillator Compare Register 0 Atmel AVR1021: Migration from ATxmega64A4/32A4/16A4 to ATxmega64A4U/32A4U/16A4U [APPLICATION NOTE] 8417B−AVR−03/2013 6 9. Revision History Doc. Rev. Date Comments 8417B 03/2013 ATxmega64A4 and ATxmega64A4U information added 8417A 07/2011 Initial document release Atmel AVR1021: Migration from ATxmega64A4/32A4/16A4 to ATxmega64A4U/32A4U/16A4U [APPLICATION NOTE] 8417B−AVR−03/2013 7 Atmel Corporation Atmel Asia Limited Atmel Munich GmbH Atmel Japan G.K. 1600 Technology Drive Unit 01-5 & 16, 19F Business Campus 16F Shin-Osaki Kangyo Building San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1)(408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1)(408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81)(3) 6417-0300 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81)(3) 6417-0370 Fax: (+852) 2722-1369 © 2013 Atmel Corporation. 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