ATA664151 - Complete

ATA664151
LIN System Basis Chip with LIN Transceiver, 5V
Regulator, Watchdog, 8-channel High Voltage Switch
Interface with High Voltage Current Sources, 16-bit SPI
DATASHEET
Features
● 8-channel HV switch interface with HV current sources
● Linear low-drop voltage regulator, up to 80mA current capability, VCC = 5.0V ±2%
● Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications
Rev.1.3”
● LIN master and slave operation possible
● Supply voltage up to 40V
● Operating voltage VS = 5V to 27V
● Internal voltage divider for VBattery sensing (±2%)
● 16-bit serial interface (daisy-chain-capable) for configuration and diagnosis
● Typically 8µA supply current during sleep mode
● Typically 35µA supply current in active low-power mode
● VCC-undervoltage detection (4ms reset time) and watchdog reset logical
combined at NRES open drain output
● LIN high-speed mode up to 200kBit/s
● Adjustable watchdog timer via external resistor
● Negative trigger input for watchdog
● LIN physical layer complies with LIN 2.1 specification and SAE J2602-2
● Wake-up capability via LIN bus and CL15
● Bus pin is overtemperature and short-circuit protected versus GND and battery
● Advanced EMC and ESD performance
● Package: QFN32 5x5mm
9268I-AUTO-04/15
1.
Description
The Atmel® ATA664151 is a system basis chip with an eight-channel high voltage switch interface, a LIN 2.1 and
SAEJ2602-2-compliant LIN transceiver, low-drop voltage regulator, and an adjustable window watchdog. The Atmel
ATA664151 provides 5V output voltage with up to 80mA current capability. This chip combination makes it possible to
develop inexpensive, simple, yet powerful slave and master nodes for LIN bus systems. The Atmel ATA664151 is especially
designed for LIN switch applications and includes almost the entire LIN node. They are designed to handle low data-rate
communication in vehicles (such as in convenience electronics). Improved slope control at the LIN driver ensures secure
data communication up to 20kBaud. Sleep Mode and Active Low-power Mode guarantee minimal current consumption even
in the case of a floating bus line or a short circuit on the LIN bus to GND.
Figure 1-1. Block Diagram
RXD TXD
LIN
VS
NCS
SCK
MOSI
16-bit Serial
Programming
Interface
(SPI)
LIN Physical Layer
Interface
Internal
Supplies
Voltage
Regulator
VCC
MISO
CL15
VBATT
HV Input
NRES
VBATT
Voltage
Divider
Control Logic
NIRQ
Int. Oscillator
HV Switch
Interface
(8x)
Window Watchdog
WD-Oscillator
VDIV
PWM1
PWM2
PWM3
NTRIG
2
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WDOSC AGND
GND
IREF CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8
2.
Pin Configuration
Figure 2-1. Pinning QFN32, 5x5mm
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
ATA664151
5
Pin
20
6
19
7
18
8
17
9
Table 2-1.
21
10 11 12 13 14 15 16
Pinning
Name
Function
1
TXD
LIN-bus logic data in from microcontroller
2
RXD
LIN-bus logic data out to microcontroller
3
NRES
Watchdog and VCC undervoltage Reset Output pin (active low, open drain)
4
NIRQ
Interrupt request output to microcontroller (active low, open drain)
5
MISO
SPI Master-In-Slave-Out output pin to microcontroller
6
MOSI
SPI Master-Out-Slave-In input pin from microcontroller
7
SCK
SPI clock input from microcontroller
8
NCS
SPI chip select logic input from microcontroller (active low)
9
PWM1
PWM control input port from microcontroller for first CS pin group
10
PWM2
PWM control input port from microcontroller for second CS pin group
11
PWM3
PWM control input port from microcontroller for third CS pin group
12
WDOSC
13
VDIV
Voltage divider output / watchdog disable input pin
14
IREF
Reference current adjustment pin
15
CS1
High-voltage current sink/source and switch I/O pin no. 1
16
CS2
High-voltage current sink/source and switch I/O pin no. 2
17
CS3
High-voltage current sink/source and switch I/O pin no. 3
18
CL15
Wake-up on ignition high-voltage input pin
19
VBATT
20
GND
Ground connection
21
LIN
LIN-bus connection
22
GND
Ground connection
23
GND
Ground connection
24
CS4
High-voltage current source and switch I/O pin no. 4
25
CS5
High-voltage current source and switch I/O pin no. 5
26
CS6
High-voltage current source and switch I/O pin no. 6
27
CS7
High-voltage current source and switch I/O pin no. 7
Connection for external resistor to set watchdog frequency
Battery voltage input for voltage divider
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Table 2-1.
4
Pinning (Continued)
Pin
Name
28
CS8
29
VS
30
AGND
31
VCC
32
NTRIG
Backside
GND
ATA664151 [DATASHEET]
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Function
High-voltage current source and switch I/O pin no. 8
Supply input pin
Analog reference ground
5V Voltage regulator output pin
Watchdog trigger input from microcontroller
Back Side Heat Slug, internally connected to GND
3.
Pin and Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent of higher LIN layers (such as the LIN protocol layer), all nodes with a LIN
physical layer as per release version 2.1 can be mixed with LIN physical layer nodes found in older versions (i.e., LIN 1.0,
LIN 1.1, LIN 1.2, LIN 1.3, LIN 2.0), without any restrictions.
3.2
Supply Pin (VS)
The operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission via the
LIN bus and the switch interface if VVS falls below VVSth in order to avoid false bus messages. After switching on VS, the IC
starts in active mode (see also Section 4.1 “Active Mode” on page 9), with the VCC voltage regulator and the window
watchdog switched on (the latter depends on the VDIV pin, see Section 10. “Watchdog” on page 28).
3.3
Ground Pins GND and AGND
The IC is neutral on the LIN pin in the event of GND disconnection. It can handle a ground shift of up to 11.5% of VS.
Note:
3.4
Please note that pin AGND is used for internal reference generation. This should be considered when designing the PCB in order to minimize the effect on the voltage thresholds.
Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads up to 80mA for supplying the microcontroller and other loads on
the PCB. It is protected against overloads by means of current limitation and overtemperature shutdown. In addition, the
output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold
VVCCthun.
A safe operating area (SOA) is defined for the voltage regulator, because the power dissipation caused by this block might
exceed the system’s thermal budget.
3.5
Bus Pin (LIN)
A low-side driver with internal current limitation, thermal shutdown and an internal pull-up resistor in compliance with the
LIN 2.1 specification are implemented. The allowed voltage range is from –30V to +40V. Reverse currents from the LIN bus
to VS are suppressed, even in the event of GND shifts or battery disconnection. The LIN receiver thresholds are compatible
with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to
recessive bus state are slope-controlled.
For higher bit rates the slope control can be switched off by setting the SPI-bit LSME. Then the slope time of the LIN falling
edge is < 2µs. The slope time of the rising edge strongly depends on the capacitive load and the pull-up resistance at the
LIN-line. To achieve a high bit rate it is recommended to use a small external pull-up resistor (500) and a small capacitor.
This allows very fast data transmission up to 200Kbit/s, e.g., for electronic control tests of the ECU, microcontroller
programming or data download. In this High-speed Mode a superior EMC performance is not guaranteed.
Note:
3.6
The internal pull-up resistor is only switched on in active mode and when the LIN transceiver is activated by the
LINE-bit (active mode with LIN bus transceiver).
Bus Logic Level Input Pin (TXD)
The TXD pin is the microcontroller interface for controlling the state of the LIN output. TXD must be pulled to ground in order
to keep the LIN bus in the dominant state. If TXD is high or not connected (internal pull-up resistor), the LIN output transistor
is turned off and the bus is in recessive state.
If configured, an internal timer prevents the bus line from being constantly driven in the dominant state. If TXD is forced to
low for longer than tDOM, the LIN bus driver is switched back to recessive state. TXD has to be switched to high for at least
tTOrel to reactivate the LIN bus driver (by resetting the time-out timer).
As mentioned above, this time-out function can be disabled via the SPI configuration register in order to achieve any long
dominant state on the connected line (such as PWM transmission, or low bit rates).
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3.7
Bus Logic Level Output Pin (RXD)
This output pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level,
LIN low (dominant state) is reported by a low level at RXD. The output has push-pull characteristics meaning no external
time defining measures are required. During states of disabled LIN-PHY (configuration bit “LINE” = 0), pin RXD is at high
level. Please note that the signal on the RXD pin is not valid for a certain period of time upon activation of the LIN transceiver
(tRXDinvalid).
Figure 3-1. RXD Timing upon Transceiver Enable
NCS
SPI word with LINE = 1
RXD
X
LIN bus state
0 = DOM --- 1 = REC
tRXDinvalid
RXD is switched off in sleep- and unpowered mode.
3.8
CL15 Pin
The CL15 pin is a high-voltage input that can be used to wake up the device from sleep mode. It is an edge-sensitive pin
(low-to-high transition). Thus, even if CL15 pin is at high voltage (VCL15 > VCL15th), it is possible to switch into sleep mode. It
is usually connected to the ignition for generating a local wake-up in the application if the ignition is switched on. The CL15
pin should be tied directly to ground if not needed. A debounce timer with a value tdebCL15 of typically 160µs is implemented.
The pin state (CL15 ON or OFF) can be read out through the SPI interface.
3.9
Reset Output Pin (NRES)
The reset output pin is an open drain output and switches to low during a VCC undervoltage event or a watchdog timing
window failure. Please note the reset hold time of typically 4ms after the undervoltage condition has disappeared.
3.10
Interrupt Request Output Pin (NIRQ)
The interrupt request output pin is an open drain output and switches to low whenever a chip-internal event occurs that is set
up to trigger an interrupt. A power-up, a wake-up over LIN bus, a change in a switch state or an overtemperature condition
are examples of such events. The pin remains at ground until the end of the next SPI command, where the interrupt source
is passed to the SPI master (bits IRQS, see also Section 7. “Serial Programming Interface (SPI)” on page 17).
3.11
WDOSC Output Pin
The WDOSC output pin provides a typical voltage of 1.2V intended to supply an external resistor with values between 34K
and 120K. The value of the resistor and with it the pin output current adjusts the watchdog oscillator frequency to provide a
certain range of time windows.
If the watchdog is disabled, the output voltage is switched off and the pin can either be tied to VCC or left open.
3.12
NTRIG Input Pin
The NTRIG input pin is the trigger input for the Window Watchdog. A pull-up resistor is implemented. A falling edge triggers
the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger and avoid false
triggers caused by transients. The NTRIG pin should be tied directly to VCC if not needed.
3.13
VBATT Input Pin
The VBATT is a high voltage input pin for measurement purposes by means of a voltage divider. The latter provides a lowvoltage signal at the VDIV pin that is linearly dependent on the input voltage. In an application with battery voltage
monitoring, this pin is connected to VBattery via a 51 resistor in series and a 10nF capacitor to GND. The divider ratio is 1:4.
This results in maximum output voltages on pin VDIV when reaching 20V at the input. The VBATT pin can be tied directly to
ground or left open if not needed.
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3.14
VDIV Input/Output Pin
This pin handles two different functions. During the VCC startup and watchdog reset phase (pin NRES driven to LOW), the
pin acts as input and determines the setting of the “WDD” bit within the SPI configuration register (see Figure 3-2). In other
words, if the window watchdog operation shall be disabled directly after power-up (e.g., for microcontroller programming or
debugging purposes), pin VDIV must be tied to HIGH level until the reset phase ends (pin NRES has a positive slope from
LOW to HIGH). In other cases, such as when pin VDIV is not driven actively by the application, the signal is assessed as
LOW and the WDD bit (watchdog disable) is thus also low and the window watchdog is operational (see Figure 3-2).
Figure 3-2. WDD Configuration Bit Setup During VCC Startup
NRES
“LOW” from VCC startup
VDIV (driven externally)
WDD config bit state
Logic Level “A”
X
Z (high imp.)
Logic Level “A”
During normal operation this pin provides a low-voltage signal for the ADC such as for a microcontroller. It is sourced either
by the VBATT pin or one of the switch input pins CS1 to CS8. An external ceramic capacitor is recommended for low-pass
filtering of this signal. If selected in the configuration register of the SPI, this pin guarantees a voltage- and temperaturestable output ratio of the selected test input and is available in all modes except sleep mode. Please note that the current
consumption values in the active low-power mode of Atmel® ATA664151 given in the electrical characteristics lose their
validity if the VDIV output pin is being used in this low-power mode. The voltage on this pin is actively clamped to VCC if the
input value would lead to higher values.
3.15
IREF Output Pin
This pin is the connection for an external resistor towards ground. It provides a regulated voltage which will cause a resistordependent current used as reference for the current sources in the switch interface I/O ports. The resistor should be placed
closely to the pin without any additional capacitor. A fail-safe circuitry detects if the resistor is missing or if there is a short
towards ground or VCC on this pin. An internal fail-safe current is generated in this event. Please see also Section 8. “Switch
Interface Unit” on page 22 for further details.
3.16
CS1 to CS8 High-voltage Input/Output Pins
These pins are intended for contact monitoring and/or constant current sourcing. A total of eight I/Os (pins CS1 through
CS8) are available, of which three (CS1, CS2 and CS3) can be configured either as current sources (such as for switches
towards ground) or as current sinks (such as for switches towards battery). The other five pins (CS4 to CS8) have only
current sourcing capability. Apart from a high voltage (HV) comparator for simple switches, the I/Os are also equipped with a
voltage divider to enable analog voltage measurements on HV pins by using the ADC of the application’s microcontroller
(see Section 3.14 “VDIV Input/Output Pin” on page 7 for further details). Also, each input can trigger an interrupt upon state
change even during Active Low-power Mode. If one or more CSx pins are not needed, can be left open or directly connected
to VS.
Note:
3.17
Unused CSx-pins should be connected directly to VS.
PWM1..3 Input Pins
These pins can be used to control the switch interface current sources directly, such as for pulse width-modulated load
control or for pulsed switch scanning. They accept logic level signals from the microcontroller and are equipped with pulldown structures so in case of an open connection, the input is well defined. For more information see Section 8. “Switch
Interface Unit” on page 22.
The assignment of the current sources to the three PWM input pins is described in Section 8.1 “Current Sources” on page
22.
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4.
Operating Modes
There are two primary modes of operation available with the Atmel® ATA664151.
● Active mode:
In this mode the VCC voltage regulator is active and the SPI is ready for operation. In addition, all other peripherals
can be enabled or disabled by configuration via SPI. After power-up the watchdog is enabled (dependent on the VDIV
pin only, see Section 3.14 “VDIV Input/Output Pin” on page 7), whereas the LIN transceiver and the switch interface
unit are switched off.
●
Sleep mode:
All peripherals are switched off (including the VCC voltage regulator), a wake-up is only possible via the LIN bus or
the CL15 pin. In this mode the IC has the lowest possible current consumption.
Figure 4-1. State Diagram
Unpowered Mode
All circuitry OFF
VVS < 3.3V
VVS > 3.5V
Config Init
Load WDD bit dependent
on VDIV input level
Active Mode
VVS < 3.3V
VCC: ON
All other peripherals
config dependent
SLEEP bit = 1
LIN Wake up or
CL15 Wake up
Sleep Mode
VCC: OFF
All other peripherals:
OFF
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VVS < 3.3V
4.1
Active Mode
If sufficient voltage is applied to the IC at the VS pin, the configuration register is initialized and the chip changes to active
mode. In this mode different states of power consumption are possible, depending on the configuration selected for the chip
and activity on the SPI. The following table lists all power states (except unpowered) for the Atmel® ATA664151.
Table 4-1.
State and Current Consumption vs. Enabled Periphery
State and VS Pin
Current Consumption
LIN bus
Transceiver
Voltage
Divider
VCC Voltage
Regulator
Watchdog
SPI Data
Comm.
Current
Sources
Sleep
IVS = IVSsleep
Off
Off
Off
Off
Off
Off
Active low-power
Off
Off
Off
Off
IVS = IVSact_lp
(LINE=0)
(VDIVE=0)
(WDD=1)
(NCS=1)
(CSEx=X and
CSCx=0 and
PWMy=0)
Active SPI comm.
Off
Off
Off
On
Off
IVS = IVSact_spi
(LINE=0)
(VDIVE=0)
(WDD=1)
(NCS=0)
(CSEx=0)
Off or standby
Active with watchdog
Off
Off
IVS = IVSact_wd
(LINE=0)
(VDIVE=0)
Active with LIN-bus
transceiver
On
Off
(LINE=1)
(VDIVE=0)
IVS = IVSact_lin
On
On
On
On
On
(WDD=0)
Off
(WDD=1)
do not care
do not care
Off
(CSEx=0)
Off
(CSEx=0)
On
Active with current
sources
IVS = IVSact_cs
Active with voltage
divider
Off
Off
(LINE=0)
(VDIVE=0)
Off
On
(LINE=0)
IVS = Iact_vdiv
Note:
Legend:
0 = bit is programmed 0
1 = bit is programmed 1,
X = Disregards
(VDIVE=1)
On
On
Off
(WDD=1)
Off
(WDD=1)
do not care
do not care
(CSEx=1 and
(CSCx=1 or
PWMy=1))
Off
(CSEx=0)
The descriptions in brackets below the peripherals refer to the configuration register of Atmel ATA664151, accessible via
SPI.
Please note that the table above only lists the active mode states with just one extra peripheral enabled. Except for active
low-power, any combination of the states above and thus also the current consumption is possible - for example, the parallel
operation of the LIN bus transceiver and the current sources. The required supply current is then at least the sum of the
values given above.
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4.2
Sleep Mode
This mode must be initialized via the SPI configuration register. All peripherals, i.e., the LIN transceiver, the watchdog, the
voltage dividers, the switch interface Unit and the VCC voltage regulator are switched off. The overall supply current on pin
VS is then reduced to a minimum.
Two wake-up mechanisms are possible to leave sleep mode again: wake-up via LIN and wake-up via CL15.
4.2.1
Wake-up from Sleep Mode via LIN
A voltage below the LIN pre-wake threshold on the LIN pin activates a wake-up detection phase.
A falling edge at the LIN pin followed by a dominant bus level maintained for a time period of at least tbus and the following
rising edge at the LIN pin (see Figure 4-2) results in a remote wake-up request. The device switches from sleep mode to
active-low power mode (VCC regulator enabled), but the LIN transceiver is still deactivated. Only the internal LIN slave
termination resistor is switched on. The remote wake-up request is indicated by a low level at the NIRQ pin to interrupt the
microcontroller (see Figure 4-2). In addition, the wake-up source is stated in the chip status register which can be read out
via SPI. Configuring the chip via SPI must be used to enable the LIN transceiver and allow data to be send and/or
transmitted via the LIN bus. Note that this can only be done after the LOW level at the NRES pin has been eliminated (after
VCC ramp-up and the stabilization phase).
Figure 4-2. LIN Wake-up from Sleep Mode
LIN Bus
VCC
NRES
NIRQ
SPI Comm.
Watchdog State
Init IC/ Read Status
Watchdog off
tbus = 90μs typ
VCC
Startup
Start Watchdog Lead Time
tnres = 4ms typ
With the initialization of the configuration register by the microcontroller, the status word of Atmel® ATA664151 is transmitted
back, including the wake-up source. In other words, the two status bits “IRQS1” and “IRQS0” both read back as '1'. For more
information see Section 7. “Serial Programming Interface (SPI)” on page 17.
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4.2.2
Wake-up from Sleep Mode via CL15
Voltage above VCL15H at pin CL15 activates a CL15 wake-up detection phase. This state must persist for at least tCLdeb in
order to detect a wake-up. If the pulse is too short, the IC remains in Sleep Mode.
When leaving sleep mode first the VCC voltage regulator is activated to enable the microcontroller supply. Then as soon as
the VCC level reaches valid levels, the VCC startup timer is started. During this time, the NRES pin is kept low in order to
keep the microcontroller from running. This ensures a proper voltage supply and signal stabilization in the application. With
the rising edge at NRES, the SPI is ready for communication and the Atmel® ATA664151 can be initialized.
Figure 4-3. CL15 Wake-up from Sleep Mode
CL15
VCC
NRES
NIRQ
SPI Comm.
Watchdog State
Init IC/ Read Status
Watchdog off
tCL15deb = 160μs typ
VCC
Startup
Start Watchdog Lead Time
tnres = 4ms typ
The wake-up behavior is analogous to a wake-up via the LIN bus as seen above. One difference is that no negative edge is
required to start the wake-up procedure as is the case for LIN wake-ups. After the VCC startup time tWDnres has elapsed,
NRES is released and therefore pulled up, either by the internal or additional external resistors. The microcontroller can then
configure the Atmel ATA664151 and thus be notified about the actual status including the wake-up source. Here, the two
status bits “IRQS1” and “IRQS0” read back as '10'.
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4.2.3
Sleep Mode: Behavior at a Floating LIN bus or a Short-circuited LIN to GND
In sleep mode the device has very low current consumption even during short-circuits or floating conditions on the bus. A
floating bus can arise if the master pull-up resistor is missing, such as when it is switched off while the LIN master is in sleep
mode or even if the power supply of the master node is switched off.
In order to minimize the current consumption IVS in sleep mode during voltage levels on the LIN pin below the LIN pre-wake
threshold, the receiver is activated only for a specific time tmon. If tmon elapses while the voltage at the bus is lower than
pre-wake detection low (VLINL) or higher than the LIN dominant level, the receiver is switched off again and the circuit
changes back to sleep mode. The current consumption is then IVSsleep_short (typ. 10µA more than IVSsleep). If a dominant state
is reached on the bus, no wake-up occurs. Even if the voltage rises above the pre-wake detection high (VLINH), the IC will
stay in sleep mode.
This means the LIN bus must be above the pre-wake detection threshold VLINH for a few microseconds before a new LIN
wake-up is possible.
Figure 4-4. Floating LIN Bus During Sleep Mode
LIN Pre-wake
VLINL
LIN BUS
LIN dominant state
VBUSdom
tmon
IVSsleep_short
IVSfail
IVS
IVSsleep
Mode of
operation
Sleep Mode
Int. Pull-up
Resistor
RLIN
IVSsleep
Wake-up Detection Phase
Sleep Mode
off (disabled)
If the Atmel® ATA664151 is in Sleep Mode and the voltage level at the LIN bus is in dominant state (VLIN < VBUSdom) for a
period exceeding tmon (during a short circuit at LIN, for example), the IC switches back to sleep Mode. The VS current
consumption is then IVSsleep_short (typ. 10µA more than IVSsleep). After a positive edge at the LIN pin the IC switches directly to
active mode.
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Figure 4-5. Short Circuit to GND on the LIN Bus During Sleep Mode
LIN Pre-wake
LIN BUS
VLINL
LIN dominant state
VBUSdom
tmon
tmon
IVSsleep_short
IVSfail
IVS
Mode of
operation
IVSsleep
Sleep Mode
Int. Pull-up
Resistor
RLIN
4.3
Wake-up Detection Phase
off (disabled)
Sleep Mode
Active Mode
on (enabled)
Active Low-power Mode
In this mode, the VCC voltage regulator is active and can therefore supply the application’s microcontroller.
All other functions of the Atmel® ATA664151 are disabled in the configuration register respectively inhibited by the PWM pins
for the CSx pin current sources. This reduces the current consumption of the chip itself to a low-power range of typically
below 50µA. Note that this is only valid if the chip select input of the SPI, NCS, is also kept at a high level. If it is pulled to
ground, SPI communication is enabled, causing a higher current consumption.
If the LIN transceiver is disabled, the bus is monitored for a wake-up event, initialized with a voltage level below the LIN
pre-wake threshold at the LIN pin.
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Figure 4-6. LIN Wake-up from Active Low-power Mode
LIN Bus
VCC
NRES
NIRQ
SPI Comm.
Enable WD/ Read Status
Watchdog State
Watchdog off
Start Watchdog Lead Time
tbus = 90μs typ
The negative edge on the NIRQ pin indicates a change of conditions, in this case a wake-up request at the LIN bus. The
microcontroller can check the IRQ source by assessing the “IRQS1” and “IRQS0” bits in the status register. Note that if a
watchdog operation is desired, it must be enabled via the configuration register.
The behavior can be transferred to a wake-up over CL15 pin from active low-power mode.
Figure 4-7. CL15 Wake-up from Active Low-power Mode
CL15
VCC
NRES
NIRQ
SPI Comm.
Watchdog State
Enable WD/ Read Status
Watchdog off
Start Watchdog Lead Time
tCL15deb = 160μs typ
Apart from the LIN transceiver and the CL15 input, the high-voltage I/O ports CS1 to CS8 can also be used to generate
interrupts while in active low-power Mode. This can be done by enabling the current sources so that they can generate an
interrupt with the corresponding CSEx- and CSIEx bits in the configuration register. As long as the current source is not
enabled (CSCx='0' and PWMy low), the IC stays in active low-power mode (if all other conditions are met, such as disabled
watchdog). The PWMy pin has to be set to high by the microcontroller, for example, controlled via a PWM timer unit, in order
to check the condition of the connected switch. Because the switch interface unit is enabled, current consumption increases
drastically. This “switch scanning phase” can be short compared to the interceding idle time so the mean current
consumption of the IC remains close to the active low-power Mode current consumption. For more information, see Section
8.1 “Current Sources” on page 22 and Section 8.2 “Switch Inputs” on page 24 for further details.
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Behavior under Low Supply Voltage Conditions
When connected to the car battery, the voltage at the VS pin increases according to the blocking capacitor (see Figure 4-8).
As soon as VVS exceeds its undervoltage threshold VVSthO, the Switch Interface Unit and the LIN transceiver can be used.
The IC is in active mode after power-up with the VCC voltage regulator and the window watchdog enabled – the latter
depends on the state of the pin VDIV. The VCC output voltage reaches its nominal value after tVCC. This time depends on the
externally applied VCC capacitor and the load.
The NRES is low for the reset time delay treset. During this time treset, no SPI communication and thus no configuration
changes or status checks are possible.
Figure 4-8. VCC versus VS
7.0
6.5
6.0
5.5
5.0
Regulator drop voltage VD
4.5
4.0
V in V
4.4
LIN
3.5
3.0
2.5
VS
2.0
NRES
1.5
VCC
1.0
0.5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
VS in V
Please note that upper graph is only valid if the VS ramp-up time is much slower than the VCC ramp-up time tVCC and the
NRES delay time treset.
If during active mode the voltage level of VS drops below the undervoltage detection threshold VVSthU, an interrupt is
indicated to the microcontroller by means of a low-signal at the NIRQ pin. Furthermore, both the switch interface unit and the
LIN transceiver are shut down in order to avoid malfunctions or false bus messages. This shutdown is achieved by simply
inhibiting the functions internally. The corresponding bits in the configuration register are not cleared. This means the
functionality resumes if enabled after the supply voltage exceeds above VVSthO again.
If during sleep mode the voltage level of VS drops below the undervoltage detection threshold VVSthU, no change of mode or
any other activity by the Atmel® ATA664151 occurs as long as the level does not drop below the minimum operation value
VVSopmin.
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5.
Wake-up Scenarios from Sleep Mode
5.1
Remote Wake-up via the LIN Bus
A voltage lower than the LIN Pre-wake detection VLINL at the LIN pin activates the internal LIN receiver.
A falling edge at the LIN pin followed by a dominant bus level VBUSdom of at least tBUS and a rising edge at pin LIN results in a
remote wake-up request. The device switches from sleep mode to active mode. The VCC voltage regulator is activated and
the internal slave termination resistor is switched on. The remote wake-up request is indicated by a low level at the NIRQ
pin. this generates an interrupt for the microcontroller and a corresponding flag in the SPI register.
5.2
Local Wake-up via Pin CL15
A positive edge at pin CL15 followed by a high voltage level for a given time period (> tCL15deb) results in a local wake-up
request. The device switches to active mode. The debouncing time ensures that no transients at CL15 create a wake-up.
The local wake-up request is indicated by a low level at the NIRQ pin, generating an interrupt for the microcontroller. During
high-level voltage at the CL15 pin, it is possible to switch to sleep mode via an SPI command. In this case the voltage at the
CL15 pin has to be switched to low for at least tCL15deb before the positive edge at this pin starts a new local wake-up request.
Note that this time can be extended by adapting the external circuitry.
5.3
Wake-up Source Recognition
The device can distinguish between different wake-up sources.
The source for the wake-up event can be read out of the SPI diagnosis register.
6.
Wake-up Scenarios from Active Low-power Mode
Generally the active low-power mode is only possible if all clock-dependent peripherals such as the LIN transceiver and the
watchdog are disabled. In addition, no SPI communication is allowed to take place to minimize current consumption.
6.1
Wake-up from CSx Pins
The switch input pins can each be used to generate an interrupt request while in active low-power mode. A state change
detection circuitry is implemented for this functionality (see Section 8.2 “Switch Inputs” on page 24). For this functionality, the
respective current source needs to be configured so that it is controlled via the dedicated PWMy pin. A rising edge on this pin
enables the current source, allowing a stable switch readback signal to be delivered at the CSx pin. The switch state is
updated with a falling edge at the PWMy pin. If a change of state is monitored, an interrupt request is generated if the CSIE
bit of the affected current source is set to '1' in the configuration register. If no wake-up should occur on a certain switch either because there is no application demand for this or a failure such as a hanging switch or a connection line short-circuit
is present - it can be prevented by disabling the current source in the SPI configuration register.
6.2
Wake-up from LIN Bus
If during active low-power mode (i.e., the LIN transceiver is disabled) the LIN bus is tied to ground for at least tbus. This
wake-up request is indicated by a negative edge at the NIRQ pin. Please note that the Atmel® ATA664151 stays in active
low-power mode for as long as no SPI communication occurs or configuration changes are made. Current consumption is
only higher during the LIN bus assessment, in other words as long as the voltage on the LIN bus is below VLIN,preL.
Regardless of the LIN bus state, this assessment phase ends after tLIN_wudet at the latest. This ensures a low current
consumption even during shorts on the LIN bus or when there are floating bus levels.
6.3
Wake-up from CL15
If during active low-power mode the voltage on the CL15 pin exceeds VCL15H for at least tCL15deb, an interrupt request is
triggered to indicate a change of state at the CL15 pin. Please note that after the tCL15deb has elapsed, the Atmel ATA664151
stays in active low-power mode for as long as no SPI communication occurs or configuration changes are made.
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6.4
Wake-up from SPI
If during active low-power mode the chip select input NCS is tied to ground, Atmel® ATA664151 leaves the active low-power
mode in order to complete a data communication with the SPI master. The operating mode of the IC is adapted in
accordance with the configuration register update. If no change in configuration has taken place – for example, because only
the actual status was polled or another bus member connected via daisy chaining was addressed – Atmel ATA664151 goes
back to active low-power mode as soon as NCS returns to high level.
7.
Serial Programming Interface (SPI)
Most features of the IC are configured via SPI. Diagnostics are carried out using this interface also. It can be used in active
mode as long as there is no undervoltage condition at the VCC pin.
The Atmel ATA664151 SPI features both POL = 0 / PHA = 0 and POL = 1 / PHA = 1 operating modes.
Figure 7-1. POL = 0 / PHA = 0 Setup
Sample
NCS
MOSI
Setup
X
MSB
14
13
12
2
1
LSB
X
X
Z
MSB
14
13
12
2
1
LSB
MOSI
MSB
Z
SCK
MISO
Figure 7-2. POL = 1 / PHA = 1 Setup
Setup
NCS
MOSI
Sample
X
X
Z
X
MSB
14
13
3
2
1
LSB
X
14
13
3
2
1
LSB
X
SCK
MISO
MSB
The interface contains four pins.
● NCS (chip select pin, active low)
●
●
●
SCK (serial data clock)
MOSI (master-out-slave-in serial data port input from master)
MISO (master-in-slave-out serial data port output from SBC; this pin is tri-state if NCS is high)
No data is loaded from MOSI on SCK edges or provided at MISO if chip select is not active. The output pin MISO is not
actively driven (tri-state) during these phases.
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The data transfer scheme (bit order) is MSB first, meaning the first bit that is transferred is the most significant bit of the
register, with the transfer ending with the least significant bit. These bits are listed on the next pages. The MOSI bits 15 to 0
refer to the configuration register. This means the configuration register is updated with each SPI communication. At the
same time the MISO word is built from the status register bits 15 to 0. Note that changes in the configuration are only visible
in the next status query. This means, for example, that if you enable the watchdog with an SPI command, the status
“Watchdog Active” is not reported in this data transmission but in the next one.
In order to load any data into the chip, the chip select signal must be removed (i.e., set to high) after the 16 SCK clock
periods. A minimum data evaluation time tSPIeval,min has to transpire before the next data transfer can start. Please note also
that any change in configuration of the IC requires this time to go into effect.
Figure 7-3. SPI Configuration Timing
NCS
MOSI Data
Chip Configuration
Config Data
New Config
Previous Config
tSPIeval_min
The following table lists the bits of the configuration register in the Atmel® ATA664151.
Table 7-1.
Bit Name
Description
Default ('0')
Programmed
with '1'
Remark
15
MSB
LSME
Enable LIN-bus
High-speed mode
Normal
High-speed
See LIN transceiver description
14
TTTD
Disable TxD time-out
timer
Enabled
Disabled
See Section 3.6 “Bus Logic
Level Input Pin (TXD)” on page
5
13
IMUL
IREF multiplier value
x100
x50
See Section 8. “Switch Interface
Unit” on page 22
12
LINE
Enable LIN transceiver Disabled
Enabled
See LIN transceiver description
11
SLEEP
Go to sleep
Stay in active
mode
Enable sleep
mode
See Section 4. “Operating
Modes” on page 8
10
VDIVE
Enable VDIV as output
VDIV off
(high-ohmic)
VDIV on (selected See Section 8.2.2 on page 26
voltage divider
and Section 8. “Switch Interface
active)
Unit” on page 22
9
VDIVP
Programming VDIV
output source
VDIV shows
VBATT divider
VDIV shows one
CS divider output
#
18
SPI ConfIguration Register
ATA664151 [DATASHEET]
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See Section 8.2.2 on page 26
and Section 8. “Switch Interface
Unit” on page 22
Table 7-1.
SPI ConfIguration Register (Continued)
Default ('0')
Programmed
with '1'
#
Bit Name
Description
8
CSPE
Enable switch interface
Disabled
unit programming
Enabled
See Section 8. “Switch Interface
Unit” on page 22
7
CSA2
Address bit 2 (MSB) for
0
switch input
1
Used as selector for VDIV
and for programming of one
current source
6
CSA1
Address bit 1 for switch
0
input
1
Used as selector for VDIV
and for programming of one
current source
5
CSA0
Address bit 0 (LSB) for
0
switch input
1
Used as selector for VDIV
and for programming of one
current source
4
CSE
Enable addressed
current source
Disabled
Enabled
See Section 8. “Switch Interface
Unit” on page 22
3
CSSSM
Switch between
source/sink mode
Source mode
selected
(highside)
Sink mode
selected (lowside)
Sink mode is only possible for
switch interfaces 1-3
2
CSC
Control of addressed
current source
External (CSE
and PWMy)
Internal
(CSE only)
See Section 8. “Switch Interface
Unit” on page 22
CSIE
(CSPE=1)
Enable interrupt
from addressed switch
input
Enabled
CSIE will be altered if CSPE
of the SPI word is '1'.
See Section 8. “Switch Interface
Unit” on page 22
CSSCD
(CSPE=0)
CS port current source
slope control
Enabled
Disabled
CSSCD will be altered if CSPE
of the SPI word is '0'.
See Section 8. “Switch Interface
Unit” on page 22
WDD
Disable watchdog
Enabled
(if pin VDIV
on low level)
Disabled
See Section 10. “Watchdog” on
page 28
Disabled
1
0
LSB
Remark
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The following table lists the bits of the status register in Atmel® ATA664151.
Figure 7-4. SPI Status Register
#
Bit Name
Description
Result = “0”
Result = “1”
Remark
OTVCC
(VDIVE=0)
Overtemperature prewarning
Temperature
from VCC regulator temp
not critical
sensor
Temperature
critical
See Section 9. on page 27; only
valid if VDIVE of prev. command
was '0'
MVBATT
(VDIVE=1)
VBATT voltage monitor
OTLIN
(VDIVE=0)
Overtemperature signal from no OverLIN driver temp sensor
temperature
MRDIV2
(VDIVE=1)
CS port voltage monitor,
address bit 2 (MSB)
OTCS
(VDIVE=0)
Overtemperature signal from no Overcurrent sources temp sensor temperature
MRDIV1
(VDIVE=1)
CS port voltage monitor,
address bit 1
MRDIV2..0 indicate the address
of the CS port volt. monitor
visible on VDIV
This bit is only shown if VDIVE of
previous command was '1'
CL15S
(VDIVE=0)
CL15 pin status
VCL15 < VCL15H VCL15 ≥ VCL15H
See Section 11. on page 30; only
valid if VDIVE of prev. command
was '0'
MRDIV0
(VDIVE=1)
CS port voltage monitor,
address bit 0 (LSB)
MRDIV2..0 indicate the address
of the CS port volt. monitor
visible on VDIV
This bit is only shown if VDIVE of
previous command was '1'
11
WDS
Watchdog status
Watchdog
disabled
See Section 10. “Watchdog” on
page 28
10
VSS
VS voltage level status
VS voltage OK VS undervoltage See Section 4.4 on page 15
9
IRQS1
8
IRQS0
Interrupt request source
“00”
“01”
“10”
“11”
7
CS8CS
Switch interface 8
comparator status
VCS8 < VCSxth
VCS8 > VCSxth
See Section 8. “Switch Interface
Unit” on page 22
6
CS7CS
Switch interface 7
comparator status
VCS7 < VCSxth
VCS7 > VCSxth
See Section 8. “Switch Interface
Unit” on page 22
5
CS6CS
Switch interface 6
comparator status
VCS6 < VCSxth
VCS6 > VCSxth
See Section 8. “Switch Interface
Unit” on page 22
4
CS5CS
Switch interface 5
comparator status
VCS5 < VCSxth
VCS5 > VCSxth
See Section 8. “Switch Interface
Unit” on page 22
3
CS4CS
Switch interface 4
comparator status
VCS4 < VCSxth
VCS4 > VCSxth
See Section 8. “Switch Interface
Unit” on page 22
2
CS3CS
Switch interface 3
comparator status
VCS3 < VCSxth
VCS3 > VCSxth
See Section 8. “Switch Interface
Unit” on page 22
1
CS2CS
Switch interface 2
comparator status
VCS2 < VCSxth
VCS2 > VCSxth
See Section 8. “Switch Interface
Unit” on page 22
0
LSB
CS1CS
Switch interface 1
comparator status
VCS1 < VCSxth
VCS1 > VCSxth
See Section 8. “Switch Interface
Unit” on page 22
15
MSB
14
13
12
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VBATT not
VBATT visible
visible on VDIV on VDIV
Overtemperature
MRDIV2..0 indicate the address
of the CS port volt. monitor
visible on VDIV
Overtemperature
Watchdog
enabled
PowerUp
CS change
CL15 wake-up
LIN wake-up
Only valid if VDIVE of prev.
command was '1'
See Section 3.5 on page 5; only
valid if VDIVE of prev. command
was '0'
This bit is only shown if VDIVE of
previous command was '1'
See Section 8. on page 22; only
valid if VDIVE of prev. command
was '0'
Information will be cleared after
status register readout via SPI
The SPI is capable of daisy chaining as well. In other words, if other ICs with a daisy-chaining-enabled SPI are to be used in
the application, they can simply be interconnected one after the other (see Figure 7-5).
Figure 7-5. Daisy Chaining Configuration
Microcontroller
NCS
NCS
SCK
SCK
MOSI
MOSI
MISO
MISO
NCS
SCK
MOSI
ATA664151
Other
SPI
Member
MISO
It can be seen that the data output of Atmel® ATA664151 is not connected to the data input of the master but of another SPI
member which is also capable of daisy chaining. In order to transmit data, the microcontroller has to send the sum of clock
pulses for all bus members. In the example above, if the other SPI member also features 16 bits, the microcontroller has to
perform 32 clock cycles with NCS kept low to completely move the data. The first 16 bits of such a transmission are initially
fed into the Atmel ATA664151. But when NCS stays low, the data is not loaded into its configuration register but instead
shifted out again with the next 16 bits. At the same time the status register of Atmel ATA664151 is first fed into the other SPI
bus member which then needs to transfer the data over to the microcontroller with the second 16 bits.
In summary, the daisy chaining is one way to have multiple bus members connected to a single master. Because not all
devices support these operating modes, the Atmel ATA664151 still supports the direct addressing mode using the NCS pin.
If NCS is not pulled to ground, all data traffic on the SPI is disregarded by the Atmel ATA664151.
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8.
Switch Interface Unit
A total of eight high-side current sources with high voltage comparators and voltage dividers are available for switch
scanning or for example, LED driving purposes. Note that three of them (CS1, CS2, and CS3) can also be switched to
low-side current sinks in the configuration register via the SPI. System wake-up from active low-power mode is possible
through state change monitoring. Please see Figure 8-1 for an overview of the interface structure.
Figure 8-1. Principle Schematic of a High-Side-Only Switch Interface (CS4 - CS5)
VS
CSE [1..8]
IIREF × rlCS
PWMy
CSC [1..8]
State
change
detector
d_statechange
VCSxth (4V DC)
HV
comp
MUX
CSx
dout_cs_x
CSA [2..0]
VBATT
3R
VDIV
VDIVP
R
AGND
VDIVE
The control signals CSE and CSC are configuration register bits, and unique for each of the eight interfaces. The output
signal dout_cs of the comparator can be probed via the SPI status register bit CSxCS.
8.1
Current Sources
The current sources are available in Active Mode. They deliver a current level derived from a reference value measured at
the IREF pin. This pin is voltage-stabilized (VIREF = 1.23V typ.) so that the reference current is directly dependent on the
externally applied resistor connected between IREF pin and ground. The resulting current at the CSx- pins is
(1.23V/RIref)  rICS. For example, with a 12K resistor between IREF and GND the value of the current at the CSx-pins is
10mA (assumed IMUL = '0' => rICS_H = 100). For fail-safe reasons, both a missing and a short-circuited resistor are detected.
In this case, an internally generated reference current IIREFfs is used instead to maintain a certain functionality.
The current sources of I/Os 1-3 (CS1..CS3) can be configured either as high-sides (current sources) or low-sides (current
sinks). This selection is done by the CSSSM bit of the configuration register. The default value of '0' enables the high-side
source whereas a '1' enables the low-side sink.
The output current level can be divided by 2 with the IMUL bit in the configuration register. With the default setting of
IMUL = '0', the ratio between the output current ICSx and the reference current IIREF is rICS_H (typ. 100). If set to '1', the ratio
reduces to rICS_L (typ. 50).
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If a current source is enabled by the configuration register (set to ready state, bit CSE = '1'), it supports two different
operating modes.
● Directly controlled by the configuration register - bit CSC = '1'
●
Externally gated (inhibited with the PWMy pin) - bit CSC = '0' (default)
These modes can be selected independently for each current source via the configuration register. While the current source
is permanently on with CSC = '1' it is controlled externally by the logic level input pins PWMy with CSC = '0' for switch
scanning or LED driving (external PWM control). The following truth table summarizes all setup variants.
Table 8-1.
CS Port Configuration Table
CSEx
CSCx
CSSSM
PWMy
CS1..3
CS4..8
Active Low-power
Mode Possible
0
X
X
X
Off
Off
Yes
1
0
X
0
Off
Off
Yes
1
1
0
X
1
1
No
1
1
1
X
0
1
No
1
0
0
1
1
1
No
1
0
1
1
0
1
No
Legend:
0 -> Bit = '0' for CSEx, CSCx and CSSSM; logic low for PWMy; LS current source active for CS1..3
1 -> Bit = '1' for CSEx, CSCx and CSSSM; logic high for PWMy; HS current source active for CS1..8
X -> Do not care for CSEx, CSCx, CSSM and PWMy
Off -> Current source disabled
Please see Table 8-2 for the assignment between the three available PWM control ports PWM1..3 and the eight current
source outputs CS1..8.
Table 8-2.
Assignment of Current Sources to the PWMy Ports
PWM
Port
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
PWM1
X
-
-
-
-
-
X
X
PWM2
-
X
-
-
X
X
-
-
PWM3
-
-
X
X
-
-
-
-
There is one common control bit for all current sources, the bit “CSSCD”. With this bit, the slope control of all eight sources
can be disabled. By default, the slope control is activated and all currents are switched on and off smoothly (see also
parameter dUCSx,rise and dUCSx,fall). When setting this bit to '1', the current sources are enabled and disabled without
transition times.
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In order to change the configuration of a certain current source via SPI, it must be addressed and the current source
programming bit CSPE must be set to '1'. Please see Table 8-3 for the eight available current sources.
Table 8-3.
CS Port Addressing Table
Current Source on Pin
Bit CSA0
Bit CSA1
Bit CSA2
CS1, high- or lowside
0
0
0
CS2, high- or lowside
1
0
0
CS3, high- or lowside
0
1
0
CS4, highside only
1
1
0
CS5, highside only
0
0
1
CS6, highside only
1
0
1
CS7, highside only
0
1
1
CS8, highside only
1
1
1
That is, if any of the following configuration bits (CSE, CSSSM, CSIE, and CSC) of a certain I/O port shall be changed, the
required data word for the SPI must contain the desired I/O number (bits CSA0..2) and the programming enable bit CSPE
must be '1'. Only in this case, the corresponding bits in the SPI data word are loaded into the configuration register of the
selected switch interface. For the global current source configuration bit CSSCD (slope control for current sources), the
CSPE bit must be '0' in order to be changed via an SPI command. That is, either the four individual configuration bits (CSE,
CSSSM, CSIE and CSC) or the global configuration bit (CSSCD) can be changed with one SPI command word.
Dependent on the selected current, the supply voltage, the externally applied load and the number of current sources
activated, a not neglectable amount of power will be dissipated in Atmel® ATA664151. In order to protect the IC from
damage, the current sources are equipped with thermal monitors. If the temperature in one of the monitors exceeds Tjsd, all
current sources will be shut down and an interrupt will be generated. Note that the current source enabled bits (CSE) in the
configuration register are not cleared by this event. That is, the current sources will be enabled after a certain cooling time.
8.2
Switch Inputs
8.2.1
Voltage Comparators
Each switch input has a high voltage comparator, a state-change-detection register for wake-up and interrupt request
generation and a voltage divider with a low-voltage output that can be fed through to the measurement pin VDIV.
In sleep mode, the HV comparators and the voltage dividers of each input are switched off. In active mode, the comparator
of a channel is activated together with its current source. It has a threshold of VCSxth. The output signal dout_csx of the
comparator is debounced with a delay of tCSdeb. A voltage above the threshold will generate a logical '1' in the status register
bit CSxCS whereas a voltage below will lead to a '0'.
The comparator output signal is also fed into a state change detection logic that can be used to generate wake-up events in
form of an interrupt request, signalized on pin NIRQ. Please see Figure 8-2 on page 25 for an overview of the state change
detection unit.
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Figure 8-2. State Change Detection Circuitry
d_statechange_x
CSx
VCSxth
HV
comp
dout_cs
(4V VDC)
D
Q
D
Q
D-FF
D-FF
R
R
CSC_x
PWMy
CSE_x
As can be seen in Figure 8-2, the data from the comparator is latched with the falling edge of either the PWMy pin or the
CSC bit. That is, the data is latched in the same moment when the current source is switched off. This ensures that the
comparator signal was already stable when its output is evaluated. The output signal d_statechange is evaluated by the
main control logic. If the interrupt enable bit CSIE is set in the configuration register and d_statechange is '1', an interrupt is
generated and reported by a low level on pin NIRQ. Please see Figure 8-3 for an example of the state change detection
system.
Figure 8-3. Interrupt Generation upon State Change
tCSdeb
Signal sample point
Signal sample point
CSE
PWMy/ CSC
CSx
dout_cs_x
sampled state
d_statechange_x
NIRQ
tNIRQtrig
The output state of the HV comparator is sampled with each falling edge of the PWMy or CSC signal. As soon as the
sampled state changes, an interrupt request is given.
In order to have minimum power consumption also for switch scanning applications, Atmel® ATA664151 is able to switch to
active low-power Mode even if current sources are enabled with the CSEx bit in the configuration register. As long as the
current source is inhibited (for example, by having CSCx programmed to 0 and PWMy also at low level), the IC can be in
active low-power mode (dependent on the other peripherals, see also Table 4-1 on page 9). The current source is then in a
kind of stand-by situation. As soon as the PWMy pin is raised, the IC switches to active mode with the defined current
sources on.
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8.2.2
Voltage Dividers
A voltage divider (division by 4) is included for each of the eight CS port channels. Please note that the divider is always
referred to local ground (pin AGND), regardless of the respective current source/sink configuration. As there is only one
output available for all voltage dividers of the chip, only one of them can be active at a time. The SPI data word must contain
the following information in order to activate the voltage divider of a certain switch interface.
● The voltage divider enable bit VDIVE must be '1'.
●
●
The VDIV programming source bit VDIVP must be '1'.
The desired channel must be coded in the three address bits CSA0..2.
Please see Table 8-4 for a list of all voltage divider programming inputs and their corresponding VDIV output state.
Table 8-4.
Voltage Divider Addressing Table
VDIVE
VDIVP
CSA2
CSA1
CSA0
VDIV
0
X
X
X
X
Off
1
0
X
X
X
VBATT / 4
1
1
0
0
0
CS1 / 4
1
1
0
0
1
CS2 / 4
1
1
0
1
0
CS3 / 4
1
1
0
1
1
CS4 / 4
1
1
1
0
0
CS5 / 4
1
1
1
0
1
CS6 / 4
1
1
1
1
0
CS7 / 4
1
1
1
1
1
CS8 / 4
Legend:
0 -> Bit = '0'
1 -> Bit = '1'
X -> Do not care
26
ATA664151 [DATASHEET]
9268I–AUTO–04/15
Voltage Regulator
The VCC voltage regulator in Atmel® ATA664151 is a linear low-drop regulator and requires an external capacitor for
compensation and for smoothing the disturbances in the microcontroller. It is mandatory to use a capacitor with C > 1.8µF
and ESR of below 5. An additional ceramic capacitor with C = 100nF is recommended for EMI suppression. The values of
these capacitors can be varied depending on the application.
Figure 9-1. VCC Voltage Regulator: Ramp-up and Undervoltage Detection
VS
12V
5.5V
t
VCC
5V
Vthun
TVCC
TReset
Tres_f
t
NRES
5V
t
The VCC output transistor is contributing to the ICs total power dissipation – defined by the voltage drop over the transistor
and the output current IVCC. In the figure below, the safe operating area of Atmel ATA664151 is shown. To avoid a thermal
shutdown of the VCC output, the maximum load current decreases with rising ambient temperature and/or battery supply
voltage. Please note also that the current sources contribute to power dissipation.
Figure 9-2. Power Dissipation: Safe Operating Area (SOA) of VCC Output Current versus Supply Voltages VS at
Different Ambient Temperatures, Rthja = 40K/W and No Current Source (Pins CSx) Active
90
80
Output Current (mA)
9.
70
60
50
Ta = 85°C
Ta = 105°C
Ta = 125°C
40
30
20
10
0
4
6
8
10
12
14
16
18
20
22
24
26
28
VS [V] (V_VCC = 5V)
ATA664151 [DATASHEET]
9268I–AUTO–04/15
27
Because the VCC voltage generation is usually fundamental to system operation, there is a thermal prewarning
implemented in the Atmel® ATA664151. The thermal monitor of the VCC output transistor can indicate a critical temperature
condition of TVCCprew by means of an interrupt and the status bit OTVCC in the status register of the chip. The microcontroller
can thus react to these events by shutting down external loads that use the VCC or reducing its own power consumption in
order to avoid a thermal shutdown.
Nevertheless, if the junction temperature of the output transistor exceeds the shutdown threshold Tjsd, the transistor as well
as the VCC are shut down until the temperature has decreased at least by Tjsdhyst. After this cooling-down period, the
regulator starts again in the same way as when powering up or for a wake-up from sleep mode.
For microcontroller programming, it may be necessary to supply the VCC output via an external power supply. It is then
mandatory to disconnect pin VS of the system basis chip, and an operation of Atmel ATA664151 is not possible.
10.
Watchdog
The watchdog expects a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window of
twd. The trigger signal must exceed a minimum time ttrigmin > 7µs. If a triggering signal is not received, a reset signal will be
generated at output NRES. The timing basis of the watchdog is provided by the internal watchdog oscillator. Its time period,
tWDosc, is adjustable via the external resistor Rwd_osc (34k to 120k).
During sleep mode the watchdog is switched off to reduce current consumption. In order to enter active low-power mode, the
watchdog also needs to be disabled via the configuration register. In order to avoid false watchdog disabling, this
configuration bit (WDD) needs to be written twice, i.e., with two consecutive SPI words in order to be altered to '1'.
In order to disable the watchdog right from the start (i.e., after external power-up or after sleep mode), pin VDIV has to be
tied to VCC until the startup time treset of typ. 4ms has elapsed (see Section 3.14 “VDIV Input/Output Pin” on page 7).
The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as
lead time td. After wake-up from sleep mode, the lead time td starts with the positive edge of the NRES output.
10.1
Typical Timing Sequence with RWD_OSC = 51k
The trigger signal Twd is adjustable between 20ms and 64ms using the external resistor RWD_OSC.
For example, with an external resistor of RWD_OSC = 51k ± 1%, the typical parameters of the watchdog are as follows.
tosc = 0.782  RWD_OSC + 1.7  10-6  (RWD_OSC)2
[RWD_OSC in k; tosc in µs]
tOSC = 39.9µs due to 51k
td = 3948 39.9µs = 157.5ms
t1 = 553  39.9µs = 22.1ms
t2 = 527  39.9µs = 21ms
tnres = constant = 4ms
After ramping up the battery voltage, the VCC regulator is switched on. The reset output NRES stays low for the time treset
(typically 4ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead
time, td, follows the reset and td = 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the
trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a
watchdog reset with treset = 4ms resets the microcontroller after td = 155ms. The times t1 and t2 have a fixed relationship. A
triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6ms. To avoid false triggering from
glitches, the trigger pulse must be longer than tTRIG,min > 7µs. This slope restarts the watchdog sequence. If the triggering
signal fails in this open window t2, the NRES output is drawn to ground. A triggering signal during the closed window t1
immediately switches NRES to low.
28
ATA664151 [DATASHEET]
9268I–AUTO–04/15
Figure 10-1. Timing Sequence with RWD_OSC = 51k
VCC
5V
Undervoltage Reset
Watchdog Reset
tnres = 4ms
treset = 4ms
NRES
td = 155ms
t1
t1 = 20.6ms
t2
t2 = 21ms
twd
NTRIG
ttrig > 7μs
10.2
Worst Case Calculation with RWD_OSC = 51k
The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%. The worst-case calculation for
the watchdog period twd is as follows.
The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2.
t1,min = 0.8 t1 = 16.8ms, t1,max = 1.2  t1 = 25.2ms
t2,min = 0.8 t2 = 17.7ms, t2,max = 1.2 t2 = 26.5ms
twdmax = t1min + t2min = 16.8ms + 17.7ms = 34.5ms
twdmin = t1max = 25.2ms
twd = 29.9ms ±4.6ms (±15%)
A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs correctly.
Table 10-1. Typical Watchdog Timings
RWD_OSC
k
Oscillator
Period
tosc/µs
Lead
Time
td/ms
Closed
Window
t1/ms
Open Window
t2/ms
Trigger Period from
Microcontroller twd/ms
Reset Time
tnres/ms
34
26.6
105
14.0
14.7
20.13
4
51
39.9
157.5
21
22.1
29.85
4
91
71.2
281
37.5
39.4
53.27
4
120
93.9
370.6
49.5
51.9
70.26
4
Note that in the case of a missing or shorted resistor on pin WDOSC, the watchdog oscillator period will be well below or
above the reachable values listed above. In other words, if not disabled after startup by using the VDIV pin or during
operation with the SPI configuration, a watchdog reset will be generated all the time for fail-safe reasons.
ATA664151 [DATASHEET]
9268I–AUTO–04/15
29
11.
CL15 HV Input
The CL15 pin can be used as ignition state detection and wake-up input. It has a weak internal pull-down structure, so if no
voltage is connected to this pin, it is at ground level, the passive state of this input. In order to generate an interrupt request
or to wake-up from sleep mode, a certain voltage needs to be applied to this pin.
The input voltage threshold can be adjusted by varying the external resistor due to the input current ICL_15. To protect this pin
against voltage transients, a serial resistor of 10k and a ceramic capacitor of 47nF are recommended. With this RC
combination you can increase the wake-up time tCL15deb as well as enhance sensitivity against transients when ignition of the
CL15 pin occurs.
You can also increase the wake-up time using external capacitors with higher values. In Figure 11-1, the reaction of the
Atmel® ATA664151 to a signal at the CL15 pin is shown. Note that the pin is connected via an R/C low-pass filter.
Figure 11-1. Timing for CL15 Debouncing
CL15
cl15_int
NIRQ
tRC
tCL15deb
In the diagram above, the voltage at the CL15 pin is shown. Due to the R/C filter, the voltage does not immediately increase
but instead slowly over time. As soon as the voltage exceeds approximately 3V, the internal debouncing time tCL15deb starts.
After this elapses, a wake-up is indicated by a falling edge on the NIRQ pin.
12.
30
Fail-safe Features
●
During a short-circuit at LIN to VBattery, the output current is limited to IBUS_lim. Due to power dissipation, the chip
temperature might exceed TLINoff, causing a shutdown of the LIN output transistor. That in turn starts the chip cooling
phase, and after a hysteresis of Thys the output can be switched on again with TXD = 0. During shutdown, RXD
indicates the LIN bus state, which is typically recessive because the output transistor is off. Please note that the VCC
voltage regulator works independently from the LIN output transistor temperature monitor because it is equipped with
its own monitor.
●
During a short-circuit at LIN to GND, the IC can be switched to sleep mode. If the short-circuit disappears, the IC
starts with a remote wake-up.
●
The reverse current is very low < 2µA at the LIN pin during loss of VBatt. This is optimal behavior for bus systems
where some slave nodes are supplied from battery or ignition.
●
During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, NRES switches
to low and can therefore reset the connected microcontroller. If the chip temperature of the VCC output transistor
exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, the output
is reactivated.
●
●
●
The NCS pin provides a pull-up resistor to force the SPI output into tri-state mode if NCS is disconnected
●
If there is no NTRIG signal and short circuit at WDOSC, the NRES switches to low after tWDOfshi. For an open circuit
(no resistor) at WDOSC it switches to low after tWDOfslo.
●
The watchdog disable bit WDD in the configuration register needs to be written twice in order to take effect. This
avoids unwanted watchdog shutdowns due to data misinterpretation caused by EMI.
●
If the IREF pin has a short-circuit to GND or the resistor is disconnected/shorted to VCC, the current sources run with
an internal reference current which guarantees basic functionality of the application.
The TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.
If the WDOSC pin has a short-circuit to GND or the resistor is disconnected, the watchdog runs with an internal
oscillator and ensures a reset takes place.
ATA664151 [DATASHEET]
9268I–AUTO–04/15
13.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Maximum voltage on supply pin VS
1)
Symbol
Min.
Vsup,Stby
–0.4
Typ.
Max.
Unit
+40
V
Operating supply voltage (load dump)
Pulse time ≤ 500ms
Ta = 25°C
VCC output current IVCC ≤ 50mA1)
Vsup,ldump
+40
V
Operating supply voltage (jump start)
Pulse time ≤ 2min
Ta = 25°C
Output current IVCC ≤ 50mA1)
Vsup,jstart
27
V
–2
–150
+40
+100
V
V
Voltage levels on pins1)
- LIN
- VBATT (with 51/10nF)
-> DC voltage
–27
+40
V
Voltage levels on logic/low-voltage pins:
RXD, TXD, NRES, NTRIG, WDOSC,
PWMy, VDIV, NCS, SCK,
MOSI, MISO
–0.4
VVCC + 0.4V
V
–0.4
+5.5
V
Voltage levels on pins
- CS1-8
- CL15 (with 10k/47nF)
-> DC voltage1)
-> Transient voltage due to ISO7637
(coupling via 1nF)
Voltage levels on pin VCC
VVCC
ESD according to IBEE LIN EMC
Test spec. 1.0 following IEC 61000-4-2
- Pin VS (100nF) to GND
- Pin LIN (220pF) to GND
- Pin CL15 (10k, 47nF) to GND
- Pin VBATT (10nF) to GND
- Pins CSx (10nF) to GND
±6
kV
HBM ESD according to
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
MIL-STD-883 (M3015.7)
±2
kV
CDM ESD according to STM 5.3.1
±750
V
MM ESD according to
EIA/JESD22-A115
ESD STM5.2
AEC-Q100 (002)
±200
V
±8
kV
ESD HBM following STM5.1
with 1.5k, 150pF
- Pins VS, LIN, CL15 to GND
Junction temperature
Tj
–40
+150
°C
Storage temperature
Ts
–55
+150
Note:
1. Voltage between any of following pins must not exceed 40V: VS, VBATT, CL15, CSx, LIN
°C
ATA664151 [DATASHEET]
9268I–AUTO–04/15
31
14.
Thermal Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Thermal resistance junction to heat slug
Rthjc
10
K/W
Thermal resistance junction to ambient,
where heat slug is soldered to PCB
according to Jedec
Rthja
35
K/W
Thermal prewarning threshold of VCC
regulator temperature monitor
Thermal shutdown threshold of all
temperature monitors
Thermal shutdown hysteresis
32
ATA664151 [DATASHEET]
9268I–AUTO–04/15
TVCCPreW
120
Tjsd
150
Tjsdhyst
10
140
°C
165
185
°C
17
25
K
15.
Electrical Characteristics
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
1
1.1
1.2
1.3
Parameters
Test Conditions
Pin
Symbol
Min.
VS
VS
5
VLIN > VS – 0.5V
VS ≤ 14V (Tj = 25°C)
VS
IVSsleep
4
VLIN > VS – 0.5V
VS ≤ 14V (Tj = 125°C)
VS
IVSsleep
4
Sleep mode
Bus shorted to GND
VS
VLIN > VS – 0.5V
VS ≤ 14V (Tj = 25°C)
Without load at VCC
Typ.
Max.
Unit
Type*
27
V
B
8
12
µA
B
11
18
µA
A
IVSsleep_short
20
35
µA
A
VS
IVSact_lp
33
45
µA
B
VS
IVSact_lpt
40
55
µA
A
VS
IVSact_lp_short
55
80
µA
B
120
200
µA
A
46
mA
A
µA
D
VS Pin
Nominal DC voltage
range for full operation
Supply current in Sleep
Mode
Supply current in active
VLIN > VS – 0.5V
low-power mode, all
VS ≤ 14V (Tj = 125°C)
peripherals off
Without load at VCC
LIN-bus shorted to GND
1.4
Supply current in active
VLIN > VS – 0.5V
mode after startup (WD
VVS ≤ 14V
active), no VCC load
VS
IVSact_wd
1.5
Supply current in active Bus recessive
mode after startup (WD VVS = 14V
active), high VCC load IVCC = –45mA
VS
IVSdom
Bus recessive
VVS = 14V
IVCC = 0
R_IREF = 5.6k
VS
IVSact_wd
IVSact_lin
IVSact_cs
IVSact_vdiv
Status bit VSS = 1
VS
VVSthU
4.0
4.4
V
A
Status bit VSS = 0
VS
VVSthO
4.3
4.95
V
A
0.19
0.65
V
A
Supply current in
1.10
different active modes
45.1
185
300
2600
300
1.7
VS undervoltage
thresholds
1.8
VS undervoltage
threshold hysteresis
VVSthO – VVsthU
VS
VVSth_hyst
1.9
Minimum VS operation
voltage
VCC active,
SPI operational
VS
VVSopmin
3.8
V
A
RXD
VRXDsink
0.4
V
A
RXD
VRXDsource
V
A
2
0.4
RXD Output Pin
2.1
Low-level output sink
capability
2.2
High-level output source
IRXD = –2mA
capability
IRXD = 2mA
VVCC –
0.4V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA664151 [DATASHEET]
9268I–AUTO–04/15
33
15.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
3
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
0.33 x
VVCC
V
A
V
A
140
k
A
TXD Input Pin
3.1
Maximum voltage level
for logic “low”
TXD
VTXDL,max
3.2
Minimum voltage-level
for logic “high”
TXD
VTXDH,min
0.66 x
VVCC
3.3
Pull-up resistor
VTXD = 0V, VVCC = 5V
TXD
RTXD
40
3.4
Input leakage current
VTXD = VVCC
TXD
ITXDleakH
+1
µA
A
NIRQ
VIRQsink
0.4
V
A
1
µA
A
200
k
A
0.33 
VVCC
V
A
V
A
140
k
A
+1
µA
A
µs
B
VS
V
B
1.2
V
A
2
V
A
0.6
V
A
V
A
47
k
A
1.0
V
D
4
NIRQ Output Pin (Open Drain)
4.1
Low-level output sink
capability
4.2
High-level input leakage
VNIRQ = VVCC
current
NIRQ
INIRQleak,H
4.3
NIRQ pin pull-up resistor
VNIRQ = 0V
value
NIRQ
RNIRQ
5
IIRQ = 2mA
60
Maximum voltage level
for logic “low”
NTRIG
VNTRIGL,max
5.2
Minimum voltage-level
for logic “high”
NTRIG
VNTRIGH,min
0.66 
VVCC
5.3
Pull-up resistor
VNTRIG = 0V, VVCC = 5V
NTRIG
RNTRIG
40
5.4
Input leakage current
VNTRIG = VCC
NTRIG
INTRIGleakH
5.5
Minimum NTRIG pulse
width for watchdog
trigger
NTRIG
ttrig
7
0.9  VS
Driver recessive output
voltage
External LIN pull-up ≤ 1k
LIN
VBUSrec
7.2
Driver dominant voltage
VVS = 7V
RBus = 500
LIN
VBUSLoSUP,
VVS = 18V
RBus = 500
LIN
VVS = 7.0V
Rload = 1000
LIN
7.4
90
LIN-bus Driver
7.1
7.3
100
NTRIG Watchdog Input Pin
5.1
7
90
Driver dominant voltage
Driver dominant voltage
max
VBUSHiSUP,ma
x
VBUSLoSUP,mi
n
7.5
Driver dominant voltage
VVS = 18V
Rload = 1000
LIN
VBUSHiSUP,min
0.8
7.6
Internal pull-up resistor
to VS
Resistor has a serial
rectifier diode
LIN
RLIN
20
7.7
Voltage drop at the
serial diodes
In pull-up path with Rslave
ISerDiode = 10mA
LIN
VSerDiode
0.4
30
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
34
ATA664151 [DATASHEET]
9268I–AUTO–04/15
15.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
Parameters
7.8
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
LIN current limitation
VBUS = VBatt_max
LIN
IBUS_LIM
70
120
200
mA
A
7.9
Module-GND disconnected
Leakage current at loss
VS = VBAT = 0V
of ground(1)
VLIN = –18V
LIN
IBUS_No_Gnd
–20
+20
µA
A
7.10
Battery disconnected
Leakage current at loss
VS = VBAT = 0V
(1)
of battery
0V ≤ VLIN ≤ 18V
LIN
IBUS_No_VS
2
µA
A
Note:
Test Conditions
1. Bus communication must not be affected if the module gets disconnected from ground or from battery.
Parameters 7.9 and 7.10 cover these LIN specification topics.
8
LIN bus Receiver
8.1
Center of receiver
threshold
VBUS_CNT =
0.475 
VS
0.5 
VS
0.525 
VS
V
A
0.4  VS
V
A
V
A
V
A
mA
A
LIN
VBUS_CNT
8.2
Maximum allowed bus
voltage to be detected
as dominant state by
receiver
LIN
VBUS_dom,max
8.3
Minimum allowed bus
voltage to be detected
as recessive state by
receiver
LIN
VBUSr_ec,min 0.6  VS
8.4
Receiver input
hysteresis
Vhys = Vth_rec – Vth_dom
LIN
VBUS_hys
8.5
Input leakage current
Dominant state receiver Driver off
input current
VBUS = 0V
VS = 12V
LIN
IBUS_PAS_dom
8.6
Driver off (recessive state)
Recessive state receiver VBatt = 18V
input current
VBUS = 18V
VBUS = 40V
LIN
8.7
LIN Pre-wake detection
High-level input voltage
LIN
VLIN_preH
VS – 2V
VS +
0.3V
V
A
8.8
LIN Pre-wake detection
Activates the LIN receiver
Low-level input voltage
LIN
VLIN_preL
–27
VS –
3.3V
V
A
8.9
LIN Receiver enabling
time
RXD
tRXDinvalid
15
µs
D
150
µs
B
10
µs
D
9
(Vth_dom + Vth_rec)/2
7V ≤ VS ≤ 27V
Time between rising edge
on NCS and receiver ready
0.028 
0.175 
0.1  VS
VS
VS
–1
–0.35
IBUS_PAS_rec1
IBUS_PAS_rec2
–0.2
11
25
µA
B
A
Internal Timers
9.1
Dominant time for wakeVLIN = 0V
up via LIN-bus
LIN
tbus
70
9.2
Time delay for LIN TRx
Delta between NCS high
enable from active mode
and TXD/RXD transparent
via SPI
CSN
RXD
tnorm
2.5
90
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA664151 [DATASHEET]
9268I–AUTO–04/15
35
15.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
Parameters
Pin
Symbol
Min.
9.3
Time delay for mode
change from active
Delta between NCS high
mode to sleep mode via and LIN-TRx offline
SPI
CSN
RXD
tsleep
2.5
9.4
TXD dominant time-out
timer
TXD
tdom
30
9.5
Time delay for mode
change from active low- Delta between CSN high
power mode into normal and TXD/RXD transparent
mode via SPI
CSN
RXD
ts_n
2.5
TXD
tTOrel
10
LIN
tmon
8
TXD time-out timer
9.11
release time
9.12
Test Conditions
Time for which TXD must
be at least at high level
after a dominant state
time-out
Monitoring time for
wake-up via LIN bus
Typ.
Max.
Unit
Type*
10
µs
D
40
56
ms
B
6
15
µs
D
µs
B
ms
A
14
LIN-bus Driver AC Parameters with Different Bus Loads
Load 1 (small): 1nF, 1k
Load 2 (large): 10nF, 500; CRXD = 20pF;
Load 3 (medium): 6.8nF, 660 characterized on samples; 9.6 and 9.7 specifies the timing parameters for proper operation of
20Kbit/s, 9.8 and 9.9 at 10.4Kbit/s
Duty cycle 1
THRec(max) = 0.744  VS
THDom(max) = 0.581  VS
VS = 7V to 18V
tBit = 50µs
D1 = tbus_rec(min)/(2  tBit)
LIN
D1
Duty cycle 2
THRec(min) = 0.422  VS
THDom(min) = 0.284  VS
VS = 7.6V to 18V
tBit = 50µs
D2 = tbus_rec(max)/(2  tBit)
LIN
D2
Duty cycle 3
THRec(max) = 0.778  VS
THDom(max) = 0.616  VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min)/(2  tBit)
LIN
D3
9.9
Duty cycle 4
THRec(min) = 0.389  VS
THDom(min) = 0.251  VS
VS = 7.6V to 18V
tBit = 96µs
D4 = tbus_rec(max)/(2  tBit)
LIN
D4
9.10
Slope time falling and
rising edge at LIN
VS = 7V
LIN
tSLOPE_fall
tSLOPE_rise
9.6
9.7
9.8
0.396
B
0.581
0.417
B
0.590
3.5
22.5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
36
ATA664151 [DATASHEET]
9268I–AUTO–04/15
B
B
µs
A
15.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
Parameters
10
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions (CRXD): 20pF
10.1
Max propagation delay
of receiver
Test Conditions
VS = 7.0V to 18V
trx_pd = max(trx_pdrise,
trx_pdfall)
11.1
Symbol
Min.
Typ.
Max.
Unit
Type*
6
µs
A
+2
µs
A
RXD
trx_pd
RXD
trx_sym
INRES = 2mA
NRES
VNRESsink
0.4
V
A
VVCC = 2.5V
INRES = 500µA
NRES
VNRESLL
0.4
V
A
6
ms
B
10
µs
A
1
µA
A
Symmetry of receiver
V = 7.0V to 18V
10.2 propagation delay rising S
=t
–t
t
edge minus falling edge rx_sym rx_pdr rx_pdf
11
Pin
–2
NRES Open Drain Output Pin
Low-level output sink
capability
11.2 Low-level at low VCC
11.3
VCC power-up reset
time
VS ≥ 5.5V
CNRES = 20pF
NRES
tUVreset
2
11.4
Reset debounce time for VS ≥ 5.5V
falling edge at VCC
CNRES = 20pF
NRES
tNRESfall
1.5
11.5
High level input leakage
VNRES = VVCC
current
NRES
INRESLeakH
11.6
NRES pin pull-up
resistor value
NRES
RNRES
60
100
200
k
A
1.23
1.33
V
A
+20
mV
A
12
VNRES = 0
4
Watchdog Oscillator
Voltage at WDOSC in
12.1 Active Mode, WDO
enabled
34k ≤ RWDOSC ≤ 120k
VVS ≥ 4V
WDOSC
VWDOSC
1.13
12.2 WDOSC load regulation
dVWDOSC =
VWDOSC,34k – VWDOSC,120k
WDOSC
dVWDOSC
–20
12.3 Oscillator period
ROSC = 34k
tWDOSC,low
21.3
26.6
31.9
µs
A
12.4 Oscillator period
ROSC = 120k
tWDOSC,hi
75.1
93.9
102
µs
A
tWDOfshi
tWDOfslo
4.5
104
18
200
µs
D
12.5
13
Watchdog oscillator
fail-safe periods
WDOSC = 0V
WDOSC = open
Watchdog Window and Reset Timing
13.1
Watchdog lead time
after reset
Cycles are relative to
tWDOSC
tWDlead
3948
cycles
B
13.2
Watchdog closed
window
Cycles are relative to
tWDOSC
tWDclose
527
cycles
B
13.3 Watchdog open window
Cycles are relative to
tWDOSC
tWDopen
553
cycles
B
ms
B
13.4
Watchdog reset time
NRES
NRES
tWDnres
3
4
6
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA664151 [DATASHEET]
9268I–AUTO–04/15
37
15.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
Parameters
14
CL15 Pin
Test Conditions
Pin
Symbol
Min.
4.5
Typ.
Max.
Unit
Type*
V
A
2
V
A
50
100
µA
A
14.1
High-level input voltage SPI status bit ‘CL15S’
threshold
readback as ‘1’
CL15
VCL15H
14.2
Low-level input voltage
threshold
SPI status bit ‘CL15S’
readback as ‘0’
CL15
VCL15L
14.3 CL15 pull-down current
VS ≤ 27V
VCL15 = 27V
CL15
ICL15
14.4 Internal debounce time
Without external capacitor
CL15
tCL15deb
80
160
250
µs
B
VCL15H – VCL15L
CL15
VCL15hsyt
0.5
1
1.5
V
A
5.5V < VS < 18V
(0mA to 50mA)
VCC
VVCCnor
4.9
5.1
V
A
6.5V < VS < 18V
(0mA to 80mA)
VCC
VVCCnor
4.9
5.1
V
C
VCC
VVCClow
2.3
5.1
V
A
250
mV
A
600
mV
A
0,8
%
B
0.2
0.8
%
B
-80
mA
A
µF
D
3.1
V
A
160
300
mV
A
700
µs
A
14.5
17
Hysteresis of input
voltage comparator
VCC Voltage Regulator in Active Mode
17.1 Output voltage VCC
17.2
Output voltage VCC at
low VS
3V < VS < 5.5V
17.3
Regulator drop voltage
for medium load
VS > 4V
IVCC = –20mA
VVCCdrop = VVS – VVCC
VS, VCC
VVCCdrop1
17.4
Regulator drop voltage
for high load
VS > 4V
IVCC = –50mA
VVCCdrop = VVS – VVCC
VS, VCC
VVCCdrop2
400
17.6 Line regulation
5.5V < VS < 18V
VCC
VCCline
17.7 Load regulation
5mA < IVCC < 50mA
100kHz
VCC
VCCload
17.8 Output current limitation VS > 5.5V
VCC
IVCClim
–240
–120
17.9 External load capacity
ESR < 5 at f = 100kHz
VCC
VthunN
1.8
2.2
17.10
VCC undervoltage
threshold
Referred to VCC
VS > 5.5V
VCC
VVCCuv
2.7
17.11
Hysteresis of
undervoltage threshold
Referred to VCC
VS > 5.5V
VCC
VVCCuv_hys
120
17.12
Ramp-up time VS > 5.5V CVCC = 2.2µF
to VCC = 5V
Iload = –5mA at VCC
VCC
tVCC
400
VDIV
rdiv_5V
1:4
VDIV
pVBATT
–2
+2
%
A
44
120
k
A
1
µA
A
18
Battery Voltage Divider
18.1 Divider ratio
18.2 Divider precision
VVBATT = 6 to 19V
18.3 Divider resistance
VVBATT = 12V
VBATT
RVBATT
VVBATT ≤ 27V
VBATT
IVBATTleak
18.4
Input leakage current
with disabled divider
0.1
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
38
ATA664151 [DATASHEET]
9268I–AUTO–04/15
15.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
Pin
Symbol
19
LIN Driver in High-speed Mode (All Tests Using RLIN = 500, CLIN = 600pF)
Min.
Typ.
Max.
Unit
Type*
kBit/s
C
19.1 Transmission bit rate
VVS = 7V to 18V
LIN
SP
200
Slope time LIN falling
edge
VVS = 7V to 18V
LIN
tHSslope_fall
0.3
1
2
µs
A
Slope time LIN rising
19.3 edge, depending on
RC-load
VVS = 7V to 18V
LIN
tHSslope_rise
0.5
2
3
µs
A
19.2
20
Switch Interface Unit (CS1-8, IREF)
20.1
Maximum highside
output current
VVS – VCSx ≥ 2.6V
VVS ≥ 7V
IIREF = –300µA
CSx
ICSx,maxH
–35
–20
mA
A
20.2
Maximum lowside
output current
VCSx ≥ 2.6V
VVS ≥ 7V
IIREF = –300µA
CSx
ICSx,maxL
20
35
mA
A
Current source multiplier VVS ≥ 7V
20.3 from reference current VCSx,HS = VVS – 2.6V
IIREF = –200µA
IIREF, IMUL=100
CSx
rICS_H
95
100
105
A
Current source multiplier VVS ≥ 7V
20.4 from reference current VCSx,HS = VVS – 2.6V
IIREF = –200µA
IIREF, IMUL=50
CSx
rICS_L
47.5
50
52.5
A
20.5
Switch input comparator
threshold
CSx
VCSxth
3.6
20.6
Switch input comparator
hysteresis
CSx
VCSxhyst
200
300
4.4
V
A
500
mV
A
Current source rising
20.7
voltage slope
VVS = 14V
IIREF = 100µA
RCSx = 1k
25% to 90%
CSx
dUCSx,rise
0.7
8
V/µs
C
Current source falling
20.8
voltage slope
VVS = 14V
IIREF = 100µA
VCSx = 0V
90% to 25%
CSx
dUCSx,fall
0.7
8
V/µs
C
Current source rising
20.22 voltage slope, slope
control disabled
VVS = 14V
IIREF = 10µA
RCSx = 1k
25% to 90%
CSSCD = 1
CSx
dUCSx0,risefast
6.5
22
V/µs
C
Current source falling
20.23 voltage slope, slope
control disabled
VVS = 14V
IIREF = 100µA
VCSx = 0V
90% to 25%
CSSCD = 1
CSx
dUCSx,fallfast
6.5
30
V/µs
C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA664151 [DATASHEET]
9268I–AUTO–04/15
39
15.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
Parameters
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VVS ≥ 7V
Output voltage on IREF 10µA ≤ IIREF ≤ 250µA
20.9
pin
At least one current source
active
IREF
VIREF
1.19
1.23
1.27
V
A
Internally generated
IREF fail-safe current in VIREF = 0V
20.10
case of open or shorted IIREF = 0µA
IREF pin
IREF
IIREFfs
60
60
140
140
µA
A
Time from voltage level
Switch input debouncing change on pin CSx to
20.11
signal state change visible
time
in SPI register
CSx
tCSxdeb
2
13
µs
B
Current source and voltage
divider off
VCSx = 0 V
VCSx = VVS
CSx
ICSx,leak
–3
µA
A
VVS = 14V
V
= 0V(H)/VCSx = 14V(L)
Current source enabling CSx
20.13
IIREF = 100µA
time
Test time until
abs(ICSx) ≥ 9.5mA
CSx
tCSxon
3
10
µs
A
CSx
tCSx,off
3
12
µs
A
150
k
A
+3
%
A
Switch input leakage
20.12
current
Test Conditions
+3
20.14
Current source
shutdown time
VVS = 14V
VCSx = 0V(H)/VCSx = 14V(L)
IIREF = 100µA
Test time until
abs(ICSx) ≤ 0.5mA
20.15
Voltage divider
resistance
VCSx = 4V
CSx
RCSxdiv
50
20.16 Voltage divider precision VCSx = 4V
CSx
pCSxdiv
–3
CSx
fCSx,max
20
kHz
D
0.33
VVCC
A
95
20.17
Maximum current source
switching frequency
20.18
Maximum voltage level
for logic “low”
PWM1..3
VPWML,max
20.19
Minimum voltage-level
for logic “high”
PWM1..3
VPWMH,min
0.66
VVCC
A
20.20
PWM input leakage
current, low level
VPWMy = 0
PWM1..3
IPWMleakL
–1
µA
A
20.21
PWM input pull-down
resistor value
VPWMy = VVCC
PWM1..3
RPWM
60
k
A
100
220
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
40
ATA664151 [DATASHEET]
9268I–AUTO–04/15
15.
Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C, chip configuration as default, unless otherwise specified. All values refer to GND pins
No.
Parameters
Test Conditions
21
Serial Programming Interface and Control Logic (SPI)
fSPI = 1/TSCK
C_MISO ≤ 140pF (external)
Pin
Symbol
Max.
Unit
Type*
SCK
fSPI,max
4
MHz
D
0.33 x
VVCC
V
A
V
A
+1
+1
+1
µA
A
200
k
A
0.4
V
A
V
A
+1
µA
A
21.1
Maximum input clock
frequency
21.2
Maximum input signal
low level threshold
MOSI
SCK
NCS
VSPIL,max
21.3
Minimum input signal
high level threshold
MOSI
SCK
NCS
VSPIH,min
VMOSI = VSCK = VNCS = VVCC
21.4 Input pin leakage current
VMOSI = VSCK = 0
21.5 NCS pin pull-up resistor VNCS = 0; VVCC = 5V
Min.
Typ.
0.66 x
VVCC
MOSI
SCK
NCS
MOSI
SCK
ILeak,H
ILeakL
–1
–1
NCS
RNCS
60
MISO
VMISOsink
120
21.6
Output low level sink
capability
21.7
Output high level source
IMISO = –2mA
capability
MISO
VMISOsource
VVCC –
0.4
21.8
MISO pin tristate input
leakage current
MISO
IMISOleak
–1
Chip select minimum
21.9 setup time (-> earliest
time to start clocking)
NCS
tSPIsetup,min
250
ns
D
Chip select minimum
hold time (-> earliest
21.10
time after clocking to
release chip select)
NCS
tSPIhold,min
250
ns
D
Minimum SPI data
evaluation time
(-> minimum time
21.11
between positive and
negative edge of chip
select)
NCS
tSPIeval,min
8
14
µs
D
21.12 Interrupt triggering delay
NIRQ
tNIRQtrig
2
7
µs
B
tSCK_H/TSCK
SCK
dSCK
0.4
0.6
C_MISO ≤ 140pF (external)
SCK
MISO
tCLK2DATA
10
120
21.13
SPI clock duty cycle
limits
Propagation delay from
21.14 SPI clock to MISO data
output
IMISO = 2mA
VNCS = VVCC
VMISO = VVCC/2
D
ns
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
ATA664151 [DATASHEET]
9268I–AUTO–04/15
41
16.
Application Information
Figure 16-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
(Transceiver supply
of transmitting node)
THDom(max)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(output of receiving node2)
trx_pdr(2)
42
ATA664151 [DATASHEET]
9268I–AUTO–04/15
trx_pdf(2)
Figure 16-2. Application Example 1: LIN Slave with Different External Circuitry at the CSx-pins
+
VBAT
22μF
100nF
100nF
+
2.2μF
VCC
TXD
GND
NRES
GND-LIN
Atmel
ATA664151
NIRQ
GND
10nF
220pF
51Ω
MOSI
VBATT
SCK
CL15
CS2
CS3
CS1
IREF
10kΩ
VDIV
WDOSC
PWM3
PWM2
CL15
PWM1
8
LIN
LIN
QFN32
5mm x 5mm
MISO
NCS
24
CS4
RXD
Microcontroller
CS5
CS6
CS7
CS8
VS
NTRIG
1
AGND
10kΩ 32
VCC
10kΩ
16
51kΩ
47nF
GND
VS
12kΩ
GND
10nF
VS
DEBUG(1)
(1)
Note: If the Watchdog shall be disabled directly after power-up (e.g. for
microcontroller programming or debugging purposes) the pin VDIV must
be tied to High Level until the Reset phase ends (Positive slope at pin NRES).
ATA664151 [DATASHEET]
9268I–AUTO–04/15
43
Figure 16-3. Application Example 2: LIN Slave for RGB-LED-Control
+
VBAT
22μF
R
100nF
+
100nF
G
2.2μF
B
VCC
TXD
CS5
CS6
CS7
CS8
VS
NTRIG
1
AGND
10kΩ 32
VCC
GND
RXD
NRES
GND-LIN
Atmel
ATA664151
NIRQ
GND
51Ω
MOSI
CS3
CS1
IREF
VDIV
WDOSC
PWM3
PWM2
CL15
PWM1
8
16
PWM1
PWM2
VS VS
PWM3
51kΩ
12kΩ
GND
10nF
DEBUG(1)
(1)
Note: If the Watchdog shall be disabled directly after power-up (e.g. for
microcontroller programming or debugging purposes) the pin VDIV must
be tied to High Level until the Reset phase ends (Positive slope at pin NRES).
44
ATA664151 [DATASHEET]
9268I–AUTO–04/15
220pF
VBATT
SCK
NCS
LIN
LIN
QFN32
5mm x 5mm
MISO
Microcontroller
24
CS4
CS2
10kΩ
10nF
GND
Figure 16-4. Application Example 3: LIN Slave for H-bridge Control of Small DC-motors
VBAT
P1
P2
M
51Ω
+
22μF
N1
N2
100nF
100nF
+
2.2μF
VCC
10kΩ 32
TXD
GND-LIN
Atmel
ATA664151
NIRQ
LIN
LIN
QFN32
5mm x 5mm
MISO
220pF
GND
MOSI
VBATT
SCK
10nF
CS2
CS3
CS1
IREF
VDIV
WDOSC
PWM3
PWM2
CL15
PWM1
NCS
Shunt
VS
GND
NRES
8
24
CS4
RXD
Microcontroller
(opt)
CS5
CS6
CS7
VS
CS8
1
AGND
Vsh
NTRIG
VCC
10kΩ
VS
16
51kΩ
GND
5.6kΩ
10nF
GND
Vsh
DEBUG(1)
(1)
Note: If the Watchdog shall be disabled directly after power-up (e.g. for
microcontroller programming or debugging purposes) the pin VDIV must
be tied to High Level until the Reset phase ends (Positive slope at pin NRES).
ATA664151 [DATASHEET]
9268I–AUTO–04/15
45
Figure 16-5. Application Example 4: LIN Slave Relay Driver
VBAT
M
+
22μF
100nF
100nF
+
51Ω
2.2μF
VCC
TXD
GND
NRES
GND-LIN
Atmel
ATA664151
NIRQ
LIN
LIN
QFN32
5mm x 5mm
MISO
VBATT
SCK
10nF
CS2
CS3
CS1
IREF
VDIV
WDOSC
PWM3
PWM2
CL15
PWM1
NCS
220pF
GND
MOSI
8
24
CS4
RXD
Microcontroller
CS5
CS6
CS7
CS8
VS
NTRIG
1
AGND
10kΩ 32
VCC
10kΩ
16
51kΩ
5.6kΩ
10nF
GND
DEBUG(1)
(1)
Note: If the Watchdog shall be disabled directly after power-up (e.g. for
microcontroller programming or debugging purposes) the pin VDIV must
be tied to High Level until the Reset phase ends (Positive slope at pin NRES).
46
ATA664151 [DATASHEET]
9268I–AUTO–04/15
GND
Extended Type Number
Package
ATA664151-WNQW-1
QFN32 5x5mm
Remarks
VCC = 5V, Voltage Divider, VVCCuv = 2.9V, 6k
Package Information
Top View
D
32
1
E
technical drawings
according to DIN
specifications
PIN 1 ID
Dimensions in mm
8
A
Side View
A3
A1
Two Step Singulation process
Partially Plated Surface
Bottom View
D2
9
16
17
8
COMMON DIMENSIONS
(Unit of Measure = mm)
E2
18.
Ordering Information
1
SYMBOL
MIN
NOM
MAX
A
0.8
0.85
0.9
A1
A3
0
0.16
0.035
0.21
0.05
0.26
24
32
Z
25
e
Z 10:1
L
17.
D
4.9
5
5.1
D2
3.5
3.6
3.7
5.1
E
4.9
5
E2
3.5
3.6
3.7
L
0.35
0.4
0.45
b
0.2
0.25
0.3
e
NOTE
0.5
b
10/18/13
TITLE
Package Drawing Contact:
[email protected]
Package: VQFN_5x5_32L
Exposed pad 3.6x3.6
GPC
DRAWING NO.
REV.
6.543-5124.03-4
1
ATA664151 [DATASHEET]
9268I–AUTO–04/15
47
19.
Errata
19.1
Atmel ATA664151
1.
The current sources, pins CS1 to CS8, may show unexpected behavior when not initialized correctly thus resulting
in small amounts of current to be provided.
Problem Fix/Workaround
The current sources can be brought into a defined status by disabling the Slope control for the CS-Ports when initializing the device. This can be achieved using the SPI bit CSSCD. The slope control can be turned off 10µs after it was
enabled.
48
ATA664151 [DATASHEET]
9268I–AUTO–04/15
20.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
 Number 17.11 in Section 15 “Electrical Characteristics” on page 38 updated
9268I-AUTO-04/15
 Section 17 “Ordering Information” on page 47 updated
9268H-AUTO-08/14
 Put datasheet in the latest template
9268G-AUTO-12/13
 Section 13 “Absolute Maximum Ratings” on pages 31 to 32 updated
 Section 18 “Package Information” on page 47 updated
 Section 13 “Absolute Maximum Ratings” on pages 31 to 32 updated
9268F-AUTO-07/13
 Section 14 “Thermal Characteristics” on page 32 updated
 Section 15 “Electrical Characteristics” numbers 3.3, 5.3, 14.3, 20.3, 20.4 and 20.16 on pages
33 to 41 updated
 Section 10.1 “Typical Timing Sequence with RWD_OSC = 51k” on page 28 updated
 Section 10.2 “Worst Case Calculation with RWD_OSC = 51k” on page 29 updated
9268E-AUTO-07/13
 Section 15 “Electrical Characteristics” numbers 1.7, 1.8, 1.9, 4.3, 11.6, 13.1, 13.2, 13.3, 17.12,
18.3, 20.11, 20.13, 20.14, and 21.5 on pages 33 to 41 updated
 Section 19 “Errata” on page 48 added
 Section 3.12 “NTRIG Input Pin” on page 6 updated
9268D-AUTO-11/12
 Section 3.13 “VBATT Input Pin” on page 6 updated
 Section 3.16 “CS1 to CS8 High-voltage Input/Output Pins” on page 7 updated
9268C-AUTO-09/12
9268B-AUTO-05/12
 ATA664131 and ATA664154 removed
 Section 17 “Ordering Information” on page 47 updated
 Section 15 “Electrical Characteristics” numbers 20.7, 20.8, 20.22 and 20.23 on page 40
updated
ATA664151 [DATASHEET]
9268I–AUTO–04/15
49
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