ATF1504BE - Complete

Features
• High-performance Fully CMOS, Electrically-erasable Complex Programmable
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Logic Device
– 64 Macrocells
– 5.0 ns Pin-to-pin Propagation Delay
– Registered Operation up to 333 MHz
– Enhanced Routing Resources
– Optimized for 1.8V Operation
– 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V
– SSTL2 and SSTL3 I/O Standards
In-System Programming (ISP) Supported
– ISP Using IEEE 1532 (JTAG) Interface
– IEEE 1149.1 JTAG Boundary Scan Test
Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– 5 Product Terms per Macrocell, Expandable up to 40
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate with Low Output Drive
– Programmable Open Collector Output Option
– Maximum Logic Utilization by Burying a Register with a Combinatorial Output and
Vice Versa
Fully Green (RoHS Compliant)
10 µA Standby Current
Power Saving Option During Operation Using PD1 and PD2 Pins
Programmable Pin-keeper Option on Inputs and I/Os
Programmable Schmitt Trigger Option on Input and I/O Pins
Programmable Input and I/O Pull-up Option
Unused I/O Pins Can Be Configured as Ground (Optional)
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead and 100-lead TQFP
Advanced Digital CMOS Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
Security Fuse Feature
Hot-Socketing Supported
Highperformance
CPLD
ATF1504BE
3637B–PLD–1/08
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Outputs Can Be Configured for High or Low Drive
Combinatorial Output with Registered Feedback and Vice Versa within each Macrocell
Three Global Clock Pins
Fast Registered Input from Product Term
Pull-up Option on TMS and TDI JTAG Pins
OTF (On-the-Fly) Reconfiguration Mode
DRA (Direct Reconfiguration Access)
1. Description
The ATF1504BE is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic
PLDs. The ATF1504BE’s enhanced routing switch matrices increase usable gate count and the
odds of successful pin-locked design modifications.
The ATF1504BE has up to 64 bi-directional I/O pins and four dedicated input pins. Each dedicated input pin can also serve as a global control signal, register clock, register reset or output
enable. Each of these control signals can be selected for use individually within each macrocell.
Figures 1-1 and 1-2 show the pin assignments for the 100-lead and 44-lead TQFP packages
respectively.
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ATF1504BE
100-lead TQFP Top View
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIOB
I/O
I/O
I/O
NC
NC
I/O
Figure 1-1.
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
GND
I/O/TDO
NC
I/O
NC
I/O
I/O
I/O
VCCIOB
I/O
I/O
I/O
I/O/TCK
I/O
I/O/VREFB
GND
I/O
I/O
I/O
NC
I/O
NC
I/O
VCCIOB
GND
NC
NC
I/O
I/O
I/O
I/O
I/O
VCCIOA
I/O
I/O
I/O
GND
VCCINT
I/O
I/O
I/O/PD2
GND
I/O
I/O
I/O
I/O
I/O
NC
NC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
VCCIOA
I/O/TDI
NC
I/O
NC
I/O
I/O
I/O
GND
VREFA/I/O/PD1
I/O
I/O
I/O/TMS
I/O
I/O
VCCIOA
I/O
I/O
I/O
NC
I/O
NC
I/O
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3637B–PLD–1/08
44-lead TQFP Top View
44
43
42
41
40
39
38
37
36
35
34
I/O
I/O
I/O
VCCINT
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
Figure 1-2.
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
I/O
I/O/TDO
I/O
I/O
VCCIOB
I/O
I/O
I/O/TCK
I/O/VREFB
GND
I/O
I/O
I/O
I/O
I/O
GND
VCCINT
I/O
PD2/I/O
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
I/O/TDI
I/O
I/O
GND
VREFA/PD1/I/O
I/O
TMS/I/O
I/O
VCCIOA
I/O
I/O
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ATF1504BE
3637B–PLD–1/08
ATF1504BE
Figure 1-3.
Block Diagram
8 or 16
8 or 16
I/O (MC64)/GCLK3
Each of the 64 macrocells generates a buried feedback signal that goes to the global bus (see
Figure 1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a
foldback logic term that goes to a regional bus. Cascade logic between macrocells in the
ATF1504BE allows fast, efficient generation of complex logic functions. The ATF1504BE contains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40
product terms.
The ATF1504BE macrocell, shown in Figure 1-4, is highly flexible and capable of supporting
complex logic functions operating at high speed. The macrocell consists of five sections: product
terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select
and enable, and logic array inputs.
A security fuse, when programmed, protects the contents of the ATF1504BE. Two bytes
(16 bits) of User Electronic Signature are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Electronic Signature is accessible regardless of the state of the security fuse.
The ATF1504BE device supports In-System Programming (ISP) via the industry-standard 4-pin
JTAG interface (IEEE 1532 standard), and is fully compliant with IEEE 1149.1 for Boundary
Scan Test. ISP allows the device to be programmed without removing it from the printed circuit
board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to
be made in the field via software.
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3637B–PLD–1/08
Figure 1-4.
ATF1504BE Macrocell
BURIED FEEDBACK
SCHMITT
TRIGGER
1.1
SSTL
Product Terms and Select Mux
Each ATF1504BE macrocell has five product terms. Each product term receives as its inputs all
signals from the switch matrix and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX configuration is determined by the design
compiler, which selects the optimum macrocell configuration.
1.2
OR/XOR/CASCADE Logic
The ATF1504BE’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR
sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to
as many as 40 product terms with minimal additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms.
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ATF1504BE
1.3
Flip-flop
The ATF1504BE’s flip-flop has very flexible data and control functions. The data input can come
from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the
separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D,
T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this
mode, data passes through when the clock is high and is latched when the clock is low.
The clock itself can be any one of the Global CLK signals (GCK[0 : 2]) or an individual product
term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the
clock, one of the macrocell product terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The
asynchronous preset (AP) can be a product term or always off.
1.4
Extra Feedback
The ATF1504BE macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the
output is combinatorial or registered. (This enhancement function is automatically implemented
by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second
latch within a macrocell.
1.5
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or bi-directional pin. The output enable for each macrocell
can be selected from the true or complement of the two output enable pins, a subset of the I/O
pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software
when the I/O is configured as an input or bi-directional pin.
1.6
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 64 macrocells. The switch matrix in each logic block receives as its inputs all signals from the
global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
1.7
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to all 16 macrocells within the logic block. The foldback is an inverse polarity of one
of the macrocell’s product terms. The 16 foldback terms in each logic block allow generation of
high fan-in sum terms or other complex logic functions with little additional delay.
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3637B–PLD–1/08
2. Input and I/O Pins
2.1
Programmable Pin-keeper Option for Inputs and I/Os
The ATF1504BE offers the option of individually programming each of its input or I/O pin so that
pin-keeper circuit can be utilized. When any pin is driven high or low and then subsequently left
floating, it will stay at that previous high or low level. This circuitry prevents undriven input and
I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors
and eliminate their DC power consumption.
Figure 2-1 shows the pin-keeper circuit for an Input Pin and Figure 2-2 shows the same for an
I/O pin. The pin-keeper circuit is a weak feedback latch and has an effective resistance that is
approximately 50 kΩ.
Figure 2-1.
Input with Programmable Pin-keeper
VCCINT
50K
Figure 2-2.
I/O with Programmable Pin-keeper
VCCIO
VCCINT
50K
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ATF1504BE
3637B–PLD–1/08
ATF1504BE
2.2
Schmitt Trigger
The Input Buffer of each input and I/O pin has an optional schmitt trigger setting. The schmitt
trigger option can be used to buffer inputs with slow rise times.
2.3
Output Drive Capability
Each output has a high/low drive option. The low drive option (slow slew rate) can be used to
reduce system noise by slowing down outputs that do not need to operate at maximum speed or
drive strength. Outputs default to high drive strength by Atmel software and can be set to low
drive strength through the slew rate option.
2.4
I/O Bank
The I/O pins of the ATF1504BE are grouped into two banks, Bank A and Bank B. Bank A comprises of I/O pins for macrocells 1 to 32 (Logic Block A and B), and it is powered by VCCIOA. Bank
B comprises of I/O pins for macrocells 33 to 64 (Logic Block C and D), and it is powered by
VCCIOB.
2.5
I/O Standard
The ATF1504BE supports a wide range of I/O standards which include LVTTL, LVCMOS33,
LVCMOS25, LVCMOS18 and LVCMOS15. The I/O pins of the ATF1504BE can also be individually configured to support SSTL-2 (Class I) and SSTL-3 (Class I) advanced I/O standards.
This and the two I/O banks, together, allow the ATF1504BE to be used for voltage level
translation.
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3637B–PLD–1/08
3. Power Management
Unlike conventional CPLDs with sense amplifiers, the ATF1504BE is designed using low-power
full CMOS design techniques. This enables the ATF1504BE to achieve extremely low power
consumption over the full operating frequency spectrum.
The ATF1504BE also has an optional power-down mode. In this mode, current drops to below
100 µA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used
to power down the part. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins.
4. Security Feature
A fuse is provided to prevent unauthorized copying of the ATF1504BE fuse patterns. Once
enabled, fuse reading or verification is inhibited. However, the 16-bit User Electronic Signature
remains accessible. To reset this feature, the entire memory array in the device must be erased.
5. Programming Methods
The ATF1504BE devices are In-System Programmable (ISP) or In-System Configurable (ISC)
devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally
required for programming and facilitates rapid design iterations and field changes.
When using the ISP hardware or software to program the ATF1504BE devices, four I/O pins
must be reserved for the JTAG interface. However, the logic features that the macrocells have
associated with these I/O pins are still available to the design for buried logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector
Format (SVF) files can be created by Atmel-provided software utilities. ATF1504BE devices can
also be programmed using standard third-party programmers. With a third-party programmer,
the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic.
The AT1504BE device supports several configuration modes which gives designers several
unique options for programming.
The different modes of programming are:
• ISC – In-System Configuration
• OTF – On-the-Fly Reconfiguration
• DRA – Direct Reconfiguration Access
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ATF1504BE
5.1
In-System Configuration – ISC (Also Referred to as ISP)
This mode is the de-facto standard used to program the CPLD when it is attached to a PCB. The
term ISC can also be used interchangeably with ISP (In-system Programming). ISC or ISP eliminates the need for an external device programmer, and the devices can be soldered to a PCB
without being preprogrammed.
In the ISC mode, the logic operation of the ATF1504BE is halted and the embedded configuration memory is programmed. The device is programmed by first erasing the configuration
memory in the CPLD and then loading the new configuration data into the memory, which in-turn
configures the PLD for functional mode. When the device is in the ISC programming mode, all
user I/Os are held in the high impedance state.
The ISC mode is best suited for working with the ATF1504BE device in a design development or
production environment. Configuration of the ATF1504BE device done via a Download Cable
(see Figure 5-1 on page 11) is the default mode used to program the device in the ISC mode. In
this mode, the PC is typically the controlling device that communicates with the CPLD.
Figure 5-1.
Configuration of ATF1504BE Device Using a Download Cable
ATF1504BE
CPLD Device
TCK
Connect
ISP Download
Cable to 10-pin
JTAG Header
VCC
TDO
TMS
TDI
1
2
3
4
5
6
7
8
9
10
JTAG
Connector
5.2
On-the-Fly Reconfiguration – OTF
In this mode, the CPLD design pattern stored in the internal configuration memory can be modified while the previously-programmed design pattern is operating with minimal disturbance to
the programming operation of the new design. The new configuration will take affect after the
OTF programming process is completed and the OTF mode is exited.
The configuration data for any design is stored in the internal configuration memory. Once the
configuration data is transferred to the internal static registers of the CPLD, the CPLD operates
with the design pattern and the configuration memory is free to be re-loaded with a new set of
configuration data. The design pattern due to the new configuration content is activated through
an initialization cycle that occurs on exiting the OTF mode or after the next power up sequence.
Figure 5-2 shows the electrical interface for configuration of the ATF1504BE device in the OTF
mode. The processor is the controlling device that communicates with the CPLD and uses configuration data stored in the external memory to configure the CPLD.
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3637B–PLD–1/08
Figure 5-2.
Configuration of ATF1504BE Device Using a Processor and Memory
ATF1504BE
CPLD Device
TCK
TDO
Processor
TMS
TDI
Serial Data
Data
Address
Memory
5.3
Direct Reconfiguration Access – DRA
This reconfiguration mode allows the user to directly modify the internal static registers of the
CPLD without affecting the configuration data stored in the embedded memory. It is more useful
in cases where immediate and temporary context change in the function of the hardware is
desired.
The embedded configuration memory in the ATF1504BE does not change when a new set of
configuration data is passed to the ATF1504BE using the DRA mode. Instead, the internal static
registers of the CPLD are directly written with the data entering the device via the JTAG port. In
other words, it's a temporary change in the function performed by the CPLD since a power
sequence results in the device being configured again by the data stored in the embedded
memory.
5.4
ISP Programming Protection
The ATF1504BE has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The I/O pins default to
high-Z state during such a condition.
All ATF1504BE devices are initially shipped in the erased state, thereby making them ready to
use for ISP.
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ATF1504BE
6. JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1504BE. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and I/O
pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller
is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1504BE’s BSC can be fully described
using a BSDL file as described in IEEE 1149.1 standard. This allows ATF1504BE testing to be
described and implemented using any one of the third-party development tools supporting this
standard.
The ATF1504BE also has the option of using the four JTAG-standard I/O pins for ISP. The
ATF1504BE is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE 1532 standard using 1.8V/2.5V/3.3V LVCMOS level
programming signals from the ISP interface for in-system programming. The JTAG feature is a
programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are
available as I/O pins.
6.1
JTAG Boundary-scan Cell (BSC) Testing
The ATF1504BE contains 64 I/O pins and four dedicated input pins. Each input pin and I/O pin
has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in
detail by IEEE 1532 standard. A typical BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one
for the macrocells. The BSCs in the device are chained together through the capture registers.
Input to the capture register chain is fed in from the TDI pin while the output is directed to the
TDO pin. Capture registers are used to capture active device data signals, to shift data in and
out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and
macrocells is shown below.
Figure 6-1.
Note:
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
The ATF1504BE has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
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3637B–PLD–1/08
Figure 6-2.
BSC Configuration for Macrocell
TDO
0
Q D
1
TDI
CLOCK
TDO
OEJ
0
0
1
D Q
D Q
1
OUTJ
0
0
Pin
1
D Q
D Q
Capture
DR
Update
DR
1
Mode
TDI
Shift
Clock
BSC for I/O Pins and Macrocells
7. Design Software Support
ATF1504BE designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high-level description languages such as VHDL® and Verilog®. Third
party synthesis and simulation tools from Mentor Graphics® are integrated into Atmel’s software
tools.
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ATF1504BE
8. Electrical Specifications
Table 8-1.
Absolute Maximum Ratings*
*NOTICE:
Operating Temperature................................... -40° C to +85° C
Storage Temperature .................................... -65° C to +150° C
Supply Voltage (VCCINT) .....................................-0.5V to +2.5V
Supply Voltage for Output Drivers (VCCIO) .........-0.5V to +4.5V
Junction Temperature ................................... -55° C to +155° C
Table 8-2.
Operating Temperature Range
Operating Temperature (Ambient)
Table 8-3.
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Commercial
Industrial
0° C - 70° C
-40° C - 85° C
Pin Capacitance(1)
Typ
Max
Units
Conditions
CIN
8
10
pF
VIN = 0V; f = 1.0 MHz
CI/O
8
10
pF
VOUT = 0V; f = 1.0 MHz
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
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3637B–PLD–1/08
Table 8-4.
DC Characteristics
Symbol
Parameter
VCCINT
Condition
Min
Typ
Max
Units
Supply Voltage for internal
logic and input buffers
1.7
1.8
1.9
V
VCCIO
Supply Voltage for output
drivers at 3.3V
3.0
3.3
3.6
V
VCCIO
Supply Voltage for output
drivers at 2.5V
2.3
2.5
2.7
V
VCCIO
Supply Voltage for output
drivers at 1.8V
1.7
1.8
1.9
V
VCCIO
Supply Voltage for Output
Drivers at 1.5V
1.4
1.5
1.6
V
ICC_INT(HD)
Operating Current(1)
for VCCINT (supply voltage)
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
150
µA
ICC_IO(HD)
Operating Current(1)
for VCCIO (supply voltage for
output drivers), per LAB
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
165
µA
ICC_INT(LD)
Operating Current(1)
for VCCINT (low drive)
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
145
µA
ICC_IO(LD)
Operating Current(1)
for VCCIO (supply voltage for
output drivers), per LAB
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
60
µA
ISB
Standby Current(1)
VCCINT = 1.9V, VCCIO = 3.6V
10
µA
IIL, IIH
Input Leakage
VCCINT = 1.8V, VIN = 0V or VCCINT
±1
µA
IOZH, IOH
Output or IO Leakage
VCCINT = 1.8V, VCCIO = 3.6V,
VIN = 0V or VCCIO
±1
µA
LVCMOS 3.3V & LVTTL (HD: High Drive, LD: Low Drive)
VIL
Input Low-voltage
-0.3
0.8
V
VIH
Input High-voltage
2
3.9
V
V
Output Low-voltage
HD: IOL = 8 mA, VCCIO = 3V
0.4
VOL
LD: IOL = 1 mA, VCCIO = 3V
0.4
V
VOH
Output High-voltage
HD: IOH = -8 mA, VCCIO = 3V
VCCIO - 0.4
V
LD: IOH = -1 mA, VCCIO = 3V
VCCIO - 0.4
V
LVCMOS 2.5V
VIL
Input Low-voltage
-0.3
0.7
V
VIH
Input High-voltage
1.7
3.9
V
V
Output Low-voltage
HD: IOL = 8 mA, VCCIO = 2.3V
0.4
VOL
LD: IOL = 1 mA, VCCIO = 2.3V
0.4
V
VOH
Output High-voltage
HD: IOH = -8 mA, VCCIO = 2.3V
VCCIO - 0.4
V
LD: IOH = -1 mA, VCCIO = 2.3V
VCCIO - 0.4
V
LVCMOS 1.8V
VIL
16
Input Low-voltage
-0.3
0.35 x VCCIO
V
ATF1504BE
3637B–PLD–1/08
ATF1504BE
Table 8-4.
DC Characteristics (Continued)
Symbol
Parameter
VIH
Input High-voltage
VOL
Output Low-voltage
VOH
Output High-voltage
Condition
Min
Typ
Max
Units
3.9
V
HD: IOL = 2 mA, VCCIO = 1.7V
0.45
V
LD: IOL = 1 mA, VCCIO = 1.7V
0.2
V
1.2
HD: IOH = -2 mA, VCCIO = 1.7V
VCCIO - 0.45
V
LD: IOH = -1 mA, VCCIO = 1.7V
VCCIO - 0.45
V
LVCMOS 1.5V
VIL
Input Low-voltage
-0.3
0.35 x VCCIO
V
VIH
Input High-voltage
1.2
3.9
V
V
Output Low-voltage
HD: IOL = 2 mA, VCCIO = 1.4V
0.45
VOL
LD: IOL = 1 mA, VCCIO = 1.4V
0.2
V
VOH
Output High-voltage
Note:
HD: IOH = -2 mA, VCCIO = 1.4V
VCCIO - 0.45
V
LD: IOH = -1 mA, VCCIO = 1.4V
VCCIO - 0.45
V
1. 16-bit up/down counter used in each LAB.
Table 8-5.
Schmitt Trigger Input Threshold Voltage
VTHL
VTLH
VCCINT
Min
Max
Min
Max
1.70
0.68
0.73
1.05
1.08
1.95
0.81
0.88
1.18
1.22
Table 8-6.
SSTL2-1 DC Voltage Specifications
Symbol
Parameter
VCCIO
VREF(1)
VTT(2)
Min
Typ
Max
Units
Input Source Voltage
2.3
2.5
2.7
V
Input Reference Voltage
1.15
1.25
1.35
V
Termination Voltage
VREF - 0.05
1.25
VREF + 0.04
V
VIH
Input High Voltage
VREF + 0.45
3.9
V
VIL
Input Low Voltage
-0.3
VREF - 0.6
V
VOH
Output High Voltage
IOH = -8 mA, VCCIO = 2.3V
VOL
Output Low Voltage
IOL = 8 mA, VCCIO = 2.3V
VIH(DC)
Input High Voltage
VIL(DC)
Input Low Voltage
Notes:
Conditions
VCCIO - 0.6
V
0.54
V
VREF + 0.15
VCCIO + 0.3
V
-0.3
VREF - 0.15
V
1. Peak-to-peak noise on VREF may not exceed ±2% VREF, VREF should track the variations in VCCIO.
2. VTT of transmitting device must track VREF of receiving devices.
17
3637B–PLD–1/08
Table 8-7.
SSTL3-1 DC Voltage Specifications
Symbol
Parameter
VCCIO
VREF(1)
VTT(2)
Min
Typ
Max
Units
Input Source Voltage
3.0
3.3
3.6
V
Input Reference Voltage
1.3
1.5
1.7
V
Termination Voltage
VREF - 0.05
1.5
VREF + 0.05
V
VIH
Input High Voltage
VREF + 0.4
VCCIO + 0.3
V
VIL
Input Low Voltage
-0.3
VREF - 0.6
V
VOH
Output High Voltage
IOH = -8 mA, VCCIO = 3V
VOL
Output Low Voltage
IOL = 8 mA, VCCIO = 2.3V
VIH(DC)
Input High Voltage
VIL(DC)
Input Low Voltage
Notes:
Conditions
VCCIO - 1.1
V
0.7
V
VREF + 0.18
VCCIO + 0.3
V
-0.3
VREF - 0.18
V
1. Peak-to-peak noise on VREF may not exceed ±2% VREF, VREF should track the variations in VCCIO.
2. VTT of transmitting device must track VREF of receiving devices.
9. Timing Model
Internal Output
Enable Delay
tIOE
Input
Delay
tIN
(+tSCH)
Global Control
Delay
tGLOB
Switch
Matrix
tUIM
Logic Array
Delay
tLAD
Register
Control
Delay
tLAC tIC tEN
Foldback Term
Delay
tSEXP
Cascade Logic
Delay
tPEXP
Fast Input
Delay
tFIN
Register/
Combinatorial
Delays
tSUI
tHI
tPRE
tCLR
tRD
tCOMB
tFSUI
tFHI
Output
Delay
tOD1
(+tSSO)
tXZ
tZX1
tZX2
(+SSTL2-1_OAD)
(+SSTL3-1_OAD)
I/O
Delay
tIO
(+tSCH)
(+SSTL2-1_IAD)
(+SSTL3-1_IAD)
18
ATF1504BE
3637B–PLD–1/08
ATF1504BE
10. Output AC Test Loads
VCCIO
Device
Under Test
R1
Test Point
R2
CL
R1
R2
CL
LVTTL
350 Ohm
350 Ohm
35 pF
LVCMOS33
300 Ohm
300 Ohm
35 pF
LVCMOS25
200 Ohm
200 Ohm
35 pF
LVCMOS18
150 Ohm
150 Ohm
35 pF
Note:
CL includes test fixtures and probe capacitance.
19
3637B–PLD–1/08
11. AC Characteristics
Table 11-1.
AC Characteristics (1)
-5
Symbol
Parameter
tPD1_INP
Delay for Single Input to Non-registered Output
tPD1
Input or Feedback to Non-registered Output
tPD2
Input or Feedback to Non-registered Feedback
tSU
Global Clock Setup Time
2.2
2.8
ns
tH
Global Clock Hold Time
0
0
ns
tFSU
Global Clock Setup Time of Fast Input
1
2
ns
tFH
Global Clock Hold Time of Fast Input
0.5
0.75
ns
tCOP
Global Clock to Output Delay
tCH
Global Clock High Time
1.25
2
ns
tCL
Global Clock Low Time
1.25
2
ns
tASU
Array Clock Setup Time
1.7
2.2
ns
tAH
Array Clock Hold Time
0.50
0.60
ns
tACOP
Array Clock to Output Delay
tACH
Array Clock High Time
1.75
2.5
ns
tACL
Array Clock Low Time
1.75
2.5
ns
tCNT
Minimum Global Clock Period
fCNT
Maximum Internal Global Clock Frequency
tACNT
Minimum Array Clock Period
fACNT
Maximum Internal Array Clock Frequency
fMAX_EXT_SYNC
Maximum External Frequency
VCCIO = 3.3V
122
103
MHz
fMAX_EXT_ASYNC
Maximum External Frequency
VCCIO = 3.3V
122
103
MHz
tIN
Input Pad and Buffer Delay
0.7
0.9
ns
tIO
I/O Input Pad and Buffer Delay
0.7
0.9
ns
tFIN
Fast Input Delay
1
1
ns
tSEXP
Foldback Term Delay
2
3
ns
tPEXP
Cascade Logic Delay
0.5
1.0
ns
tLAD
Logic Array Delay
1.8
1.8
ns
tLAC
Logic Control Delay
1.5
2
ns
tIOE
Internal Output Enable Delay
2
2
ns
tOD1
Output Buffer Delay (HD)
(High Drive; CL = 35 pF)
4.5
4.0
3.5
2.8
4.5
4.0
3.5
2.8
ns
20
Min
-7
Max
Min
Max
Units
5.0
6
ns
7
7.5
ns
4.2
4.7
ns
6
6.9
6.5
7.5
3
333
4.75
210
4
250
VCCIO = 1.5V
VCCIO = 1.8V
VCCIO = 2.5V
VCCIO = 3.3V
ns
ns
ns
MHz
5.5
181
ns
MHz
ATF1504BE
3637B–PLD–1/08
ATF1504BE
Table 11-1.
AC Characteristics (Continued)(1)
-5
Symbol
Parameter
tZX1
Output Buffer Enable Delay
(High Drive; CL = 35 pF)
VCCIO = 1.5V
VCCIO = 1.8V
VCCIO = 2.5V
VCCIO = 3.3V
tZX2
Output Buffer Enable Delay
(Low Drive; CL = 35 pF)
VCCIO = 1.5V
VCCIO = 1.8V
VCCIO = 2.5V
VCCIO = 3.3V
tXZ
Output Buffer Disable Delay (CL = 5 pF)
tSUI
Register Setup Time
1.7
2.2
ns
tHI
Register Hold Time
0.5
0.6
ns
tFSUI
Register Setup Time of Fast Input
0.5
0.6
ns
tFHI
Register Hold Time of Fast Input
0.5
0.6
ns
tRD
Register Delay
0.7
1.2
ns
tCOMB
Combinatorial Delay
1.2
1.2
ns
tIC
Array Clock Delay
1.8
1.8
ns
tEN
Register Enable Time
2.5
3
ns
tGLOB
Global Control Delay
1.8
2
ns
tPRE
Register Preset Time
1.75
2
ns
tCLR
Register Clear Time
1.75
2
ns
tUIM
Switch Matrix Delay
0.5
0.8
ns
tSCH
Schmitt Trigger Added Delay
1.5
2
ns
tSSO
Output Added Delay for VCCIO Level
(LD)
VCCIO = 1.5V
VCCIO = 1.8V
VCCIO = 2.5V
VCCIO = 3.3V
6.5
5.5
5.25
5
8.5
7.5
7.25
7
ns
SSTL2-1_IAD(2)
SSTL3-1_IAD(2)
SSTL Input Delay Adder (HD)
VCCIO = 2.5V
VCCIO = 3.3V
1.5
1.5
1.5
1.5
ns
SSTL2-1_OAD(2)
SSTL3-1_OAD(2)
SSTL Output Delay Adder (HD)
VCCIO = 2.5V
VCCIO = 3.3V
1
1
1
1
ns
Note:
Min
-7
Max
Min
Max
Units
5.0
4.5
3.5
3.0
6.0
5.5
4.5
4.0
ns
6.0
5.5
4.5
4.0
7.0
6.5
5.5
5.0
ns
4
4
ns
1. See ordering information for valid part numbers.
2. SSTL is not supported for low drive output (LD).
21
3637B–PLD–1/08
12. Power-down Mode
The ATF1504BE includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 100 µA. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all
input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
ensure that pins do not float to indeterminate levels, further reducing system power. The powerdown pin feature is enabled in the logic design file or through Atmel software. Designs using the
power-down pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
Table 12-1.
Power-down AC Characteristics(1)(2)
-5/-7
Symbol
Parameter
Min
tIVDH
Valid I, I/O before PD High
10
ns
(2)
Max
Units
Valid OE
before PD High
10
ns
tCVDH
Valid Clock
(2)
10
ns
tDHIX
I, I/O Don’t Care after PD High
tGVDH
tDHGX
before PD High
5
ns
Don’t Care after PD High
5
ns
(2)
5
ns
(2)
OE
tDHCX
Clock
Don’t Care after PD High
tDLIV
PD Low to Valid I, I/O
2
µs
tDLGV
PD Low to Valid OE (Pin or Term)
2
µs
tDLCV
PD Low to Valid Clock (Pin or Term)
2
µs
tDLOV
PD Low to Valid Output
2
µs
Notes:
1. For low-drive outputs, add tSSO.
2. Pin or product term.
22
ATF1504BE
3637B–PLD–1/08
ATF1504BE
13. ATF1504BE Dedicated Pinouts
Table 13-1.
ATF1504BE Dedicated Pinouts
44-lead
TQFP
100-lead
TQFP
INPUT / OE2 / GCLK2
40
90
INPUT / GCLR
39
89
INPUT / OE1
38
88
INPUT / GCLK1
37
87
I/O / GCLK3
35
85
I/O / PD1 / VREFA
5
12
I/O / PD2
19
42
I/O / VREFB
25
60
I/O / TDI (JTAG)
1
4
I/O / TMS (JTAG)
7
15
I/O / TCK (JTAG)
26
62
I/O / TDO (JTAG)
32
73
GND
4, 16, 24, 36
11, 26, 38, 43, 59, 74, 86, 95
VCCINT
17, 41
39, 91
VCCIOA
9
3, 18, 34
VCCIOB
29
51, 66, 82
-
1, 2, 5, 7, 22, 24, 27, 28, 49,
50, 53, 55, 70, 72, 77, 78
# of Signal Pins
36
68
# User I/O Pins
32
64
Dedicated Pin
N/C
OE (1, 2)
Global OE pins
GCLR
Global Clear pin
GCLK (1, 2, 3)
Global Clock pins
PD (1, 2)
Power-down pins
TDI, TMS, TCK, TDO
JTAG pins used for boundary-scan testing or in-system
programming
GND
Ground pins
VCCINT
VCC pins for the device (+1.8V)
VCCIOA
LAB A and B – VCC supply pins for I/Os (1.5V, 1.8V, 2.5V, or
3.3V)
VCCIOB
LAB C and D – VCC supply pins for I/Os (1.5V, 1.8V, 2.5V, or
3.3V)
VREFA
Reference voltage pin for SSTL inputs in banks A and B
VREFB
Reference voltage pin for SSTL inputs in banks C and D
23
3637B–PLD–1/08
Table 13-2.
MC
Logic
Block
44-lead
TQFP
100-lead
TQFP
1
A
6
14
2
A
-
13
3/
PD1/
VREFA
A
5
12
4
A
3
5
A
6
A
Logic
Block
44-lead
TQFP
33
C
18
40
34
C
-
41
35/
PD2
C
19
42
10
36
C
20
44
2
9
37
C
21
45
-
8
38
C
-
46
MC
100-lead
TQFP
7
A
-
6
39
C
-
47
8/
TDI
A
1
4
40
C
22
48
9
A
-
100
41
C
23
52
10
A
-
99
42
C
-
54
11
A
44
98
43
C
-
56
12
A
-
97
44
C
-
57
13
A
-
96
45
C
-
58
14
A
43
94
46/
VREFB
C
25
60
15
A
-
93
47
C
-
61
C
26
62
27
63
16
A
42
92
48/
TCK
17
B
15
37
49
D
18
B
-
36
50
D
-
64
19
B
14
35
51
D
28
65
20
B
13
33
52
D
30
67
21
B
12
32
53
D
31
68
22
B
-
31
54
D
-
69
23
B
-
30
55
D
-
71
24
B
11
29
56/
TDO
D
32
73
25
B
10
25
57
D
33
75
26
B
-
23
58
D
-
76
27
B
-
21
59
D
-
79
28
B
-
20
60
D
-
80
29
B
-
19
61
D
-
81
30
B
8
17
62
D
34
83
31
B
-
16
63
D
-
84
15
64/
GCLK3
D
35
85
32/
TMS
24
ATF1504BE I/O Pinouts
B
7
ATF1504BE
3637B–PLD–1/08
ATF1504BE
14. Typical DC and AC Characteristic Graphs
Icc_int,Icc_io @ Vccint=1.8V (HD) over frequency
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
icc_int_vccio_3.3V
Icc (ua)
Icc (mA)
icc_io_vccio_2.5V
icc_io_vccio_3.3V
icc_io_vccio_1.8V
80
100
40
30
25
20
13.3
5
10
2.5
1.25
1
icc_io_vccio_1.5V
Icc_Int, Icc_io @ Vccint=1.8V (HD) over
frequency
900
850
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
icc_int_vccio_3.3V
icc_io_vccio_1.8V
icc_io_vccio_2.5V
icc_io_vccio_3.3v
icc_io_vccio_1.5V
0.1
0.2
FREQUENCY (MHZ)
0.5
1
1.25
2.5
5
FREQUENCY (MHZ)
Icc_int, Icc_io(LD) Vs Frequency Per Lab
Icc_int, Icc_io Vs frequency (LD) per Lab
650
12
600
550
10
450
icc_int_Vccio_3.3V
400
icc_io_Vccio_1.5V
350
icc_io_Vccio_1.8V
300
icc_io_Vccio_2.5V
250
icc_io_Vccio_3.3V
200
ICC_IO (mA)
ICC (uA)
500
150
icc_io_vccio_1.5V
8
icc_io_Vccio_1.8V
icc_io_Vccio_2.5V
6
icc_io_Vccio_3.3V
4
icc_int_Vccio_3.3V
2
100
50
0
0.1 0.2
0.5
1
5
5
10 13.3 20
25
30
40
80
100
3.2
3.0
2.8
2.6
2.4
2.2
2.0
0.6
0.4
160
0.2
OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE
(VCCINT = 1.8V, VCCIO = 1.5-3.3V, TA = 25C), High Drive
0.0
OUTPUT SINK CURRENT(IOL) VS. OUTPUT VOLTAGE
(VCCINT = 1.8V, VCCIO = 1.5-3.3V, TA = 25C), High Drive
0
-20
120
1.5V
1.8V
80
2.5V
3.3V
-40
IOH ( mA )
IOL ( mA )
1.25 2.5
FREQUENCY (MHZ)
FREQUENCY (MHZ)
1.8
2.5
1.6
1.25
1.4
1
1.2
0.5
1.0
0.2
0.8
0
0.1
1.5V
1.8V
-60
2.5V
3.3V
-80
40
-100
OUTPUT VOLTAGE ( V )
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
-120
OUTPUT VOLTAGE ( V )
25
3637B–PLD–1/08
OUTPUT SINK CURRENT(IOL) VS. OUTPUT VOLTAGE
(VCCINT = 1.8V, VCCIO = 1.5-3.3V, TA = 25C), Low Drive
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
25
0.2
0.0
OUTPUT SOURCE CURRENT(IOH) VS. OUTPUT VOLTAGE
(VCCINT = 1.8V, VCCIO =1.5-3.3V, TA = 25C), Low Drive
0
20
1.8V
2.5V
10
3.3V
IOH ( mA )
IOL ( mA )
-5
1.5V
15
1.5V
-10
1.8V
2.5V
-15
3.3V
5
-20
-25
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
OUTPUT VOLTAGE ( V )
OUTPUT VOLTAGE ( V )
INPUT & I/O CURRENT VS. INPUT VOLTAGE
VCCINT = 1.8V, VCCIO = 1.8V (TA = 25°C)
(Pull-Up On)
INPUT CURRENT VS. INPUT VOLTAGE
INPUT PIN (VCCINT = 1.8V, TA = 25C)
(PIN-KEEPER ON)
0.0
80
-5.0
INPUT CURRENTN (µA)
INPUT CURRENT ( uA )
60
40
20
0
-20
-10.0
-15.0
-20.0
-25.0
-30.0
-35.0
-40.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-40
0
0.5
1
INPUT VOLTAGE ( V )
1.5
1.8
INPUT VOLTAGE (V)
TPD VS. # MC SWITCHING
(VCCINT = 1.8V, VCCIO = 1.5-3.3V, TA = 25C)
I/O PIN CURRENT VS. I/O PIN VOLTAGE
I/O PIN (VCCINT = 1.8V, VCCIO = 1.5V-3.3V, TA = 25C)
(PIN KEEPER ON)
7.2
7.0
200
6.8
6.6
1.5V
50
1.8V
2.5V
0
3.3V
-50
6.2
1.5V
6.0
1.8V
5.8
2.5V
5.6
3.3V
5.4
60.0
32.0
16.0
8.0
4.0
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
4.8
0.2
5.0
-150
1.0
5.2
-100
I/O PIN VOLTAGE ( V )
26
TPD (ns)
6.4
100
0.0
I/O PIN CURRENT ( uA )
150
# MC SWITCHING
ATF1504BE
3637B–PLD–1/08
ATF1504BE
15. Ordering Information
15.1
Lead-free Package Options (RoHS Compliant)
tPD
(ns)
tCO
(ns)
5
Ordering Code
Package
Operation Range
6
ATF1504BE-5AX100
100A
Commercial
(0° C to +70° C)
7
6.5
ATF1504BE-7AU100
100A
Industrial
(-40° C to +85° C)
5
6
ATF1504BE-5AX44
44A
Commercial
(0° C to +70° C)
7
6.5
ATF1504BE-7AU44
44A
Industrial
(-40° C to +85° C)
Package Type
44A
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
100A
100-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
27
3637B–PLD–1/08
16. Packaging Information
16.1
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
28
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
ATF1504BE
3637B–PLD–1/08
ATF1504BE
16.2
100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
Notes:
1.
2.
3.
This package conforms to JEDEC reference MS-026, Variation AED.
Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
Lead coplanarity is 0.08 mm maximum.
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
15.75
16.00
16.25
D1
13.90
14.00
14.10
E
15.75
16.00
16.25
E1
13.90
14.00
14.10
B
0.17
–
0.27
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.50 TYP
10/5/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
100A
REV.
C
29
3637B–PLD–1/08
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3637B–PLD–1/08
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