ATF1502BE - Datasheet

Features
• High-performance Fully CMOS, Electrically-erasable Complex Programmable
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Logic Device
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44 Pins
– 5.0 ns Pin-to-pin Propagation Delay
– Registered Operation up to 333 MHz
– Enhanced Routing Resources
– Optimized for 1.8V Operation
– 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.8V, 2.5V, 3.3V
In-System Programming (ISP) Supported
– 1.8V ISP Using IEEE 1532 (JTAG) Interface
– Boundary-scan Testing to IEEE JTAG Std. 1149.1 Supported
Flexible Logic Macrocell
– D/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate with Low Output Drive
– Programmable Open Collector Output Option
– Maximum Logic Utilization by Burying a Register with a COM Output and Vice
Versa
Fully Green (RoHS Compliant)
10 µA Static Current
Power Saving Option During Operation Using PD1, PD2 Pins
Programmable Pin-keeper Option on Inputs and I/Os
Programmable Schmitt Trigger Option on Input and I/O Pins
Programmable Input and I/O Pull-up Option (per Pin)
Unused Pins Can Be Configured as Ground (Optional)
Available in Commercial and Industrial Temperature Ranges
Available in 44-lead TQFP
Advanced Digital CMOS Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 10-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
Security Fuse Feature
Hot-Socketing Supported
Highperformance
CPLD
ATF1502BE
Rev. 3492A–PLD–12/05
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Outputs Can Be Configured for High or Low Drive
Combinatorial Output with Registered Feedback and Vice Versa within each Macrocell
Three Global Clock Pins
Fast Registered Input from Product Term
Pull-up Option on TMS and TDI JTAG Pins
OTF (On-the-Fly) Mode
DRA (Direct Reconfiguration Access)
1. Description
The ATF1502BE is a high-performance, high-density complex programmable logic device
(CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 32 logic macrocells
and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs.
The ATF1502BE’s enhanced routing switch matrices increase usable gate count and the odds
of successful pin-locked design modifications.
The ATF1502BE has up to 32 bi-directional I/O pins and four dedicated input pins, depending on
the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected
for use individually within each macrocell. Figure 1-1 shows the pin assignments for 44-lead
TQFP Package.
44-lead TQFP Top View
44
43
42
41
40
39
38
37
36
35
34
I/O
I/O
I/O
VCCINT
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
Figure 1-1.
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
I/O
I/O/TDO
I/O
I/O
VCCIOB
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCCINT
I/O
PD2/I/O
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
I/O/TDI
I/O
I/O
GND
PD1/I/O
I/O
TMS/I/O
I/O
VCCIOA
I/O
I/O
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ATF1502BE
3492A–PLD–12/05
ATF1502BE
Figure 1-2.
Block Diagram
B
32
Each of the 32 macrocells generates a buried feedback signal that goes to the global bus (see
Figure 1-2). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a
foldback logic term that goes to a regional bus. Cascade logic between macrocells in the
ATF1502BE allows fast, efficient generation of complex logic functions. The ATF1502BE contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40
product terms.
The ATF1502BE macrocell, shown in Figure 1-3, is flexible enough to support highly complex
logic functions operating at high speed. The macrocell consists of five sections: product terms
and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and
enable, and logic array inputs.
A security fuse, when programmed, protects the contents of the ATF1502BE. Two bytes
(16 bits) of User Signature are accessible to the user for purposes such as storing project name,
part number, revision or date. The User Signature is accessible regardless of the state of the
security fuse.
The ATF1502BE device is an In-System Programming (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan
Description Language (BSDL). ISP allows the device to be programmed without removing it from
the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design
modifications to be made in the field via software.
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3492A–PLD–12/05
Figure 1-3.
ATF1502BE Macrocell
BURIED FEEDBACK
SCHMITT
TRIGGER
1.1
Product Terms and Select Mux
Each ATF1502BE macrocell has five product terms. Each product term receives as its inputs all
signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as needed to the
macrocell logic gates and control signals. The PTMUX programming is determined by the design
compiler, which selects the optimum macrocell configuration.
1.2
OR/XOR/CASCADE Logic
The ATF1502BE’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR
sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to
as many as 40 product terms with minimal additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.
One input to the XOR comes from the OR sum term. The other XOR input can be a product term
or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms.
The XOR gate is also used to emulate T- and JK-type flip-flops.
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ATF1502BE
3492A–PLD–12/05
ATF1502BE
1.3
Flip-flop
The ATF1502BE’s flip-flop has very flexible data and control functions. The data input can come
from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the
separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D,
T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this
mode, data passes through when the clock is high and is latched when the clock is low.
The clock itself can be any one of the Global CLK signals (GCK[0 : 2]) or an individual product
term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the
clock, one of the macrocell product terms can be selected as a clock enable. When the clock
enable function is active and the enable signal (product term) is low, all clock edges are ignored.
The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The
asynchronous preset (AP) can be a product term or always off.
1.4
Extra Feedback
The ATF1502BE macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the
output is combinatorial or registered. (This enhancement function is automatically implemented
by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second
latch within a macrocell.
1.5
I/O Control
The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or bi-directional pin. The output enable for each macrocell
can be selected from the true or complement of the two output enable pins, a subset of the I/O
pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software
when the I/O is configured as an input or bi-directional pin.
1.6
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback signal from
all 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the
global bus. Under software control, up to 40 of these signals can be selected as inputs to the
logic block.
1.7
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional bus and
is available to all 16 macrocells within the logic block. The foldback is an inverse polarity of one
of the macrocell’s product terms. The 16 foldback terms in each logic block allow generation of
high fan-in sum terms or other complex logic functions with little additional delay.
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2. Programmable Pin-keeper Option for Inputs and I/Os
The ATF1502BE offers the option of programming each of its input or I/O pin so that pin-keeper
circuit can be utilized. When any pin is driven high or low and then subsequently left floating, it
will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate
their DC power consumption.
Figure 2-1 shows the pin-keeper circuit for an Input Pin and Figure 2-2 shows the same for an
I/O pin. The pin-keeper circuit is a weak feedback latch and has an effective resistance that is
approximately 50 kΩ.
Figure 2-1.
Input with Programmable Pin-keeper
50K
Figure 2-2.
I/O with Programmable Pin-keeper
50K
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ATF1502BE
3492A–PLD–12/05
ATF1502BE
2.1
Schmitt Trigger
The Input Buffer of each input and I/O pin has an optional schmitt trigger setting. The schmitt
trigger option can be used to buffer inputs with slow rise times.
3. Speed/Power Management
Unlike conventional CPLDs with sense amplifiers, the ATF1502BE is designed using low-power
full CMOS design techniques. This enables the ATF1502BE to achieve extremely low power
consumption over the full operating frequency spectrum.
The ATF1502BE also has an optional power-down mode. In this mode, current drops to below
100 µA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used
to power down the part. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins.
3.1
Output Drive Capability
Each output has a high/low drive option. The low drive option (slow slew rate) can be used to
reduce system noise by slowing down outputs that do not need to operate at maximum speed or
drive strength. Outputs default to high drive strength by Atmel software and can be set to low
drive strength through the slew rate option.
4. Security Feature
A fuse is provided to prevent unauthorized copying of the ATF1502BE fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains accessible. To
reset this feature, the entire memory array in the device must be erased.
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5. Programming Methods
The ATF1502BE devices are In-System Programmable (ISP) or In-System Configurable (ISC)
devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally
required for programming and facilitates rapid design iterations and field changes.
When using the ISP hardware or software to program the ATF1502BE devices, four I/O pins
must be reserved for the JTAG interface. However, the logic features that the macrocells have
associated with these I/O pins are still available to the design for buried logic functions.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector
Format (SVF) files can be created by Atmel-provided software utilities. ATF1502BE devices can
also be programmed using standard third-party programmers. With a third-party programmer,
the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic.
The AT1502BE device supports several configuration modes which gives designers several
unique options for programming.
The different modes of programming are:
• ISC – In System Configuration
• OTF – On-the-Fly Reconfiguration
• DRA – Direct Reconfiguration Access
5.1
In-System Configuration – ISC (Also Referred to as ISP)
This mode is the de-facto standard used to program the CPLD when it is attached to a PCB. The
term ISC can also be used interchangeably with ISP (In-system Programming). ISC or ISP eliminates the need for an external device programmer, and the devices can be soldered to a PCB
without being preprogrammed.
In the ISC mode, the logic operation of the ATF1502BE is halted and the embedded configuration memory is programmed. The device is programmed by first erasing the configuration
memory in the CPLD and loading the new configuration data into the memory, which in-turn configures the PLD for functional mode. When the device is in the ISC programming mode, all user
I/Os are held in the high impedance state.
The ISC mode is best suited for working with the ATF1502BE device in a design development or
production environment. Configuration of the ATF1502BE device done via a Download Cable
(see Figure 5-1 on page 8) is the default mode used to program the device in the ISC mode. In
this mode, the PC is typically the controlling device that communicates with the CPLD.
Figure 5-1.
Configuration of ATF1502BE Device Using a Download Cable
ATF1502BE
CPLD Device
TCK
Connect
ISP Download
Cable to 10-pin
JTAG Header
VCC
TDO
TMS
TDI
1
2
3
4
5
6
7
8
9
10
JTAG
Connector
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ATF1502BE
3492A–PLD–12/05
ATF1502BE
5.2
On-the-Fly – OTF
In this mode, the CPLD design pattern stored in the internal configuration memory can be modified while the previous design pattern is operating with minimal disturbance to the operation of
the current design. The new configuration will take affect after the OTF programming process is
completed and the OTF mode is exited.
The configuration data for any design is stored in the internal configuration memory. Once the
configuration data is transferred to the internal static registers of the CPLD, the CPLD operates
with the design pattern and the configuration memory is free to be re-loaded with a new set of
configuration data. The design pattern due to the new configuration content is activated through
an initialization cycle that occurs on exiting the OTF mode or after the next power up sequence.
Figure 5-2 shows the electrical interface for configuration of the ATF1502BE device in the OTF
mode. The processor is the controlling device that communicates with the CPLD and uses configuration data stored in the external memory to configure the CPLD.
Figure 5-2.
Configuration of ATF1502BE Device Using a Processor and Memory
ATF1502BE
CPLD Device
TCK
TDO
Processor
TMS
TDI
Serial Data
Data
Address
Memory
5.3
Direct Reconfiguration Access – DRA
This reconfiguration mode allows the user to directly modify the internal static registers of the
CPLD without affecting the configuration data stored in the embedded memory. It is more useful
in cases where immediate and temporary context change in the function of the hardware is
desired.
The CPLD embedded configuration memory does not change when a new set of configuration
data is passed to the chip using the DRA mode. Instead, the internal static registers of the CPLD
are directly written with the data entering the chip via the JTAG port. In other words, it's a temporary change in the function performed by the CPLD since a power sequence results in the device
being configured again by the data stored in the embedded memory.
5.4
ISP Programming Protection
The ATF1502BE has a special feature that locks the device and prevents the inputs and I/O
from driving if the programming process is interrupted for any reason. The inputs and I/O default
to high-Z state during such a condition.
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All ATF1502BE devices are initially shipped in the erased state, thereby making them ready to
use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel CPLDs”
application note.
6. JTAG-BST/ISP Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the
ATF1502BE. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component
boundaries can be controlled and observed using scan testing methods. Each input pin and I/O
pin has its own boundary-scan cell (BSC) to support boundary-scan testing. The TAP controller
is automatically reset at power-up. The five JTAG modes supported include:
SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502BE’s ISP can be
fully described using JTAG’s BSDL as described in IEEE Standard 1149.1. This allows
ATF1502BE programming to be described and implemented using any one of the third-party
development tools supporting this standard.
The ATF1502BE has the option of using four JTAG-standard I/O pins for boundary-scan testing
(BST) and ISP purposes. The ATF1502BE is programmable through the four JTAG pins using
the IEEE standard JTAG programming protocol established by IEEE Standard 1532 using 1.8V
LVCMOS level programming signals from the ISP interface for in-system programming. The
JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins.
6.1
JTAG Boundary-scan Cell (BSC) Testing
The ATF1502BE contains 32 I/O pins and four input pins. Each input pin and I/O pin has its own
boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and
up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the
macrocells. The BSCs in the device are chained together through the capture registers. Input to
the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin.
Capture registers are used to capture active device data signals, to shift data in and out of the
device and to load data into the update registers. Control signals are generated internally by the
JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is shown
below.
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ATF1502BE
3492A–PLD–12/05
ATF1502BE
Figure 6-1.
Note:
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
The ATF1502BE has a pull-up option on TMS and TDI pins. This feature is selected as a design
option.
Figure 6-2.
BSC Configuration for Macrocell
TDO
0
Q D
1
TDI
CLOCK
TDO
OEJ
0
0
1
D Q
D Q
1
OUTJ
0
0
Pin
1
D Q
D Q
Capture
DR
Update
DR
1
Mode
TDI
Shift
Clock
BSC for I/O Pins and Macrocells
7. Design Software Support
ATF1502BE designs are supported by several third-party tools. Automated fitters allow logic
synthesis using a variety of high-level description languages such as VHDL® and Verilog®. Third
party synthesis and simulation tools from Mentor Graphics® are integrated into Atmel’s software
tools.
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3492A–PLD–12/05
8. Electrical Specifications
Table 8-1.
Absolute Maximum Ratings*
*NOTICE:
Operating Temperature....................................–40°C to +85°C
Storage Temperature .....................................–65°C to +150°C
Supply Voltage (VCCINT) .................................... –0.5V to +2.5V
Supply Voltage for Output Drivers (VCCIO) ........ –0.5V to +4.5V
Junction Temperature ....................................–55°C to +155°C
Table 8-2.
Operating Temperature Range
Operating Temperature (Ambient)
Table 8-3.
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Commercial
Industrial
0°C - 70°C
-40°C - 85°C
Pin Capacitance(1)
Typ
Max
Units
Conditions
CIN
8
10
pF
VIN = 0V; f = 1.0 MHz
CI/O
8
10
pF
VOUT = 0V; f = 1.0 MHz
Note:
12
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
ATF1502BE
3492A–PLD–12/05
ATF1502BE
Table 8-4.
DC Characteristics
Symbol
Parameter
VCCINT
Condition
Min
Typ
Max
Units
Supply Voltage for internal
logic and input buffers
1.7
1.8
1.9
V
VCCIO
Supply Voltage for output
drivers at 3.3V
3.0
3.3
3.6
V
VCCIO
Supply Voltage for output
drivers at 2.5V
2.3
2.5
2.7
V
VCCIO
Supply Voltage for output
drivers at 1.8V
1.7
1.8
1.9
V
ICC_INT
Operating Current(1)
for VCCINT (supply voltage)
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
40
µA
ISB
Standby Current(1)
VCCINT = 1.9V, VCCIO = 3.6V
5
µA
IIL, IIH
Input Leakage
VCCINT = 1.8V, VIN = 0V or VCCINT
±1
µA
IOZH, IOH
Output or IO Leakage
VCCINT = 1.8V, VCCIO = 3.6V,
VIN = 0V or VCCIO
±1
µA
LVCMOS & LVTTL = 3.3V (HD: High Drive, LD: Low Drive)
VIL
Input Low-voltage
-0.3
0.8
V
VIH
Input High-voltage
2
3.9
V
V
Output Low-voltage
HD: IOL = 8 mA, VCCIO = 3V
0.4
VOL
LD: IOL = 1 mA, VCCIO = 3V
0.4
V
VOH
Output High-voltage
HD: IOH = -8 mA, VCCIO = 3V
VCCIO - 0.4V
V
LD: IOH = 1 mA, VCCIO = 3V
VCCIO - 0.4V
V
LVCMOS = 2.5V
VIL
Input Low-voltage
-0.3
0.7
V
VIH
Input High-voltage
1.7
3.9
V
V
Output Low-voltage
HD: IOL = 8 mA, VCCIO = 2.3V
0.4
VOL
LD: IOL = 1 mA, VCCIO = 2.3V
0.4
V
VOH
Output High-voltage
HD: IOH = -8 mA, VCCIO = 2.3V
VCCIO - 0.4V
V
LD: IOH = 1 mA, VCCIO = 2.3V
VCCIO - 0.4V
V
LVCMOS = 1.8V
VIL
Input Low-voltage
-0.3
0.35 x VCCIO
V
VIH
Input High-voltage
0.65 x VCCIO
3.9
V
V
Output Low-voltage
HD: IOL = 2 mA, VCCIO = 1.7V
0.45
VOL
LD: IOL = 1 mA, VCCIO = 1.7V
0.2
V
VOH
Output High-voltage
ICC_IO
Operating Current(1)
for VCCIO (supply voltage for
output drivers)
Note:
HD: IOH = -2 mA, VCCIO = 1.7V
VCCIO - 0.45V
V
LD: IOH = 1 mA, VCCIO = 1.7V
VCCIO - 0.45V
V
VCCINT = 1.8V, VCCIO = 3.3V,
f = 1 MHz
175
µA
1. 16-bit up/down counter used in each Lab.
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9. Timing Model
Internal Output
Enable Delay
tIOE
Global Control
Delay
tGLOB
Input
Delay
tIN
Logic Array
Delay
tLAD
Switch
Matrix
tUIM
Register
Delay
tSUI
tHI
tPRE
tCLR
tRD
tCOMB
tFSUI
tFHI
Cascade Logic
Delay
tPEXP
Register
Control
Delay
tLAC tIC tEN
Fast Input
Delay
tFIN
Foldback Term
Delay
tSEXP
Output
Delay
tOD1
tOD2
tOD3
tXZ
tXZ1
tXZ2
tXZ3
I/O
Delay
tIO
10. Output AC Test Loads
VCCIO
Device
Under Test
R1
Test Point
R2
R1
R2
CL
LVTTL
350 Ohm
350 Ohm
35 pF
LVCMOS33
300 Ohm
300 Ohm
35 pF
LVCMOS25
200 Ohm
200 Ohm
35 pF
LVCMOS18
150 Ohm
150 Ohm
35 pF
Note:
14
CL
CL includes test fixtures and probe capacitance.
ATF1502BE
3492A–PLD–12/05
ATF1502BE
11. AC Characteristics
Table 11-1.
AC Characteristics (1)
-5
Min
-7
Symbol
Parameter
Max
Min
Max
Units
tPD1_INP
Switching Delay for Single Input
5.0
5.75
ns
tPD1
Input or Feedback to Non-registered Output
7
7.5
ns
tPD2
I/O Input or Feedback to Non-registered Feedback
4.5
6
ns
tSU
Global Clock Setup Time
2.5
3.0
ns
tH
Global Clock Hold Time
0
0
ns
tFSU
Global Clock Setup Time of Fast Input
1
2
ns
tFH
Global Clock Hold Time of Fast Input
0.5
0.75
ns
tCOP
Global Clock to Output Delay
tCH
Global Clock High Time
1.25
2.15
ns
tCL
Global Clock Low Time
1.25
2.15
ns
tASU
Array Clock Setup Time
1.5
2.0
ns
tAH
Array Clock Hold Time
0.50
0.50
ns
tACOP
Array Clock to Output Delay
tACH
Array Clock High Time
1.75
2.5
ns
tACL
Array Clock Low Time
1.75
2.5
ns
tCNT
Minimum Clock Global Period
3
4.75
ns
fCNT
Maximum Internal Global Clock Frequency
333
210
MHz
tACNT
Minimum Array Clock Period
fACNT
Maximum Internal Array Clock Frequency
250
181
MHz
tIN
Input Pad and Buffer Delay
0.5
0.7
ns
tIO
I/O Input Pad and Buffer Delay
0.5
tFIN
Fast Input Delay
tSEXP
6
7
6
7.5
4
5.5
ns
ns
ns
0.5
ns
1
1
ns
Foldback Term Delay
2
3
ns
tPEXP
Cascade Logic Delay
0.5
1.0
ns
tLAD
Logic Array Delay
1.2
1.5
ns
tLAC
Logic Control Delay
1.5
2
ns
tIOE
Internal Output Enable Delay
2
2
ns
Output Buffer and Pad Delay
(High Drive; CL = 35 pF)
2
2.5
ns
tOD1
tZX1
Output Buffer Enable Delay
(High Drive; VCCIO = 1.8V; CL = 35 pF)
3
4.0
ns
tZX2
Output Buffer Enable Delay
(High Drive; VCCIO = 3.3V; CL = 35 pF)
2
3
ns
VCCIO = 1.8V
VCCIO = 3.3V
15
3492A–PLD–12/05
Table 11-1.
AC Characteristics (Continued)(1)
-5
Symbol
Parameter
tZX3
Output Buffer Enable Delay
(Low Drive; CL = 35 pF)
tXZ
Output Buffer Disable Delay (CL = 5 pF)
tSUI
Min
-7
Max
Min
Max
Units
ns
VCCIO = 1.8V
5
6
VCCIO = 3.3V
4
5
4
4
ns
Register Setup Time
1.0
1.5
ns
tHI
Register Hold Time
0.5
0.5
ns
tFSUI
Register Setup Time of Fast Input
0.5
1
ns
tFHI
Register Hold Time of Fast Input
0.5
0.5
ns
tRD
Register Delay
0.8
1.2
ns
tCOMB
Combinatorial Delay
0.8
1.2
ns
tIC
Array Clock Delay
2.5
3
ns
tEN
Register Enable Time
2.5
3
ns
tGLOB
Global Control Delay
0.75
1
ns
tPRE
Register Preset Time
1.75
2
ns
tCLR
Register Clear Time
1.75
2
ns
tUIM
Switch Matrix Delay
0.75
1
ns
Output Buffer and Pad Delay
(Slow slew rate = ON)
VCCIO = 1.8V
2.5
3.5
ns
tOD3
VCCIO = 3.3V
1.5
2.5
ns
tSCH
Schmitt Added Delay
1.5
2.0
ns
tSSO
Output Buffer Pad Added Delay for
VCCIO = 1.8V with output Low Drive
5
7
ns
Note:
16
1. See ordering information for valid part numbers.
ATF1502BE
3492A–PLD–12/05
ATF1502BE
12. Power-down Mode
The ATF1502BE includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 100 µA. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all
input signals except the power-down pin are blocked. Input and I/O hold latches remain active to
ensure that pins do not float to indeterminate levels, further reducing system power. The powerdown pin feature is enabled in the logic design file or through Atmel software. Designs using the
power-down pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
Table 12-1.
Power-down AC Characteristics(1)(2)
-5/-7
Symbol
Parameter
Min
tIVDH
Valid I, I/O before PD High
10
ns
(2)
Max
Units
Valid OE
before PD High
10
ns
tCVDH
Valid Clock
(2)
10
ns
tDHIX
I, I/O Don’t Care after PD High
tGVDH
tDHGX
before PD High
5
ns
Don’t Care after PD High
5
ns
(2)
5
ns
(2)
OE
tDHCX
Clock
Don’t Care after PD High
tDLIV
PD Low to Valid I, I/O
2
µs
tDLGV
PD Low to Valid OE (Pin or Term)
2
µs
tDLCV
PD Low to Valid Clock (Pin or Term)
2
µs
tDLOV
PD Low to Valid Output
2
µs
Notes:
1. For low-drive outputs, add tSSO.
2. Pin or product term.
17
3492A–PLD–12/05
13. ATF1502BE Dedicated Pinouts
Table 13-1.
ATF1502BE Dedicated Pinouts
44-lead
TQFP
Dedicated Pin
INPUT/OE2/GCLK2
40
INPUT/GCLR
39
INPUT/OE1
38
INPUT/GCLK1
37
I/O / GCLK3
35
I/O / PD (1,2)
5, 19
I/O / TDI (JTAG)
1
I/O / TMS (JTAG)
7
I/O / TCK (JTAG)
26
I/O / TDO (JTAG)
32
GND
18
4, 16, 24, 36
VCCINT
17, 41
VCCIOA
9
VCCIOB
29
# of Signal Pins
36
# User I/O Pins
32
OE (1, 2)
Global OE pins
GCLR
Global Clear pin
GCLK (1, 2, 3)
Global Clock pins
PD (1, 2)
Power-down pins
TDI, TMS, TCK, TDO
JTAG pins used for boundary-scan
testing or in-system programming
GND
Ground pins
VCCINT
VCC pins for the device (+1.8V)
VCCIOA
LAB A - VCC supply pins for I/Os (1.8V,
2.5V, or 3.3V)
VCCIOB
LAB B - VCC supply pins for I/Os (1.8V,
2.5V, or 3.3V)
ATF1502BE
3492A–PLD–12/05
ATF1502BE
Table 13-2.
ATF1502BE I/O Pinouts
MC
Logic Block
44-lead TQFP
1
A
42
2
A
43
3
A
44
4/TDI
A
1
5
A
2
6
A
3
7 (PD1)
A
5
8
A
6
9/TMS
A
7
10
A
8
11
A
10
12
A
11
13
A
12
14
A
13
15
A
14
16
A
15
17
B
35
18
B
34
19
B
33
20/TDO
B
32
21
B
31
22
B
30
23
B
28
24
B
27
25/TCK
B
26
26
B
25
27
B
23
28
B
22
29
B
21
30
B
20
31 (PD2)
B
19
32
B
18
19
3492A–PLD–12/05
14. Typical DC and AC Characteristic Graphs
SUPPLY CURRENT (ICC_IO) VS. FREQUENCY
VCCINT = 1.8V, VCCIO = 3.3V (TA = 25°C)
SUPPLY CURRENT (ICC_INT) VS. FREQUENCY
VCCINT = 1.8V, VCCIO = 3.3V (TA = 25°C)
20.0
6.0
18.0
16.0
ICC_IO (mA)
ICC_INT (mA)
5.0
4.0
3.0
2.0
14.0
12.0
10.0
8.0
6.0
4.0
1.0
2.0
0.0
0.0
0
0.1
1
2
5
10
20
50
75
83.3
100
0
0.1
1
2
5
FREQUENCY (MHz)
10
20
50
75
83.3
100
FREQUENCY (MHz)
OUTPUT SINK CURRENT (IOL) VS. OUTPUT VOLTAGE (HIGH DRIVE)
VCCINT = 1.8V, VCCIO = 3.3V (T A = 25°C)
OUTPUT SOURCE CURRENT (IOH) VS. OUTPUT VOLTAGE (HIGH DRIVE)
VCCINT = 1.8V, VCCIO = 3.3V (T A = 25°C)
0.0
180.0
160.0
-20.0
140.0
IOH (mA)
IOL (mA)
120.0
100.0
80.0
-40.0
-60.0
-80.0
60.0
40.0
-100.0
20.0
0.0
0.05
-120.0
0.1
0.2
0.5
0.6
1
1.5
2
2.5
2.5
3
3.3
3.3
3.2
3
2.75
OUTPUT VOLTAGE (mV)
OUTPUT SINK CURRENT (IOL) VS. OUTPUT VOLTAGE (HIGH DRIVE)
VCCINT = 1.8V, VCCIO = 1.8V (T A = 25°C)
1.5
1
0.5
0
0.0
60.0
-5.0
50.0
-10.0
IOH (mA)
IOL (mA)
2
OUTPUT SOURCE CURRENT (IOH) VS. OUTPUT VOLTAGE (HIGH DRIVE)
VCCINT = 1.8V, VCCIO = 1.8V (T A = 25°C)
70.0
40.0
30.0
-15.0
-20.0
20.0
-25.0
10.0
-30.0
0.0
0.05
-35.0
0.1
0.2
0.3
0.4
0.5
0.6
OUTPUT VOLTAGE (mV)
20
2.5
OUTPUT VOLTAGE (V)
1
1.5
1.8
1.8
1.7
1.6
1.4
1.2
1
0.8
0.5
0.3
0
OUTPUT VOLTAGE (V)
ATF1502BE
3492A–PLD–12/05
ATF1502BE
INPUT & I/O CURRENT VS. INPUT VOLTAGE
VCCINT = 1.8V, VCCIO = 1.8V (TA = 25°C)
(Pull-Up On)
70.0
0.0
60.0
-5.0
INPUT CURRENTN (µA)
INPUT CURRENTN (µA)
INPUT & I/O CURRENT VS. INPUT VOLTAGE
VCCINT = 1.8V, VCCIO = 1.8V (TA = 25°C)
(Pin Keeper On)
50.0
40.0
30.0
20.0
10.0
0.0
-10.0
-10.0
-15.0
-20.0
-25.0
-30.0
-20.0
-35.0
-30.0
-40.0
-40.0
0
0.5
0.9
1
1.5
1.8
0
0.5
1
INPUT VOLTAGE (V)
I/O CURRENT VS. INPUT VOLTAGE
VCCINT = 1.8V, VCCIO = 3.3V (TA = 25°C)
(Pin Keeper On)
1.8
I/O CURRENT VS. INPUT VOLTAGE
VCCINT = 1.8V, VCCIO = 3.3V (TA = 25°C)
(Pull-Up On)
100.0
0.0
-20.0
50.0
INPUT CURRENT (µA)
INPUT CURRENT (µA)
1.5
INPUT VOLTAGE (V)
0.0
-50.0
-100.0
-150.0
-40.0
-60.0
-80.0
-100.0
-120.0
-140.0
-200.0
-160.0
0
0.5
1
1.1
1.2
1.5
2
2.5
3
3.3
0
0.5
1
INPUT VOLTAGE (V)
1.5
2
2.5
3
3.3
INPUT VOLTAGE (V)
TPD VS. MACROCELL SWITCHING
VCCINT = 1.8V, VCCIO = 1.8V (TA = 25°C)
(Single Input Switching, tPDI_INP)
TPD VS. MACROCELL SWITCHING
VCCINT = 1.8V, VCCIO = 3.3V (TA = 25°C)
(Single Input Switching, tPDI_INP)
7.0
6.2
6.0
6.0
5.8
5.0
5.4
TPD
TPD
5.6
5.2
4.0
3.0
5.0
2.0
4.8
1.0
4.6
4.4
0.0
1
4
8
# MC SWITCHING
16
32
1
4
8
16
32
# MC SWITCHING
21
3492A–PLD–12/05
15. Ordering Information
15.1
Lead-free Package Options (RoHS Compliant)
tPD
(ns)
tCO
(ns)
5
7
Ordering Code
Package
Operation Range
6
ATF1502BE-5AX44
44A
Commercial
(0°C to +70°C)
7
ATF1502BE-7AU44
44A
Industrial
(-40°C to +85°C)
Package Type
44A
22
44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
ATF1502BE
3492A–PLD–12/05
ATF1502BE
16. Packaging Information
16.1
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
23
3492A–PLD–12/05
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3492A–PLD–12/05
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