SC2596 Datasheet

SC2596
Low Voltage Integrated DDR
Termination Regulator
POWER MANAGEMENT
Description
Features
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The SC2596 is an integrated linear DDR termination
device, which provides a complete solution for DDR
termination regulator designs; while meeting the JEDEC
requirements of SSTL-2 and SSTL-18 specifications for
DDR-SDRAM termination.
The SC2596 regulates up to +/- 2.5A for DDR-I and +/1.5A for DDR-II application requirements.
VTT is regulated to track the VREF voltage over the entire
current range with shoot through protection.
A VSENSE pin is incorporated to provide excellent load
regulation, along with a buffered reference voltage for
internal use.
Sourcing or sinking 2.5A for DDR-I
Sourcing or sinking 1.5A for DDR-II
AVCC undervoltage lockout
Reference output
Minimum number of external components
Accurate internal voltage divider
Disable function, puts device into sleep mode
Thermal shutdown
Over current protection
Available in SOIC8-EDP package
Pb-free, Halogen free, and RoHS/WEEE compliant
Applications
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The SC2596 also features a disable function which is to
tri-state the output during Suspend To Ram (STR) states
by pulling the EN pin low.
DDR-I and DDR-II memory termination
SSTL-2 and SSTL-3 termination
HSTL termination
PC motherboards
Graphics boards
Disk drives
CD-ROM drives
Typical Application Circuit
VDDQ
SC2596
EN
VDDQ
VSENSE
PVCC
VREF
GND
EN
AVCC
AVCC
VTT
VTT
VREF
0
Septenber 24, 2009
1
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SC2596
POWER MANAGEMENT
Absolute Maximum Ratings
PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied.
P ar am et er
S y m b ol
PVCC, AVCC, VDDQ, EN to GN D
M ax i m u m
Units
-0.3 to +6.0
V
Thermal Resistance Junction to Case
θJC
5.5
O
Thermal Resistance Junction to Ambient
θJA
36.5
O
Maximum Junction Temperature Range
TJ
-40 to +125
O
Storage Temperature Range
TSTG
-65 to +150
O
Peak IR Reflow Temperature 10-40S
T PKG
260
O
ESD Rating (Human Body Model)
ESD
2
C/W
C/W
C
C
C
kV
Electrical Characteristics (DDR-I)
Unless otherwise specified: TJ = -40oC to +125oC, AVCC = PVCC = 2.5V, VDDQ = 2.5V.
S y m b ol
Te s t C o n d i t i o n s
Min
Ty p
M ax
Units
Reference Voltage
V REF
IREF_OUT = 0mA
0.49VDDQ
0.5VDDQ
0.51VDDQ
V
VREF Output Impedance
ZVREF
IREF = -30uA to +30uA
(VTT - VREF)
IOUT = 0A
IOUT = -1.5A
IOUT = +1.5A
IQ
ILOAD = 0A
P ar am et er
V TT Output Regulation
(1)
Quiescent Current
-25
AVCC Enable Threshold
VDDQ Input Impedance
EN = 0
EN Pin Leakage Current
IQ_SD
EN = 0
EN Threshold Voltage
VH
VL
V TT Leakage Current in
Shutdown
© 2009 Semtech Corp.
IV TT_L
0
+25
mV
400
700
uA
2.1
2.2
V
100
ZVDDQ
ISD
Quiescent Current in Shutdown
Ω
230
150
kΩ
250
uA
1
uA
2
V
0.8
SD = 0V, V TT = 1.25V,
at 25 OC
2
6
uA
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SC2596
POWER MANAGEMENT
Electrical Characteristics (DDR-I Cont.)
Unless otherwise specified: TJ = -40oC to +125oC, AVCC = PVCC = 2.5V, VDDQ = 2.5V.
P ar am et er
Ty p
M ax
Units
ISENSE
50
200
nA
TSD
160
O
TSD_HYS
10
O
S y m b ol
VSEN SE Current
Thermal Shutdown
Thermal Shutdown Hysteresis
Te s t C o n d i t i o n s
Min
C
C
Note: (1) Regulation is measured by using a load current pulse. (Pulse Width less than 10mS, Duty Cycle less than 2%, TA = 25oC)
Electrical Characteristics (DDR-II)
Unless otherwise specified: TJ = -40oC to +125 oC, AVCC = 3.3V, PVCC = VDDQ = 1.8V.
S y m b ol
Te s t C o n d i t i o n s
Min
Ty p
M ax
Units
Reference Voltage
V REF
IREF_OUT = 0mA
0.49VDDQ
0.5VDDQ
0.51VDDQ
V
VREF Output Impedance
ZVREF
IREF = -30uA to +30uA
(VTT - VREF)
IOUT = 0A
IOUT = -1.0A
IOUT = +1.0A
IQ
ILOAD = 0A
P ar am et er
V TT Output Regulation
(1)
Quiescent Current
-25
AVCC Enable Threshold
VDDQ Input Impedance
Quiescent Current in Shutdown
Ω
230
0
+25
mV
400
700
uA
2.1
2.2
V
100
ZVDDQ
ISD
EN = 0
150
EN Pin Leakage Current
IQ_SD
EN = 0
0.5
EN Threshold Voltage
VH
VL
kΩ
250
uA
uA
2
V
0.8
SD = 0V, V TT = 0.9V,
at 25 OC
6
uA
V TT Leakage Current in
Shutdown
IV TT_L
VSENSE Current
ISENSE
50
TSD
160
O
TSD_HYS
10
O
Thermal Shutdown
Thermal Shutdown Hysteresis
200
nA
C
C
Note: (1) Regulation is measured by using a load current pulse. (Pulse Width less than 10mS, Duty Cycle less than 2%, TA = 25oC)
© 2009 Semtech Corp.
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SC2596
POWER MANAGEMENT
PRELIMINARY
Waveforms
AVCC
AVCC
VDDQ//PVCC
VDDQ//PVCC
Vref
VREF
VTT
VTT
Start up.
Shut down.
AVCC
AVCC
PVCC
PVCC
EN
EN
VTT
VTT
Shut down by EN.
Start up by EN.
AVCC
PVCC//VDDQ
AVCC
PVCC
VTT
VTT
IO
IO
1A load
© 2009 Semtech Corp.
Transient with +/- 1A load
4
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SC2596
POWER MANAGEMENT
Waveforms
4.0
Output Current (A)
Output Current (A)
4.0
3.5
3.0
2.5
3.5
3.0
2.5
2.0
2.0
2
2.5
3
3.5
4
4.5
5
2
5.5
2.5
3
4
4.5
5
5.5
5
5.5
AVCC (V)
AVCC (V)
Maximum Sourcing Current vs AVCC.
(VDDQ=1.8V, PVCC=2.5V)
Maximum Sinking Current vs AVCC.
(VDDQ=1.8V, PVCC=2.5V)
3.0
4.0
Output Current (A)
Output Current (A)
3.5
2.5
2.0
1.5
3.5
3.0
2.5
2.0
1.0
2
2.5
3
3.5
4
4.5
5
2
5.5
3
3.5
4
4.5
AVCC(V)
AVCC(V)
Maximum Sinking Current vs AVCC.
(VDDQ=1.8V, PVCC=1.8V)
Maximum Sourcing Current vs AVCC.
(VDDQ=1.8V, PVCC=1.8V)
© 2009 Semtech Corp.
2.5
5
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SC2596
POWER MANAGEMENT
Pin Configuration
PRELIMINARY
Ordering Information
TOP VIEW
GND
1
8
VTT
EN
2
7
PVCC
VSENSE
3
6
AVCC
VREF
4
5
VDDQ
Part Number
Package(3)
Temp. Range (T A)
SC2596SETRT(1)
SOIC8-EDP
-40 to +105 OC
SC2596EVB (2)
Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel contains 2500
devices for SOIC8-EDP.
(2) EVB provided with SOIC8-EDP package.
(3) Pb-free, Halogen free, and RoHS/WEEE compliant.
(SOIC8-EDP)
© 2009 Semtech Corp.
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SC2596
POWER MANAGEMENT
Pin Descriptions
Pin #
P i n N am e
1
GN D
2
EN
3
VSEN SE
VSEN SE p in is a feedback p in. Connect a 10nF to 100nF Ceramic cap acitor
between this p in to ground and p lace this cap acitor close to VSEN SE p in is
required to avoid oscillation during transient condition.
4
V REF
VREF p in is an outp ut p in, which p rovides the buffered outp ut of the internal
reference voltage. A 100nF ceramic cap acitor should be connected from
VREF p in to ground with shor t trace.
5
VDDQ
The VDDQ p in is an inp ut p in for creating internal reference voltage to
regulate V TT. The VDDQ voltage is connected to an internal resistor divider.
The central tap of resistor divider (VDDQ/2) is connected to the internal
voltage buffer, which outp ut is connected to VREF p in and the non-inver ting
inp ut of the error amp lifier as the reference voltage. With the feedback loop
closed, the V TT outp ut voltage will always track the VDDQ/2 p recisely. It is
recommended that a 1uF ceramic cap acitor should be added next to the
VDDQ p in to ground to increase the noise immunity.
6
AVCC
The AVCC p in is used to sup p ly all of the internal control circuitry. The AVCC
voltage has to be greater than its UVLO threshold voltage (2.1V typ ical) to
allow the SC2596 to be in normal op eration. If AVCC voltage is lower than
the UVLO threshold voltage, the V TT p in should be in high imp edance
status.
7
PVCC
The PVCC p in p rovides the rail voltage from where the V TT p in draws load
current. There is a limitation between AVCC and PVCC. The PVCC voltage must
be less or equal to AVCC voltage to ensure the correct outp ut voltage regulation.
The V TT source current cap ability is dep endent on PVCC voltage. Higher the
voltage on PVCC, higher the source current.
8
V TT
The V TT p in is the outp ut of SC2596. It can sink and source continuous current
while keep ing excellent load regulation. It is recommended that one should
use at least one 220uF low ESR cap acitor and a 1uF ceramic cap acitor or
on e 220u F h i gh ESR el ectrol y ti c cap aci tor an d a 6.8u F cerami c cap aci tor,
which are p laced on the V TT strip p lane to ground reducing the voltage
sp ike under load transient condition.
THERMAL
PAD
Pad for heatsinking p urp oses. Connect to ground p lane using multip le vias.
N ot connected internally.
© 2009 Semtech Corp.
P i n Fu n c t i o n
Ground.
Enable p in. SC2596 is disabled when EN p in is low.
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SC2596
POWER MANAGEMENT
Block Diagram
PRELIMINARY
EN
AVCC
PVCC
UVLO +
Thermal
Shutdown
VDDQ
-
+
+
-
Vref Buffer
AntiShootthru
+
Driver
Circuit
VTT
Error Am p.
GND
VREF
Vsense
Description
ERROR AMP
SC2596 is a low-voltage, low-dropout DDR termination
regulator with separate power supply to support both
DDR1 and DDR2 applications. AVCC and PVCC can be
tied together for DDR1 and can also be separated for
DDR2.
Low input offset op-amp for the main linear regulator. It
controls the VTT output voltage and which side of the
MOSFET to turn on (or turn off) to achieve zero shoot
through current.
ANTI-Shoot Thought Driver
SC2596 regulates VTT to the voltage of VREF. VTT will
sink or source upto 2.5A. Internal shoot-through protection ensure both top and bottom MOSFET will not conduct while maintaining fast source-to-sink load transient.
Thermal shut-down and internal current limit protect
SC2596 from shorted load or over-heated
Buffer stage takes the error voltage to control MOSFET.
Internal current limit is incorporated to protect from
shorted load.
THERMAL SHUTDOWN & UVLO
VREF BUFF
The Thermal shutdown block prevent the junction temperature exceed 165 oC. UVLO circuit to ensure proper
power is available for correct operation of the IC.
VREF is derived from VDDQ with an accurate divide by
op-amps(VREF Buffer). It is capable to sink and source
30uA. It is used as the reference voltage to the Error
amp. A 100nF or higher capacitor is recommended for
VREF pin to ground; To enhance the noise immunity from
board, an additional pull-down resistor (1MΩ) is
recomanded as well from VREF pin to ground.
© 2009 Semtech Corp.
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SC2596
POWER MANAGEMENT
Application Information
Overview
cause a large trace inductance and trace resistance.
Consider the load transient condition, a fast load current going through VTT strip plane will create a voltage
spike on VTT plane and a DC voltage drop for load current. It is recommanded the VSENSE pin should be connected center of VTT plane to improve regulation and
transient response.
Double Data Rate (DDR) SDRAM was defined by JEDEC
1997. Its clock speed is the same as previous SDRAM
but data transfer speed is twice than previous SDRAM.
By now, the requirement voltage range is changed from
3.3V to 2.5V or 1.8V; the power dissipation is smaller
than SDRAM. For above reasons, it is very popular and
widely used in M/B, N/B, Video-cards, CD ROM drives,
Disk drives.
A longer trace of VSENSE may pick up noise and cause
the error of load regulation. Hence designer should avoid
a longer trace between VSENSE to VTT plane. A 100nF
ceramic capacitor close to VSENSE pin is required.
Regarding the DDR power management solution, there
are two topologies can be selected for system designers. One is switching mode regulator that has bigger sink/
source current capability, but the cost is higher and needs
more board space. Another solution is linear mode regulator, which costs less, and needs less board space. For
two DIMM motherboards, system designers usually
choose the linear mode regulator for DDR power management solution.
VREF
VREF pin is an output pin to provid internal reference
voltage. System designer can use the voltage for
Northbridge chipset and memory. It is necessary to add
a ceramic capacitor (100nF) from VREF pin to ground
with shortest trace.
Thermal shutdown
Typical Application Circuits & Waveforms
The SC2596 has built-in thermal detected circuit to prevent this device from over temperature and damage.
The SC2596 goes into shunt down mode when temperature is higher than 165OC. The protection condition
will release when the temperature of device drop down
by 10OC.
Four different application circuits are shown below in Figure 1, Figure 2, Figure 3 and Figure 4. Each circuit is
designed for a specific condition. See Note a. and b.
below for recommended power up sequencing.
AVCC and PVCC
The AVCC pin, PVCC pin and the VDDQ pin can be tied
together for SSTL-2 application (Figure 1). It only needs
a 2.5V power rail for normal operation. System designer
can save the PCB space and reduce the cost.
Application_1: Standard SSTL-2 Application
AVCC and PVCC are the input supply pins for the SC2596.
AVCC is supply voltage for all the internal control circuitry.
The AVCC voltage has to be greater than its UVLO threshold voltage (2.1V typical) to allow the SC2596 to be normal operation.
VDDQ/EN=2.5V
SC2596
The PVCC pin provides the rail voltage from where the
VTT pin draws load current. There is a limitation between
AVCC and PVCC. The PVCC voltage must be less or equal
to AVCC voltage to ensure the correct VTT output voltage
regulation.
VREF/1.25V
VSENSE
VSENSE pin is a feedback pin from VTT plane. VTT plane
is always a narrow and long strip plane in most
montherboard applications. This long strip plane will
© 2009 Semtech Corp.
1
GND
VTT
8
2
EN
PVCC
7
3
VSENSE
AVCC
6
4
VREF
VDDQ
5
Csense
CREF
100nF
100nF
VTT/1.25V
CIN1
CIN2
1uF
COUT
100uF
220uF
0
Figure 1: Standard SSTL-2 application.
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SC2596
POWER MANAGEMENT
Application Information (Cont.)
PRELIMINARY
Application_4: High Source Current Configuration
Application_2: Lower Power Loss Configuration for
SSTL-2
If power loss is a major concern, separating the PVCC
form AVCC and VDDQ will be a good choice (Figure 2).
The PVCC can operate at lower voltage (1.8V to 2.5V) if
2.5V voltage is applied on AVCC and the VDDQ, the source
current is lower due to the lower operating voltage applied on the PVCC.
If there is a need for VTT to source more current, especially for DDR-II applications, the system designer can tie
the AVCC and PVCC to 3.3V while has the VDDQ tie to
1.8V. This configuration can ensure more than 2A source
and sink capability from the VTT rail.
SC2596
SC2596
EN/2.5V
VREF/1.25V
Csense
100nF
1
GND
2
8
EN
PVCC
7
3
VSENSE
AVCC
6 VDDQ/AVCC=2.5V
4
VREF
VDDQ
5
CREF
1M
VTT/1.25V
VTT
EN
PVCC=2.5V
VREF/0.9V
CIN1
100nF
CIN2
1uF
COUT
Csense
100uF 220uF
100nF
1
GND
VTT
8
2
EN
PVCC
7
3
VSENSE
AVCC
6
4
VREF
VDDQ
5
CREF
1M
VTT/0.9V
AVCC/PVCC=3.3V
VDDQ=1.8V
CIN2
CIN1
100nF
1uF
COUT COUT
100uF 10uF
220uF
0
0
Figure 4: High current set up for SSTL-18(DDR-II).
Figure 2: Lower power loss for SSTL-2(DDR-I).
Application_5: All Ceramic Capacitor Configuration
Application_3: Low Power Loss Configuration for
SSTL-18(DDR-II)
If power loss is a major concern, setting the PVCC to be
2.5V will be a good choice (Figure 3). The PVCC can operate at lower voltage. if 2.5V voltage is applied on AVCC
and PVCC, the source current is lower due to the lower
operating voltage applied on the PVCC.
For some pure ceramic output capacitor designs, one
needs to add small ESR in series with the output capacitor in order to enhance stability margin. For example, an
100mohm external ESR is suggested to help improve
the phase margin for the circuit in Figure 5. Figure 6
shows the corresponding Bode plot.
SC2596
EN
VREF/0.9V
1
GND
2
3
4
Csense
100nF
8
EN
PVCC
7
VSENSE
AVCC
6
VDDQ
5 VDDQ=1.8V
VREF
CREF
1M
100nF
SC2596
VTT/0.9V
VTT
1 GND
AVCC/PVCC=2.5V
EN
1uF
2 EN
PVCC 7
3 VSENSE
AVCC 6
4 VREF
VDDQ 5
VDDQ/PVCC=1.8V
COUT
AVCC=3.3V
10uF
VREF/0.9V
CIN2 COUT
CIN1
VTT/0.9V
VTT 8
100uF 220uF
0
Csense
CREF
CIN1
CIN2
CIN3
100nF
1M 100nF
1uF
1uF
10uF
External R
100mOhm
0
Figure 5: All ceramic capacitor configuration.
Figure 3: Lower power loss for SSTL-18(DDR-II).
Notes:
(a) The preferred configuration for DDR-I applications is to tie AVCC and PVCC to VDDQ, which is typically 2.5V.
(b) If AVCC and PVCC rails are tied together, then the VDDQ cannot lead the AVCC and PVCC.
© 2009 Semtech Corp.
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SC2596
POWER MANAGEMENT
Application Information (Cont.)
Application_5: Bode Plot of an all ceramic capacitor solution in Figure 5.
Figure 6: Bode Plot of an all ceramic capacitor application
The phase margin is 72° and the bandwidth is around 1MHz, where: AVCC=3.3V, PVCC=VDDQ=1.8V, VTT=0.9V,
IOUT=380mA, COUT=10uF & 100mhom. For this application, we further measured the corresponding phase
margins for different output capacitor values and ESR values at designed sourcing and sinking currents in
Figure 7.
Phase Margin vs External ESR
IO=380mA_SINK
IO=380mA_Soure
90.00
120.00
80.00
100.00
70.00
Phase Magnitude
Phase Magnitude
80.00
Cout=4.7uF
60.00
50.00
Cout=10uF
40.00
30.00
Cout=22uF
Cout=10uF
40.00
20.00
20.00
0.00
10.00
-20.00
0.00
Cout=4.7uF
60.00
Cout=22uF
-40.00
10mR
50mR
100mR
200mohm
10mR
50mR
100mR
200mohm
Figure 7: Phase margin vs external ESR values for different output ceramic capacitor values
Layout guidelines
1) The SOIC8-EDP package of SC2596 can improve the thermal impedance (θJC) significantly. A suitable thermal
pad should be add when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB
ground layer. This will improve the thermal performance. Please refer to the recommanded landing pattern.
2) To increase the noise immunity, a ceramic capacitor of 100nF is required to decouple the VREF pin with the
shortest connection trace.
3) To reduce the noise on input power rail for standard SSTL-2 application, a 100µF low ESR capacitor and a 1µF
ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection.
4) VTT output copper plane should be as large as possible. A 4.7uF to 10µF capacitor have to be used to
decouple the VTT pin.
5) The trace between VSENSE pin and VTT rail should be as short as possible and put a 10nF ~100nF capacitor
close this vsense pin.
© 2009 Semtech Corp.
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SC2596
POWER MANAGEMENT
Typical Application Circuit
PRELIMINARY
VDDQ
1.8V
U1
1
SC2596
GND
VTT
8
VTT
0.9V
4
1M
100nF
R1 C1
0.9V
VSENSE
AVCC
VREF
VDDQ
7
3.3V
6
5
C2
C3
10nF
VREF
PVCC
1uF
C7
C4
1uF
C5
C6
1uF
3
EN
220uF
2
100uF
EN
0
DDR-II VTT Solution
Bill of Material
R ef
Qty
1
1
C1
100nF, 25V, X5R,Ceramic, 0603
Yageo
2
1
C2
10nF, 16V, X5R, Ceramic , 0603
Yageo
3
1
C3
1uF, 16V, X5R, Ceramic , 0603
Yageo
4
1
C6
1uF, 16V, X5R, Ceramic , 0603
Yageo
5
1
C7
1uF, 16V, X5R, Ceramic , 0603
Yageo
6
1
C4
100uF, 6.3V, Aluminum
Yageo
7
1
C5
220uF, 6.3V, Aluminum
Rubycon
8
1
R1
1M OHM
Yageo
9
1
U1
SC2596
Semtech
© 2009 Semtech Corp.
R ef er en ce
P a r t N u m b e r / Va l u e
12
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SC2596
POWER MANAGEMENT
Outline Drawing - SOIC8-EDP
© 2009 Semtech Corp.
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SC2596
POWER MANAGEMENT
PRELIMINARY
Land Pattern - SOIC8-EDP
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
© 2009 Semtech Corp.
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