PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 Rev. A2 Silicon Errata The PIC18F2331/2431/4331/4431 parts you have received conform functionally to the Device Data Sheet (DS39616), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2331/2431/4331/4431 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. All the issues listed here will be addressed in future revisions of the PIC18F2331/2431/4331/4431 silicon. The following silicon errata apply only to PIC18F2331/2431/4331/4431 devices with these Device/Revision IDs: 2. Module: In-Circuit Serial Programming™ (ICSP™) A small number of parts may be difficult to program successfully at certain voltages using the MPLAB® ICD 2. Work around If such a part is encountered, attempt to program several times. If unsuccessful, adjust VDD up or down slightly, within the operating range of the device. If this is not possible, then try another part. Date Codes that pertain to this issue: Part Number Device ID Revision ID PIC18F2331 00 1000 111 00001 PIC18F2431 00 1000 110 00001 PIC18F4331 00 1000 101 00001 PIC18F4431 00 1000 100 00001 The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in the device’s configuration space. They are shown in hexadecimal in the format “DEVID2 DEVID1”. All engineering and production devices. 3. Module: PCPWM When the PCPWM is operated in Complementary mode with a non-zero dead-time value and the duty cycle results in an active-low time of less than 1 TCY, the PWM generator will miss the rising edge for a new PWM period and the PWM output will alternate between one PWM period high and one PWM period low. Work around 1. Module: Timer5 ® In Debug mode (using the MPLAB ICD 2), if “Freeze on Halt” is selected (an option in the MPLAB ICD 2 settings under the Program tab), TMR5L will not increment properly when single stepping if the prescaler is not set to 1:1. Work around When in Complementary mode with a non-zero dead-time value, ensure that the active-low time will always be greater than 1 TCY. In other words, when dead-time is not equal to zero, ensure that: PDCH:PDCL < (4 * PTPERH:PTPERL) or PDCH:PDCL > (4 * (PTPERH:PTPERL + 1)) None. Use in Debug mode only with the 1:1 prescaler. Date Codes that pertain to this issue: Date Codes that pertain to this issue: All engineering and production devices. All engineering and production devices. © 2005 Microchip Technology Inc. DS80180C-page 1 PIC18F2331/2431/4331/4431 4. Module: PCPWM When the PCPWM is operated in Center-Aligned mode with double updates and the duty cycle alternates on each update between a zero and non-zero value, an incorrect waveform is generated (the PWM output will alternate between one PWM period high and one PWM period low). If in Complementary mode, dead time will not be inserted properly. Work around 7. Module: PCPWM The PTMRH register will read as ‘00’ or the last value written to it, even though the upper four bits of the PWM timer may be different. Writing to PTMRH will effect the upper four bits of the PWM timer when PTMRL is subsequently written. Although the PWM timer operates correctly, the double-buffer circuit does not transfer data to the PTMRH register from the upper four bits of the PWM timer. Do not use zero duty cycle when in Center-Aligned mode with double updates. Instead of zero, set the duty cycle to a small, non-zero value. Work around Date Codes that pertain to this issue: Date Codes that pertain to this issue: All engineering and production devices. All engineering and production devices. 5. Module: PCPWM When the PCPWM is operated in Center-Aligned mode with double updates and the duty cycle alternates on each update between a greater than 100% duty cycle and a non-zero value, an incorrect waveform is generated. PWM operation is not affected. Do not attempt to read PTMRH. 8. Module: PCPWM In Complementary mode with dead-time insertion, when using OVDCOND and OVDCONS to override the PWM outputs, dead time is not inserted correctly when the dead-time prescaler is FOSC/4, FOSC/8 or FOSC/16. Work around Work around Do not use equal to or greater than 100% duty cycle when in Center-Aligned mode with double updates. Ensure that the maximum duty cycle value is always smaller than or equal to the PWM period, i.e., PDCH:PDCL ≤ (4 * (PTPERH:PTPERL)). None. Use dead-time prescaler of FOSC/2 in these circumstances. Date Codes that pertain to this issue: All engineering and production devices. 6. Module: PCPWM If dead-time insertion is enabled and it is a nonzero value, glitches in the PWM output will occur under the following conditions: 1. When the PWM Timer is stopped by clearing the PTEN bit. 2. When the duty cycle is changed to zero. Work around 1. Before disabling the PWM timer, ensure that PORTB is set up to maintain a safe state of external hardware and that TRISB is set up to define the pins as outputs. 2. Do not use zero duty cycle when dead-time insertion is enabled. Instead of zero, set the duty cycle to a small, non-zero value (such as ‘1’). Date Codes that pertain to this issue: All engineering and production devices. 9. Module: Data EEPROM When writing to the data EEPROM, the contents of the data EEPROM memory may not be written as expected if the internal voltage reference is not enabled. Work around Either of two work arounds can be used: 1. Before beginning any writes to the data EEPROM, enable the LVD (any voltage) and wait for the internal voltage reference to become stable. LVD interrupt requests may be ignored. Once the LVD voltage reference is stable, perform all EEPROM writes normally. When writes have been completed, the LVD may be disabled. 2. Configure the BOR as enabled (any voltage). Select a threshold below VDD to allow normal operation. If VDD is below the BOR threshold, the device will be held in Brown-out Reset. Date Codes that pertain to this issue: All engineering and production devices. DS80180C-page 2 © 2005 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10. Module: Program Memory 12. Module: EUSART When writing to the program memory, the contents of the program memory may not be written as expected if the internal voltage reference is not enabled. Bit SENDB in the TXSTA register is not automatically cleared by hardware upon completion of transmission of a Sync Break. Work around Check the TRMT bit in TXSTA. If the TRMT bit is set, Break transmission is said to be complete. Either of two workarounds can be used: 1. Before beginning any writes to the program memory, enable the LVD (any voltage) and wait for the internal voltage reference to become stable. LVD interrupt requests may be ignored. Once the LVD voltage reference is stable, perform all program memory writes normally. When writes have been completed, the LVD may be disabled. 2. Configure the BOR as enabled (any voltage). Select a threshold below VDD to allow normal operation. If VDD is below the BOR threshold, the device will be held in BOR Reset. Date Codes that pertain to this issue: Work around 13. Module: EUSART If the transmitter is left enabled while the module is performing an auto-baud operation, an arbitrary data byte may get transmitted. Work around Clear TXEN (TXSTA<5>) before any auto-baud operation and set it after auto-baud is complete. Enable TXEN only when a data byte is to be transmitted. Care must be taken to ensure that the TX pin is pulled high, either through an external resistor, or by making the TX pin an output and writing ‘1’ to it to not disturb the transmit line. All engineering and production devices. 11. Module: Core (DAW Instruction) 14. Module: EUSART The DAW instruction may improperly clear the Carry bit (Status<0>) when executed. This module may perform incorrect auto-baud calculation if the ABDEN (BAUDCON<0>) bit was set while the receive pin was at a low level. Work around Work around Test the Carry bit state before executing the DAW instruction. If the Carry bit is set, increment the next higher byte to be added, using an instruction such as INCFSZ (this instruction does not affect any Status flags and will not overflow a BCD nibble). After the DAW instruction has been executed, process the Carry bit normally (see Example 1). Wait for the RX pin to go high and then set the ABDEN bit. EXAMPLE 1: PROCESSING THE CARRY BIT DURING BCD ADDITIONS MOVLW ADDLW 0x80 0x80 ; .80 (BCD) ; .80 (BCD) BTFSC INCFSZ DAW BTFSC INCFSZ STATUS, C byte2 ; test C ; inc next higher LSB STATUS, C byte2 ; test C ; inc next higher LSB This is repeated for each DAW instruction. 15. Module: EUSART In Asynchronous Receiver mode, the EUSART does not load the SPBRGH value after completion of auto-baud. Work around Do not enable the BRG16 (BAUDCON<3>) bit. If the BRG16 is in use, ensure that the auto-baud SPBRG value does not exceed the 8-bit value. 16. Module: EUSART The CREN (RCSTA<4>) bit is cleared after every auto-baud operation. Work around Upon completion of auto-baud, manually set the CREN bit. Date Codes that pertain to this issue: All engineering and production devices. © 2005 Microchip Technology Inc. DS80180C-page 3 PIC18F2331/2431/4331/4431 17. Module: EUSART Writing to the USART/EUSART TXREG register faster than the baud rate in Synchronous mode will overwrite the previous value instead of double-buffering as in Asynchronous mode. Work around Load the first character into TXREG and then wait for a TX interrupt, or check the TXIF bit before writing each additional character to TXREG. 18. Module: EUSART The EUSART cannot receive asynchronous data at the four fastest baud rates (BRGH = 1, BRG16 = 1 and SPBRG < 4). Work around 19. Module: HSADC A ΔIAD (parameter D026) of greater than 300 μA (for VDD = 3V) is observed when the device is put into Sleep mode with the HSADC enabled (ADON = 1) without setting the GO/DONE bit so that at least one conversion is performed. Observed ΔIAD will increase in proportion to VDD. Work around If no conversion will be done while in Sleep mode, disable the HSADC module by clearing the ADON bit before entering Sleep mode. If power consumption is an issue for the application, do not put the part into Sleep mode with the HSADC enabled if no conversion is to be performed. Use a slower baud rate or a faster system clock speed. DS80180C-page 4 © 2005 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REVISION HISTORY Rev A Document (1/2004) First revision of this document. Silicon issues 1 (Timer5), 2 (In-Circuit Serial Programming), 3-8 (PCPWM), 9 (Data EEPROM), 10 (Program Memory), 11 (Core – DAW Instruction) and 12-18 (EUSART) and Data Sheet Clarification issue 1 (Power-on Reset). Rev B Document (2/2004) Modifications to the Work Around for Silicon issue 3 (PCPWM). Rev C Document (05/2005) Added silicon issue 19 (HSADC). All Data Sheet Clarification issues were removed and placed into a separate Data Sheet Errata. © 2005 Microchip Technology Inc. DS80180C-page 5 PIC18F2331/2431/4331/4431 NOTES: DS80180C-page 6 © 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2005 Microchip Technology Inc. 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