PIC18F2331/2431/4331/4431 Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D 2003 Microchip Technology Inc. Preliminary DS39616B Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartShunt and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003 . The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39616B-page ii Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High Performance PWM and A/D 14-bit Power Control PWM Module: Power-Managed Modes: • • • • • • • • • • • • • Up to 4 channels with complementary outputs Edge- or center-aligned operation Flexible dead-band generator Hardware fault protection inputs Simultaneous update of duty cycle and period: - Flexible special event trigger output Motion Feedback Module: • Three independent input capture channels: - Flexible operating modes for period and pulse width measurement - Special Hall Sensor interface module - Special event trigger output to other modules • Quadrature Encoder Interface: - 2 phase inputs and one index input from encoder - High and low position tracking with direction status and change of direction interrupt - Velocity measurement Peripheral Highlights: • High current sink/source 25 mA/25 mA • Three external interrupts • Two Capture/Compare/PWM (CCP) modules: - Capture is 16-bit, max. resolution 6.25 ns (TCY/16) - Compare is 16-bit, max. resolution 100 ns (TCY) - PWM output: PWM resolution is 1 to 10 bits • Enhanced USART module: - Supports RS-485, RS-232 and LIN 1.2 - Auto-Wake-up on Start bit - Auto-Baud detect • RS-232 operation using internal oscillator block (no external crystal required) High-Speed, 200 Ksps 10-bit A/D Converter: • • • • • • • Run CPU on, peripherals on Idle CPU off, peripherals on Sleep CPU off, peripherals off Idle mode currents down to 5.8 µA typical Sleep current down to 0.1 µA typical Timer1 oscillator, 1.8 µA typical, 32 kHz, 2V Watchdog Timer (WDT), 2.1 µA typical Two-Speed oscillator start-up Up to 9 channels Simultaneous two-channel sampling Sequential sampling: 1, 2 or 4 selected channels Auto-conversion capability 4-word FIFO with selectable interrupt frequency Selectable external conversion triggers Programmable acquisition time Special Microcontroller Features: • 100,000 erase/write cycle enhanced Flash program memory typical • 1,000,000 erase/write cycle data EEPROM memory typical • Flash/data EEPROM retention: 100 years • Self-programmable under software control • Priority levels for interrupts • 8 X 8 Single-cycle Hardware Multiplier • Extended Watchdog Timer (WDT): - Programmable period from 41 ms to 131s • Single-supply In-Circuit Serial Programming™ (ICSP™) via two pins • In-Circuit Debug (ICD) via two pins - Drives PWM outputs safely when debugging Flexible Oscillator Structure: Quadrature Encoder • Four crystal modes up to 40 MHz • Two external clock modes up to 40 MHz • Internal oscillator block: - 8 user selectable frequencies: 31 kHz to 8 MHz - OSCTUNE can compensate for frequency drift • Secondary oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor: - Allows for safe shutdown of device if clock fails 14-bit PWM (ch) PIC18F2331 8192 4096 768 256 24 5 2 Y Y Y Y 6 PIC18F2431 16384 8192 768 256 24 5 2 Y Y Y Y 6 1/3 PIC18F4331 8192 4096 768 256 36 9 2 Y Y Y Y 8 1/3 PIC18F4431 16384 8192 768 256 36 9 2 Y Y Y Y 8 1/3 Program Memory Device Data Memory Flash # Single-Word SRAM EEPROM (bytes) Instructions (bytes) (bytes) 2003 Microchip Technology Inc. I/O SSP 10-bit A/D CCP Slave EUSART SPI 2 (ch) I C™ Preliminary Timers 8/16-bit 1/3 DS39616B-page 1 PIC18F2331/2431/4331/4431 Pin Diagrams 28-Pin SDIP, SOIC 28 RB7/KBI3/PGD 2 27 RB6/KBI2/PGC RA1/AN1 3 26 RB5/KBI1/PWM4/PGM(1) RA2/AN2/VREF-/CAP1/INDX 25 24 RB4/KBI0/PWM5 RA3/AN3/VREF+/CAP2/QEA 4 5 RA4/AN4/CAP3/QEB 6 23 RB2/PWM2 AVDD 7 8 22 21 RB1/PWM1 20 19 VDD AVSS RB3/PWM3 RB0/PWM0 OSC2/CLKO/RA6 9 10 RC0/T1OSO/T1CKI 11 18 RC7/RX/DT/SDO RC1/T1OSI/CCP2/FLTA 12 13 14 17 16 15 RC6/TX/CK/SS OSC1/CLKI/RA7 RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 Note 1: PIC18F2331/2431 •1 RA0/AN0 MCLR/VPP/RE3 VSS RC5/INT2/SCK/SCL RC4/INT1/SDI/SDA Low-voltage programming must be enabled. MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB RA5/AN5/LVDIN RE0/AN6 RE1/AN7 RE2/AN8 AVDD AVSS OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI(1)/T5CKI(1)/INT0 RD0/T0CKI/T5CKI RD1/SDO Note 1: 2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIC18F4331/4431 40-Pin PDIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PWM4/PGM(2) RB4/KBI0/PWM5 RB3/PWM3 RB2/PWM2 RB1/PWM1 RB0/PWM0 VDD VSS RD7/PWM7 RD6/PWM6 RD5/PWM4(4) RD4/FLTA(3) RC7/RX/DT/SDO(1) RC6/TX/CK/SS RC5/INT2/SCK(1)/SCL(1) RC4/INT1/SDI(1)/SDA(1) RD3/SCK/SCL RD2/SDI/SDA RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. Low-voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. DS39616B-page 2 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SS RC5/INT2/SCK(1)/SCL(1) RC4/INT1/SDI(1)/SDA(1) RD3/SCK/SCL RD2/SDI/SDA RD1/SDO RD0/T0CKI/T5CKI RC3/T0CKI(1)/T5CKI(1)/INT0 RC2/CCP1/FLTB RC1/T1OSI/CCP2/FLTA NC 44-Pin TQFP PIC18F4331 PIC18F4431 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 NC RC0/T1OSO/T1CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 AVSS AVDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB NC NC RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM(2) RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RC7/RX/DT/SDO(1) RD4/FLTA(3) RD5/PWM4(4) RD6/PWM6 RD7/PWM7 VSS VDD RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 Note 1: 2: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. Low-voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. 2003 Microchip Technology Inc. Preliminary DS39616B-page 3 PIC18F2331/2431/4331/4431 Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SS RC5/INT2/SCK(1)/SCL(1) RC4/INT1/SDI(1)/SDA(1) RD3/SCK/SCL RD2/SDI/SDA RD1/SDO RD0/T0CKI/T5CKI RC3/T0CKI(1)/T5CKI(1)/INT0 RC2/CCP1/FLTB RC1/T1OSI/CCP2/FLTA RC0/T1OSO/T1CKI 44-Pin QFN PIC18F4331 PIC18F4431 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS AVSS AVDD VDD RE2/AN8 RE1/AN7 RE0/AN6 RA5/AN5/LVDIN RA4/AN4/CAP3/QEB RB3/PWM3 NC RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM(2) RB6/KBI2/PGC RB7/KBI3/PGD MCLR/VPP/RE3 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RC7/RX/DT/SDO(1) RD4/FLTA(3) RD5/PWM4(4) RD6/PWM6 RD7/PWM7 VSS VDD AVDD RB0/PWM0 RB1/PWM1 RB2/PWM2 Note 1: 2: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL. Low-voltage programming must be enabled. 3: RD4 is the alternate pin for FLTA. 4: RD5 is the alternate pin for PWM4. DS39616B-page 4 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Oscillator Configurations ............................................................................................................................................................ 21 3.0 Power-Managed Modes ............................................................................................................................................................. 31 4.0 Reset .......................................................................................................................................................................................... 45 5.0 Memory Organization ................................................................................................................................................................. 57 6.0 Flash Program Memory.............................................................................................................................................................. 75 7.0 Data EEPROM Memory ............................................................................................................................................................. 85 8.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 89 9.0 Interrupts .................................................................................................................................................................................... 91 10.0 I/O Ports ................................................................................................................................................................................... 107 11.0 Timer0 Module ......................................................................................................................................................................... 133 12.0 Timer1 Module ......................................................................................................................................................................... 137 13.0 Timer2 Module ......................................................................................................................................................................... 143 14.0 Timer5 Module ......................................................................................................................................................................... 145 15.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 151 16.0 Motion Feedback Module ......................................................................................................................................................... 159 17.0 Power Control PWM Module .................................................................................................................................................... 181 18.0 Synchronous Serial Port (SSP) Module ................................................................................................................................... 211 19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 221 20.0 10-bit High-Speed Analog-to-Digital Converter (A/D) Module.................................................................................................. 243 21.0 Low-Voltage Detect .................................................................................................................................................................. 261 22.0 Special Features of the CPU.................................................................................................................................................... 267 23.0 Instruction Set Summary .......................................................................................................................................................... 287 24.0 Development Support............................................................................................................................................................... 331 25.0 Electrical Characteristics .......................................................................................................................................................... 337 26.0 Preliminary DC and AC Characteristics Graphs and Tables.................................................................................................... 371 27.0 Packaging Information.............................................................................................................................................................. 373 Appendix A: Revision History............................................................................................................................................................. 379 Appendix B: Device Differences ........................................................................................................................................................ 379 Appendix C: Conversion Considerations ........................................................................................................................................... 380 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 380 Appendix E: Migration from Mid-range to Enhanced Devices ........................................................................................................... 381 Appendix F: Migration from High-end to Enhanced Devices ............................................................................................................. 381 INDEX ................................................................................................................................................................................................ 383 On-Line Support................................................................................................................................................................................. 391 Systems Information and Upgrade Hot Line ...................................................................................................................................... 391 Reader Response .............................................................................................................................................................................. 392 PIC18F2331/2431/4331/4431 Product Identification System ............................................................................................................ 393 2003 Microchip Technology Inc. Preliminary DS39616B-page 5 PIC18F2331/2431/4331/4431 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. DS39616B-page 6 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 1.0 DEVICE OVERVIEW This document contains device specific information for the following devices: • PIC18F2331 • PIC18F2431 • PIC18F4331 • PIC18F4431 This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance at an economical price, with the addition of high endurance enhanced Flash program memory and a highspeed 10-bit A/D converter. On top of these features, the PIC18F2331/2431/4331/4431 family introduces design enhancements that make these microcontrollers a logical choice for many high performance, power control and motor control applications. These special peripherals include: • 14-bit resolution Power Control PWM Module (PCPWM) with programmable dead time insertion • Motion Feedback Module (MFM), including a 3-channel Input Capture (IC) Module and Quadrature Encoder Interface (QEI) • High-speed 10-bit A/D Converter (HSADC) The PCPWM can generate up to eight complementary PWM outputs with dead-band time insertion. Overdrive current is detected by off-chip analog comparators or the digital fault inputs (FLTA, FLTB). The MFM Quadrature Encoder Interface provides precise rotor position feedback and/or velocity measurement. The MFM 3 X input capture or external interrupts can be used to detect the rotor state for electrically commutated motor applications using Hall Sensor feedback, such as BLDC motor drives. PIC18F2331/2431/4331/4431 devices also feature Flash program memory and an internal RC oscillator with built-in LP modes. 1.1 1.1.1 New Core Features nanoWatt TECHNOLOGY All of the devices in the PIC18F2331/2431/4331/4431 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run with its CPU core disabled, but the peripherals are still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. 2003 Microchip Technology Inc. • On-the-fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power saving ideas into their application’s software design. • Lower Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer have been reduced by up to 80%, with typical values of 1.1 and 2.1 µA, respectively. 1.1.2 MULTIPLE OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F2331/2431/4331/4431 family offer nine different oscillator options, allowing users a wide range of choices in developing application hardware. These include: • Four crystal modes, using crystals or ceramic resonators. • Two external clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O). • Two external RC oscillator modes, with the same pin options as the external clock modes. • An internal oscillator block, which provides an 8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of 6 user-selectable clock frequencies (from 125 kHz to 4 MHz) for a total of 8 clock frequencies. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low speed operation or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset or wake-up from Sleep mode, until the primary clock source is available. This allows for code execution during what would otherwise be the clock start-up interval, and can even allow an application to perform routine background activities and return to Sleep without returning to full power operation. Preliminary DS39616B-page 7 PIC18F2331/2431/4331/4431 1.2 Other Special Features • Memory Endurance: The enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 100 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. • Power Control PWM Module: In PWM mode, this module provides 1, 2 or 4 modulated outputs for controlling half-bridge and full-bridge drivers. Other features include Auto-Shutdown on fault detection and Auto-Restart to reactivate outputs once the condition has cleared. • Enhanced USART: This serial communication module is capable of standard RS-232 operation using the internal oscillator block, removing the need for an external crystal (and its accompanying power requirement) in applications that talk to the outside world. This module also includes autobaud detect and LIN capability. DS39616B-page 8 • High-speed 10-bit A/D Converter: This module incorporates Programmable Acquisition Time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. • Motion Feedback Module (MFM): This module features a Quadrature Encoder Interface (QEI) and an Input Capture (IC) module. The QEI accepts two phase inputs (QEA, QEB) and one index input (INDX) from an incremental encoder. The QEI supports high and low precision position tracking, direction status and change of direction interrupt, and velocity measurement. The input capture features 3 channels of independent input capture with Timer5 as the time base, a special event trigger to other modules, and an adjustable noise filter on each IC input. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing a time-out range from 4 ms to over 2 minutes, that is stable across operating voltage and temperature. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 1.3 Details on Individual Family Members The devices are differentiated from each other in three ways: Devices in the PIC18F2331/2431/4331/4431 family are available in 28-pin (PIC18F2X31) and 40/44-pin (PIC18F4X31) packages. The block diagram for the two groups is shown in Figure 1-1. 1. Flash program memory (8 Kbytes for PIC18F2X31 devices, 16 Kbytes for PIC18F4X31). A/D channels (5 for PIC18F2X31 devices, 9 for PIC18F4X31 devices). I/O ports (3 bidirectional ports on PIC18F2X31 devices, 5 bidirectional ports on PIC18F4X31 devices). 2. 3. All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. TABLE 1-1: DEVICE FEATURES Features PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431 DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHz Program Memory (Bytes) 8192 16384 8192 16384 Program Memory (Instructions) 4096 8192 4096 8192 Data Memory (Bytes) 768 768 768 768 Data EEPROM Memory (Bytes) 256 256 256 256 34 34 Operating Frequency Interrupt Sources 22 22 Ports A, B, C Ports A, B, C Timers 4 4 4 4 Capture/Compare/PWM modules 2 2 2 2 (6 Channels) (6 Channels) (8 Channels) (8 Channels) 1 QEI or 3x IC 1 QEI or 3x IC 1 QEI or 3x IC 1 QEI or 3x IC I/O Ports 14-bit Power Control PWM Motion Feedback module (Input Capture/Quadrature Encoder Interface) Serial Communications 10-bit High-Speed Analog-to-Digital Converter module Resets (and Delays) Ports A, B, C, D, E Ports A, B, C, D, E SSP, SSP, SSP, SSP, Enhanced USART Enhanced USART Enhanced USART Enhanced USART 5 Input Channels 5 Input Channels 9 Input Channels 9 Input Channels POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), WDT WDT WDT WDT Programmable Low-voltage Detect Yes Yes Yes Yes Programmable Brown-out Reset Yes Yes Yes Yes 75 Instructions 75 Instructions 75 Instructions 75 Instructions 28-pin SDIP 28-pin SOIC 40-pin DIP 44-pin TQFP 44-pin QFN 40-pin DIP 44-pin TQFP 44-pin QFN Instruction Set Packages 2003 Microchip Technology Inc. 28-pin SDIP 28-pin SOIC Preliminary DS39616B-page 9 PIC18F2331/2431/4331/4431 FIGURE 1-1: PIC18F2331/2431 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 21 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Latch Data RAM (768 bytes) inc/dec logic 21 Address Latch Address Latch 20 Program Memory PCLATU PCLATH 12 Address<12> PCU PCH PCL Program Counter 4 Data Latch 12 BSR 31 Level Stack 16 Decode TABLELATCH PORTB 4 FSR0 FSR1 FSR2 Bank0, F 12 inc/dec logic RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM RB6/KBI2/PGC RB7/KBI3/PGD 8 ROMLATCH PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0 RC4/INT1/SDI/SDA RC5/INT2/SCK/SCL RC6/TX/CK/SS RC7/RX/DT/SDO IR 8 Instruction Decode & Control PRODH PRODL 3 8 x 8 Multiply Power-up Timer OSC2/CLKO Timing Generation OSC1/CLKI T1OSI 8 Power-on Reset T1OSO 4X PLL Precision Band Gap Reference W 8 BITOP 8 Oscillator Start-up Timer 8 8 ALU<8> Watchdog Timer 8 Brown-out Reset PORTE Power Managed Mode Logic MCLR/VPP INTRC Timer0 Data EE Note 1: 2: MCLR/VPP/RE3(1, 2) OSC VDD, VSS Timer1 Timer2 CCP1 CCP2 Synchronous Serial Port Timer5 EUSART HS 10-bit ADC PCPWM AVDD, AVSS MFM RE3 input pin is only enabled when MCLRE fuse is programmed to ‘0’. RE3 is available only when MCLR is disabled. DS39616B-page 10 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 1-2: PIC18F4331/4431 BLOCK DIAGRAM Data Bus<8> PORTA 21 Table Pointer<21> 8 8 21 RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CAP1/INDX RA3/AN3/VREF+/CAP2/QEA RA4/AN4/CAP3/QEB RA5/AN5/LVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 Data Latch Data RAM (768 bytes) inc/dec logic 21 Address Latch Address Latch 20 Program Memory PCLATU PCLATH 12 Address<12> PCU PCH PCL Program Counter 4 Data Latch 12 BSR 31 Level Stack 16 Decode TABLELATCH PORTB 4 FSR0 FSR1 FSR2 Bank0, F 12 inc/dec logic RB0/PWM0 RB1/PWM1 RB2/PWM2 RB3/PWM3 RB4/KBI0/PWM5 RB5/KBI1/PWM4/PGM(4) RB6/KBI2/PGC RB7/KBI3/PGD 8 ROMLATCH PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2/FLTA(2) RC2/CCP1/FLTB RC3/T0CKI/T5CKI/INT0(3) RC4/INT1/SDI/SDA(3) RC5/INT2/SCK/SCL(3) RC6/TX/CK/SS RC7/RX/DT/SDO* IR 8 Instruction Decode & Control PRODH PRODL 3 OSC1/CLKI Timing Generation T1OSI T1OSO 4X PLL MCLR/VPP Note 1: 2: 3: 4: W 8 BITOP 8 Oscillator Start-up Timer PORTD 8 8 ALU<8> Watchdog Timer RD0/IT0CKI/T5CKI RD1/SDO RD2/SDI/SDA RD3/SCK/SCL RD4/FLTA(2) RD5/PWM4(4) RD6/PWM6 RD7/PWM7 8 Brown-out Reset PORTE Power Managed Mode Logic RE0/AN6 INTRC RE2/AN8 RE1/AN7 MCLR/VPP/RE3(1) OSC VDD, VSS Data EE 8 Power-on Reset Precision Band Gap Reference Timer0 8 x 8 Multiply Power-up Timer OSC2/CLKO Timer1 Timer2 CCP1 CCP2 Synchronous Serial Port Timer5 EUSART HS 10-bit ADC PCPWM AVDD, AVSS MFM RE3 is available only when MCLR is disabled. RD4 is the alternate pin for FLTA. RC3, RC4 and RC5 are alternate pins for T0CKI/T5CKI, SDI/SDA, SCK/SCL respectively. RD5 is the alternate pin for PWM4. 2003 Microchip Technology Inc. Preliminary DS39616B-page 11 PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Buffer Type Type Description DIP SOIC MCLR/VPP/RE3 MCLR VPP RE3 OSC1/CLKI/RA7 OSC1 1 1 I P I 9 9 I CLKI RA7 OSC2/CLKO/RA6 OSC2 I I/O 10 10 O CLKO O RA6 I/O Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. High-voltage ICSP programming enable pin. ST Digital input. Available only when MCLR is disabled. Oscillator crystal or external clock input. ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise. CMOS External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) TTL General purpose I/O pin. Oscillator crystal or clock output. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. — In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. TTL General purpose I/O pin. PORTA is a bidirectional I/O port. ST RA0/AN0 2 2 RA0 I/O TTL AN0 I Analog RA1/AN1 3 3 RA1 I/O TTL AN1 I Analog 4 RA2/AN2/VREF-/CAP1/INDX 4 TTL I/O RA2 I Analog AN2 I Analog VREFCAP1 I ST INDX I ST RA3/AN3/VREF+/CAP2/QEA 5 5 I/O RA3 TTL I AN3 Analog I VREF+ Analog CAP2 I ST QEA I ST RA4/AN4/CAP3/QEB 6 6 RA4 I/O TTL AN4 I Analog CAP3 I ST QEB I ST Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to VDD) DS39616B-page 12 Digital I/O. Analog input 0. Digital I/O. Analog input 1. Digital I/O. Analog input 2. A/D Reference Voltage (Low) input. Input capture pin 1. Quadrature Encoder Interface index input pin. Digital I/O. Analog input 3. A/D Reference Voltage (High) input. Input capture pin 2. Quadrature Encoder Interface channel A input pin. Digital I/O. Analog input 4. Input capture pin 3. Quadrature Encoder Interface channel B input pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type Description DIP SOIC PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/PWM0 21 21 RB0 I/O TTL PWM0 O TTL RB1/PWM1 22 22 RB1 I/O TTL PWM1 O TTL RB2/PWM2 23 23 RB2 I/O TTL PWM2 O TTL RB3/PWM3 24 24 RB3 I/O TTL PWM3 O TTL RB4/KBI0/PWM5 25 25 RB4 I/O TTL KBI0 I TTL PWM5 O TTL RB5/KBI1/PWM4/PGM 26 26 RB5 I/O TTL KBI1 I TTL PWM4 O TTL PGM I/O ST RB6/KBI2/PGC 27 27 RB6 TTL I/O KBI2 I TTL PGC I/O ST RB7/KBI3/PGD 28 28 RB7 I/O TTL KBI3 I TTL PGD I/O ST Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to VDD) 2003 Microchip Technology Inc. Digital I/O. PWM output 0. Digital I/O. PWM output 1. Digital I/O. PWM output 2. Digital I/O. PWM output 3. Digital I/O. Interrupt-on-change pin. PWM output 5. Digital I/O. Interrupt-on-change pin. PWM output 4. Low-voltage ICSP programming entry pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Preliminary DS39616B-page 13 PIC18F2331/2431/4331/4431 TABLE 1-2: PIC18F2331/2431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer Type Type Description DIP SOIC PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI 11 11 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T1CKI I ST Timer1 external clock input. RC1/T1OSI/CCP2/FLTA 12 12 I/O ST Digital I/O. RC1 I CMOS Timer1 oscillator input. T1OSI I/O ST Capture2 input, Compare2 output, PWM2 output. CCP2 I ST Fault interrupt input pin. FLTA RC2/CCP1/FLTB 13 13 I/O RC2 ST Digital I/O. I/O CCP1 ST Capture1 input/Compare1 output/PWM1 output. I FLTB ST Fault interrupt input pin,. RC3/T0CKI/T5CKI/INT0 14 14 RC3 I/O ST Digital I/O. T0CKI ST Timer0 alternate clock input. I T5CKI I ST Timer5 alternate clock input. INT0 External interrupt 0. I ST RC4/INT1/SDI/SDA 15 15 RC4 I/O ST Digital I/O. INT1 I ST External interrupt 1. SDI I ST SPI™ data in. SDA I/O ST I2C™ data I/O. RC5/INT2/SCK/SCL 16 16 RC5 I/O ST Digital I/O. INT2 I ST External interrupt 2. SCK I/O ST Synchronous serial clock input/output for SPI mode. SCL I/O ST Synchronous serial clock input/output for I2C mode. RC6/TX/CK/SS 17 17 RC6 I/O ST Digital I/O. TX O — USART Asynchronous Transmit. CK I/O ST USART Synchronous Clock (see related RX/DT). SS I TTL SPI Slave Select input. RC7/RX/DT/SDO 18 18 RC7 I/O ST Digital I/O. RX ST USART Asynchronous Receive. I DT I/O ST USART Synchronous Data (see related TX/CK). SDO O — SPI data out. 8, 19 8, 19 P — Ground reference for logic and I/O pins. VSS VDD 7, 20 7, 20 P — Positive supply for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power OD = Open-Drain (no diode to VDD) DS39616B-page 14 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS Pin Number Pin Buffer DIP TQFP QFN Type Type Pin Name MCLR/VPP/RE3 MCLR 1 18 18 I P I VPP RE3 OSC1/CLKI/RA7 OSC1 13 30 32 I I CLKI RA7 OSC2/CLKO/RA6 OSC2 I/O 14 31 33 O CLKO O RA6 I/O RA0/AN0 RA0 AN0 2 RA1/AN1 RA1 AN1 3 RA2/AN2/VREF-/CAP1/ INDX RA2 AN2 VREFCAP1 INDX 4 RA3/AN3/VREF+/ CAP2/QEA RA3 AN3 VREF+ CAP2 QEA 5 RA4/AN4/CAP3/QEB RA4 AN4 CAP3 QEB 6 RA5/AN5/LVDIN RA5 AN5 LVDIN Legend: TTL ST O OD 7 19 20 21 22 23 24 Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low. Reset to the device. Programming voltage input. Digital input. Available only when MCLR is disabled. ST Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST ST buffer when configured in RC mode, CMOS otherwise. External clock source input. Always associated with pin CMOS function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator — in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the — frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. TTL PORTA is a bidirectional I/O port. ST 19 I/O I TTL Analog Digital I/O. Analog input 0. I/O I TTL Analog Digital I/O. Analog input 1. I/O I I I I TTL Analog Analog ST ST Digital I/O. Analog input 2. A/D Reference Voltage (Low) input. Input capture pin 1. Quadrature Encoder Interface index input pin. I/O I I I I TTL Analog Analog ST ST Digital I/O. Analog input 3. A/D Reference Voltage (High) input. Input capture pin 2. Quadrature Encoder Interface channel A input pin. I/O I I I TTL Analog ST ST Digital I/O. Analog input 4. Input capture pin 3. Quadrature Encoder Interface channel B input pin. I/O I I TTL Analog Analog Digital I/O. Analog input 5. Low-voltage Detect input. CMOS = CMOS compatible input or output I = Input P = Power 20 21 22 23 24 = TTL compatible input = Schmitt Trigger input with CMOS levels = Output = Open-Drain (no diode to VDD) 2003 Microchip Technology Inc. Description Preliminary DS39616B-page 15 PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer DIP TQFP QFN Type Type Pin Name Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/PWM0 RB0 PWM0 33 RB1/PWM1 RB1 PWM1 34 RB2/PWM2 RB2 PWM2 35 RB3/PWM3 RB3 PWM3 36 RB4/KBI0/PWM5 RB4 KBI0 PWM5 37 RB5/KBI1/PWM4/ PGM RB5 KBI1 PWM4 PGM 38 RB6/KBI2/PGC RB6 KBI2 PGC 39 RB7/KBI3/PGD RB7 KBI3 PGD Legend: TTL ST O OD 40 DS39616B-page 16 8 9 10 11 14 15 16 17 9 I/O O TTL TTL Digital I/O. PWM output 0. I/O O TTL TTL Digital I/O. PWM output 1. I/O O TTL TTL Digital I/O. PWM output 2. I/O O TTL TTL Digital I/O. PWM output 3. I/O I O TTL TTL TTL Digital I/O. Interrupt-on-change pin. PWM output 5. I/O I O I/O TTL TTL TTL ST Digital I/O. Interrupt-on-change pin. PWM output 4. Low-voltage ICSP programming entry pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin. I/O I I/O TTL TTL ST Digital I/O. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power 10 11 12 14 15 16 17 = TTL compatible input = Schmitt Trigger input with CMOS levels = Output = Open-Drain (no diode to VDD) Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Name Pin Number Pin Buffer DIP TQFP QFN Type Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2/ FLTA RC1 T1OSI CCP2 FLTA 16 RC2/CCP1/FLTB RC2 CCP1 FLTB 17 RC3/T0CKI/T5CKI/ INT0 RC3 T0CKI T5CKI INT0 18 RC4/INT1/SDI/SDA RC4 INT1 SDI SDA 23 RC5/INT2/SCK/SCL RC5 INT2 SCK SCL 24 RC6/TX/CK/SS RC6 TX CK SS 25 32 35 36 37 42 43 44 34 I/O O I ST — ST I/O I I/O I ST CMOS ST ST Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. Fault interrupt input pin. I/O I/O I ST ST ST Digital I/O. Capture1 input/Compare1 output/PWM1 output. Fault interrupt input pin. I/O I I I ST ST ST ST Digital I/O. Timer0 alternate clock input. Timer5 alternate clock input. External interrupt 0. I/O I I I/O ST ST ST ST Digital I/O. External interrupt 1. SPI Data in. I2C Data I/O. I/O I I/O I/O ST ST ST ST Digital I/O. External interrupt 2. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. I/O O I/O I ST — ST ST Digital I/O. USART Asynchronous Transmit. USART Synchronous Clock (see related RX/DT). SPI Slave Select input. 35 36 37 42 43 44 RC7/RX/DT/SDO 26 1 1 RC7 I/O ST RX I ST DT I/O ST SDO O — Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-Drain (no diode to VDD) 2003 Microchip Technology Inc. Digital I/O. Timer1 oscillator output. Timer1 external clock input. Digital I/O. USART Asynchronous Receive. USART Synchronous Data (see related TX/CK). SPI Data out. CMOS = CMOS compatible input or output I = Input P = Power Preliminary DS39616B-page 17 PIC18F2331/2431/4331/4431 TABLE 1-3: PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer DIP TQFP QFN Type Type Pin Name Description PORTD is a bidirectional I/O port, or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled. RD0/T0CKI/T5CKI RD0 T0CKI T5CKI 19 RD1/SDO RD1 SDO 20 RD2/SDI/SDA RD2 SDI SDA 21 RD3/SCK/SCL RD3 SCK SCL 22 RD4/FLTA RD4 FLTA 27 RD5/PWM4 RD5 PWM4 28 RD6/PWM6 RD6 PWM6 29 RD7/PWM7 RD7 PWM7 Legend: TTL ST O OD 30 DS39616B-page 18 38 39 40 41 2 3 4 5 38 I/O I I ST ST ST Digital I/O. Timer0 external clock input. Timer5 input clock. I/O O ST — Digital I/O. SPI Data out. I/O I I/O ST ST ST Digital I/O. SPI Data in. I2C Data I/O. I/O I/O I/O ST ST ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2C mode. I/O I ST ST Digital I/O. Fault interrupt input pin. I/O O ST TTL Digital I/O. PWM output 4. I/O O ST TTL Digital I/O. PWM output 6. I/O O ST TTL Digital I/O. PWM output 7. CMOS = CMOS compatible input or output I = Input P = Power 39 40 41 2 3 4 5 = TTL compatible input = Schmitt Trigger input with CMOS levels = Output = Open-Drain (no diode to VDD) Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 1-3: Pin Name PIC18F4331/4431 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Buffer DIP TQFP QFN Type Type Description PORTE is a bidirectional I/O port. RE0/AN6 RE0 AN6 8 RE1/AN7 RE1 AN7 9 RE2/AN8 RE2 AN8 10 VSS 12, 31 VDD NC Legend: TTL ST O OD 25 26 27 25 ST Analog Digital I/O. Analog input 6. I/O I ST Analog Digital I/O. Analog input 7. I/O I ST Analog Digital I/O. Analog input 8. P — Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. 26 27 6, 29 6, 30, 31 11, 32 7, 28 I/O I 7, 8, 28, 29 — 12, 13 NC NC No connect 13, 33, 34 = TTL compatible input CMOS = Schmitt Trigger input with CMOS levels I = Output P = Open-Drain (no diode to VDD) 2003 Microchip Technology Inc. Preliminary = CMOS compatible input or output = Input = Power DS39616B-page 19 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 20 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types FIGURE 2-1: C1(1) The PIC18F2331/2431/4331/4431 devices can be operated in 10 different oscillator modes. The user can program the configuration bits FOSC3:FOSC0 in Configuration register 1H to select one of these 10 modes: 1. 2. 3. 4. LP XT HS HSPLL 5. RC 6. RCIO 7. INTIO1 8. INTIO2 9. EC 10. ECIO 2.2 Low-power Crystal Crystal/Resonator High-speed Crystal/Resonator High-speed Crystal/Resonator with PLL enabled External Resistor/Capacitor with FOSC/4 output on RA6 External Resistor/Capacitor with I/O on RA6 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 Internal Oscillator with I/O on RA6 and RA7 External Clock with FOSC/4 output External Clock with I/O on RA6 The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturers’ specifications. OSC1 XTAL To Internal Logic RF(3) Sleep RS(2) C2(1) Note 1: PIC18FXXXX OSC2 See Table 2-1 and Table 2-2 for initial values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the oscillator mode chosen. TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq OSC1 OSC2 XT 455 kHz 2.0 MHz 4.0 MHz 56 pF 47 pF 33 pF 56 pF 47 pF 33 pF HS 8.0 MHz 16.0 MHz 27 pF 22 pF 27 pF 22 pF Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HSPLL oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION) Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes on page 22 for additional information. Resonators Used: 455 kHz 4.0 MHz 2.0 MHz 8.0 MHz 16.0 MHz 2003 Microchip Technology Inc. Preliminary DS39616B-page 21 PIC18F2331/2431/4331/4431 Osc Type LP XT HS CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq 32 kHz Typical Capacitor Values Tested: C1 C2 33 pF 33 pF 200 kHz 15 pF 15 pF 1 MHz 33 pF 33 pF 4 MHz 27 pF 27 pF 4 MHz 27 pF 27 pF 8 MHz 22 pF 22 pF 20 MHz 15 pF 15 pF 2.3 Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 200 kHz 8 MHz 1 MHz 20 MHz OSC1 PIC18FXXXX OSC2 (HS Mode) HSPLL A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency crystal oscillator circuit, or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals. The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLL is enabled only when the oscillator configuration bits are programmed for HSPLL mode. If programmed for any other mode, the PLL is not enabled. Note 1: Higher capacitance increases the stability of oscillator, but also increases the startup time. FIGURE 2-3: 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application. DS39616B-page 22 EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) Open These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. 4 MHz FIGURE 2-2: Clock from Ext. System Capacitor values are for design guidance only. 32 kHz An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 2-2. Preliminary PLL BLOCK DIAGRAM HS Osc Enable PLL Enable (from Configuration Register 1H) OSC2 HS Mode OSC1 Crystal Osc FIN Phase Comparator FOUT Loop Filter ÷4 VCO MUX TABLE 2-2: SYSCLK 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.4 External Clock Input 2.5 The EC and ECIO oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-4 shows the pin connections for the EC Oscillator mode. FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX FOSC/4 OSC2/CLKO RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 2-6 shows how the R/C combination is connected. In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. FIGURE 2-6: The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows the pin connections for the ECIO Oscillator mode. RC OSCILLATOR MODE VDD REXT OSC1 Internal Clock CEXT FIGURE 2-5: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) PIC18FXXXX VSS FOSC/4 OSC2/CLKO Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) The RCIO Oscillator mode (Figure 2-7) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). FIGURE 2-7: RCIO OSCILLATOR MODE VDD REXT OSC1 Internal Clock CEXT PIC18FXXXX VSS RA6 I/O (OSC2) Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ CEXT > 20 pF 2003 Microchip Technology Inc. Preliminary DS39616B-page 23 PIC18F2331/2431/4331/4431 2.6 2.6.2 Internal Oscillator Block The PIC18F2331/2431/4331/4431 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system’s clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives a postscaler, which can provide a range of clock frequencies from 125 kHz to 4 MHz. The INTOSC output is enabled when a system clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC), which provides a 31 kHz output. The INTRC oscillator is enabled by selecting the internal oscillator block as the system clock source, or when any of the following are enabled: • • • • Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up These features are discussed in greater detail in Section 22.0 “Special Features of the CPU”. INTRC OUTPUT FREQUENCY The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. This changes the frequency of the INTRC source from its nominal 31.25 kHz. Peripherals and features that depend on the INTRC source will be affected by this shift in frequency. 2.6.3 OSCTUNE REGISTER The internal oscillator’s output has been calibrated at the factory, but can be adjusted in the user's application. This is done by writing to the OSCTUNE register (Register 2-1). The tuning sensitivity is constant throughout the tuning range. When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 µs = 256 µs). The INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (Register 2-2). 2.6.1 INTIO MODES Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: • In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. DS39616B-page 24 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 — bit 7 bit 7, 6 bit 5-0 U-0 — R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0 Unimplemented: Read as ‘0’ TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency • • • • 000001 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 • • • • 100000 = Minimum frequency Legend: R = Readable bit -n = Value at POR 2003 Microchip Technology Inc. W = Writable bit ‘1’ = Bit is set Preliminary U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DS39616B-page 25 PIC18F2331/2431/4331/4431 2.7 2.7.1 Clock Sources and Oscillator Switching Like previous PIC18 devices, the PIC18F2331/2431/ 4331/4431 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. PIC18F2331/2431/4331/4431 devices offer two alternate clock sources. When enabled, these give additional options for switching to the various powermanaged operating modes. Essentially, there are three clock sources for these devices: • Primary oscillators • Secondary oscillators • Internal oscillator block The primary oscillators include the external crystal and resonator modes, the external RC modes, the external clock modes and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Register 1H. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F2331/2431/4331/4431 devices offer only the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO and RC1/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 12.2 “Timer1 Oscillator”. In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F2331/2431/4331/ 4431 devices are shown in Figure 2-8. See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 22.1 “Configuration Bits” for Configuration register details. OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-2) controls several aspects of the system clock’s operation, both in full power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in power-managed modes. The available clock sources are the primary clock (defined in Configuration register 1H), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock selection has no effect until a SLEEP instruction is executed and the device enters a power-managed mode of operation. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). If the internal oscillator block is supplying the system clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the system clock. The OSTS indicates that the Oscillator Start-up Timer has timed out, and the primary clock is providing the system clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabilized, and is providing the system clock in RC clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the system clock in secondary clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the system clock, or the internal oscillator block has just started and is not yet stable. The IDLEN bit controls the selective shut down of the controller’s CPU in power-managed modes. The use of these bits is discussed in more detail in Section 3.0 “Power-Managed Modes” Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source when executing a SLEEP instruction will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before executing the SLEEP instruction, or a very long delay may occur while the Timer1 oscillator starts. DS39616B-page 26 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PIC18F2331/2431/4331/4431 CLOCK DIAGRAM Primary Oscillator PIC18F2331/2431/4331/4431 C4NFIG1H <3:0> OSC2 LP, XT, HS, RC, EC OSC1 Secondary Oscillator T1OSC T1OSO T1OSI OSCCON<1:0> HSPLL 4 x PLL Sleep Clock Control Clock Source Option for Other Modules T1OSCEN Enable Oscillator OSCCON<6:4> 8 MHz OSCCON<6:4> MUX FIGURE 2-8: Peripherals Internal Oscillator CPU 111 4 MHz 110 Internal Oscillator Block 100 500 kHz 250 kHz 125 kHz 31 kHz 2003 Microchip Technology Inc. IDLEN 101 1 MHz 011 MUX 8 MHz (INTOSC) Postscaler INTRC Source 2 MHz 010 001 000 Preliminary WDT, FSCM DS39616B-page 27 PIC18F2331/2431/4331/4431 REGISTER 2-2: OSCCON REGISTER R/W-0 IDLEN bit 7 bit 7 bit 6-4 bit 3 bit 2 bit 1-0 R/W-0 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 R(1) OSTS R-0 IOFS R/W-0 SCS1 R/W-0 SCS0 bit 0 IDLEN: Idle Enable bit 1 = Idle mode enabled; CPU core is not clocked in power-managed modes 0 = Run mode enabled; CPU core is clocked in power-managed modes IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (8 MHz source drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (INTRC source drives clock directly) OSTS: Oscillator Start-up Time-out Status bit 1 = Oscillator start-up time-out timer has expired; primary oscillator is running 0 = Oscillator start-up time-out timer is running; primary oscillator is not ready IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block (RC modes) 01 = Timer1 oscillator (Secondary modes) 00 = Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on state of the IESO bit in Configuration Register 1H. Legend: R = Readable bit - n = Value at POR 2.7.2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown OSCILLATOR TRANSITIONS The PIC18F2331/2431/4331/4431 devices contain circuitry to prevent clocking “glitches” when switching between clock sources. A short pause in the system clock occurs during the clock switch. The length of this pause is between 8 and 9 clock periods of the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Clock transitions are discussed in greater detail in Section 3.1.2 “Entering Power-Managed Modes”. DS39616B-page 28 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 2.8 Effects of Power-Managed Modes on the Various Clock Sources When the device executes a SLEEP instruction, the system is switched to one of the power-managed modes, depending on the state of the IDLEN and SCS1:SCS0 bits of the OSCCON register. See Section 3.0 “Power-Managed Modes” for details. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the system clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the system clock source. The INTRC output can be used directly to provide the system clock, and may be enabled to support various special features, regardless of the power-managed mode (see Sections 22.2 through 22.4). The INTOSC output at 8 MHz may be used directly to clock the system, or may be divided down first. The INTOSC output is disabled if the system clock is provided directly from the INTRC output. 2.9 Power-up Delays Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances, and the primary clock is operating and stable. For additional information on power-up delays, see Sections 4.1 through 4.5. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 25-8), if enabled, in Configuration register 2L. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of 5 to 10 µs following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a realtime clock. Other features may be operating that do not require a system clock source (i.e., SSP slave, PSP, INTn pins, A/D conversions and others). TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTIO1 Floating, external resistor should pull high At logic low (clock/4 output) RCIO, INTIO2 Floating, external resistor should pull high Configured as PORTA, bit 6 ECIO Floating, pulled by external clock Configured as PORTA, bit 6 EC Floating, pulled by external clock At logic low (clock/4 output) LP, XT, and HS Feedback inverter disabled, at quiescent voltage level Feedback inverter disabled, at quiescent voltage level Note: See Table 4-1 in the Section 4.0 “Reset”, for time-outs due to Sleep and MCLR Reset. 2003 Microchip Technology Inc. Preliminary DS39616B-page 29 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 30 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.0 POWER-MANAGED MODES 3.1 Selecting Power-Managed Modes The PIC18F2331/2431/4331/4431 devices offer a total of six operating modes for more efficient power management (see Table 3-1). These operating modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). Selecting a power-managed mode requires deciding if the CPU is to be clocked or not, and selecting a clock source. The IDLEN bit controls CPU clocking, while the SC1:SCS0 bits select a clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 3-1. There are three categories of power-managed modes: 3.1.1 • Sleep mode • Idle modes • Run modes CLOCK SOURCES The clock source is selected by setting the SCS bits of the OSCCON register. Three clock sources are available for use in power-managed idle modes: the primary clock (as configured in Configuration Register 1H), the secondary clock (Timer1 oscillator), and the internal oscillator block. The secondary and internal oscillator block sources are available for the power-managed modes (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source). These categories define which portions of the device are clocked and sometimes, what speed. The run and idle modes may use any of the three available clock sources (Primary, Secondary or INTOSC multiplexer); the Sleep mode does not use a clock source. The clock switching feature offered in other PIC18 devices (i.e., using the Timer1 oscillator in place of the primary oscillator), and the Sleep mode offered by all PICmicro® devices (where all system clocks are stopped) are both offered in the PIC18F2331/2431/ 4331/4431 devices (SEC_RUN and Sleep modes, respectively). However, additional power-managed modes are available that allow the user greater flexibility in determining what portions of the device are operating. The power-managed modes are event driven; that is, some specific event must occur for the device to enter or (more particularly) exit these operating modes. For PIC18F2331/2431/4331/4431 devices, the powermanaged modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when triggered by an interrupt, a Reset or a WDT timeout (PRI_RUN mode is the normal full power execution mode; the CPU and peripherals are clocked by the primary oscillator source). In addition, power-managed run modes may also exit to Sleep mode or their corresponding idle mode. TABLE 3-1: POWER-MANAGED MODES OSCCON bits Mode Sleep Module Clocking Available Clock and Oscillator Source IDLEN <7> SCS1:SCS0 <1:0> 0 00 Off Off Clocked CPU Peripherals None – All clocks are disabled Primary – LP, XT, HS, HSPLL, RC, EC, INTRC(1) This is the normal full power execution mode. PRI_RUN 0 00 Clocked SEC_RUN 0 01 Clocked Clocked Secondary – Timer1 Oscillator RC_RUN 0 1x Clocked Clocked Internal Oscillator Block(1) PRI_IDLE 1 00 Off Clocked Primary – LP, XT, HS, HSPLL, RC, EC SEC_IDLE 1 01 Off Clocked Secondary – Timer1 Oscillator RC_IDLE 1 1x Off Clocked Internal Oscillator Block(1) Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. 2003 Microchip Technology Inc. Preliminary DS39616B-page 31 PIC18F2331/2431/4331/4431 3.1.2 ENTERING POWER-MANAGED MODES In general, entry, exit and switching between powermanaged clock sources requires clock source switching. In each case, the sequence of events is the same. Any change in the power-managed mode begins with loading the OSCCON register and executing a SLEEP instruction. The SCS1:SCS0 bits select one of three power-managed clock sources; the primary clock (as defined in Configuration Register 1H), the secondary clock (the Timer1 oscillator) and the internal oscillator block (used in RC modes). Modifying the SCS bits will have no effect until a SLEEP instruction is executed. Entry to the power-managed mode is triggered by the execution of a SLEEP instruction. Figure 3-5 shows how the system is clocked while switching from the primary clock to the Timer1 oscillator. When the SLEEP instruction is executed, clocks to the device are stopped at the beginning of the next instruction cycle. Eight clock cycles from the new clock source are counted to synchronize with the new clock source. After eight clock pulses from the new clock source are counted, clocks from the new clock source resume clocking the system. The actual length of the pause is between eight and nine clock periods from the new clock source. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. Three bits indicate the current clock source: OSTS and IOFS in the OSCCON register, and T1RUN in the T1CON register. Only one of these bits will be set while in a power-managed mode other than PRI_RUN. When the OSTS bit is set, the primary clock is providing the system clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source and is providing the system clock. When the T1RUN bit is set, the Timer1 oscillator is providing the system clock. If none of these bits are set, then either the INTRC clock source is clocking the system, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source in Configuration Register 1H, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering an RC power-managed mode (same frequency) would clear the OSTS bit. DS39616B-page 32 Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode; executing a SLEEP instruction is simply a trigger to place the controller into a power-managed mode selected by the OSCCON register, one of which is Sleep mode. 3.1.3 MULTIPLE SLEEP COMMANDS The power-managed mode that is invoked with the SLEEP instruction is determined by the settings of the IDLEN and SCS bits at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by these same bits at that time. If the bits have changed, the device will enter the new power-managed mode specified by the new bit settings. 3.1.4 COMPARISONS BETWEEN RUN AND IDLE MODES Clock source selection for the run modes is identical to the corresponding idle modes. When a SLEEP instruction is executed, the SCS bits in the OSCCON register are used to switch to a different clock source. As a result, if there is a change of clock source at the time a SLEEP instruction is executed, a clock switch will occur. In idle modes, the CPU is not clocked and is not running. In run modes, the CPU is clocked and executing code. This difference modifies the operation of the WDT when it times out. In idle modes, a WDT time-out results in a wake from power-managed modes. In run modes, a WDT time-out results in a WDT Reset (see Table 3-2). During a wake-up from an idle mode, the CPU starts executing code by entering the corresponding run mode, until the primary clock becomes ready. When the primary clock becomes ready, the clock source is automatically switched to the primary clock. The IDLEN and SCS bits are unchanged during and after the wake-up. Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode). Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 3-2: Power Managed Mode COMPARISON BETWEEN POWER-MANAGED MODES CPU is clocked by ... WDT time-out causes a ... Peripherals are clocked by ... Clock during wake-up (while primary becomes ready) Sleep Not clocked (not running) Wake-up Not clocked None or INTOSC multiplexer if Two-Speed Start-up or Fail-Safe Clock Monitor are enabled. Any idle mode Not clocked (not running) Wake-up Primary, Secondary or INTOSC multiplexer Unchanged from Idle mode (CPU operates as in corresponding Run mode). Any run mode Secondary, or INTOSC multiplexer Secondary or INTOSC multiplexer Unchanged from Run mode. 3.2 Reset Sleep Mode 3.3 Idle Modes The power-managed Sleep mode in the PIC18F2331/ 2431/4331/4431 devices is identical to that offered in all other PICmicro® controllers. It is entered by clearing the IDLEN and SCS1:SCS0 bits (this is the Reset state), and executing the SLEEP instruction. This shuts down the primary oscillator and the OSTS bit is cleared (see Figure 3-1). The IDLEN bit allows the controller’s CPU to be selectively shut down while the peripherals continue to operate. Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-2). The peripherals continue to be clocked regardless of the setting of the IDLEN bit. When a wake event occurs in Sleep mode (by interrupt, Reset, or WDT time-out), the system will not be clocked until the primary clock source becomes ready (see Figure 3-2), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the FailSafe Clock Monitor are enabled (see Section 22.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock provides the system clocks. The IDLEN and SCS bits are not affected by the wake-up. There is one exception to how the IDLEN bit functions. When all the low-power OSCCON bits are cleared (IDLEN:SCS1:SCS0 = 000), the device enters Sleep mode upon the execution of the SLEEP instruction. This is both the Reset state of the OSCCON register and the setting that selects Sleep mode. This maintains compatibility with other PICmicro devices that do not offer power-managed modes. If the Idle Enable bit, IDLEN (OSCCON<7>), is set to a ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. Since the CPU is not executing instructions, the only exits from any of the idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed approximately 10 µs while it becomes ready to execute code. When the CPU begins executing code, it is clocked by the same clock source as was selected in the power-managed mode (i.e., when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals until the primary clock source becomes ready – this is essentially RC_RUN mode). This continues until the primary clock source becomes ready. When the primary clock becomes ready, the OSTS bit is set, and the system clock source is switched to the primary clock (see Figure 3-4). The IDLEN and SCS bits are not affected by the wake-up. While in any idle mode or the Sleep mode, a WDT timeout will result in a WDT wake-up to full power operation. 2003 Microchip Technology Inc. Preliminary DS39616B-page 33 PIC18F2331/2431/4331/4431 FIGURE 3-1: TIMING TRANSITION FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC FIGURE 3-2: PC + 2 TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event Note 1: PC + 2 PC + 4 PC + 6 PC + 8 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39616B-page 34 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.3.1 PRI_IDLE MODE This mode is unique among the three low-power idle modes, in that it does not disable the primary system clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. When a wake event occurs, the CPU is clocked from the primary clock source. A delay of approximately 10 µs is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 3-4). PRI_IDLE mode is entered by setting the IDLEN bit, clearing the SCS bits, and executing a SLEEP instruction. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified in Configuration Register 1H. The OSTS bit remains set in PRI_IDLE mode (see Figure 3-3). FIGURE 3-3: TRANSITION TIMING TO PRI_IDLE MODE Q1 Q3 Q2 Q4 Q1 OSC1 CPU Clock Peripheral Clock Program Counter FIGURE 3-4: PC PC + 2 TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE Q1 Q3 Q2 Q4 OSC1 CPU Start-up Delay CPU Clock Peripheral Clock Program Counter PC + 2 PC Wake Event 2003 Microchip Technology Inc. Preliminary DS39616B-page 35 PIC18F2331/2431/4331/4431 3.3.2 SEC_IDLE MODE When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After a 10 µs delay following the wake event, the CPU begins executing code, being clocked by the Timer1 oscillator. The microcontroller operates in SEC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. In SEC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered by setting the Idle bit, modifying to SCS1:SCS0 = 01, and executing a SLEEP instruction. When the clock source is switched (see Figure 3-5) to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, a forced NOP will be executed instead and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started; in such situations, initial oscillator operation is far from stable and unpredictable operation may result. FIGURE 3-5: TIMING TRANSITION FOR ENTRY TO SEC_IDLE MODE Q1 Q2 Q3 Q4 Q1 1 T1OSI 2 3 4 5 6 Clock Transition 7 8 OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-6: PC + 2 TIMING TRANSITION FOR WAKE FROM SEC_RUN MODE (HSPLL) Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 T1OSI OSC1 TOST(1) TPLL(1) PLL Clock Output 1 2 3 4 5 6 Clock Transition 7 8 CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note 1: PC + 4 PC + 2 PC + 6 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39616B-page 36 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.3.3 RC_IDLE MODE was executed, and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. In RC_IDLE mode, the CPU is disabled, but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a 10 µs delay following the wake event, the CPU begins executing code, being clocked by the INTOSC multiplexer. The microcontroller operates in RC_RUN mode until the primary clock becomes ready. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set, and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. This mode is entered by setting the IDLEN bit, setting SCS1 (SCS0 is ignored), and executing a SLEEP instruction. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer (see Figure 3-7), the primary oscillator is shut down, and the OSTS bit is cleared. If the IRCF bits are set to a non-zero value (thus enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable, in about 1 ms. Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value before the SLEEP instruction FIGURE 3-7: TIMING TRANSITION TO RC_IDLE MODE Q1 Q2 Q3 Q4 Q1 1 INTRC 2 3 4 5 6 7 8 Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC FIGURE 3-8: PC + 2 TIMING TRANSITION FOR WAKE FROM RC_RUN MODE (RC_RUN TO PRI_RUN) Q4 Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) PLL Clock Output 1 2 3 4 5 6 Clock Transition 7 8 CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note 1: PC + 4 PC + 2 PC + 6 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2003 Microchip Technology Inc. Preliminary DS39616B-page 37 PIC18F2331/2431/4331/4431 3.4 Run Modes SEC_RUN mode is entered by clearing the IDLEN bit, setting SCS1:SCS0 = 01, and executing a SLEEP instruction. The system clock source is switched to the Timer1 oscillator (see Figure 3-9), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. If the IDLEN bit is clear when a SLEEP instruction is executed, the CPU and peripherals are both clocked from the source selected using the SCS1:SCS0 bits. While these operating modes may not afford the power conservation of Idle or Sleep modes, they do allow the device to continue executing instructions by using a lower frequency clock source. RC_RUN mode also offers the possibility of executing code at a frequency greater than the primary clock. Note: Wake-up from a power-managed run mode can be triggered by an interrupt, or any Reset, to return to full power operation. As the CPU is executing code in run modes, several additional exits from run modes are possible. They include exit to Sleep mode, exit to a corresponding idle mode, and exit by executing a RESET instruction. While the device is in any of the powermanaged run modes, a WDT time-out will result in a WDT Reset. 3.4.1 When a wake event occurs, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set, and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. PRI_RUN MODE The PRI_RUN mode is the normal full power execution mode. If the SLEEP instruction is never executed, the microcontroller operates in this mode (a SLEEP instruction is executed to enter all other power-managed modes). All other power-managed modes exit to PRI_RUN mode when an interrupt or WDT time-out occur. Firmware can force an exit from SEC_RUN mode. By clearing the T1OSCEN bit (T1CON<3>), an exit from SEC_RUN back to normal full power operation is triggered. The Timer1 oscillator will continue to run and provide the system clock even though the T1OSCEN bit is cleared. The primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the primary clock provides the system clock. The IDLEN and SCS bits are not affected by the wake-up. There is no entry to PRI_RUN mode. The OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 2.7.1 “Oscillator Control Register”). 3.4.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. FIGURE 3-9: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, a forced NOP will be executed instead and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, system clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. TIMING TRANSITION FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 T1OSI 2 3 4 5 6 Clock Transition 7 Q3 Q4 Q1 Q2 Q3 8 OSC1 CPU Clock Peripheral Clock Program Counter PC DS39616B-page 38 PC + 2 Preliminary PC + 2 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.4.3 RC_RUN MODE Note: In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer, and the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the run modes, while still executing code. This mode works well for user applications that are not highly timing sensitive, or do not require high-speed clocks at all times. If the IRCF bits are all clear, the INTOSC output is not enabled, and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the system clocks. If the primary clock source is the internal oscillator block (either of the INTIO1 or INTIO2 oscillators), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to, and exit from, RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended. If the IRCF bits are changed from all clear (thus enabling the INTOSC output), the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the system continue while the INTOSC source stabilizes in approximately 1 ms. If the IRCF bits were previously at a non-zero value before the SLEEP instruction was executed, and the INTOSC source was already stable, the IOFS bit will remain set. This mode is entered by clearing the IDLEN bit, setting SCS1 (SCS0 is ignored) and executing a SLEEP instruction. The IRCF bits may select the clock frequency before the SLEEP instruction is executed. When the clock source is switched to the INTOSC multiplexer (see Figure 3-10), the primary oscillator is shut down and the OSTS bit is cleared. When a wake event occurs, the system continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-8). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock provides the system clock. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. The IRCF bits may be modified at any time to immediately change the system clock speed. Executing a SLEEP instruction is not required to select a new clock frequency from the INTOSC multiplexer. FIGURE 3-10: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. TIMING TRANSITION TO RC_RUN MODE Q4 Q1 Q2 Q3 Q4 Q1 1 INTRC Q2 2 3 4 5 6 7 Q3 Q4 Q1 Q2 Q3 8 Clock Transition OSC1 CPU Clock Peripheral Clock Program Counter PC 2003 Microchip Technology Inc. PC + 2 Preliminary PC + 4 DS39616B-page 39 PIC18F2331/2431/4331/4431 3.4.4 EXIT TO IDLE MODE 3.5 An exit from a power-managed run mode to its corresponding idle mode is executed by setting the IDLEN bit and executing a SLEEP instruction. The CPU is halted at the beginning of the instruction following the SLEEP instruction. There are no changes to any of the clock source status bits (OSTS, IOFS, or T1RUN). While the CPU is halted, the peripherals continue to be clocked from the previously selected clock source. An exit from any of the power-managed modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Sections 3.2 through 3.4). Note: 3.4.5 EXIT TO SLEEP MODE An exit from a power-managed run mode to Sleep mode is executed by clearing the IDLEN and SCS1:SCS0 bits and executing a SLEEP instruction. The code is no different than the method used to invoke Sleep mode from the normal operating (full power) mode. The primary clock and internal oscillator block are disabled. The INTRC will continue to operate if the WDT is enabled. The Timer1 oscillator will continue to run, if enabled, in the T1CON register. All clock source status bits are cleared (OSTS, IOFS and T1RUN). DS39616B-page 40 Wake From Power-Managed Modes If application code is timing sensitive, it should wait for the OSTS bit to become set before continuing. Use the interval during the Low-power exit sequence (before OSTS is set) to perform timing insensitive “housekeeping” tasks. Device behavior during Low-power mode exits is summarized in Table 3-3. 3.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit a power-managed mode and resume full power operation. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. On all exits from Low-power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock in PowerManaged Mode Primary System Clock LP, XT, HS Primary System HSPLL Clock (1) (PRI_IDLE mode) EC, RC, INTRC (2) INTOSC LP, XT, HS HSPLL T1OSC or INTRC(1) (2) LP, XT, HS HSPLL INTOSC(2) INTOSC (2) LP, XT, HS Sleep mode HSPLL EC, RC, INTRC(1) INTOSC(2) Note 1: 2: 3: 4: 5: 5-10 µs(5) — Activity During Wake from Power-Managed Mode Exit by Interrupt CPU and peripherals clocked by primary clock and executing instructions. Exit by Reset Not clocked, or Two-Speed Start-up (if enabled)(3). IOFS OST OSTS 5-10 µs(5) — 1 ms(4) IOFS OST OST + 2 ms EC, RC, INTRC(1) Clock Ready Status bit (OSCCON) OSTS OST + 2 ms EC, RC, INTRC(1) INTOSC PowerManaged Mode Exit Delay OSTS 5-10 µs(5) — None IOFS OST OST + 2 ms 5-10 µs(5) 1 ms(4) OSTS — IOFS CPU and peripherals clocked by selected power-managed mode clock and executing instructions until primary clock source becomes ready. Not clocked or Two-Speed Start-up (if enabled) until primary clock source becomes ready(3). In this instance, refers specifically to the INTRC clock source. Includes both the INTOSC 8 MHz source and postscaler derived frequencies. Two-Speed Start-up is covered in greater detail in Section 22.3 “Two-Speed Start-up”. Execution continues during the INTOSC stabilization period. Required delay when waking from Sleep and all idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). 2003 Microchip Technology Inc. Preliminary DS39616B-page 41 PIC18F2331/2431/4331/4431 3.5.2 EXIT BY RESET 3.5.4 Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock (defined in Configuration register 1H) becomes ready. At that time, the OSTS bit is set and the device begins executing code. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 22.3 “Two-Speed Start-up”) or Fail-Safe Clock Monitor (see Section 22.4 “Fail-Safe Clock Monitor”) are enabled in Configuration Register 1H, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Since the OSCCON register is cleared following all Resets, the INTRC clock source is selected. A higher speed clock may be selected by modifying the IRCF bits in the OSCCON register. Execution is clocked by the internal oscillator block until either the primary clock becomes ready, or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down. 3.5.3 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all idle modes and Sleep mode), the time-out will result in a wake from the power-managed mode (see Section 3.2 “Sleep Mode” through Section 3.4 “Run Modes”). If the device is executing code (all run modes), the time-out will result in a WDT Reset (see Section 22.2 “Watchdog Timer (WDT)”). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled), and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the system clock source. DS39616B-page 42 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. These are: • PRI_IDLE mode where the primary clock source is not stopped; and • the primary clock source is not any of LP, XT, HS or HSPLL modes. In these cases, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC, and INTIO oscillator modes). However, a fixed delay (approximately 10 µs) following the wake event is required when leaving Sleep and idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 3.6 INTOSC Frequency Drift The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has the side effect that the INTRC clock source frequency is also affected. However, the features that use the INTRC source often do not require an exact frequency. These features include the Fail-Safe Clock Monitor, the Watchdog Timer and the RC_RUN/RC_IDLE modes when the INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made, and in some cases, how large a change is needed. Three examples follow, but other techniques may be used. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 3.6.1 EXAMPLE – USART 3.6.3 An adjustment may be indicated when the USART begins to generate framing errors, or receives data with errors while in Asynchronous mode. Framing errors indicate that the system clock frequency is too high – try decrementing the value in the OSCTUNE register to reduce the system clock frequency. Errors in data may suggest that the system clock speed is too low – increment OSCTUNE. 3.6.2 EXAMPLE – TIMERS This technique compares system clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. 2003 Microchip Technology Inc. EXAMPLE – CCP IN CAPTURE MODE A CCP module can use free running Timer1, clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is much greater than the calculated time, the internal oscillator block is running too fast – decrement OSCTUNE. If the measured time is much less than the calculated time, the internal oscillator block is running too slow – increment OSCTUNE. Preliminary DS39616B-page 43 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 44 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 4.0 RESET The PIC18F2331/2431/4331/4431 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 4-1. The enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. FIGURE 4-1: Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 4-2. These bits are used in software to determine the nature of the Reset. See Table 4-3 for a full description of the Reset states of all registers. The MCLR pin is not driven low by any internal Resets, including the WDT. The MCLR input provided by the MCLR pin can be disabled with the MCLRE bit in Configuration Register 3H (CONFIG3H<7>). See Section 22.1 “Configuration Bits” for more information. SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Stack Pointer Stack Full/Underflow Reset External Reset MCLRE MCLR ( )_IDLE Sleep WDT Time-out VDD Rise Detect POR Pulse VDD Brown-out Reset S BOREN OST/PWRT OST 1024 Cycles Chip_Reset 10-bit Ripple Counter R Q OSC1 32 µs INTRC(1) PWRT 65.5 ms 11-bit Ripple Counter Enable PWRT Enable OST(2) Note 1: 2: This is the INTRC source from the internal oscillator block, and is separate from the RC oscillator of the CLKI pin. See Table 4-1 for time-out situations. 2003 Microchip Technology Inc. Preliminary DS39616B-page 45 PIC18F2331/2431/4331/4431 4.1 Power-on Reset (POR) 4.3 A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin through a resistor (1k to 10 kΩ) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 4-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. FIGURE 4-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) D R R1 MCLR C PIC18FXXXX Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 kΩ is recommended to make sure that the voltage drop across R does not violate the device’s electrical specification. 3: R1 ≥ 1 kΩ will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 4.2 Power-up Timer (PWRT) The Power-up Timer (PWRT) of the PIC18F2331/2431/ 4331/4431 devices is an 11-bit counter, which uses the INTRC source as the clock input. This yields a count of 2048 x 32 µs = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC parameter #33 for details. The PWRT is enabled by clearing configuration bit PWRTEN. DS39616B-page 46 The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes, and only on Power-on Reset or on exit from most power-managed modes. 4.4 PLL Lock Time-out With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A portion of the Powerup Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out. 4.5 VDD VDD Oscillator Start-up Timer (OST) Brown-out Reset (BOR) A configuration bit, BOREN, can disable (if clear/ programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below VBOR (parameter D005) for greater than TBOR (parameter #35), the brown-out situation will reset the chip. A Reset may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay TPWRT (parameter #33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. Enabling BOR Reset does not automatically enable the PWRT. 4.6 Time-out Sequence On power-up, the time-out sequence is as follows: First, after the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figures 4-3 through 4-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 4-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel. Table 4-2 shows the Reset conditions for some Special Function registers, while Table 4-3 shows the Reset conditions for all the registers. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 4-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) and Brown-out Oscillator Configuration PWRTEN = 1 Exit from Power-Managed Mode 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) PWRTEN = 0 HSPLL 66 ms(1) + 1024 TOSC + 2 ms (1) HS, XT, LP 66 ms (2) 1024 TOSC 1024 TOSC (1) — — RC, RCIO 66 ms(1) — — INTIO1, INTIO2 66 ms(1) — — EC, ECIO Note 1: 2: + 1024 TOSC 66 ms 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2 ms is the nominal time required for the 4x PLL to lock. REGISTER 4-1: RCON REGISTER BITS AND POSITIONS R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-1 R/W-1 IPEN — — RI TO PD POR BOR bit 7 Note: TABLE 4-2: bit 0 Refer to Section 5.14 “RCON Register” for bit definitions. STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter RCON Register RI TO PD POR BOR STKFUL STKUNF Power-on Reset 0000h 0--1 1100 1 1 1 0 0 0 0 RESET Instruction 0000h 0--0 uuuu 0 u u u u u u Brown-out 0000h 0--1 11u- 1 1 1 u 0 u u MCLR during power-managed run modes 0000h 0--u 1uuu u 1 u u u u u MCLR during power-managed idle modes and Sleep 0000h 0--u 10uu u 1 0 u u u u WDT Time-out during full power or power-managed Run 0000h 0--u 0uuu u 0 u u u u u u u 1 u u 1 Condition MCLR during full power execution Stack Full Reset (STVREN = 1) 0000h 0--u uuuu u u u u u Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) 0000h u--u uuuu u u u u u u 1 WDT Time-out during powermanaged Idle or Sleep PC + 2 u--u 00uu u 0 0 u u u u PC + 2(1) u--u u0uu u u 0 u u u u Interrupt Exit from power-managed modes Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’. Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2003 Microchip Technology Inc. Preliminary DS39616B-page 47 PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets TOSU 2331 2431 4331 4431 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu(3) TOSL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 2331 2431 4331 4431 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu PCLATH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PCL 2331 2431 4331 4431 0000 0000 0000 0000 PC + 2(2) TBLPTRU 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu TBLPTRH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TBLPTRL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TABLAT 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PRODH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 2331 2431 4331 4431 0000 000x 0000 000u uuuu uuuu(1) INTCON2 2331 2431 4331 4431 1111 -1-1 1111 -1-1 uuuu -u-u(1) INTCON3 2331 2431 4331 4431 11-0 0-00 11-0 0-00 uu-u u-uu(1) INDF0 2331 2431 4331 4431 N/A N/A Register Wake-up via WDT or Interrupt N/A POSTINC0 2331 2431 4331 4431 N/A N/A N/A POSTDEC0 2331 2431 4331 4431 N/A N/A N/A PREINC0 2331 2431 4331 4431 N/A N/A N/A PLUSW0 2331 2431 4331 4431 N/A N/A N/A FSR0H 2331 2431 4331 4431 ---- xxxx ---- uuuu ---- uuuu FSR0L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu WREG 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 2331 2431 4331 4431 N/A N/A N/A POSTINC1 2331 2431 4331 4431 N/A N/A N/A POSTDEC1 2331 2431 4331 4431 N/A N/A N/A PREINC1 2331 2431 4331 4431 N/A N/A N/A PLUSW1 2331 2431 4331 4431 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. DS39616B-page 48 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H 2331 2431 4331 4431 ---- xxxx ---- uuuu ---- uuuu FSR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu BSR 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu INDF2 2331 2431 4331 4431 N/A N/A N/A Register POSTINC2 2331 2431 4331 4431 N/A N/A N/A POSTDEC2 2331 2431 4331 4431 N/A N/A N/A PREINC2 2331 2431 4331 4431 N/A N/A N/A PLUSW2 2331 2431 4331 4431 N/A N/A N/A FSR2H 2331 2431 4331 4431 ---- xxxx ---- uuuu ---- uuuu FSR2L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 2331 2431 4331 4431 ---x xxxx ---u uuuu ---u uuuu TMR0H 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TMR0L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 2331 2431 4331 4431 11-- 1111 11-- 1111 uu-- uuuu OSCCON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu LVDCON 2331 2431 4331 4431 --00 0101 --00 0101 --uu uuuu WDTCON 2331 2431 4331 4431 ---- ---0 ---- ---0 ---- ---u RCON(4) 2331 2431 4331 4431 0--1 11q0 0--q qquu u--u qquu TMR1H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 2331 2431 4331 4431 0000 0000 u0uu uuuu uuuu uuuu TMR2 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PR2 2331 2431 4331 4431 1111 1111 1111 1111 1111 1111 T2CON 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu SSPBUF 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SSPSTAT 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SSPCON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. Preliminary DS39616B-page 49 PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADRESH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu ADCON1 2331 2431 4331 4431 00-0 1000 00-- 1000 uu-u uuuu ADCON2 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu CCPR1H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu CCPR2H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu ANSEL0 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu ANSEL1 2331 2431 4331 4431 ---- ---0 ---- ---0 ---- ---u T5CON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu QEICON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SPBRGH 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SPBRG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu RCREG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TXREG 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TXSTA 2331 2431 4331 4431 0000 -010 0000 -010 uuuu -uuu RCSTA 2331 2431 4331 4431 0000 000x 0000 000x uuuu uuuu BAUDCTL 2331 2431 4331 4431 -1-1 0-00 -1-1 0-00 -u-u u-uu EEADR 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu EEDATA 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu EECON1 2331 2431 4331 4431 xx-0 x000 uu-0 u000 uu-0 u000 EECON2 2331 2431 4331 4431 0000 0000 0000 0000 0000 0000 IPR3 2331 2431 4331 4431 ---1 1111 ---1 1111 ---u uuuu PIE3 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu PIR3 2331 2431 4331 4431 ---0 0000 ---0 0000 ---u uuuu Register Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. DS39616B-page 50 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt IPR2 2331 2431 4331 4431 1--1 -1-1 1--1 -1-1 u--u -u-u PIR2 2331 2431 4331 4431 0--0 -0-0 0--0 -0-0 u--u -u-u Register PIE2 IPR1 PIR1 PIE1 2331 2431 4331 4431 0--0 -0-0 0--0 -0-0 u--u -u-u 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu 2331 2431 4331 4431 -111 1111 -111 1111 -uuu uuuu 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu(1) 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu(1) 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu ADCON3 2331 2431 4331 4431 00-0 0000 00-0 0000 uu-u uuuu ADCHS 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu TRISE(6) 2331 2431 4331 4431 ---- -111 ---- -111 ---- -uuu TRISD 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu TRISC 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu TRISB 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu OSCTUNE (5) 1111(5) TRISA 2331 2431 4331 4431 1111 PR5H 2331 2431 4331 4431 1111 1111 1111 1111(5) 1111 1111 uuuu uuuu(5) uuuu uuuu PR5L 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu LATE(6) 2331 2431 4331 4431 ---- -xxx ---- -uuu ---- -uuu LATD 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu LATC 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu LATB 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu LATA(5) 2331 2431 4331 4431 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5) TMR5H 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu TMR5L 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu (6) 2331 2431 4331 4431 ---- xxxx ---- xxxx ---- uuuu PORTD 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu PORTE (5) PORTA 2331 2431 4331 4431 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. Preliminary DS39616B-page 51 PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt 2331 2431 4331 4431 0000 0000 uuuu uuuu uuuu uuuu PTCON1 2331 2431 4331 4431 00-- ---- 00-- ---- uu-- ---- PTMRL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PTMRH 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu PTPERL 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu PTPERH 2331 2431 4331 4431 ---- 1111 ---- 1111 ---- uuuu PDC0L 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu PDC0H 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PDC1L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PDC1H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu PDC2L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PDC2H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu PDC3L 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu PDC3H 2331 2431 4331 4431 --00 0000 --00 0000 --uu uuuu SEVTCMPL 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu SEVTCMPH 2331 2431 4331 4431 ---- 0000 ---- 0000 ---- uuuu PWMCON0 2331 2431 4331 4431 -101 0000 -101 0000 -uuu uuuu PWMCON1 2331 2431 4331 4431 0000 0-00 0000 0-00 uuuu u-uu DTCON 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu FLTCONFIG 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu OVDCOND 2331 2431 4331 4431 1111 1111 1111 1111 uuuu uuuu OVDCONS 2331 2431 4331 4431 0000 0000 0000 0000 uuuu uuuu CAP1BUFH/ VELRH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP1BUFL/ VELRL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP2BUFH/ POSCNTH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP2BUFL/ POSCNTL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu Register PTCON0 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. DS39616B-page 52 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register Applicable Devices Power-on Reset, Brown-out Reset CAP3BUFH/ MAXCNTH 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP3BUFL/ MAXCNTL 2331 2431 4331 4431 xxxx xxxx uuuu uuuu uuuu uuuu CAP1CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu CAP2CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu CAP3CON 2331 2431 4331 4431 -0-- 0000 -0-- 0000 -u-- uuuu DFLTCON 2331 2431 4331 4431 -000 0000 -000 0000 -uuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE pin, they are disabled and read as ‘0’. The 28-pin devices have only RE3 on PORTE when MCLR is disabled. 2003 Microchip Technology Inc. Preliminary DS39616B-page 53 PIC18F2331/2431/4331/4431 FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 4-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 4-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39616B-page 54 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) FIGURE 4-7: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL ≈ 2 ms max. First three stages of the PWRT timer. 2003 Microchip Technology Inc. Preliminary DS39616B-page 55 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 56 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.0 MEMORY ORGANIZATION 5.1 There are three memory types in enhanced MCU devices. These memory types are: • Program Memory • Data RAM • Data EEPROM Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ‘0’s (a NOP instruction). Data and program memory use separate busses, which allows for concurrent access of these types. The PIC18F2331 and PIC18F4331 each have 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. Additional detailed information for Flash program memory and data EEPROM is provided in Section 6.0 “Flash Program Memory” and Section 7.0 “Data EEPROM Memory”, respectively. The PIC18F2431 and PIC18F4431 each have 16 Kbytes of Flash memory and can store up to 8,192 single-word instructions. The Reset vector address is at 000000h and the interrupt vector addresses are at 000008h and 000018h. The Program Memory Maps for PIC18F2X31 and PIC18F4X31 devices are shown in Figure 5-1 and Figure 5-2, respectively. FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18F2331/4331 FIGURE 5-2: PC<20:0> PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW PROGRAM MEMORY MAP AND STACK FOR PIC18F2431/4431 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 1 • • • • • • Stack Level 31 Stack Level 31 Reset Vector LSb 000000h Reset Vector LSb High Priority Interrupt Vector LSb 000008h 000000h High Priority Interrupt Vector LSb 000008h Low Priority Interrupt Vector LSb 000018h Low Priority Interrupt Vector LSb 000018h On-Chip Flash Program Memory 001FFFh 002000h User Memory Space On-Chip Flash Program Memory User Memory Space 003FFFh 004000h Unused Read ‘0’s Unused Read ‘0’s 1FFFFFh 1FFFFFh 2003 Microchip Technology Inc. Preliminary DS39616B-page 57 PIC18F2331/2431/4331/4431 5.2 5.2.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. The STKPTR register (Register 5-1) contains the stack pointer value, the STKFUL (stack full) status bit, and the STKUNF (stack underflow) status bits. The value of the stack pointer can be 0 through 31. The stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. At Reset, the stack pointer value will be zero. The user may read and write the stack pointer value. This feature can be used by a Real-Time Operating System for return stack maintenance. The stack operates as a 31-word by 21-bit RAM and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all Resets. There is no RAM associated with stack pointer 00000b. This is only a Reset value. During a CALL type instruction, causing a push onto the stack, the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC (already pointing to the instruction following the call). During a RETURN type instruction, causing a pop from the stack, the contents of the RAM location pointed to by the STKPTR are transferred to the PC and then the stack pointer is decremented. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) configuration bit. (Refer to Section 22.1 “Configuration Bits” for a description of the device configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit, and reset the device. The STKFUL bit will remain set and the stack pointer will be set to zero. The stack space is not part of either program or data space. The stack pointer is readable and writable, and the address on the top of the stack is readable and writable through the top-of-stack Special File registers. Data can also be pushed to, or popped from, the stack using the top-of-stack SFRs. Status bits indicate if the stack is full, has overflowed or underflowed. 5.2.1 If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31. Any additional pushes will not overwrite the 31st push, and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and set the STKUNF bit, while the stack pointer remains at zero. The STKUNF bit will remain set until cleared by software or a POR occurs. TOP-OF-STACK ACCESS The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL hold the contents of the stack location pointed to by the STKPTR register (Figure 5-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. Note: The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. FIGURE 5-3: RETURN STACK POINTER (STKPTR) Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU 00h TOSH 1Ah Top-of-Stack DS39616B-page 58 STKPTR<4:0> 00010 TOSL 34h 00011 001A34h 00010 000D58h 00001 00000 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 5-1: STKPTR REGISTER R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKFUL STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7(1) STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6(1) STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as ‘0’ bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software or by a POR. Legend: 5.2.3 R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PUSH AND POP INSTRUCTIONS 5.2.4 Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place data or a return address on the stack. STACK FULL/UNDERFLOW RESETS These Resets are enabled by programming the STVREN bit in Configuration Register 4L. When the STVREN bit is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device Reset. When the STVREN bit is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a POR Reset. The ability to pull the TOS value off of the stack and replace it with the value that was previously pushed onto the stack, without disturbing normal execution, is achieved by using the POP instruction. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 2003 Microchip Technology Inc. Preliminary DS39616B-page 59 PIC18F2331/2431/4331/4431 5.3 Fast Register Stack 5.4 A “fast return” option is available for interrupts. A fast register stack is provided for the Status, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers, if the RETFIE, FAST instruction is used to return from the interrupt. All interrupt sources will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. Users must save the key registers in software during a low priority interrupt. If interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. If no interrupts are used, the fast register stack can be used to restore the Status, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a CALL label, FAST instruction must be executed to save the Status, WREG and BSR registers to the fast register stack. A RETURN, FAST instruction is then executed to restore these registers from the fast register stack. PCL, PCLATH and PCLATU The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register. The contents of PCLATH and PCLATU will be transferred to the program counter by any operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 5.8.1 “Computed GOTO”). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSB of PCL is fixed to a value of ‘0’. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. Example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. EXAMPLE 5-1: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK • • • • RETURN FAST SUB1 DS39616B-page 60 ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.5 Clocking Scheme/Instruction Cycle 5.6 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 5-2). The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the Instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 5-4. A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 5-4: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal Phase Clock Q3 Q4 PC OSC2/CLKO (RC mode) EXAMPLE 5-2: Execute INST (PC-2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC+2) TCY0 TCY1 Fetch 1 Execute 1 2. MOVWF PORTB 4. BSF PC+4 Execute INST (PC+2) Fetch INST (PC+4) INSTRUCTION PIPELINE FLOW 1. MOVLW 55h 3. BRA PC+2 PC SUB_1 Fetch 2 TCY2 TCY3 TCY4 TCY5 Execute 2 Fetch 3 Execute 3 Fetch 4 PORTA, BIT3 (Forced NOP) Flush (NOP) Fetch SUB_1 Execute SUB_1 5. Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed. 2003 Microchip Technology Inc. Preliminary DS39616B-page 61 PIC18F2331/2431/4331/4431 5.7 Instructions in Program Memory The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = 0). Figure 5-5 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 5.4 “PCL, PCLATH and PCLATU”). FIGURE 5-5: The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 5-5 shows how the instruction ‘GOTO 000006h’ is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 23.0 “Instruction Set Summary” provides further details of the instruction set. INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 LSB = 0 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h Program Memory Byte Locations → 5.7.1 Instruction 1: Instruction 2: MOVLW GOTO 055h 000006h Instruction 3: MOVFF 123h, 456h TWO-WORD INSTRUCTIONS PIC18F2331/2431/4331/4431 devices have four twoword instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is decoded as a NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If EXAMPLE 5-3: CASE 1: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 CASE 2: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 DS39616B-page 62 Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two-word instruction is preceded by a conditional instruction that results in a skip operation. A program example that demonstrates this concept is shown in Example 5-3. Refer to Section 23.0 “Instruction Set Summary” for further details of the instruction set. TWO-WORD INSTRUCTIONS 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; No, skip this word ; Execute this word as a NOP ADDWF REG3 ; continue code 0000 0011 0110 0000 Source Code TSTFSZ REG1 ; is RAM location 0? MOVFF REG1, REG2 ; Yes, execute this word ; 2nd word of instruction ADDWF REG3 ; continue code Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.8 Look-up Tables 5.9 Look-up tables are implemented two ways: The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 5-6 shows the data memory organization for the PIC18F2331/2431/4331/4431 devices. • Computed GOTO • Table Reads 5.8.1 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 5-4. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions, which returns the value 0xnn to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance, and should be multiples of 2 (LSB = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. EXAMPLE 5-4: COMPUTED GOTO USING AN OFFSET VALUE MOVFWOFFSET CALLTABLE ORG 0xnn00 TABLEADDWFPCL RETLW0xnn RETLW0xnn RETLW0xnn . . . 5.8.2 The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratch pad operations in the user’s application. The SFRs start at the last location of Bank 15 (FFFh) and extend to F60h. Any remaining space beyond the SFRs in the bank may be implemented as GPRs. GPRs start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as ‘0’s. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of a File Select Register (FSRn) and a corresponding Indirect File Operand (INDFn). Each FSR holds a 12bit address value that can be used to access any location in the Data Memory map without banking. See Section 5.12 “Indirect Addressing, INDF and FSR Registers” for indirect addressing details. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two-word/two-cycle instruction that moves a value from one register to another. TABLE READS/TABLE WRITES A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table latch (TABLAT) contains the data that is read from, or written to program memory. Data is transferred to/from program memory, one byte at a time. The Table Read/Table Write operation is discussed further in Section 6.1 “Table Reads and Table Writes”. 2003 Microchip Technology Inc. Data Memory Organization To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 5.10 “Access Bank” provides a detailed description of the Access RAM. 5.9.1 GENERAL PURPOSE REGISTER FILE Enhanced MCU devices may have banked memory in the GPR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Data RAM is available for use as GPR registers by all instructions. The second half of Bank 15 (F60h to FFFh) contains SFRs. All other banks of data memory contain GPRs, starting with Bank 0. Preliminary DS39616B-page 63 PIC18F2331/2431/4331/4431 FIGURE 5-6: DATA MEMORY MAP FOR PIC18F2331/2431/4331/4431 DEVICES BSR<3:0> = 0000 = 0001 Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 GPR Bank 1 1FFh 200h FFh 00h = 0010 000h 05Fh 060h 0FFh 100h GPR Bank 2 FFh 00h 2FFh 300h Access Bank Access RAM Low = 0011 = 1110 Bank 3 to Bank 14 00h 5Fh Access RAM High 60h (SFRs) FFh Unused Read ‘00h’ When a = 0: The BSR is ignored and the Access Bank is used. = 1111 00h Unused FFh SFR Bank 15 EFFh F00h F5Fh F60h FFFh The first 96 bytes are General Purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction. DS39616B-page 64 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.9.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFRs) are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 5-1 and Table 5-2. The SFRs can be classified into two sets; those associated with the “core” function and those related to the peripheral functions. Those registers related to the TABLE 5-1: Address “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFRs are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as ‘0’s. SPECIAL FUNCTION REGISTER MAP FOR PIC18F2331/2431/4331/4431 DEVICES Address Name Address Name FFFh FFEh FFDh FFCh TOSU TOSH TOSL STKPTR Name Address FDFh INDF2 FDEh POSTINC2 FDDh POSTDEC2 FDCh PREINC2 Name Address FBFh FBEh FBDh FBCh CCPR1H CCPR1L CCP1CON CCPR2H Name F9Fh F9Eh F9Dh F9Ch IPR1 PIR1 PIE1 F7Fh F7Eh F7Dh F7Ch PTCON0 PTCON1 PTMRL FFBh FFAh FF9h FF8h PCLATU PCLATH PCL TBLPTRU FDBh FDAh FD9h FD8h PLUSW2 FSR2H FSR2L STATUS FBBh FBAh FB9h FB8h CCPR2L CCP2CON ANSEL1 ANSEL0 F9Bh F9Ah F99h F98h OSCTUNE ADCON3 ADCHS PTPERL PTPERH PDC0L FF7h TBLPTRH FD7h TMR0H FB7h T5CON F97h — — F7Bh F7Ah F79h F78h F77h PDC1L FF6h FF5h FF4h TBLPTRL TABLAT PRODH FD6h FD5h FD4h TMR0L T0CON QEICON TRISE TRISD TRISC F76h F75h F74h PDC2H FF3h PRODL FD3h OSCCON FB3h F93h TRISB F73h PDC3L FF2h INTCON FD2h LVDCON FB2h F92h TRISA F72h PDC3H FF1h INTCON2 FD1h WDTCON FB1h — — — — F96h F95h F94h PDC1H PDC2L — FB6h FB5h FB4h F91h PR5H F71h SEVTCMPL FF0h FEFh INTCON3 INDF0 FD0h FCFh RCON TMR1H FB0h FAFh SPBRGH SPBRG F90h F8Fh PR5L F70h F6Fh SEVTCMPH FEEh — — — — POSTINC0 FCEh TMR1L FAEh RCREG F8Eh FEDh POSTDEC0 FECh PREINC0 FEBh PLUSW0 FEAh FSR0H FE9h FSR0L FE8h WREG FE7h INDF1 FE6h POSTINC1 FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON FADh FACh FABh FAAh FA9h FA8h FA7h FA6h TXREG TXSTA RCSTA BAUDCTL EEADR EEDATA EECON2 EECON1 F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h FE5h POSTDEC1 FC5h — FA5h IPR3 F85h — — FE4h FE3h FE2h FE1h FE0h FC4h FC3h FC2h FC1h FC0h ADRESH ADRESL ADCON0 ADCON1 ADCON2 FA4h FA3h FA2h FA1h FA0h PIR3 PIE3 IPR2 PIR2 PIE2 F84h F83h F82h F81h F80h PORTE PORTD PORTC PORTB PORTA PREINC1 PLUSW1 FSR1H FSR1L BSR 2003 Microchip Technology Inc. Preliminary LATE LATD LATC LATB LATA TMR5H TMR5L PTMRH PDC0H PWMCON0 F6Eh PWMCON1 F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h DTCON FLTCONFIG OVDCOND OVDCONS CAP1BUFH CAP1BUFL CAP2BUFH F65h CAP3BUFH F64h F63h F62h F61h F60h CAP3BUFL CAP1CON CAP2CON CAP3CON DFLTCON CAP2BUFL DS39616B-page 65 PIC18F2331/2431/4331/4431 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 48, 58 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 48, 58 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 48, 58 Return Stack Pointer 00-0 0000 48, 59 Holding register for PC<20:16> TOSU STKPTR STKFUL STKUNF — PCLATU — — bit 21(3) Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR ---0 0000 48, 60 PCLATH Holding register for PC<15:8> 0000 0000 48, 60 PCL PC Low Byte (PC<7:0>) 0000 0000 48, 60 --00 0000 48, 78 TBLPTRU — — bit 21(3) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 48, 78 TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 0000 0000 48, 78 TABLAT Program Memory Table Latch 0000 0000 48, 78 PRODH Product register High Byte xxxx xxxx 48, 89 PRODL Product register Low Byte xxxx xxxx 48, 89 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0F RBIF 0000 000x 48, 93 INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP 1111 -1-1 48, 94 INT2P INT1P — INT2IE INT1IE — INT2IF INT1IF 11-0 0-00 48, 95 INTCON3 INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 48, 71 POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 48, 71 POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 48, 71 PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 48, 71 PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register) N/A 48, 71 ---- 0000 48, 71 48, 71 FSR0H — — — — Indirect Data Memory Address Pointer 0 High FSR0L Indirect Data Memory Address Pointer 0 Low Byte xxxx xxxx WREG Working register xxxx xxxx 48 INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 48, 71 POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 48, 71 POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 48, 71 PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 48, 71 PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register) N/A 48, 71 Indirect Data Memory Address Pointer 1 High ---- 0000 49, 71 xxxx xxxx 49, 71 Bank Select Register ---- 0000 49, 70 FSR1H — FSR1L — — — Indirect Data Memory Address Pointer 1 Low Byte BSR — — — — INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 49, 71 POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 49, 71 POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 49, 71 PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 49, 71 PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register) N/A 49, 71 ---- 0000 49, 71 FSR2H — FSR2L — — — Indirect Data Memory Address Pointer 2 High Indirect Data Memory Address Pointer 2 Low Byte STATUS — — — N OV Z DC C xxxx xxxx 49, 71 ---x xxxx 49, 73 TMR0H Timer0 register High Byte 0000 0000 49, 135 TMR0L Timer0 register Low Byte xxxx xxxx 49, 135 11-- 1111 49, 133 T0CON TMR0ON Legend: Note 1: 2: 3: 4: 5: 6: T016BIT — — T0PS3 T0PS2 T0PS1 T0PS0 x = unknown, u = unchanged, – = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read ‘0’ in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes. Bit 21 of the PC is only available in Test mode and serial programming modes. If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as analog input and read ‘0’ following a Reset. These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’. The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only. DS39616B-page 66 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: Bit 6 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0 0000 q000 28, 49 LVDCON — — IVRST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 --00 0101 49, 263 WDTCON WDTW — — — — — — SWDTEN 0000 0000 49, 279 IPEN — — RI TO PD POR BOR RCON Bit 5 Value on POR, BOR Bit 7 0--1 11qq 47, 74, 105 TMR1H Timer1 register High Byte xxxx xxxx 49, 141 TMR1L Timer1 register Low Byte xxxx xxxx 49, 141 0000 0000 49, 137 T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TMR2 Timer2 register 0000 0000 49, 143 PR2 Timer2 Period register 1111 1111 49, 143 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 49, 143 SSPBUF SSP Receive Buffer/Transmit register xxxx xxxx 49, 220 SSPADD SSP Address register in I2C Slave mode. SSP Baud Rate Reload register in I2C Master mode. 0000 0000 49, 220 SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 49, 212 SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 49, 213 50, 259 ADRESH A/D Result register High Byte xxxx xxxx ADRESL A/D Result register Low Byte xxxx xxxx 50, 259 ADCON0 — — ACONV ACSCH ACMOD1 ACMOD0 GO/DONE ADON --00 0000 50, 244 ADCON1 VCFG1 VCFG0 — FIFOEN BFEMT FFOVFL ADPNT1 ADPNT0 00-0 1000 50, 245 ADCON2 ADFM ACQT3 ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0000 0000 50, 246 ADCON3 ADRS1 ADRS0 — SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000 51. 247 GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 0000 0000 51, 248 50, 152 ADCSH CCPR1H Capture/Compare/PWM register1 High Byte xxxx xxxx CCPR1L Capture/Compare/PWM register1 Low Byte xxxx xxxx 50, 152 0000 0000 50, 155, 149 CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 CCPR2H Capture/Compare/PWM register2 High Byte xxxx xxxx 50, 152 CCPR2L Capture/Compare/PWM register2 Low Byte xxxx xxxx 50, 152 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 50, 155 ANSEL1 — — — — — — — ANS8 ---- ---1 50, 249 ANSEL0 ANS7(6) ANS6(6) ANS5(6) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 50, 249 T5CON T5SEN T5MOD T5PS1 T5PS0 T5SYNC TMR5CS TMR5ON 0100 0000 50, 145 UP/DOWN QEIM2 QEIM1 QEIM0 PDEC1 PDEC0 0000 0000 50, 171 0000 0000 50, 225 QEICON SPBRGH VELM RESEN (5) ERROR Baud Rate Generator register, High Byte SPBRG USART Baud Rate Generator 0000 0000 50, 225 RCREG USART Receive register 0000 0000 50, 233, 232 TXREG USART Transmit register 0000 0000 50, 230, 232 TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 50, 222 RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 000x 50, 223 — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 50, 224 BAUDCTL Legend: Note 1: 2: 3: 4: 5: 6: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read ‘0’ in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes. Bit 21 of the PC is only available in Test mode and serial programming modes. If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as analog input and read ‘0’ following a Reset. These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’. The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only. 2003 Microchip Technology Inc. Preliminary DS39616B-page 67 PIC18F2331/2431/4331/4431 TABLE 5-2: File Name REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: 50, 85 EEADR EEPROM Address register 0000 0000 EEDATA EEPROM Data register 0000 0000 50, 88 EECON2 EEPROM Control register2 (not a physical register) 0000 0000 50, 76, 85 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 50, 77, 86 IPR3 EECON1 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111 50 PIR3 — — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000 50 PIE3 — — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000 50 IPR2 OSFIP — — EEIP — LVDIP — CCP2IP 1--1 -1-1 51, 103 PIR2 OSFIF — — EEIF — LVDIF — CCP2IF 0--0 -0-0 51, 97 PIE2 OSFIE — — EEIE — LVDIE — CCP2IE 0--0 -0-0 51, 100 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 51, 102 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 51, 96 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 51, 99 OSCTUNE — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 25, 51 ADRS1 ADRS0 — SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000 50 0000 0000 50 ---- -111 51, 131 ADCON3 ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 TRISE(5) — — — — — GCSEL0 GASEL1 GASEL0 Data Direction bits for PORTE(5) TRISD(5) Data Direction Control register for PORTD 1111 1111 51, 128 TRISC Data Direction Control register for PORTC 1111 1111 51, 123 TRISB Data Direction Control register for PORTB 1111 1111 51, 117 1111 1111 51, 111 TRISA7(2) TRISA TRISA6(1) Data Direction Control register for PORTA PR5H Timer5 Period register High Byte 1111 1111 50 PR5L Timer5 Period register Low Byte 1111 1111 50 LATE(5) ---- -xxx 51, 132 LATD(5) Read/Write PORTD Data Latch — — — xxxx xxxx 51, 128 LATC Read/Write PORTC Data Latch xxxx xxxx 51, 123 LATB Read/Write PORTB Data Latch xxxx xxxx 51, 117 xxxx xxxx 51, 111 xxxx xxxx 146 LATA LATA<7>(2) TMR5H Timer5 Timer register High Byte TMR5L Timer5 Timer register Low Byte PORTE — LATA<6>(1) — — Read/Write PORTE Data Latch Read/Write PORTA Data Latch — — RE3(6) — Read PORTE pins, Write PORTE Data Latch(5) xxxx xxxx 146 ---- xxxx 51, 132 PORTD Read PORTD pins, Write PORTD Data Latch xxxx xxxx 51, 128 PORTC Read PORTC pins, Write PORTC Data Latch xxxx xxxx 51, 123 PORTB Read PORTB pins, Write PORTB Data Latch(4) xxxx xxxx 51, 117 xx0x 0000 51, 111 RA7(2) RA6(1) PTCON0 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0 0000 0000 52, 186 PTCON1 PTEN PTDIR — — — — — — 00-- ---- 52, 186 0000 0000 184 ---- 0000 184 PORTA PTMRL Read PORTA pins, Write PORTA Data Latch PWM Time Base register (lower 8 bits). PTMRH UNUSED Legend: Note 1: 2: 3: 4: 5: 6: PWM Time Base register (Upper 4 bits) x = unknown, u = unchanged, – = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read ‘0’ in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes. Bit 21 of the PC is only available in Test mode and serial programming modes. If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as analog input and read ‘0’ following a Reset. These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’. The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only. DS39616B-page 68 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 5-2: File Name PTPERL REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED) Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWM Time Base Period register (Lower 8 bits). PTPERH PDC0L Bit 5 UNUSED PWM Time Base Period register (Upper 4 bits) PWM Duty Cycle #0L register (Lower 8 bits) PDC0H UNUSED PDC1L PWM Duty Cycle #0H register (Upper 6 bits) PWM Duty Cycle #1L register (Lower 8 bits) PDC1H UNUSED PDC2L PWM Duty Cycle #1H register (Upper 6 bits) PWM Duty Cycle #2L register (Lower 8 bits) PDC2H UNUSED PDC3L PWM Duty Cycle #2H register (Upper 6 bits) PWM Duty Cycle #3L register (Lower 8 bits) PDC3H UNUSED PWM Duty Cycle #3H register (Upper 6 bits) SEVTCMPL PWM Special Event Compare register (Lower 8 bits) SEVTCMPH UNUSED Value on POR, BOR Details on page: 1111 1111 184 ---- 1111 184 --00 0000 184 0000 0000 184 0000 0000 184 --00 0000 184 0000 0000 184 --00 0000 184 0000 0000 184 --00 0000 184 0000 0000 N/A PWM Special Event Compare reg (Upper 4 bits) ---- 0000 N/A PWMCON0 — PWMEN2 PWMEN1 PWMEN0 PMOD3 PMOD2 PMOD1 PMOD0 -101 0000 52, 187 PWMCON1 SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR — UDIS OSYNC 0000 0-00 52, 188 DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0 0000 0000 52, 200 FLTCONFIG — FLTBS FLTBMOD FLTBEN FLTCON FLTAS FLTAMOD FLTAEN -000 0000 52, 208 OVDCOND POVD7 POVD6 POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 1111 1111 52, 203 OVDCONS POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0000 0000 52, 204 DTCON CAP1BUFH/ VELRH Capture 1 register, High Byte/ Velocity register, High Byte xxxx xxxx 52, CAP1BUFL/ VELRL Capture 1 register Low Byte/ Velocity register, Low Byte xxxx xxxx 52 CAP2BUFH/ POSCNTH Capture 2 register, High Byte/ QEI Position Counter register, High Byte xxxx xxxx 52 CAP2BUFL/ POSCNTL Capture 2 Reg., Low Byte/ QEI Position Counter register, Low Byte xxxx xxxx 52 CAP3BUFH/ MAXCNTH Capture 3 Reg., High Byte/ QEI Max. Count Limit register, High Byte xxxx xxxx 53 CAP3BUFL/ MAXCNTL Capture 3 Reg., Low Byte/ QEI Max. Count Limit register, Low Byte xxxx xxxx 53 CAP1CON — CAP1REN — — CAP1M3 CAP1M2 CAP1M1 CAP1M0 -0-0 0000 53, 163 CAP2CON — CAP2REN — — CAP2M3 CAP2M2 CAP2M1 CAP2M0 -0-0 0000 53, 163 CAP3CON — CAP3REN — — CAP3M3 CAP3M2 CAP3M1 CAP3M0 -0-0 0000 53, 163 DFLTCON — FLT4EN FLT3EN FLT2EN FLT1EN FLTCK2 FLTCK1 FLTCK0 -000 0000 53, 178 Legend: Note 1: 2: 3: 4: 5: 6: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only, and read ‘0’ in all other oscillator modes. RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes. Bit 21 of the PC is only available in Test mode and serial programming modes. If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown, and if PBADEN = 1, PORTB<4:0> are configured as analog input and read ‘0’ following a Reset. These registers and/or bits are not implemented on the PIC18F2X31 devices, and read as ‘0’. The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is read-only. 2003 Microchip Technology Inc. Preliminary DS39616B-page 69 PIC18F2331/2431/4331/4431 5.10 Access Bank 5.11 The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into as many as sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. This data memory region can be used for: • • • • • BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read ‘0’s, and writes will have no effect (see Figure 5-7). Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFRs (no banking) A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all ‘0’s and all writes are ignored. The Status register bits will be set/cleared as appropriate for the instruction performed. The Access Bank is comprised of the last 128 bytes in Bank 15 (SFRs) and the first 128 bytes in Bank 0. These two sections will be referred to as Access RAM High and Access RAM Low, respectively. Figure 5-6 indicates the Access RAM areas. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register or in the Access Bank. This bit is denoted as the ‘a’ bit (for access bit). A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word. Section 5.12 “Indirect Addressing, INDF and FSR Registers” provides a description of indirect addressing, which allows linear addressing of the entire RAM space. When forced in the Access Bank (a = 0), the last address in Access RAM Low is followed by the first address in Access RAM High. Access RAM High maps the Special Function Registers, so these registers can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. FIGURE 5-7: Bank Select Register (BSR) DIRECT ADDRESSING Direct Addressing BSR<7:4> 0 0 0 BSR<3:0> 7 From Opcode(3) 0 0 Bank Select(2) Location Select(3) 00h 01h 0Eh 0Fh 000h 100h E00h F00h 0FFh 1FFh EFFh FFFh Bank 14 Bank 15 Data Memory(1) Bank 0 Bank 1 Note 1: For register file map detail, see Table 5-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS39616B-page 70 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 5-8 shows how the fetched instruction is modified prior to being executed. Indirect addressing is possible by using one of the INDF registers. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0), will read 00h. Writing to the INDF register indirectly, results in a no operation. The FSR register contains a 12-bit address, which is shown in Figure 5-9. The INDFn register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is indirect addressing. Example 5-5 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions. EXAMPLE 5-5: NEXT LFSR CLRF BTFSS GOTO CONTINUE HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 0x100 ; POSTINC0 ; ; ; FSR0H, 1 ; ; NEXT ; ; Clear INDF register then inc pointer All done with Bank1? NO, clear next YES, continue There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12-bits wide. To store the 12 bits of addressing information, two 8-bit registers are required: 1. 2. 3. FSR0: composed of FSR0H:FSR0L FSR1: composed of FSR1H:FSR1L FSR2: composed of FSR2H:FSR2L In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. If an instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads the data from the address pointed to by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. 2003 Microchip Technology Inc. If INDF0, INDF1 or INDF2 are read indirectly via a FSR, all ‘0’s are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the Status bits are not affected. 5.12.1 INDIRECT ADDRESSING OPERATION Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation using one of these five registers determines how the FSR will be modified during indirect addressing. When data access is performed using one of the five INDFn locations, the address selected will configure the FSRn register to: • Do nothing to FSRn after an indirect access (no change) – INDFn • Auto-decrement FSRn after an indirect access (post-decrement) – POSTDECn • Auto-increment FSRn after an indirect access (post-increment) – POSTINCn • Auto-increment FSRn before an indirect access (pre-increment) – PREINCn • Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) – PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the Status register. For example, if the indirect address causes the FSR to equal ‘0’, the Z bit will not be set. Auto-incrementing or auto-decrementing a FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a stack pointer, in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the signed value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. The WREG offset range is -128 to +127. If an FSR register contains a value that points to one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (Status bits are not affected). If an indirect addressing write is performed when the target address is an FSRnH or FSRnL register, the data is written to the FSR register, but no pre- or postincrement/decrement is performed. Preliminary DS39616B-page 71 PIC18F2331/2431/4331/4431 FIGURE 5-8: INDIRECT ADDRESSING OPERATION RAM 0h Instruction Executed Opcode Address FFFh 12 File Address = access of an indirect addressing register BSR<3:0> Instruction Fetched 4 12 8 Opcode FIGURE 5-9: 12 File FSR INDIRECT ADDRESSING Indirect Addressing FSRnH:FSRnL 3 0 7 0 11 0 Location Select 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 5-1. DS39616B-page 72 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 5.13 Status Register The Status register, shown in Register 5-2, contains the arithmetic status of the ALU. The Status register can be the operand for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the Status register as destination may be different than intended. REGISTER 5-2: For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the Status register, because these instructions do not affect the Z, C, DC, OV or N bits in the Status register. For other instructions not affecting any status bits, see Table 23-2. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. STATUS REGISTER U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — N OV Z DC C bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive bit 3 OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: bit 0 For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. C: Carry/borrow bit For ADDWF, ADDLW, SUBLW and SUBWF instructions 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high- or low-order bit of the source register. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 73 PIC18F2331/2431/4331/4431 5.14 RCON Register Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is ‘1’ on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will be cleared and must be set by firmware to indicate the occurrence of the next Brown-out Reset. The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. REGISTER 5-3: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in firmware after a Brown-out Reset occurs) bit 3 TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 2 PD: Power-down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Cleared by execution of the SLEEP instruction bit 1 POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in firmware after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in firmware after a Brown-out Reset occurs) Legend: DS39616B-page 74 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.0 FLASH PROGRAM MEMORY The program memory space is 16-bits wide, while the data RAM space is 8-bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. Table read operations retrieve data from program memory and place it into TABLAT in the data RAM space. Figure 6-1 shows the operation of a table read with program memory and data RAM. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. Table write operations store data from TABLAT in the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 6.5 “Writing to Flash Program Memory”. Figure 6-2 shows the operation of a table write with program memory and data RAM. While writing or erasing program memory, instruction fetches cease until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word aligned, (TBLPTRL<0> = 0). A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. 6.1 Table Reads and Table Writes The EEPROM on-chip timer controls the write and erase times. The write and erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: • Table Read (TBLRD) • Table Write (TBLWT) FIGURE 6-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) TBLPTRU TBLPTRH Program Memory Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2003 Microchip Technology Inc. Preliminary DS39616B-page 75 PIC18F2331/2431/4331/4431 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: 6.2 Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in Section 6.5 “Writing to Flash Program Memory”. Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: • • • • EECON1 register EECON2 register TABLAT register TBLPTR registers 6.2.1 EECON1 AND EECON2 REGISTERS EECON1 is the control register for memory accesses. EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit CFGS determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The FREE bit controls program memory erase operations. When the FREE bit is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. DS39616B-page 76 The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled – the WR bit cannot be set while the WREN bit is clear. This process helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It will be necessary to reload the data and address registers (EEDATA and EEADR) as these registers have cleared as a result of the Reset. Control bits RD and WR start read and erase/write operations, respectively. These bits are set by firmware, and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.3 “Reading the Flash Program Memory” regarding table reads. Note: Preliminary Interrupt flag bit EEIF, in the PIR2 register, is set when the write is complete. It must be cleared in software. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 6-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation – TBLPTR<5:0> are ignored) 0 = Perform write only bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (any Reset during self-timed programming) 0 = The write operation completed normally Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Write Enable bit 1 = Allows erase or write cycles 0 = Inhibits erase or write cycles bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle completed bit 0 RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’ W = Writable bit - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown 2003 Microchip Technology Inc. Preliminary DS39616B-page 77 PIC18F2331/2431/4331/4431 6.2.2 TABLAT – TABLE LATCH REGISTER 6.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the Table Pointer determine which byte is read from program or configuration memory into TABLAT. TBLPTR – TABLE POINTER REGISTER When a TBLWT is executed, the three LSbs of the Table Pointer (TBLPTR<2:0>) determine which of the eight program memory holding registers is written to. When the timed write to program memory (long write) begins, the 19 MSbs of the Table Pointer, TBLPTR (TBLPTR<21:3>), will determine which program memory block of 8 bytes is written to (TBLPTR<2:0> are ignored). For more detail, see Section 6.5 “Writing to Flash Program Memory”. The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low order 21 bits allow the device to address up to 2 Mbytes of program memory space. Setting the 22nd bit allows access to the Device ID, the User ID and the Configuration bits. When an erase of program memory is executed, the 16 MSbs of the Table Pointer (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. The TBLPTR is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 6-1. These operations on the TBLPTR only affect the low order 21 bits. TABLE 6-1: TABLE POINTER BOUNDARIES Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Example Operation on Table Pointer TBLRD* TBLWT* TBLPTR is not modified TBLRD*+ TBLWT*+ TBLPTR is incremented after the read/write TBLRD*TBLWT*- TBLPTR is decremented after the read/write TBLRD+* TBLWT+* TBLPTR is incremented before the read/write FIGURE 6-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE – TBLPTR<21:6> LONG WRITE – TBLPTR<21:3> READ or WRITE – TBLPTR<21:0> DS39616B-page 78 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.3 Reading the Flash Program Memory The TBLRD instruction is used to retrieve data from program memory and placed into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space. Executing a TBLRD instruction places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. FIGURE 6-4: READS FROM FLASH PROGRAM MEMORY Program Memory Odd (High) Byte Even (Low) Byte TBLPTR LSB = 0 TBLPTR LSB = 1 Instruction Register (IR) EXAMPLE 6-1: MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF TABLAT Read Register READING A FLASH PROGRAM MEMORY WORD CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word READ_WORD TBLRD*+ MOVFW TABLAT MOVWF WORD_EVEN TBLRD*+ MOVFW TABLAT MOVWF WORD_ODD 2003 Microchip Technology Inc. ; read into TABLAT and increment TBLPTR ; get data ; read into TABLAT and increment TBLPTR ; get data Preliminary DS39616B-page 79 PIC18F2331/2431/4331/4431 6.4 6.4.1 Erasing Flash Program Memory The minimum erase block size is 32 words or 64 bytes under firmware control. Only through the use of an external programmer, or through ICSP control can larger blocks of program memory be bulk erased. Word erase in Flash memory is not supported. The sequence of events for erasing a block of internal program memory location is: 1. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. 2. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The CFGS bit must be clear to access program Flash and data EEPROM memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. The WR bit is set as part of the required instruction sequence (as shown in Example 6-2), and starts the actual erase operation. It is not necessary to load the TABLAT register with any data, as it is ignored. 3. 4. 5. 6. 7. For protection, the write initiate sequence using EECON2 must be used. 8. 9. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. EXAMPLE 6-2: FLASH PROGRAM MEMORY ERASE SEQUENCE Load table pointer with address of row erased. Set the EECON1 register for the operation: - set EEPGD bit to point to program memory; - clear the CFGS bit to access program memory; - set WREN bit to enable writes; - set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the row cycle. The CPU will stall for duration of the (about 2 ms using internal timer). Execute a NOP. Re-enable interrupts. being erase erase erase ERASING A FLASH PROGRAM MEMORY ROW MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; load TBLPTR with the base ; address of the memory block BSF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF NOP BSF EECON1,EEPGD EECON1,WREN EECON1,FREE INTCON,GIE 55h EECON2 AAh EECON2 EECON2,WR ; ; ; ; INTCON,GIE ; re-enable interrupts ERASE_ROW Required Sequence DS39616B-page 80 point to Flash program memory enable write to memory enable Row Erase operation disable interrupts ; write 55H ; write AAH ; start erase (CPU stall) Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 6.5 Writing to Flash Program Memory The programming block size is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. FIGURE 6-5: Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes, because only the holding registers are written. At the end of updating 8 registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 8 TBLPTR = xxxxx0 8 TBLPTR = xxxxx2 TBLPTR = xxxxx1 Holding Register Holding Register Holding Register 8 TBLPTR = xxxxx7 Holding Register Program Memory 6.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. 8. 9. Read 64 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer with address being erased. Do the row erase procedure (see Section 6.4.1 “Flash Program Memory Erase Sequence”). Load Table Pointer with address of first byte being written. Write the first 8 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: - set EEPGD bit to point to program memory; - clear the CFGS bit to access program memory; - set WREN bit to enable byte writes. Disable interrupts. Write 55h to EECON2. 2003 Microchip Technology Inc. 10. Write AAh to EECON2. 11. Set the WR bit. This will begin the write cycle. 12. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Execute a NOP. 14. Re-enable interrupts. 15. Repeat steps 6-14 seven times, to write 64 bytes. 16. Verify the memory (table read). This procedure will require about 18 ms to update one row of 64 bytes of memory. An example of the required code is given in Example 6-3. Preliminary DS39616B-page 81 PIC18F2331/2431/4331/4431 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL TBLRD*+ MOVFW MOVWF DECFSZ GOTO TABLAT POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; number of bytes in erase block ; point to buffer ; Load TBLPTR with the base ; address of the memory block ; 6 LSB = 0 READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data and increment FSR0 done? repeat MODIFY_WORD ; point to buffer ; update buffer word and increment FSR0 ; update buffer word ERASE_BLOCK MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL BCF EECON1,CFGS BSF EECON1,EEPGD BSF EECON1,WREN BSF EECON1,FREE BCF INTCON,GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1,WR NOP BSF INTCON,GIE WRITE_BUFFER_BACK MOVLW 8 MOVWF COUNTER_HI MOVLW BUFFER_ADDR_HIGH MOVWF FSR0H MOVLW BUFFER_ADDR_LOW MOVWF FSR0L PROGRAM_LOOP MOVLW 8 MOVWF COUNTER WRITE_WORD_TO_HREGS MOVFW POSTINC0 MOVWF TABLAT TBLWT+* DECFSZ COUNTER GOTO WRITE_WORD_TO_HREGS DS39616B-page 82 ; load TBLPTR with the base ; address of the memory block ; 6 LSB = 0 ; ; ; ; ; ; ; point to PROG/EEPROM memory point to Flash program memory enable write to memory enable Row Erase operation disable interrupts Required sequence write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts ; number of write buffer groups of 8 bytes ; point to buffer ; number of bytes in holding register ; ; ; ; ; ; get low byte of buffer data and increment FSR0 present data to table latch short write to internal TBLWT holding register, increment TBLPTR loop until buffers are full Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) PROGRAM_MEMORY BCF INTCON,GIE MOVLW 55h MOVWF EECON2 MOVLW AAh MOVWF EECON2 BSF EECON1,WR NOP BSF INTCON, GIE DECFSZ COUNTER_HI GOTO PROGRAM_LOOP BCF EECON1, WREN 6.5.2 ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ; loop until done ; disable write to memory WRITE VERIFY 6.6 Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 Flash Program Operation During Code Protection See Section 22.5 “Program Verification and Code Protection” for details on code protection of Flash program memory. UNEXPECTED TERMINATION OF WRITE OPERATION If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed if needed. The WRERR bit is set when a write operation is interrupted by a MCLR Reset, or a WDT Time-out Reset during normal operation. In these situations, users can check the WRERR bit and rewrite the location. TABLE 6-2: Name TBLPTRU REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 7 Bit 6 Bit 5 — — bit21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) Value on: POR, BOR Value on all other Resets --00 0000 --00 0000 TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 0000 0000 0000 0000 TBLPTRL Program Memory Table Pointer High Byte (TBLPTR<7:0>) 0000 0000 0000 0000 TABLAT Program Memory Table Latch INTCON GIE/GIEH PEIE/GIEL TMR0IE EECON2 EEPROM Control Register2 (not a physical register) 0000 0000 0000 0000 INT0IE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD xx-0 x000 uu-0 u000 IPR2 OSFIP — — EEIP — LVDIP — CCP2IP 1--1 -1-1 1--1 -1-1 PIR2 OSFIF — — EEIF — LVDIF — CCP2IF 0--0 -0-0 0--0 -0-0 PIE2 OSFIE — — EEIE — LVDIE — CCP2IE 0--0 -0-0 0--0 -0-0 Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2003 Microchip Technology Inc. Preliminary DS39616B-page 83 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 84 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 7.0 DATA EEPROM MEMORY The Data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: • • • • EECON1 EECON2 EEDATA EEADR The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 256 bytes of data EEPROM with an address range from 00h to FFh. The EEPROM data memory is rated for high erase/ write cycle endurance. A byte write automatically erases the location and writes the new data (erasebefore-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to parameter D122 (Table 25-1 in Section 25.0 “Electrical Characteristics”) for exact limits. 7.1 EEADR The address register can address 256 bytes of data EEPROM. 7.2 EECON1 and EECON2 Registers Control bit CFGS determines if the access will be to the configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit enables and disables erase and write operations. When set, erase and write operations are allowed. When clear, erase and write operations are disabled; the WR bit cannot be set while the WREN bit is clear. This mechanism helps to prevent accidental writes to memory due to errant (unexpected) code execution. Firmware should keep the WREN bit clear at all times, except when starting erase or write operations. Once firmware has set the WR bit, the WREN bit may be cleared. Clearing the WREN bit will not affect the operation in progress. The WRERR bit is set when a write operation is interrupted by a Reset. In these situations, the user can check the WRERR bit and rewrite the location. It is necessary to reload the data and address registers (EEDATA and EEADR), as these registers have cleared as a result of the Reset. Control bits RD and WR start read and erase/write operations, respectively. These bits are set by firmware, and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 6.1 “Table Reads and Table Writes” regarding table reads. Note: EECON1 is the control register for memory accesses. Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all ‘0’s. The EECON2 register is used exclusively in the memory write and erase sequences. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. 2003 Microchip Technology Inc. Preliminary DS39616B-page 85 PIC18F2331/2431/4331/4431 REGISTER 7-1: EECON1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access program Flash memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration or calibration registers 0 = Access program Flash or data EEPROM memory bit 5 Unimplemented: Read as ‘0’ bit 4 FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write only bit 3 WRERR: EEPROM Error Flag bit 1 = A write operation was prematurely terminated (MCLR or WDT Reset during self-timed erase or program operation) 0 = The write operation completed normally Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. bit 2 WREN: Erase/Write Enable bit 1 = Allows erase/write cycles 0 = Inhibits erase/write cycles bit 1 WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is completed bit 0 RD: Read Control bit 1 = Initiates a memory read (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed Legend: R = Readable bit S = Settable only U = Unimplemented bit, read as ‘0’ W = Writable bit - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown DS39616B-page 86 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). 7.4 To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware. MOVLW MOVWF BCF BSF MOVF Write Verify Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. DATA EEPROM READ DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, RD EEDATA, W EXAMPLE 7-2: Required Sequence At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM interrupt flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software. 7.5 Writing to the Data EEPROM Memory EXAMPLE 7-1: After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. ; ; ; ; ; Data Memory Address to read Point to DATA memory EEPROM Read W = EEDATA DATA EEPROM WRITE MOVLW MOVWF MOVLW MOVWF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF DATA_EE_ADDR EEADR DATA_EE_DATA EEDATA EECON1, EEPGD EECON1, WREN INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; SLEEP BCF EECON1, WREN ; Wait for interrupt to signal write complete ; Disable writes 2003 Microchip Technology Inc. Data Memory Address to write Data Memory Value to write Point to DATA memory Enable writes Disable Interrupts Write 55h Write AAh Set WR bit to begin write Enable Interrupts Preliminary DS39616B-page 87 PIC18F2331/2431/4331/4431 7.7 Operation During Code-Protect 7.8 Data EEPROM memory has its own code-protect bits in configuration words. External Read and Write operations are disabled if either of these mechanisms are enabled. Using the Data EEPROM The Data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124 or D124A. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect configuration bit. Refer to Section 22.0 “Special Features of the CPU” for additional information. A simple data EEPROM refresh routine is shown in Example 7-3. Note: EXAMPLE 7-3: DATA EEPROM REFRESH ROUTINE CLRF BCF BCF BCF BSF EEADR EECON1, EECON1, INTCON, EECON1, BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA EECON1, RD 55h EECON2 AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F Loop BCF BSF EECON1, WREN INTCON, GIE ; ; ; ; ; ; ; ; ; ; ; ; ; CFGS EEPGD GIE WREN LOOP TABLE 7-1: Name INTCON If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124 or D124A. Start at address 0 Set for memory Set for Data EEPROM Disable interrupts Enable writes Loop to refresh array Read current address Write 55h Write AAh Set WR bit to begin write Wait for write to complete ; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR GIE/GIEH PEIE/GIEL TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u EEADR EEPROM Address Register 0000 0000 0000 0000 EEDATA EEPROM Data Register 0000 0000 0000 0000 EECON2 EEPROM Control Register2 (not a physical register) — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD — xx-0 x000 uu-0 u000 IPR2 OSFIP — — EEIP — LVDIP — PIR2 OSFIF — — EEIF — LVDIF — CCP2IF PIE2 OSFIE — — EEIE — LVDIE — CCP2IE 0--0 -0-0 0--0 -0-0 Legend: CCP2IP 1--1 -1-1 1--1 -1-1 0--0 -0-0 0--0 -0-0 x = unknown, u = unchanged, r = reserved, - = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. DS39616B-page 88 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 8.0 8 X 8 HARDWARE MULTIPLIER Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: 8.1 Introduction • Higher computational throughput • Reduces code size requirements for multiply algorithms An 8 x 8 hardware multiplier is included in the ALU of the PIC18F2331/2431/4331/4431 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the Status register. TABLE 8-1: Table 8-1 shows a performance comparison between enhanced devices using the single cycle hardware multiply, and performing the same function without the hardware multiply. PERFORMANCE COMPARISON Routine 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed 8.2 The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. Multiply Method Program Memory (Words) Cycles (Max) @ 40 MHz @ 10 MHz @ 4 MHz 13 69 6.9 µs 27.6 µs 69 µs Without hardware multiply Time Hardware multiply 1 1 100 ns 400 ns 1 µs Without hardware multiply 33 91 9.1 µs 36.4 µs 91 µs Hardware multiply 6 6 600 ns 2.4 µs 6 µs Without hardware multiply 21 242 24.2 µs 96.8 µs 242 µs Hardware multiply 24 24 2.4 µs 9.6 µs 24 µs Without hardware multiply 52 254 25.4 µs 102.6 µs 254 µs Hardware multiply 36 36 3.6 µs 14.4 µs 36 µs EXAMPLE 8-1: Operation Example 8-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 8-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. 2003 Microchip Technology Inc. MOVF MULWF 8 x 8 UNSIGNED MULTIPLY ROUTINE ARG1, W ARG2 EXAMPLE 8-2: ; ; ARG1 * ARG2 -> ; PRODH:PRODL 8 x 8 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1, ARG2 BTFSC SUBWF ARG2, SB PRODH, F MOVF BTFSC SUBWF ARG2, W ARG1, SB PRODH, F Preliminary W ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 DS39616B-page 89 PIC18F2331/2431/4331/4431 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8-1: RES3:RES0 = = 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L (ARG1H • ARG2H • 216)+ (ARG1H • ARG2L • 28)+ (ARG1L • ARG2H • 28)+ (ARG1L • ARG2L) EXAMPLE 8-3: EQUATION 8-2: RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 216)+ (ARG1H • ARG2L • 28)+ (ARG1L • ARG2H ² 28)+ (ARG1L • ARG2L)+ (-1 • ARG2H<7> • ARG1H:ARG1L • 216)+ (-1 • ARG1H<7> • ARG2H:ARG2L • 216) EXAMPLE 8-4: 16 x 16 UNSIGNED MULTIPLY ROUTINE MOVFARG1L, W MULWFARG2L MOVFFPRODH, RES1 MOVFFPRODL, RES0 ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; 16 x 16 SIGNED MULTIPLICATION ALGORITHM 16 x 16 SIGNED MULTIPLY ROUTINE MOVF MULWF ARG1L, W ARG2L MOVFF MOVFF PRODH, RES1 PRODL, RES0 MOVF MULWF ARG1H, W ARG2H MOVFF MOVFF PRODH, RES3 PRODL, RES2 MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, RES1, PRODH, RES2, WREG RES3, MOVF MULWF ARG1H, W ARG2L MOVF ADDWF MOVF ADDWFC CLRF ADDWFC PRODL, RES1, PRODH, RES2, WREG RES3, BTFSS BRA MOVF SUBWF MOVF SUBWFB ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; ; ; MOVFARG1H, W MULWFARG2H MOVFFPRODH, RES3 MOVFFPRODL, RES2 ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; MOVFPRODL, W ADDWFRES1, F MOVFPRODH, W ADDWFCRES2, F CLRFWREG ADDWFCRES3, F ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products W F W F F MOVFPRODL, W ADDWFRES1, F MOVFPRODH, W ADDWFCRES2, F CLRFWREG ADDWFCRES3, F ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ARG1L * ARG2H -> PRODH:PRODL Add cross products W F W F F ; ; ; ; ; ; ; ; ; ARG1H * ARG2L -> PRODH:PRODL Add cross products ; Example 8-4 shows the sequence to do a 16 x 16 signed multiply. Equation 8-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pair’s Most Significant bit (MSb) is tested, and the appropriate subtractions are done. DS39616B-page 90 ; ; ; ; ; ; ; ; ; ; MOVFARG1H, W MULWFARG2L ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; MOVFARG1L, W MULWFARG2H ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE : Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 9.0 INTERRUPTS The PIC18F2331/2431/4331/4431 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will interrupt any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation. These registers are: • • • • • • • RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, each interrupt source has three bits to control its operation. The functions of these bits are: • Flag bit to indicate that an interrupt event occurred • Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set • Priority bit to select high priority or low priority (most interrupt sources have priority bits) When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro® mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. Low priority interrupts are not processed while high priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before reenabling interrupts to avoid recursive interrupts. The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. Note: The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits. 2003 Microchip Technology Inc. Preliminary Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. DS39616B-page 91 PIC18F2331/2431/4331/4431 FIGURE 9-1: INTERRUPT LOGIC Wake-up if in Power-Managed mode TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Interrupt to CPU Vector to Location 0008h INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP PSPIF PSPIE PSPIP GIEH/GIE ADIF ADIE ADIP IPE IPEN GIEL/PEIE RCIF RCIE RCIP IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation PSPIF PSPIE PSPIP ADIF ADIE ADIP RCIF RCIE RCIP Interrupt to CPU Vector to Location 0018h TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP GIEL\PEIE INT0IF INT0IE INT1IF Additional Peripheral Interrupts INT1IE INT1IP INT2IF INT2IE INT2IP DS39616B-page 92 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 9.1 INTCON Registers Note: The INTCON Registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. INTCON REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF bit 7 bit 0 bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all high priority interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all low priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt bit 4 INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt bit 3 RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt for RB7:RB4 pins 0 = Disables the RB port change interrupt for RB7:RB4 pins bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur bit 0 RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Note: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 93 PIC18F2331/2431/4331/4431 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 4 INTEDG2: External Interrupt2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 3 Unimplemented: Read as ‘0’ bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Note: DS39616B-page 94 x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 9-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3 INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt bit 2 Unimplemented: Read as ‘0’ bit 1 INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur bit 0 INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Note: 2003 Microchip Technology Inc. x = Bit is unknown Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. Preliminary DS39616B-page 95 PIC18F2331/2431/4331/4431 9.2 PIR Registers Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag Registers (PIR1, PIR2). REGISTER 9-4: 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’. bit 6 ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full bit 3 SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2 CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: This bit is reserved on PIC18F2X31 devices; always maintain this bit clear. Legend: DS39616B-page 96 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 OSFIF — — EEIF — LVDIF — CCP2IF bit 7 bit 0 bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = System Oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = System clock operating bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIF: EEPROM or Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software) 0 = The supply voltage is greater than the specified LVD voltage bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Not used in PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 97 PIC18F2331/2431/4331/4431 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT FLAG REGISTER 3 U-0 — bit 7 U-0 — U-0 — R/W-0 PTIF R/W-0 IC3DRIF R/W-0 IC2QEIF R/W-0 IC1IF R/W-0 TMR5IF bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIF: PWM Time Base Interrupt bit 1 = PWM Time Base matched the value in PTPER register. Interrupt is issued according to the postscaler settings. PTIF must be cleared in software. 0 = PWM Time Base has not matched the value in PTPER register. bit 3 IC3DRIF: IC3 Interrupt Flag/Direction Change Interrupt Flag bit IC3 Enabled (CAP3CON<3:0>) 1 = TMR5 value was captured by the active edge on CAP3 input (must be cleared in software). 0 = TMR5 capture has not occurred. QEI Enabled (QEIM<2:0>) 1 = Direction of rotation has changed (must be cleared in software). 0 = Direction of rotation has not changed. bit 2 IC2QEIF: IC2 Interrupt Flag/QEI Interrupt Flag bit IC2 Enabled (CAP2CON<3:0>) 1 = TMR5 value was captured by the active edge on CAP2 input (must be cleared in software). 0 = TMR5 capture has not occurred. QEI Enabled (QEIM<2:0>) 1 = The QEI position counter has reached the MAXCNT value or the index pulse, INDX, has been detected. Depends on the QEI operating mode enabled. Must be cleared in software. 0 = The QEI position counter has not reached the MAXCNT value or the index pulse has not been detected. bit 1 IC1IF: IC1 Interrupt Flag bit IC1 Enabled (CAP1CON<3:0>) 1 = TMR5 value was captured by the active edge on CAP1 input (must be cleared in software). 0 = TMR5 capture has not occurred. QEI Enabled (QEIM<2:0>) and Velocity Measurement mode enabled (VELM = 0 in QEICON Register) 1 = Timer5 value was captured by the active velocity edge (based on PHA or PHB input). CAP1REN bit must be set in CAP1CON register. IC1IF must be cleared in software. 0 = Timer5 value was not captured by the active velocity edge. bit 0 TMR5IF: Timer5 Interrupt Flag bit 1 = Timer5 time base matched the PR5 value (must be cleared in software). 0 = Timer5 time base did not match the PR5 value. Legend: DS39616B-page 98 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared Preliminary x = bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable Registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-7: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 99 PIC18F2331/2431/4331/4431 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 U-0 U-0 R/W-0 U-0 R/W-0 U-0 R/W-0 OSFIE — — EEIE — LVDIE — CCP2IE bit 7 bit 0 bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIE: Interrupt Enable bit 1 = Enabled 0 = Disabled bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend: DS39616B-page 100 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 — bit 7 U-0 — U-0 — R/W-0 PTIE R/W-0 IC3DRIE R/W-0 IC2QEIE bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIE: PWM Time Base Interrupt Enable bit 1 = PTIF enabled 0 = PTIF disabled bit 3 IC3DRIE: IC3 Interrupt Enable/Direction Change Interrupt Enable bit IC3 Enabled (CAP3CON<3:0>) 1 = IC3 interrupt enabled 0 = IC3 interrupt disabled QEI Enabled (QEIM<2:0>) 1 = Change-of-direction interrupt enabled 0 = Change-of-direction interrupt disabled bit 2 IC2QEIE: IC2 Interrupt Flag/QEI Interrupt Flag Enable bit IC2 Enabled (CAP2CON<3:0>) 1 = IC2 interrupt enabled) 0 = IC2 interrupt disabled QEI Enabled (QEIM<2:0>) 1 = QEI interrupt enabled 0 = QEI interrupt disabled bit 1 IC1IE: IC1 Interrupt Enable bit 1 = IC1 interrupt enabled 0 = IC1 interrupt disabled bit 0 TMR5IE: Timer5 Interrupt Enable bit 1 = Timer5 interrupt enabled 0 = Timer5 interrupt disabled R/W-0 IC1IE R/W-0 TMR5IE bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared 2003 Microchip Technology Inc. Preliminary x = bit is unknown DS39616B-page 101 PIC18F2331/2431/4331/4431 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two peripheral interrupt priority registers (IPR1, IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 SSPIP: Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority Legend: DS39616B-page 102 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 9-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 U-0 U-0 R/W-1 U-0 R/W-1 U-0 R/W-1 OSFIP — — EEIP — LVDIP — CCP2IP bit 7 bit 0 bit 7 OSFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6-5 Unimplemented: Read as ‘0’ bit 4 EEIP: Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 Unimplemented: Read as ‘0’ bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 103 PIC18F2331/2431/4331/4431 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 U-0 U-0 — U-0 — R/W-1 PTIP R/W-1 IC3DRIP R/W-1 IC2QEIP R/W-1 IC1IP bit 7 bit 7-5 Unimplemented: Read as ‘0’ bit 4 PTIP: PWM Time Base Interrupt Priority bit 1 = High Priority 0 = Low Priority bit 3 IC3DRIP: IC3 Interrupt Priority/Direction Change Interrupt Priority bit IC3 Enabled (CAP3CON<3:0>) 1 = IC3 Interrupt High Priority 0 = IC3 Interrupt Low Priority QEI Enabled (QEIM<2:0>) 1 = Change of Direction Interrupt High Priority 0 = Change of Direction interrupt Low Priority bit 2 IC2QEIP: IC2 Interrupt Priority/QEI Interrupt Priority bit IC2 Enabled (CAP2CON<3:0>) 1 = IC2 Interrupt High Priority 0 = IC2 Interrupt Low Priority QEI Enabled (QEIM<2:0>) 1 = High Priority 0 = Low Priority bit 1 IC1IP: IC1 Interrupt Priority bit 1 = High Priority 0 = Low Priority bit 0 TMR5IP: Timer5 Interrupt Priority bit 1 = High Priority 0 = Low Priority R/W-1 TMR5IP bit 0 Legend: DS39616B-page 104 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared Preliminary x = bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from powermanaged mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-13: RCON REGISTER R/W-0 U-0 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN — — RI TO PD POR BOR bit 7 bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit For details of bit operation, see Register 5-3 bit 3 TO: Watchdog Time-out Flag bit For details of bit operation, see Register 5-3 bit 2 PD: Power-down Detection Flag bit For details of bit operation, see Register 5-3 bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 5-3 bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 105 PIC18F2331/2431/4331/4431 9.6 INTn Pin Interrupts 9.7 External interrupts on the RC3/INT0, RC4/INT1 and RC5/INT2 pins are edge triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RC3/INT0 pin, the corresponding flag bit INTxF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxE. Flag bit INTxF must be cleared in software in the interrupt service routine before re-enabling the interrupt. All external interrupts (INT0, INT1 and INT2) can wake-up the processor from the power-managed modes, if bit INTxE was set prior to going into powermanaged modes. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1 and INT2 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>) and INT2IP (INTCON3<7>). There is no priority bit associated with INT0. It is always a high priority interrupt source. TMR0 Interrupt In 8-bit mode (which is the default), an overflow (FFh → 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (FFFFh → 0000h) in the TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2<2>). See Section 11.0 “Timer0 Module” for further details. 9.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>). 9.9 Context Saving During Interrupts During interrupts, the return PC address is saved on the stack. Additionally, the WREG, Status and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (See Section 5.3 “Fast Register Stack”), the user may need to save the WREG, Status and BSR registers on entry to the interrupt service routine. Depending on the user’s application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, Status and BSR registers during an interrupt service routine. EXAMPLE 9-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF SAVING STATUS, WREG AND BSR REGISTERS IN RAM W_TEMP STATUS,STATUS_TEMP BSR,BSR_TEMP ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ISR CODE BSR_TEMP,BSR W_TEMP, W STATUS_TEMP, STATUS DS39616B-page 106 ; Restore BSR ; Restore WREG ; Restore STATUS Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.0 I/O PORTS 10.1 Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: • TRIS register (data direction register) • PORT register (reads the levels on the pins of the device) • LAT register (output latch) The data latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. A simplified model of a generic I/O port without the interfaces to other peripherals is shown in Figure 10-1. FIGURE 10-1: GENERIC I/O PORT OPERATION RD LAT Data Bus D Q I/O pin(1) WR LAT or PORT CK PORTA, TRISA and LATA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch register (LATA) is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The RA<2:4> pins are multiplexed with three input capture pins and Quadrature Encoder Interface pins. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in Configuration Register 1H (see Section 22.1 “Configuration Bits” for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as ‘0’. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins RA3:RA0 and RA5 as A/D converter inputs is selected by clearing/setting the control bits in the ANSEL0 and ANSEL1 registers. Data Latch D WR TRIS Note 1: On a Power-on Reset, RA5:RA0 are configured as analog inputs and read as ‘0’. Q 2: RA5 I/F is available only on 40-pin devices (PIC18F4X31). CK TRIS Latch Input Buffer RD TRIS Q The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. D EXAMPLE 10-1: ENEN CLRF RD PORT Note 1: I/O pins have diode protection to VDD and VSS. CLRF MOVLW MOVWF MOVLW MOVWF 2003 Microchip Technology Inc. Preliminary PORTA ; ; ; LATA ; ; ; 0x3F ; ANSEL0 ; 0xCF ; ; ; TRISA ; ; INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs DS39616B-page 107 PIC18F2331/2431/4331/4431 FIGURE 10-2: BLOCK DIAGRAM OF RA0 FIGURE 10-3: BLOCK DIAGRAM OF RA1 VDD P RD LATA Data Bus D Data Bus Q VDD WR LATA or PORTA Q CK WR LATA or PORTA P Data Latch D WR TRISA CK I/O Pin WR TRISA TRIS Latch RA1 Q N CK VSS Q Q Analog Input Mode TRIS Latch VSS Analog Input Mode Q Q Data Latch D N Q CK RD LATA D RD TRISA TTL TTL Input Buffer RD TRISA Q Q D EN D RD PORTA EN To A/D Converter RD PORTA To A/D Converter FIGURE 10-4: BLOCK DIAGRAM OF RA3:RA2 PINS VDD P RD LATA Data Bus WR LATA or PORTA D I/O Pin CK Q Data Latch D WR TRISA Q N Q VSS CK Q Analog Input Mode TRIS Latch TTL RD TRISA Q Schmitt Trigger Input Buffer D EN RD PORTA To A/D Converter To CAP1/INDX or CAP2/QEA DS39616B-page 108 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 10-5: BLOCK DIAGRAM OF RA4 RD LATA Data Bus WR LATA or PORTA D Q VDD CK Q P Data Latch D Q WR TRISA CK RA4(1) N VSS Schmitt Trigger Input Buffer Q Analog Input Mode TRIS Latch TTL Input Buffer RD TRISA Q D EN RD PORTA To A/D Converter To CAP3/QEB Note 1: Open-drain usually available on RA4 has been removed for this device. 2003 Microchip Technology Inc. Preliminary DS39616B-page 109 PIC18F2331/2431/4331/4431 FIGURE 10-6: BLOCK DIAGRAM OF RA5 FIGURE 10-8: BLOCK DIAGRAM OF RA7 INTOSC Enable RD LATA Data Bus D Data Bus TO OSCILLATOR Q RD LATA VDD WR LATA or PORTA CK Q P Data Latch D WR TRISA N Q CK I/O Pin WR LATA or PORTA Analog Input Mode or LVDIN Enabled TRIS Latch CK Q VDD P D Q N CK Q VSS TRIS Latch TTL Input Buffer RD TRISA Q Q Data Latch VSS Q D D I/O Pin INTOSC w/RA7 Enable TTL Input Buffer RD TRISA EN Q RD PORTA D EN To A/D Converter/LVD Module Input FIGURE 10-7: Data Bus RD PORTA BLOCK DIAGRAM OF RA6 ECRA6 or RCRA6 Enable TO OSCILLATOR RD LATA WR LATA or PORTA D Q CK Q VDD P Data Latch D Q CK Q TRIS Latch N I/O Pin VSS ECRA6 or RCRA6 Enable TTL Input Buffer RD TRISA Q D EN RD PORTA DS39616B-page 110 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 10-1: PORTA FUNCTIONS Name Bit # Buffer Function RA0/AN0 bit 0 TTL Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF-/CAP1/INDX bit 2 TTL/ST Input/output, analog input, VREF-, capture input, or QEI Index input. RA3/AN3/VREF+/CAP2/QEA bit 3 TTL/ST Input/output, analog input, VREF+, capture input, or Quadrature Channel A input. RA4/AN4/CAP3/QEB bit 4 TTL/ST Input/output, analog input, capture input, or Quadrature Channel B input. RA5/AN5/LVDIN bit 5 TTL Input/output, analog input, or low-voltage detect input. OSC2/CLKO/RA6 bit 6 TTL OSC2, clock output or I/O pin. OSC1/CLKI/RA7 bit 7 TTL OSC1, clock input or I/O pin. Legend: TTL = TTL input, ST = Schmitt Trigger input TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 xx0x 0000 uu0u 0000 LATA LATA7(1) LATA6(1) xxxx xxxx uuuu uuuu TRISA TRISA7(1) TRISA6(1) PORTA Data Direction Register 1111 1111 1111 1111 Name PORTA ADCON1 VCFG1 VCFG0 ANSEL0 ANS7(2) ANS6(2) ANSEL1 — — Legend: Note 1: 2: LATA Data Output Register — FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0 00-1 0000 00-1 0000 ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 — — — — — ANS8(2) ---- ---1 ---- ---1 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. ANS5 through ANS8 are available only on the PIC18F4X31 devices. 2003 Microchip Technology Inc. Preliminary DS39616B-page 111 PIC18F2331/2431/4331/4431 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 10-2: CLRF PORTB CLRF LATB MOVLW 0xCF MOVWF TRISB INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; This interrupt can wake the device from Sleep. The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. DS39616B-page 112 Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are ORed together to generate the RB port change interrupt with flag bit, RBIF (INTCON<0>). RB<0:3> and RB4 pins are multiplexed with the 14-bit PWM module for PWM<0:3> and PWM5 output. The RB5 pin can be configured by the configuration bit PWM4MX as the alternate pin for PWM4 output. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 10-9: BLOCK DIAGRAM OF RB3:RB0 PINS VDD RBPU(1) Weak P Pull-up PORT/PWM Select PWM0,1,2, 3 Data VDD 0 P RD LATC Data Bus WR LATB or PORTB D CK Q RB<3:0> Pins Q Data Latch D WR TRISB 1 N Q VSS CK Q TTL Input Buffer TRIS Latch RD TRISB Q EN RD PORTB Note 1: D To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2003 Microchip Technology Inc. Preliminary DS39616B-page 113 PIC18F2331/2431/4331/4431 FIGURE 10-10: BLOCK DIAGRAM OF RB4 VDD RBPU(1) Weak P Pull-up PORT/PWM Select PWM5 Data VDD 0 P 1 RD LATC Data Bus WR LATB or PORTB D CK RB4 Pin Q Data Latch D WR TRISB Q N Q VSS CK Q TTL Input Buffer TRIS Latch RD TRISB RD LATB Q D EN Q1 RD PORTB Set RBIF From other RB7:RB4 pins Q D RD PORTB EN Note 1: DS39616B-page 114 Q3 To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 10-11: BLOCK DIAGRAM OF RB5 PORT/PWM Select 0 PWM4 Data VDD P 1 N VSS VDD RBPU Data Bus D Weak P Pull-up Q RB5/PGM WR PORT Q CK Data Latch D WR TRIS Q CK TRIS Latch TTL Input Buffer Schmitt Trigger RD TRIS Q D RD PORT EN Q1 Set RBIF Q From other RB7:RB4 pins D RD Port EN Q3 LVP Configuration Bit 1 = Low V Prog Enable 0 = only HV Prog Enable ICSP 2003 Microchip Technology Inc. Preliminary DS39616B-page 115 PIC18F2331/2431/4331/4431 FIGURE 10-12: BLOCK DIAGRAM OF RB7:RB6 PINS Enable Debug or ICSP RBPU(1) P Weak Pull-up 0 1 RD LATB D Data Bus WR LATB or PORTB CK Enable Debug Q 0 Data Latch D WR TRISB CK RB7/RB6 Pin BRBx Q 1 Enable Debug Q BTRISx Q TRIS Latch TTL Input Buffer RD TRISC Q RD PORTB Enable Debug or ICSP Schmitt Trigger D EN Q1 Set RBIF Q D RD PORTB From other RB7:RB4 pins EN Q3 PGC(2)/PGD(3) Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 2: PGC is available on RB6. 3: PGD is available on RB7. DS39616B-page 116 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 10-3: PORTB FUNCTIONS Name Bit # Buffer RB0/PWM0 bit 0 (1) Function TTL Input/output pin, or PCPWM output PWM0. Internal software programmable weak pull-up. RB1/PWM1 bit 1 TTL(1) Input/output pin, or PCPWM output PWM1. Internal software programmable weak pull-up. RB2/PWM2 bit 2 TTL(1) Input/output pin, or PCPWM output PWM2. Internal software programmable weak pull-up. RB3/PWM3 bit 3 TTL(1) Input/output pin, or PCPWM output PWM3. Internal software programmable weak pull-up. RB4/KBI0/PWM5 bit 4 TTL Input/output pin (with interrupt-on-change), or PCPWM output PWM5. Internal software programmable weak pull-up. RB5/KBI1/PWM4/ PGM bit 5 TTL/ST(2) Input/output pin (with interrupt-on-change) or PCPWM output PWM4. Internal software programmable weak pull-up. Low-voltage ICSP enable pin. RB6/KBI2/PGC bit 6 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. RB7/KBI3/PGD bit 7 TTL/ST(2) Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a TTL input when configured as digital I/O. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 10-4: Name PORTB SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxq qqqq uuuu uuuu LATB LATB Data Output Register xxxx xxxx uuuu uuuu TRISB PORTB Data Direction Register 1111 1111 1111 1111 INTCON GIE/GIEH PEIE/GIEL TMR0IE 0000 000u INTCON2 RBPU INTCON3 INT2IP Legend: INT0IE INTEDG0 INTEDG1 INTEDG2 INT1IP — INT2IE RBIE TMR0IF INT0IF RBIF 0000 000x — TMR0IP — RBIP 1111 -1-1 1111 -1-1 INT1IE — INT2IF INT1IF 11-0 0-00 11-0 0-00 x = unknown, u = unchanged, q = value depends on condition. Shaded cells are not used by PORTB. 2003 Microchip Technology Inc. Preliminary DS39616B-page 117 PIC18F2331/2431/4331/4431 10.3 PORTC, TRISC and LATC Registers External interrupts, IN0, INT1 and INT2, are placed on RC3, RC4 and RC5 respectively. SSP alternate interface pins, SDI/SDA, SCK/SCL and SDO are placed on RC4, RC5, and RC7 pins respectively. PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). These pins are multiplexed on PORTC and PORTD by using the SSPMX bit in the CONFIG3L register. USART pins RX/DT and TX/CK are placed on RC7 and RC6 respectively. The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. The alternate Timer5 external clock input, T5CKI, and the alternate TMR0 external clock input, T0CKI, are placed on RC3 and are multiplexed with the PORTD (RD0) pin using the EXCLKMX configuration bit in CONFIG3L. Fault inputs to the 14-bit PWM module, FLTA and FLTB, are located on RC1 and RC2. FLTA input on RC1 is multiplexed with RD4 using the FLTAMX bit. PORTC is multiplexed with several peripheral functions (Table 10-5). The pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. Note: EXAMPLE 10-3: On a Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. FIGURE 10-13: CLRF PORTC CLRF LATC MOVLW 0xCF MOVWF TRISC INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC<3:0> as inputs RC<5:4> as outputs RC<7:6> as inputs BLOCK DIAGRAM OF RC0 VDD P RD LATC Data Bus WR LATC or PORTC D CK RC0 Pin Q Data Latch D WR TRISC Q N Q VSS CK Q Timer1 Oscillator TRIS Latch T1 OSC EN Schmitt Trigger RD TRISC Q To RC1 Pin D EN RD PORTC T1 Clock Input DS39616B-page 118 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 10-14: BLOCK DIAGRAM OF RC1 PORT/CCP2 Select CCP2 Data Out VDD 0 To RC0 Pin P 1 RD LATC Data Bus WR LATC or PORTC D Q CK Data Latch D WR TRISC RC1 Pin Q N Q VSS CK Q TRIS Latch Schmitt Trigger RD TRISC Q FLTAMX D EN RD PORTC CCP2 Input FLTA input(1) Note 1: FLTA input is multiplexed with RC1 and RD4 using FLTAMX configuration bit in CONFIG3L register. FIGURE 10-15: BLOCK DIAGRAM OF RC2 PORT/CCP1 Select CCP1 Data Out VDD 0 P RD LATC Data Bus WR LATC or PORTC D CK Q RC2 Pin Q Data Latch D WR TRISC 1 N Q VSS CK Q TRIS Latch Schmitt Trigger RD TRISC Q D EN RD PORTC CCP1 Input/FLTB input 2003 Microchip Technology Inc. Preliminary DS39616B-page 119 PIC18F2331/2431/4331/4431 FIGURE 10-16: BLOCK DIAGRAM OF RC3 VDD P RD LATC Data Bus D WR LATC or PORTC Q RC3 Pin Q CK Data Latch D N Q VSS WR TRISC Q CK TRIS Latch Schmitt Trigger RD TRISC Q EXCLKMX_enable(1) D EN RD PORTC T0CKI/T5CKI Input Note 1: The T0CKI/T5CKI bit is multiplexed with RD0 when the EXCLKM is enabled (= 1 ) in the configuration register. FIGURE 10-17: BLOCK DIAGRAM OF RC4 PORT/SSP Mode & SSPMX Select SDA Data Out VDD 0 P RD LATC Data Bus WR LATC or PORTC D CK Q RC4 Pin Q Data Latch D WR TRISC 1 N Q VSS CK Q TRIS Latch SDA Drive Schmitt Trigger RD TRISC Q SSPMX(1) D EN RD PORTC SDI/SDA Input Note 1: The SDI/SDA bits are multiplexed on RD2 and RC4 pins by SSPMX bit in the configuration register. DS39616B-page 120 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 10-18: BLOCK DIAGRAM OF RC5 I2C™ Mode PORT/ SSPEN & SSPMX_ Select SCK/SCL Data Out VDD 0 P 1 RD LATC Data Bus D WR LATC or PORTC Q RC5 Pin Q CK Data Latch D N Q VSS WR TRISC Q CK TRIS Latch SSPMX(1) Schmitt Trigger RD TRISC SDO Drive Q D EN RD PORTC SCL or SCL input Note 1: SCK/SCL are multiplexed on RD3 and RC5 using SSPMX bit in the configuration register. FIGURE 10-19: BLOCK DIAGRAM OF RC6 USART Select TX Data Out/CK VDD 0 P RD LATC Data Bus WR LATC or PORTC D CK Q RC6 Pin Q Data Latch D WR TRISC 1 N Q VSS CK Q TRIS Latch USART Select Schmitt Trigger RD TRISC Q TTL D EN RD PORTC CK Input SS input 2003 Microchip Technology Inc. Preliminary DS39616B-page 121 PIC18F2331/2431/4331/4431 FIGURE 10-20: BLOCK DIAGRAM OF RC6 USART Select (1) DT Data Out PORT/(SSPEN * SPI Mode ) Select 0 SDO Data Out(2) 0 VDD 1 P RD LATC Data Bus WR LATC or PORTC D CK Q RC7 Pin Q Data Latch D WR TRISC 1 N Q VSS CK Q TRIS Latch USART Select(1) Schmitt Trigger RD TRISC Q D EN RD PORTC RX/DT Data Input Note 1: 2: USART is in Synchronous Master Transmission mode only (SYNC = 1, TXEN = 1). SDO must have its TRISC bit cleared in order to be able to drive RC7. DS39616B-page 122 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 10-5: PORTC FUNCTIONS Name Bit # Buffer Type Function RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2/ FLTA bit 1 ST/CMOS Input/output port pin, Timer1 oscillator input, or Capture2 input/ Compare2 output/PWM output when CCP2MX configuration bit is disabled, or FLTA input. RC2/CCP1/FLTB bit 2 ST Input/output port pin, Capture1 input/Compare1 output/PWM1 output, or FLTB input. RC3/T0CKI/T5CKI/ INT0 bit 3 ST Input/output port pin, Timer0 and Timer5 alternate clock input, or external interrupt 0. RC4/INT1/SDI/SDA bit 4 ST Input/output port pin, SPI Data in, I2C Data I/O, or external interrupt 1. RC5/INT2/SCK/SCL bit 5 ST Input/output port pin or Synchronous Serial Port Clock I/O, or external interrupt 2. RC6/TX/CK/SS bit 6 ST Input/output port pin, EUSART Asynchronous Transmit, EUSART Synchronous Clock, or SPI Slave Select input. RC7/RX/DT/SDO bit 7 ST Input/output port pin, EUSART Asynchronous Receive, EUSART Synchronous Data, or SPI Data out. Legend: ST = Schmitt Trigger input TABLE 10-6: Name PORTC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu LATC LATC Data Output Register TRISC PORTC Data Direction Register INTCON GIE/GIEH PEIE/GIEL INTCON2 INTCON3 Legend: RBPU INTEDG0 INT2IP INT1IP TMR0IE INT0IE INTEDG1 INTEDG2 — INT2IE 1111 1111 1111 1111 RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u — TMR0IP — RBIP 1111 -1-1 1111 -1-1 INT1IE — INT2IF INT1IF 11-0 0-00 11-0 0-00 x = unknown, u = unchanged 2003 Microchip Technology Inc. Preliminary DS39616B-page 123 PIC18F2331/2431/4331/4431 10.4 PORTD, TRISD and LATD Registers Note: PORTD includes PWM<7:6> complementary fourth channel PWM outputs. PWM4 is the complementary output of PWM5 (the third channel), which is multiplexed with the RB5 pin. This output can be used as the alternate output using the PWM4MX configuration bit in CONFIG3L when the low-voltage programming pin (PGM) is used on RB5. PORTD is only available on PIC18F4X31 devices. PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). RD1, RD2 and RD3 can be used as the alternate output for SDO, SDI/SDA and SCK/SCL using the SSPMX configuration bit in CONFIG3L. RD4 an be used as the alternate output for FLTA using the FLTAMX configuration bit in CONFIG3L. EXAMPLE 10-4: The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Note: On a Power-on Reset, these pins are configured as digital inputs. FIGURE 10-21: CLRF PORTD CLRF LATD MOVLW 0xCF MOVWF TRISD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD<3:0> as inputs RD<5:4> as outputs RD<7:6> as inputs BLOCK DIAGRAM OF RD7:RD6 PINS PORT/PWM Select PWM6,7 Data Out VDD 0 P 1 RD LATD Data Bus WR LATD or PORTD D CK RD[7:6] Pin Q Data Latch D WR TRISD Q N Q VSS CK Q TRIS Latch RD TRISD Schmitt Trigger Q D EN RD PORTD DS39616B-page 124 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 10-22: BLOCK DIAGRAM OF RD5 PORT/PWM Select PWM4 Data Out* VDD 0 P 1 RD LATD Data Bus D WR LATD or PORTD Q CK RD5 Pin Q Data Latch D N Q VSS WR TRISD CK Q TRIS Latch RD TRISD Schmitt Trigger Q D EN RD PORTD FIGURE 10-23: BLOCK DIAGRAM OF RD4 VDD P RD LATD Data Bus WR LATD or PORTD D CK RD4 Pin Q Data Latch D WR TRISD Q N Q VSS CK Q TRIS Latch RD TRISD Schmitt Trigger Q Schmitt Trigger FLTAMX(1) D EN RD PORTD FLTA input Note 1: FLTAMX is located in the configuration register. 2003 Microchip Technology Inc. Preliminary DS39616B-page 125 PIC18F2331/2431/4331/4431 FIGURE 10-24: I2C™ BLOCK DIAGRAM OF RD3 Mode PORT/ SSPEN & SSPMX Select SCK/SCL Data Out VDD 0 P 1 RD LATD Data Bus WR LATD or PORTD D CK RD3 Pin Q Data Latch D WR TRISD Q N Q VSS CK Q TRIS Latch SSPMX Schmitt Trigger RD TRISD Q (1) D EN RD PORTC SCK or SCL input Note 1: SCK/SCL are multiplexed on RD3 and RC5 using SSPMX bit in the configuration register. FIGURE 10-25: BLOCK DIAGRAM OF RD2 PORT/SSP Mode & SSPMX Select SDA Data Out VDD 0 P RD LATC Data Bus WR LATC or PORTC D CK Q RD2Pin Q Data Latch D WR TRISC 1 N Q VSS CK Q TRIS Latch SDA Drive Schmitt Trigger RD TRISC Q SSPMX(1) D EN RD PORTC SDI/SDA Input Note 1: The SDI/SDA bits are multiplexed on RD2 and RC4 pins by SSPMX bit in the configuration register. DS39616B-page 126 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 10-26: BLOCK DIAGRAM OF RD1 PORT/SPI Mode & SSPMX Select SDO Data Out VDD 0 P RD LATD Data Bus WR LATD or PORTD D CK 1 Q RD1 Pin Q Data Latch D N Q VSS WR TRISD CK Q TRIS Latch Schmitt Trigger RD TRISD Q D EN RD PORTD Note 1: The SDO output is multiplexed by SSPMX bit in the configuration register. FIGURE 10-27: BLOCK DIAGRAM OF RD0 VDD P RD LATD Data Bus WR LATD or PORTD D CK Q RD0 Pin Q Data Latch D N Q VSS WR TRISD CK Q TRIS Latch Schmitt Trigger RD TRISD Q SSPMX(1) D EN RD PORTD T0CKI/T5CKI Input Note 1: T0CKI/T5CKI are multiplexed by SSPMX bit in the configuration register. 2003 Microchip Technology Inc. Preliminary DS39616B-page 127 PIC18F2331/2431/4331/4431 TABLE 10-7: PORTD FUNCTIONS Name Bit # Buffer Type Function RD0/T0CKI/T5CKI bit 0 ST Input/output port pin. RD1/SDO bit 1 ST Input/output port pin. RD2/SDI/SDA bit 2 ST Input/output port pin. RD3/SCK/SCL bit 3 ST Input/output port pin. RD4/FLTA bit 4 ST Input/output port pin. RD5/PWM4 bit 5 ST Input/output port pin, or PCPWM output PWM4. RD6/PWM6 bit 6 ST Input/output port pin, or PCPWM output PWM6. RD7/PWM7 bit 7 ST Input/output port pin, or PCPWM output PWM7. Legend: ST = Schmitt Trigger input, TTL = TTL input TABLE 10-8: Name PORTD SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu LATD LATD Data Output Register xxxx xxxx uuuu uuuu TRISD PORTD Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. DS39616B-page 128 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 10.5 Note: PORTE, TRISE and LATE Registers PORTE is only available on PIC18F4X31 devices. PORTE is a 4-bit wide bidirectional port. Three pins (RE0/AN6, RE1/AN67 and RE2/AN8) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, RE2:RE0 are configured as analog inputs. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. The fourth pin of PORTE (MCLR/VPP/RE3) is an input only pin. Its operation is controlled by the MCLRE configuration bit in Configuration Register 3H (CONFIG3H<7>). When selected as a port pin (MCLRE = 0), it functions as a digital input only pin. As such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the device’s master clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note: On a Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled. EXAMPLE 10-5: CLRF PORTE CLRF LATE MOVLW MOVWF bcf MOVLW 0x3F ANSEL0 ANSEL1, 0 0x03 MOVWF TRISE 10.5.1 INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RE<0> as input RE<1> as output RE<2> as input PORTE IN 28-PIN DEVICES For PIC18F2X31 devices, PORTE is only available when master clear functionality is disabled (CONFIG3H<7> = 0). In these cases, PORTE is a single bit, input only port comprised of RE3 only. The pin operates as previously described. 2003 Microchip Technology Inc. Preliminary DS39616B-page 129 PIC18F2331/2431/4331/4431 FIGURE 10-28: RE2:RE0 BLOCK DIAGRAM VDD P RD LATE Data Bus D WR LATE or PORTE Q CK RE<0:2> Pins Q Data Latch D WR TRISE N Q CK VSS Q TRIS Latch Analog Input Mode RD TRISE Schmitt Trigger Q TTL D EN RD PORTE To A/D Converter ch. AN6 or AN7 or AN8 FIGURE 10-29: RE3 BLOCK DIAGRAM MCLR/VPP/RE3 MCLRE Data Bus Schmitt Trigger RD TRISE RD LATE Latch Q D EN RD PORTE High Voltage Detect Internal MCLR HV MCLRE FILTER Low Level MCLR Detect Note 1: Pin requires special protection due to HV. DS39616B-page 130 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 10-1: TRISE REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 Unimplemented: Read as ‘0’ bit 5 Unimplemented: Read as ‘0’ bit 4 Unimplemented: Read as ‘0’ bit 3 Unimplemented: Read as ‘0’ bit 2 TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1 TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 131 PIC18F2331/2431/4331/4431 TABLE 10-9: PORTE FUNCTIONS Name Bit # Buffer Type Function RE0/AN6 bit 0 ST Input/output port pin, analog input. RE1/AN7 bit 1 ST Input/output port pin, analog input. RE2/AN8 bit 2 ST Input/output port pin, analog input. MCLR/VPP/RE3 bit 3 ST Input only port pin or programming voltage input (if MCLR is disabled); Master Clear input or programming voltage input (if MCLR is enabled). Legend: ST = Schmitt Trigger input, TTL = TTL input TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 2 Bit 1 Bit 0 RE2 RE1 RE0 Value on POR, BOR Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PORTE — — — — RE3(1) ---- q000 ---- q000 LATE — — — — — LATE Data Output Register ---- -xxx ---- -uuu TRISE — — — — — PORTE Data Direction bits ---- -111 ---- -111 ANSEL0 ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 ANSEL1 ANS15 ANS14 ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 ---- ---0 ---- ---0 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’, q = value depends on condition. Shaded cells are not used by PORTE. Note 1: Implemented only when Master Clear functionality is disabled (CONFIG3H<7> = 0). DS39616B-page 132 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.0 TIMER0 MODULE The Timer0 module has the following features: • Software selectable as an 8-bit or 16-bit timer/ counter • Readable and writable • Dedicated 8-bit software programmable prescaler • Clock source selectable to be external or internal • Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode • Edge select for external clock REGISTER 11-1: Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. T0CON: TIMER0 CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 TMR0ON T016BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 bit 7 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 bit 6 T016BIT: Timer0 16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) bit 4 T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. bit 2-0 T0PS2:T0PS0: Timer0 Prescaler Select bits 111 =1:256 prescale value 110 =1:128 prescale value 101 =1:64 prescale value 100 =1:32 prescale value 011 =1:16 prescale value 010 =1:8 prescale value 001 =1:4 prescale value 000 =1:2 prescale value Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 133 PIC18F2331/2431/4331/4431 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 T0CKI pin 0 1 Programmable Prescaler 1 Sync with Internal Clocks TMR0 (2 TCY delay) T0SE 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE FOSC/4 T0CKI pin 0 0 1 Programmable Prescaler 1 Sync with Internal Clocks TMR0L TMR0 High Byte 8 (2 TCY delay) T0SE 3 Set Interrupt Flag bit TMR0IF on Overflow Read TMR0L T0PS2, T0PS1, T0PS0 T0CS PSA Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale. DS39616B-page 134 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 11.1 11.2.1 Timer0 Operation Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. 11.3 When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. 11.4 The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. A write to the high byte of Timer0 must also take place through the TMR0H buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, x....etc.) will clear the prescaler count. Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment. TABLE 11-1: Name 16-Bit Mode Timer Reads and Writes TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 11-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. Prescaler An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. Note: Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep mode, since the timer requires clock cycles, even when T0CS is set. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RC3/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. 11.2 SWITCHING PRESCALER ASSIGNMENT REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0L Timer0 Module Low Byte Register xxxx xxxx uuuu uuuu TMR0H Timer0 Module High Byte Register 0000 0000 0000 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u T0CON TMR0ON T016BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 1111 1111 1111 1111 1111 1111 1111 1111 TRISA RA7 (1) RA6 (1) PORTA Data Direction Register Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the Oscillator mode selected in Configuration Word 1H. 2003 Microchip Technology Inc. Preliminary DS39616B-page 135 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 136 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module special event trigger • Status of system clock operation Figure 12-1 is a simplified block diagram of the Timer1 module. REGISTER 12-1: Register 12-1 details the Timer1 control register. This register controls the Operating mode of the Timer1 module, and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit TMR1ON (T1CON<0>). The Timer1 oscillator can be used as a secondary clock source in power-managed modes. When the T1RUN bit is set, the Timer1 oscillator provides the system clock. If the Fail-Safe Clock Monitor is enabled and the Timer1 oscillator fails while providing the system clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. T1CON: TIMER1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON bit 7 bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register read/write of TImer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations bit 6 T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 =1:8 Prescale value 10 =1:4 Prescale value 01 =1:2 Prescale value 00 =1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut-off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1 (External Clock): 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0 (Internal Clock): This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 137 PIC18F2331/2431/4331/4431 12.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2/FLTA and RC0/T1OSO/ T1CKI pins become inputs. That is, the TRISC1:TRISC0 value is ignored, and the pins are read as ‘0’. The Operating mode is determined by the Clock Select bit, TMR1CS (T1CON<1>). Timer1 also has an internal “Reset input”. This Reset can be generated by the CCP module (see Section 15.4.4 “Special Event Trigger”). FIGURE 12-1: TIMER1 BLOCK DIAGRAM CCP Special Event Trigger TMR1IF Overflow Interrupt Flag Bit TMR1 TMR1H 1 TMR1ON On/Off T1OSC T1CKI/T1OSO T1OSCEN Enable Oscillator(1) T1OSI Synchronized Clock Input 0 CLR TMR1L T1SYNC 1 Synchronize Prescaler 1, 2, 4, 8 FOSC/4 Internal Clock det 0 2 T1CKPS1:T1CKPS0 Peripheral Clocks TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. FIGURE 12-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 8 Write TMR1L CCP Special Event Trigger Read TMR1L TMR1IF Overflow Interrupt Flag bit TMR1 8 Timer 1 High Byte CLR TMR1L 1 TMR1ON on/off T1OSC T1CKI/T1OSO T1OSI Synchronized Clock Input 0 T1SYNC 1 T1OSCEN Enable Oscillator(1) Synchronize Prescaler 1, 2, 4, 8 FOSC/4 Internal Clock det 0 2 Peripheral Clocks TMR1CS T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS39616B-page 138 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 12.2 Timer1 Oscillator 12.3 A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure 12-3. Table 12-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 12-3: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR C1 33 pF PIC18FXXXX XTAL 32.768 kHz The low-power option is enabled by clearing the T1OSCMX bit (CONFIG3L<5>). By default, the option is disabled, which results in a more-or-less constant current draw for the Timer1 oscillator. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. T1OSO C2 33 pF See the notes with Table 12-1 for additional information about capacitor selection. TABLE 12-1: The Timer1 oscillator for PIC18F2331/2431/4331/4431 devices incorporates an additional low-power feature. When this option is selected, it allows the oscillator to automatically reduce its power consumption when the microcontroller is in Sleep mode. During normal device operation, the oscillator draws full current. As high noise environments may cause excessive oscillator instability in Sleep mode, this option is best suited for low noise applications where power conservation is an important design consideration. Due to the low power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. T1OSI Note: Timer1 Oscillator Layout Considerations CAPACITOR SELECTION FOR THE TIMER OSCILLATOR If a high-speed circuit must be located near the oscillator (such as the CCP1 pin in output compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 12-4, may be helpful when used on a single sided PCB, or in addition to a ground plane. FIGURE 12-4: Osc Type Freq C1 C2 LP 32 kHz 27 pF(1) 27 pF(1) OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit. VSS 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. OSC1 OSC2 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. RC0 RC1 4: Capacitor values are for design guidance only. RC2 Note: Not drawn to scale. 2003 Microchip Technology Inc. Preliminary DS39616B-page 139 PIC18F2331/2431/4331/4431 12.4 Timer1 Interrupt 12.7 The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). 12.5 Resetting Timer1 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion if the A/D module is enabled (see Section 15.4.4 “Special Event Trigger” for more information.). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>). Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1. 12.6 Timer1 16-Bit Read/Write Mode Using Timer1 as a Real-Time Clock Adding an external LP oscillator to Timer1 (such as the one described in Section 12.2 “Timer1 Oscillator”), gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base, and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine RTCisr, shown in Example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one. Additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16-bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the MSbit of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode, and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine RTCinit. The Timer1 oscillator must also be enabled and running at all times. Timer1 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid, due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 high byte buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. DS39616B-page 140 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 0x80 TMR1H TMR1L b’00001111’ T1OSC secs mins .12 hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .59 secs ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? ; ; ; ; No, done Clear seconds Increment minutes 60 minutes elapsed? ; ; ; ; No, done clear minutes Increment hours 24 hours elapsed? ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ; ; Enable Timer1 interrupt RTCisr TABLE 12-2: Name Bit 7 secs mins, F .59 mins mins hours, F .23 hours ; No, done ; Reset hours to 1 .01 hours ; Done REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF -000 000x 0000 000u PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 -111 1111 INTCON GIE/GIEH PEIE/GIEL TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON Legend: RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 u0uu uuuu x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2003 Microchip Technology Inc. Preliminary DS39616B-page 141 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 142 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 13.0 TIMER2 MODULE 13.1 The Timer2 module timer has the following features: • • • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match with PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 has a control register shown in Register 13-1. TMR2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 13-1 is a simplified block diagram of the Timer2 module. Register 13-1 shows the Timer2 control register. The prescaler and postscaler selection of Timer2 are controlled by this register. REGISTER 13-1: Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). The prescaler and postscaler counters are cleared when any of the following occurs: • A write to the TMR2 register • A write to the T2CON register • Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 R/W-0 R/W-0 TMR2ON T2CKPS1 R/W-0 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 =1:2 Postscale • • • 1111 =1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 143 PIC18F2331/2431/4331/4431 13.2 Timer2 Interrupt 13.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 13-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate the shift clock. TIMER2 BLOCK DIAGRAM Sets Flag bit TMR2IF TMR2 Output(1) Prescaler 1:1, 1:4, 1:16 FOSC/4 2 TMR2 Reset Postscaler 1:1 to 1:16 Comparator EQ T2CKPS1:T2CKPS0 4 PR2 TOUTPS3:TOUTPS0 Note 1: TABLE 13-1: Name TMR2 register output can be software selected by the SSP module as a baud clock. REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 -111 1111 INTCON GIE/GIEH PEIE/GIEL TMR2 T2CON PR2 Legend: Timer2 Module Register — 0000 0000 0000 0000 TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 Timer2 Period Register 1111 1111 1111 1111 x = unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module. DS39616B-page 144 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 14.0 TIMER5 MODULE Timer5 is a general-purpose timer/counter that incorporates additional features for use with the Motion Feedback module (see Section 16.0 “Motion Feedback Module”). It may also be used as a general-purpose timer or a special event trigger delay timer. When used as a general-purpose timer, it can be configured to generate a delayed special event trigger (e.g., an ADC special event trigger) using a pre-programmed period delay. The Timer5 module implements these features: • • • • • • • • • • 16-bit timer/counter operation Synchronous and asynchronous counter modes Continuous and Single-Shot operating modes Four programmable prescaler values (1:1 to 1:8) Interrupt generated on period match Special event trigger Reset function Double-buffered registers Operation during Sleep CPU wake-up from Sleep Selectable hardware Reset input with a wake-up feature REGISTER 14-1: Timer5 is controlled through the Timer5 Control Register (T5CON), shown in Register 14-1. The timer can be enabled or disabled by setting or clearing the control bit TMR5ON (T5CON<0>). A block diagram of Timer5 is shown in Figure 14-1. T5CON: TIMER5 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T5SEN RESEN T5MOD T5PS1 T5PS0 T5SYNC TMR5CS TMR5ON bit 7 bit 0 bit 7 T5SEN: Timer5 Sleep Enable bit(1) 1 = Timer5 enabled during Sleep 0 = Timer5 disabled during Sleep bit 6 RESEN: Special Event Reset Enable bit 1 = Special Event Reset disabled 0 = Special Event Reset enabled bit 5 T5MOD: Timer5 Mode bit 1 = Single-Shot mode enabled 0 = Continuous Count mode enabled bit 4:3 T5PS1:T5PS0: Timer5 Input Clock Prescale Select bits 11 =1:8 10 =1:4 01 =1:2 00 =1:1 bit 2 T5SYNC: Timer5 External Clock Input Synchronization Select bit When TMR5CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR5CS = 0: This bit is ignored. Timer5 uses the internal clock when TMR5CS = 0 bit 1 TMR5CS: Timer5 Clock Source Select bit 1 = External clock from pin T5CKI 0 = Internal clock (TCY) bit 0 TMR5ON: Timer5 On bit 1 = Timer5 enabled 0 = Timer5 disabled Note 1: For Timer5 to operate during Sleep mode, T5SYNC must be set. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 145 PIC18F2331/2431/4331/4431 FIGURE 14-1: TIMER5 BLOCK DIAGRAM (16-BIT READ/WRITE MODE SHOWN) T5CKI Internal Data Bus 1 Noise Filter 1 FOSC/4 Internal Clock Synchronize Prescaler 1, 2, 4, 8 0 detect 0 2 Sleep Input Timer5 On/Off TMR5CS T5PS1:T5PS0 T5SYNC TMR5ON 8 8 TMR5H 8 Write TMR5L Read TMR5L Special Event Trigger Input from IC1 TMR5 8 1 TMR5L Timer5 Reset Timer5 Reset (external) 0 TMR5 High Byte 16 Reset Logic Comparator 16 PR5 8 PR5L Set TMR5IF Special Event Trigger Output 14.1 Special Event Logic 8 Timer5 Operation Timer5 supports three configurations: Timer5 combines two 8-bit registers to function as a 16bit timer. The TMR5L register is the actual low byte of the timer; it can be read and written to directly. The high byte is contained in an unmapped register; it is read and written to through TMR5H, which serves as a buffer. Each register increments from 00h to FFh. A second register pair, PR5H and PR5L, serves as a period register; it sets the maximum count for the TMR5 register pair. When TMR5 reaches the value of PR5, the timer rolls over to 00h and sets the TMR5IF interrupt flag. A simplified block diagram of the Timer5 module is shown in Figure 2-1. Note: The TIMER5 may be used as a general purpose timer and as the time base resource to the Motion Feedback module (Input Capture or Quadrature Encoder Interface). DS39616B-page 146 PR5H • 16-bit Synchronous Timer • 16-bit Synchronous Counter • 16-bit Asynchronous Counter In Synchronous Timer configuration, the timer is clocked by the internal device clock. The optional Timer5 prescaler divides the input by 2, 4, 8, or not at all (1:1). The TMR5 register pair increments on Q1. Clearing TMR5CS (= 0) selects the internal device clock as the timer sampling clock. In Synchronous Counter configuration, the timer is clocked by the external clock (T5CKI) with the optional prescaler. The external T5CKI is selected by setting the TMR5CS bit (TMR5CS = 1); the internal clock is selected by clearing TMR5CS. The external clock is synchronized to the internal clock by clearing the T5SYNC bit. The input on T5CKI is sampled on every Q2 and Q4 of the internal clock. The low to rise transition is decoded on three adjacent samples and Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 the Timer5 is incremented on the next Q1. The T5CKI minimum pulse width high and low time must be greater than TCY/2. In Asynchronous Counter configuration, Timer5 is clocked by the external clock (T5CKI) with the optional prescaler. In this mode, T5CKI is not synchronized to the internal clock. By setting TMR5CS, the external input clock (T5CKI) can be used as the counter sampling clock. When T5SYNC is set, the external clock is not synchronized to the internal device clock. The timer count is not reset automatically when the module is disabled. The user may write the counter register to initialize the counter. Note: 14.1.1 The Timer5 module does NOT prevent writes to the PR5 registers (PR5H:PR5L) while the timer is enabled. Writing to PR5 while the timer is enabled may result in unexpected period match events. CONTINUOUS AND SINGLE-SHOT OPERATION Timer5 has two operating modes: Continuous-count and Single-shot. Continuous-count mode is selected by clearing the T5MOD control bit (= 0). In this mode, the Timer5 time base will start incrementing according to the prescaler settings until a TMR5/PR5 match occurs, or until TMR5 rolls over (FFFFh to 0000h). The TMR5IF interrupt flag is set, the TMR5 register is reset on the following input clock edge, and the timer continues to count for as long as the TMR5ON bit remains set. Single-shot mode is selected by setting T5MOD (= 1). In this mode, the Timer5 time base begins to increment according to the prescaler settings until a TMR5/PR5 match occurs. This causes the TMR5IF interrupt flag to be set, the TMR5 register pair to be cleared on the following input clock edge, and the TMR5ON bit to be cleared by the hardware to halt the timer. The Timer5 time base can only start incrementing in Single-shot mode under two conditions: 1. 2. Timer5 is enabled (TMR5ON is set), or Timer5 is disabled, and a Special Event Reset trigger is present on the Timer5 reset input. (See Section 14.7 “Timer5 Special Event Reset Input” for additional information). 14.2 16-bit Read/Write and Write Modes As noted, the actual high byte of the Timer5 register pair is mapped to TMR5H, which serves as a buffer. Reading TMR5L will load the contents of the high byte of the register pair into the TMR5H register. This allows the user to accurately read all 16 bits of the register pair, without having to determine whether a read of the high byte followed by the low byte is valid due to a rollover between reads. 2003 Microchip Technology Inc. Since the actual high byte of the Timer5 register pair is not directly readable or writable, it must be read and written to through the Timer5 High Byte Buffer register (TMR5H). The T5 high byte is updated with the contents of TMR5H when a write occurs to TMR5L. This allows a user to write all 16 bits to both the high and low bytes of Timer5 at once. Writes to TMR5H do not clear the Timer5 prescaler. The prescaler is only cleared on writes to TMR5L. 14.2.1 16-BIT READ-MODIFY-WRITE Read-modify-write instructions like BSF and BCF will read the contents of a register, make the appropriate changes, and place the result back into the register. The write portion of a read-modify-write instruction of TMR5H will not update the contents of the high byte of TMR5 until a write of TMR5L takes place. Only then will the contents of TMR5H be placed into the high byte of TMR5. 14.3 Timer5 Prescaler The Timer5 clock input (either TCY or the external clock) may be divided by using the Timer5 programmable prescaler. The prescaler control bits T5PS1:T5PS0 (T5CON<4:3>) select a prescale factor of 2, 4, 8 or no prescale. The Timer5 prescaler is cleared by any of the following: • A write to the Timer5 register • Disabling Timer5 (TMR5ON = 0) • A device Reset such as Master Clear, POR or BOR Note: 14.4 Writing to the T5CON register does not clear the Timer5. Noise Filter The Timer5 module includes an optional input noise filter, designed to reduce spurious signals in noisy operating environments. The filter ensures that the input is not permitted to change until a stable value has been registered for three consecutive sampling clock cycles. The noise filter is part of the input filter network associated with the Motion Feedback Module (see Section 16.0 “Motion Feedback Module”). All of the filters are controlled using the Digital Filter Control (DFLTCON) register (Register 16-3). The Timer5 filter can be individually enabled or disabled by setting or clearing the FLT4EN bit (DFLTCON<7>). It is disabled on all BOR and BOR resets. For additional information, refer to Section 16.3 “Noise Filters” in the Motion Feedback module. Preliminary DS39616B-page 147 PIC18F2331/2431/4331/4431 14.5 14.7.2 Timer5 Interrupt Timer5 has the ability to generate an interrupt on a period match. When the PR5 register is loaded with a new period value (00FFh), the Timer5 time base increments until its value is equal to the value of PR5. When a match occurs, the Timer5 interrupt is generated on the rising edge of Q4; TMR5IF is set on the next TCY. The interrupt latency (i.e., the time elapsed from the moment Timer5 rolls over until TMR5IF is set) will not exceed 1 TCY. When the Timer5 clock input is prescaled and a TMR5/PR5 match occurs, the interrupt will be generated on the first Q4 rising edge after TMR5 resets. 14.6 Timer5 Special Event Trigger Output A Timer5 special event trigger is generated on a TMR5/ PR5 match. The special event trigger is generated on the falling edge of Q3. Timer5 must be configured for either Synchronous mode (counter or timer) to take advantage of the special event trigger feature. If Timer5 is running in Asynchronous Counter mode, the special event trigger may not work and should not be used. 14.7 Timer5 Special Event Reset Input In addition to the special event output, Timer5 has a Special Event Reset input that may be used with Input Capture channel 1 (IC1) of the Motion Feedback module. To use the Special Event Reset, the Capture 1 Control register CAP1CON must be configured for one of the special event trigger modes (CAP1M3:CAP1M0 = 1110 or 1111). The Special Event Reset trigger can be disabled by setting the RESEN control bit (T5CON<6>). The Special Event Reset resets the Timer5 time base. This reset occurs in either Continuous-count or Singleshot modes. 14.7.1 An active edge on CAP1 can also be used to initiate some later action delayed by the Timer5 time base. In this case, Timer5 increments as before after being triggered. When the hardware time-out occurs, the special event trigger output is generated and used to trigger another action, such as an A/D conversion. This allows a given hardware action to be referenced from a capture edge on CAP1 and delayed by the timer. The event timing for the delayed action event trigger is discussed further in Section 16.1 “Input Capture”. 14.7.3 DS39616B-page 148 SPECIAL EVENT RESET WHILE TIMER5 IS INCREMENTING In the event that a bus write to Timer5 coincides with a Special Event Reset trigger, the bus write will always take precedence over Special Event Reset trigger. 14.8 Operation in Sleep Mode When Timer5 is configured for asynchronous operation, it will continue to increment each timer clock (or prescale multiple of clocks). Executing the SLEEP instruction will either stop the timer or let the timer continue, depending on the setting of the Timer5 Sleep Enable bit, T5SE. If T5SE is set (= 1), the timer continues to run when the SLEEP instruction is executed and the external clock is selected (TMR5CS = 1). If T5SE is cleared, the timer stops when a SLEEP instruction is executed, regardless of the state of the GTPCS bit. To summarize, Timer5 will continue to increment when a SLEEP instruction is executed only if all of these bits are set: • • • • TMR5ON T5SE TMR5CS T5SYNC 14.8.1 WAKE-UP ON IC1 EDGE The Timer5 Special Event Reset input can act as a Timer5 wake-up and a start-up pulse. Timer5 must be in Single-shot mode and disabled (TMR5ON = 0). An active edge on the CAP1 input pin will set TMR5ON; the timer is subsequently incremented on the next following clock according to the prescaler and the Timer5 clock settings. A subsequent hardware time-out (such as TMR5/PR5 match) will clear the TMR5ON bit and stop the timer. DELAYED-ACTION EVENT TRIGGER INTERRUPT DETECT IN SLEEP MODE When configured as described above, Timer5 will continue to increment on each rising edge on T5CKI while in Sleep mode. When a TMR5/PR5 match occurs, an interrupt is generated which can wake the part. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 14-1: Name REGISTERS ASSOCIATED WITH TIMER5 Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Value on all other Resets Bit 0 Value on: POR, BOR RBIF 0000 000x 0000 000u INT0IE RBIE TMR0IF INT0IF IPR3 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111 ---1 1111 PIE3 — — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000 ---0 0000 PIR3 — — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000 ---0 0000 INTCON GIE/GIEH PEIE/GIEL TMR0IE Bit 4 TMR5H Timer5 Register High Byte xxxx xxxx uuuu uuuu TMR5L TImer5 Register Low Byte xxxx xxxx uuuu uuuu PR5H Timer5 Period Register High Byte 1111 1111 1111 1111 PR5L Timer5 Period Register Low Byte T5CON T5MOD 1111 1111 1111 1111 T5PS1 T5SEN RESEN CAP1CON — CAP1REN — — DFLTCON — FLT4EN FLT3EN FLT2EN Legend: T5PS0 T5SYNC TMR5CS TMR5ON 0000 0000 0000 0000 CAP1M3 CAP1M2 CAP1M1 CAP1M0 -1-- 0000 -1-0 0000 FLT1EN FLTCK2 FLTCK1 FLTCK0 -000 0000 -000 0000 x = unknown, u = unchanged, – = unimplemented. 2003 Microchip Technology Inc. Preliminary DS39616B-page 149 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 150 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.0 CAPTURE/COMPARE/PWM (CCP) MODULES The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. Table 15-1 shows the timer resources required for each of the CCP module modes. The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger. Therefore, operation of a CCP module is described with respect to CCP1, except where noted. REGISTER 15-1: CCPxCON: CCP MODULE CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0 Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs (bit 1 and bit 0) of the 10-bit PWM duty cycle. The upper eight bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 =Capture/Compare/PWM disabled (resets CCPx module) 0001 =Reserved 0010 =Compare mode, toggle output on match (CCPxIF bit is set) 0011 =Reserved 0100 =Capture mode, every falling edge 0101 =Capture mode, every rising edge 0110 =Capture mode, every 4th rising edge 0111 =Capture mode, every 16th rising edge 1000 =Compare mode, Initialize CCP pin Low, on compare match force CCP pin High (CCPxIF bit is set) 1001 =Compare mode, Initialize CCP pin High, on compare match force CCP pin Low (CCPxIF bit is set) 1010 =Compare mode, Generate software interrupt-on-compare match (CCPxIF bit is set, CCP pin is unaffected) 1011 =Compare mode, Trigger special event (CCP2IF bit is set) 11xx =PWM mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 151 PIC18F2331/2431/4331/4431 15.1 CCP1 Module 15.2 Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 15-1: CCP2 Module Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. CCP MODE – TIMER RESOURCE CCP Mode Timer Resource Capture Compare PWM Timer1 Timer1 Timer2 DS39616B-page 152 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 15.3 15.3.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: 15.3.2 If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition. TIMER1 MODE SELECTION Timer 1 must be running in Timer mode or Synchronized Counter mode to be used with the capture feature. In Asynchronous Counter mode, the capture operation may not work. FIGURE 15-1: When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode. 15.3.4 The event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set; it must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value. 15.3.1 SOFTWARE INTERRUPT CCP PRESCALER There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 15-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. EXAMPLE 15-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW CCP1CON, F NEW_CAPT_PS MOVWF CCP1CON ; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP1CON with this value CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCP1IF Prescaler ÷ 1, 4, 16 CCPR1H CCPR1L TMR1 Enable CCP1 pin and Edge Detect TMR1H TMR1L CCPR2H CCPR2L CCP1CON<3:0> Q’s Set Flag bit CCP2IF Prescaler ÷ 1, 4, 16 TMR1 Enable CCP2 pin and Edge Detect TMR1H TMR1L CCP2CON<3:0> Q’s 2003 Microchip Technology Inc. Preliminary DS39616B-page 153 PIC18F2331/2431/4331/4431 15.4 15.4.2 Compare Mode TIMER1 MODE SELECTION In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/ CCP1 (RC1/CCP2) pin: Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. • • • • 15.4.3 Is driven High Is driven Low Toggles output (High-to-Low or Low-to-High) Remains unchanged (interrupt only) When generate software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled). The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the same time, interrupt flag bit CCP1IF (CCP2IF) is set. 15.4.1 15.4.4 The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The user must configure the CCPx pin as an output by clearing the appropriate TRISC bit. Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. The special trigger output of CCP2 resets the TMR1 register pair. Additionally, the CCP2 special event trigger will start an A/D conversion if the A/D module is enabled. Note: FIGURE 15-2: SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. CCP PIN CONFIGURATION Note: SOFTWARE INTERRUPT MODE The special event trigger from the CCP2 module will not set the Timer1 interrupt flag bit. COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1, but not set Timer1 interrupt flag bit, and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion (CCP2 only) Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q RC2/CCP1 pin S R TRISC<2> Output Enable Output Logic Match Comparator CCP1CON<3:0> Mode Select TMR1H TMR1L Special Event Trigger Set Flag bit CCP2IF Q RC1/CCP2 pin TRISC<1> Output Enable DS39616B-page 154 S R Output Logic Comparator Match CCPR2H CCPR2L CCP2CON<3:0> Mode Select Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 15-2: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 -111 1111 INTCON IPR1 GIE/GIEH PEIE/GIEL TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu CCPR1L Capture/Compare/PWM Register1 (LSB) CCPR1H Capture/Compare/PWM Register1 (MSB) CCP1CON — — DC1B1 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC1B0 CCPR2L Capture/Compare/PWM Register2 (LSB) CCPR2H Capture/Compare/PWM Register2 (MSB) CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu — — DC2B1 DC2B0 CCP2M3 PIR2 OSCFIF CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF 00-0 0000 00-0 0000 PIE2 OSCFIE CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE 00-0 0000 00-0 0000 IPR2 OSCFIP CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP 11-1 1111 11-1 1111 CCP2CON Legend: CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 x = unknown, u = unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. 2003 Microchip Technology Inc. Preliminary DS39616B-page 155 PIC18F2331/2431/4331/4431 15.5 15.5.1 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 15-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 15.5.3 “Setup for PWM Operation”. FIGURE 15-3: SIMPLIFIED PWM BLOCK DIAGRAM The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation. EQUATION 15-1: PWM period = [(PR2) + 1] • 4 • TOSC • (TMR2 prescale value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP1 pin is set (if PWM duty cycle = 0%, the CCP1 pin will not be set) • The PWM duty cycle is copied from CCPR1L into CCPR1H Note: CCP1CON<5:4> Duty Cycle Registers CCPR1L 15.5.2 CCPR1H (Slave) R Comparator Q RC2/CCP1 TMR2 (Note 1) S TRISC<2> Comparator Clear Timer, CCP1 pin and latch D.C. PR2 The Timer2 postscaler (see Section 13.0 “Timer2 Module”) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is calculated by the following equation. EQUATION 15-2: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) • Tosc • (TMR2 prescale value) Note: 8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time base. A PWM output (Figure 15-4) has a time base (period) and a time that the output is high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 15-4: PWM PERIOD CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not copied into CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 DS39616B-page 156 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or two bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. 15.5.3 EQUATION 15-3: 4. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 15-4: INTCON 5. If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. TABLE 15-3: Name Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. 3. log FOSC FPWM PWM Resolution (max) = bits log(2) Note: SETUP FOR PWM OPERATION 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz 16 4 1 1 1 1 FFh FFh FFh 3Fh 1Fh 17h 10 10 10 8 7 6.58 Value on POR, BOR Value on all other Resets REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 7 Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -111 1111 -111 1111 IPR1 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR2 Timer2 Module Register 0000 0000 0000 0000 PR2 Timer2 Module Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCPR1L Capture/Compare/PWM Register1 (LSB) CCPR1H Capture/Compare/PWM Register1 (MSB) CCP1CON — — DC1B1 Capture/Compare/PWM Register2 (LSB) CCPR2H Capture/Compare/PWM Register2 (MSB) Legend: — — DC2B1 xxxx xxxx uuuu uuuu DC1B0 CCPR2L CCP2CON xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. 2003 Microchip Technology Inc. Preliminary DS39616B-page 157 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 158 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.0 MOTION FEEDBACK MODULE The Motion Feedback module is a special-purpose peripheral designed for motion feedback applications. Together with the Power Control PWM module (see Section 17.0 “Power Control PWM Module”), it provides a variety of control solutions for a wide range of electric motors. The module actually consists of two hardware sub-modules: Many of the features for the IC and QEI submodules are fully programmable, creating a flexible peripheral structure that can accommodate a wide range of in-system uses. An overview of the available features is presented in Table 16-1. A simplified block diagram of the entire Motion Feedback module is shown in Figure 16-1. Note: • Input Capture module (IC) • Quadrature Encoder Interface (QEI). Because the same input pins are common to the IC and QEI submodules, only one of these two submodules may be used at any given time. If both modules are on, the QEI submodule will take precedence. Together with Timer5 (see Section 14.0 “Timer5 Module”), these modules provide a number of options for motion and control applications. TABLE 16-1: SUMMARY OF MOTION FEEDBACK MODULE FEATURES Submodule IC (3x) QEI Mode(s) • Synchronous • Input Capture QEI Velocity measurement • • • • • • • • • • • • • • • • 2003 Microchip Technology Inc. Features Timer Flexible input capture modes Available prescaler Selectable time base reset Special event trigger for ADC sampling/conversion or optional TMR5 Reset feature (CAP1 only) Wake-up from Sleep function Selectable interrupt frequency Optional noise filter Detect position Detect direction of rotation Large bandwidth (Fcy/16) Optional noise filter 2x and 4x update modes Velocity event postscaler Counter overflow flag for low rotation speed Utilizes Input Capture 1 logic (IC1) High and low velocity support TMR5 Preliminary Function • 3x Input Capture (edge capture, pulse width, period measurement, capture on change) • Special event triggers the A/D conversion on the CAP1 input 16-bit • Position measurement position • Direction of rotation status counter TMR5 • Precise velocity measurement • Direction of rotation status DS39616B-page 159 PIC18F2331/2431/4331/4431 FIGURE 16-1: MOTION FEEDBACK MODULE BLOCK DIAGRAM Special Reset Trigger TMR5IF TMR5 Reset Control Timer Reset Special Event output Timer5 TMR5<15:0> 8 Filter Data Bus<7:0> TCY T5CKI 3x Input Capture Logic Filter Prescaler Filter Prescaler Filter Prescaler TMR5<15:0> IC3IF IC3 8 CAP3/QEB CAP2/QEA CAP1/INDX TCY IC2IF IC2 IC1 Clock Divider 8 IC1IF Special Reset Trigger 8 8 Postscaler QEB Velocity Event Timer reset QEA 8 Direction Clock Position Counter QEIF QEI Control Logic INDX CHGIF 8 QEI Logic CHGIF IC3DRIF IC3IF QEI Mode Decoder 8 QEIF IC2QEIF IC2IF DS39616B-page 160 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.1 Input Capture The Input Capture (IC) submodule implements the following features: • Three channels of independent input capture (16-bits/channel) on the CAP1, CAP2 and CAP3 pins • Edge-trigger, period or pulse width measurement operating modes for each channel • Programmable prescaler on every input capture channel • Special event trigger output (IC1 only) • Selectable noise filters on each capture input FIGURE 16-2: Input channel (IC1) includes a special event trigger that can be configured for use in Velocity Measurement mode. Its block diagram is shown in Figure 16-2. IC2 and IC3 are similar, but lack the special event trigger features or additional velocity-measurement logic. A representative block diagram is shown in Figure 16-3. Please note that the time base is Timer5. INPUT CAPTURE BLOCK DIAGRAM FOR IC1 CAP1 Pin and Mode Select Prescaler 1, 4, 16 Noise Filter CAP1BUF/VELR(1) Clock 3 FLTCK<2:0> 4 CAP1M<3:0> Q clocks IC1IF IC1_TR 1 MUX 0 velcap (2) Clock/ Reset/ Interrupt Decode Logic Special Event Reset Reset Control Timer5 Logic CAP1BUF_clk First Event Reset VELM Timer Reset Control Timer5 Reset CAP1M<3:0> CAPxREN Q Clocks Reset TMR5 Note 1: 2: CAP1BUF register is reconfigured as VELR register when QEI mode is active. QEI generated velocity pulses, vel_out, are downsampled to produce this velocity capture signal. 2003 Microchip Technology Inc. Preliminary DS39616B-page 161 PIC18F2331/2431/4331/4431 FIGURE 16-3: INPUT CAPTURE BLOCK DIAGRAM FOR IC2 AND IC3 Capture Clock CAPxBUF(1,2,3) CAP2/CAP3 Pin Prescaler 1, 4, 16 Noise Filter and Mode Select 3 FLTCK<2:0> TMR5 Enable Q’s 4 CAPxM<3:0>(1) TMR5 ICxIF(1) Capture Clock/ Reset/ Interrupt Decode Logic CAPxBUF_clk(1) Reset Timer Reset Control TMR5 Reset Q clocks CAPxM<3:0>(1) CAPxREN(2) Note 1: IC2 and IC3 are denoted as x=2 and 3. 2: CAP2BUF is enabled as POSCNT when QEI mode is active. 3: CAP3BUF is enabled as MAXCNT when QEI mode is active. DS39616B-page 162 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 The three Input Capture channels are controlled through the Input Capture Control Registers CAP1CON, CAP2CON, and CAP3CON. Each channel is configured independently with its dedicated register. The implementation of the registers is identical, except for the Special Event trigger (see Section 16.1.8 “Special Event Trigger (CAP1 Only)”). The typical Capture Control register is shown in Register 16-1. REGISTER 16-1: CAPxCON: INPUT CAPTURE CONTROL REGISTER U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CAPxREN — — CAPxM3 CAPxM2 CAPxM1 CAPxM0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CAPxREN: Time Base Reset Enable bit 1 = Enabled 0 = Disable selected time base Reset on capture. bit 5 Unimplemented: Read as ‘0’ bit 4 Unimplemented: Read as ‘0’ bit 3-0 CAPxM3:CAPxM0: Input Capture 1 (ICx) Mode Select bits 1111 = Special Event Trigger mode. The trigger occurs on every rising edge on CAP1 input(1) 1110 = Special Event Trigger mode. The trigger occurs on every falling edge on CAP1 input(1) 1101 = Unused 1100 = Unused 1011 = Unused 1010 = Unused 1001 = Unused 1000 = Capture on every CAPx input state change 0111 = Pulse Width Measurement mode, every rising to falling edge 0110 = Pulse Width Measurement mode, every falling to rising edge 0101 = Frequency Measurement mode, every rising edge 0100 = Capture mode, every 16th rising edge 0011 = Capture mode, every 4th rising edge 0010 = Capture mode, every rising edge 0001 = Capture mode, every falling edge 0000 = Input Capture 1 (ICx) off Note 1: Special Event Trigger is only available on CAP1. For CAP2 and CAP3, this configuration is unused. Legend: Note: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Throughout this section, references to registers and bit names that may be associated with a specific capture channel will be referred to generically by the use of the term ‘x’ in place of the channel number. For example, ‘CAPxREN’ may refer to the Capture Reset Enable bit in CAP1CON, CAP2CON or CAP3CON. 2003 Microchip Technology Inc. x = Bit is unknown When in Counter mode, the counter must be configured as the synchronous counter only (TMR5SYNC = 0). When configured in Asynchronous mode, the IC module will not work properly. Preliminary DS39616B-page 163 PIC18F2331/2431/4331/4431 Note 1: Input capture prescalers are reset (cleared) when the Input Capture module is disabled (CAPxM = 0000). 2: When the Input Capture mode is changed without first disabling the module and entering the new Input Capture mode, a false interrupt (or special event trigger on IC1) may be generated. The user should either (1) disable the Input Capture before entering another mode or (2) disable IC interrupts to avoid false interrupts during IC mode changes. 3: During IC mode changes, the prescaler count will not be cleared, therefore the first capture in the new IC mode may be from the non-zero prescaler. FIGURE 16-4: 16.1.1 EDGE CAPTURE MODE In this mode, the value of the time base is captured either on every rising edge, every falling edge, every 4th rising edge, or every 16th rising edge. The edge present on the input capture pin (CAP1, CAP2 or CAP3) is sampled by the synchronizing latch. The signal is used to load the input capture buffer (ICxBUF register) on the following Q1 clock (see Figure 16-4). Consequently, Timer5 is either reset to ‘0’ (Q1 immediately following the capture event) or left free running, depending on the setting of Capture Reset Enable, CAPxREN, in the CAPxCON register. Note: On the first capture edge following the setting of the Input Capture mode (i.e., MOVWF CAP1CON), Timer5 contents are always captured into the corresponding input capture buffer (i.e., CAPxBUF). Timer5 can optionally be reset; however, this is dependent on the setting of the Capture Reset Enable bit (CAPxREN), see Figure 16-4. EDGE CAPTURE MODE TIMING Q1Q2 Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2 Q3 Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2 Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 OSC TMR5(1) 0012 0013 0014 0015 0000 0001 0002 0000 0001 0002 CAP1 pin(2) CAP1BUF(3) ABCD 0003 0016 Note 5 TMR5 reset(4) Instruction MOVWF CAP1CON Execution Note 1: 0002 BCF CAP1CON, CAP1REN TMR5 is a synchronous time base input to the Input Capture, prescaler = 1:1. It increments on Q1 rising edge. 2: IC1 is configured in Edge Capture mode (CAP1M3:CAP1M0 = 0010) with the time base reset upon edge capture (CAP1REN = 1) and no noise filter. 3: TMR5 value is latched by CAP1BUF on TCY. In the event that a write to TMR5 coincides with an input capture event, the write will always take precedence. All input capture buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated with the incremented value of the time base on the next TCY clock edge when the capture event takes place (see Note 4 when Reset occurs). 4: TMR5 Reset is normally an asynchronous reset signal to TMR5. When used with the input capture, it is active immediately after the time base value is captured. 5: TMR5 Reset pulse is disabled by clearing CAP1REN bit (e.g, BCF CAP1CON, CAP1REN). DS39616B-page 164 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.1.2 PERIOD MEASUREMENT MODE The Period Measurement mode is selected by setting CAPxM3:CAPxM0 = 0101. In this mode, the value of Timer5 is latched into the CAPxBUF register on the rising edge of the input capture trigger and Timer5 is subsequently reset to 0000h (optional by setting CAPxREN = 1) on the next TCY (see capture and reset relationship in Figure 16-4). 16.1.3 PULSE WIDTH MEASUREMENT MODE The Pulse Width Measurement mode can be configured for two different edge sequences, such that the pulse width is based on either the falling to rising edge FIGURE 16-5: of the CAPx input pin (CAPxM3:CAPxM0 = 0110), or on the rising to falling edge (CAPxM3:CAPxM0 = 0111). Timer5 is always reset on the edge when the measurement is first initiated. For example, when the measurement is based on the falling to rising edge, Timer5 is first reset on the falling edge and the timer value is captured on the rising edge thereafter. Upon entry into the Pulse Width Measurement mode, the very first edge detected on the CAPx pin is always captured. The TMR5 value is reset on the first active edge (see Figure 16-5). PULSE WIDTH MEASUREMENT MODE TIMING Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 TMR5(1) 0012 0013 0014 0015 0000 0001 0002 0000 0001 0002 CAP1 pin(2) CAP1BUF(3) 0015 0001 0002 TMR5 reset(4,5) Instruction MOVWF CAP1CON Execution(2) Note 1: TMR5 is a synchronous time base input to the Input Capture, prescaler = 1:1. It increments on every Q1 rising edge. 2: IC1 is configured in Pulse Width Measurement mode (CAP1M3:CAP1M0 = 0111, rising to falling pulse width measurement). No noise filter on CAP1 input is used. MOVWF instruction loads CAP1CON when W = 0111. 3: TMR5 value is latched by CAP1BUF on TCY rising edge. In the event that a write to TMR5 coincides with an input capture event, the write will always take precedence. All input capture buffers, CAP1BUF, CAP2BUF and CAP3BUF, are updated with the incremented value of the time base on the next TCY clock edge when the capture event takes place (see Note 4 when Reset occurs). 4: TMR5 Reset is normally an asynchronous Reset signal to TMR5. When used in Pulse Width Measurement mode, it is always present on the edge that first initiates the pulse width measurement (i.e., when configured in the rising to falling Pulse Width Measurement mode, it is active on each rising edge detected. In the falling to rising Pulse Width Measurement mode, it is active on each falling edge detected. 5: TMR5 Reset pulse is activated on the capture edge. CAP1REN bit has no bearing in this mode. 2003 Microchip Technology Inc. Preliminary DS39616B-page 165 PIC18F2331/2431/4331/4431 16.1.3.1 Pulse Width Measurement Timing 16.1.4 Pulse width measurement accuracy can be only ensured when the pulse width high and low present on CAPx input exceeds one TCY clock cycle. The limitations depend on the mode selected: INPUT CAPTURE ON STATE CHANGE When CAPxM3:CAPxM0 = 1000, the value is captured on every signal change on the CAPx input. If all three capture channels are configured in this mode, the three-input-capture can be used as the Hall-effect sensor state transition detector. The value of Timer5 can be captured, Timer5 reset and the interrupt generated. Any change on CAP1, CAP2 or CAP3 is detected and the associated time base count is captured. • When CAPxM3:CAPxM0 = 0110 (rising-to-falling edge delay), the CAPx input high pulse width (TccH) must exceed TCY + 10 ns. • When CAPxM3:CAPxM0 = 0111 (falling-to-rising edge delay), the CAPx input low pulse width (TccL) must exceed TCY + 10 ns. For position and velocity measurement in this mode, the timer can be optionally reset (see Section 16.1.6 “Timer5 Reset” for Reset options). Note 1: The Period Measurement mode will produce valid results upon sampling of the second rising edge of the input capture. CAPxBUF values latched during the first active edge after initialization are invalid. 2: The Pulse Width Measurement mode will latch the value of the timer upon sampling of the first input signal edge by the input capture. CAP1 CAP2 CAP3 State 6 State 5 State 4 State 3 State 2 INPUT CAPTURE ON STATE CHANGE (HALL-EFFECT SENSOR MODE) State 1 FIGURE 16-6: 1 1 1 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0FFFh Time Base(1) 0000h CAP1BUF(2) CAP2BUF(2) CAP3BUF(2) Time Base Reset(1) Note 1: TMR5 can be selected as the time base for input capture. Time base can be optionally reset when the capture reset enabled bit is set (CAPXREN = 1). 2: Detailed CAPxBUF event timing (all modes reflect same capture and Reset timing) is shown in Figure 16-4.There are six commutation BLDC hall-effect sensor states shown. The other two remaining states (i.e., 000h and 111h) are invalid in the normal operation. They are still to be decoded by the CPU firmware in BLDC motor application. DS39616B-page 166 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.1.5 ENTERING INPUT CAPTURE MODE AND CAPTURE TIMING The following is a summary of functional operation upon entering any of the Input Capture modes: 1. 2. After the module is configured for one of the capture modes by setting the Mode Select bits (CAPxM3:CAPxM0), the first detected edge captures Timer5 value and stores it in the CAPxBUF register. The timer is then reset (depending on the setting of CAPxREN bit) and starts to increment according to its settings, see Figure 16-4, Figure 16-5 and Figure 16-6. On all edges, the capture logic performs the following: a) Input Capture mode is decoded and the active edge is identified b) The CAPxREN bit is checked to determine whether Timer5 is reset or not. c) On every active edge, the Timer5 value is recorded in the input capture buffer (CAPxBUF). d) Reset Timer5 after capturing the value of the timer when CAPxREN bit is enabled. Timer5 is reset on every active capture edge in this case. e) On all continuing capture edge events repeat steps 1 through 4 until the Operational mode is terminated either by user firmware, POR or BOR. f) The timer value is not affected when switching into and out of various input capture modes. 2003 Microchip Technology Inc. 16.1.6 TIMER5 RESET Every Input Capture trigger can optionally reset (TMR5). Capture Reset Enable bit, CAPxREN, gates the automatic Reset of the time base of the capture event with this enable Reset signal. All capture events reset the selected timer when CAPxREN is set. Resets are disabled when CAPxREN is cleared (see Figure 16-4, Figure 16-5 and Figure 16-6). Note: 16.1.7 The CAPxREN bit has no effect in Pulse Width Measurement mode. IC INTERRUPTS There are four operating modes for which the IC module can generate an interrupt and set one of the Interrupt Capture flag bits (IC1IF, IC2QEIF or IC3DRIF). The interrupt flag that is set depends on the channel in which the event occurs. The modes are: • Edge capture (CAPxM3:CAPxM0 = 0001, 0010, 0011 or 0100) • Period measurement event (CAPxM3:CAPxM0 = 0101) • Pulse width measurement event (CAPxM3:CAPxM0 = 0110 or 0111) • State change event (CAPxM3:CAPxM0 = 1000) Note: The special event trigger is generated only in the Special Event Trigger mode on CAP1 input (CAP1M2:CAP1M0> = 1110 and 1111). IC1IF interrupt is not set in this mode. The timing of interrupt and special trigger events is shown in Figure 16-7. Any active edge is detected on the rising edge of Q2 and propagated on the rising edge of Q4 rising edge. If an active edge happens to occur any later than this (on the falling edge of Q2, for example), then it will be recognized on the next Q2 rising edge. Preliminary DS39616B-page 167 PIC18F2331/2431/4331/4431 FIGURE 16-7: CAPXIF INTERRUPTS AND IC1 SPECIAL EVENT TRIGGER Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC CAP1 pin IC1IF TMR5 Reset TMR5 XXXX 0000 0001 TMR5ON(1) Note 1: 16.1.8 Timer5 is only reset and enabled (assuming: TMR5ON = 0 and TMR5MOD = 1) when the Special Event Reset Trigger is enabled for the Timer5 Reset input. TMR5ON bit is asserted and Timer5 is reset on the Q1 rising edge following the event capture. With the Special Event Reset Trigger disabled, Timer5 cannot be reset by the Special Event Reset Trigger on CAP1 input. In order for the Special Event Reset Trigger to work as the Reset trigger to Timer5, IC1 must be configured in the Special Event Trigger mode (CAP1M<3:0> = 1110 or 1111). SPECIAL EVENT TRIGGER (CAP1 ONLY) The Special Event Trigger mode of IC1 (CAP1M3:CAP1M0 = 1110 or 1111) enables the Special Event Trigger signal. The trigger signal can be used as the Special Event Reset input to TMR5, resetting the timer when the specific event happens on IC1. The events are summarized in Table 16-2. TABLE 16-2: SPECIAL EVENT TRIGGER CAP1M3: CAP1M0 1110 1111 16.1.9 Description The trigger occurs on every falling edge on CAP1 input The trigger occurs on every rising edge on CAP1 input 16.1.10 OTHER OPERATING MODES Although the IC and QEI submodules are mutually exclusive, the IC can be reconfigured to work with the QEI module to perform specific functions. In effect, the QEI “borrows” hardware from the IC to perform these operations. For velocity measurement, the QEI uses dedicated hardware in channel IC1. The CAP1BUF registers are remapped, becoming the VREG registers. Its operation and use are described in Section 16.2.6 “Velocity Measurement”. While in QEI mode, the CAP2BUF and CAP3BUF registers of channel IC2 and IC3 are used for position determination. They are remapped as the POSCNT and MAXCNT buffer registers, respectively. OPERATING MODES SUMMARY Table 16-3 shows a summary of the input capture configuration when used in conjunction with TMR5 timer resource. DS39616B-page 168 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 16-3: INPUT CAPTURE TIME BASE RESET SUMMARY Mode Timer Reset Timer on Capture CAP1 0001-0100 Edge Capture TMR5 optional(1) TMR5 TMR5 optional(1) always Simple edge Capture mode (includes a selectable prescaler) Captures Timer5 on period boundaries Captures Timer5 on pulse boundaries TMR5 optional(1) Captures Timer5 on state change TMR5 optional(2) CAP2 0001-0100 Edge Capture TMR5 optional(1) 0101 Period Measurement 0110-0111 Pulse Width Measurement 1000 Input Capture on State Change CAP3 0001-0100 Edge Capture TMR5 TMR5 optional(1) always Used as a special event trigger to be used with the Timer5 or other peripheral modules Simple edge Capture mode (includes a selectable prescaler Captures Timer5 on period boundaries Captures Timer5 on pulse boundaries TMR5 optional(1) Captures Timer5 on state change TMR5 optional(1) Simple edge Capture mode (includes a selectable prescaler Captures Timer5 on period boundaries Captures Timer5 on pulse boundaries Pin CAPxM 0101 Period Measurement 0110-0111 Pulse Width Measurement 1000 Input Capture on State Change 1110-1111 Special Event Trigger (rising or falling edge) Description 0101 Period Measurement TMR5 optional(1) 0110-0111 Pulse Width TMR5 always Measurement 1000 Input Capture on State TMR5 optional(1) Captures Timer5 on state change Change Note 1: Timer5 may be reset on capture events only when CAPxRE = 1. 2: Trigger mode will not reset Timer5 unless RESEN = 0 in the T5CON register. 2003 Microchip Technology Inc. Preliminary DS39616B-page 169 PIC18F2331/2431/4331/4431 Quadrature Encoder Interface The QEI control logic detects the leading edge on the QEA or QEB phase input pins, and generates the count pulse which is sent to the position counter logic. It also samples the index input signal (INDX), and generates the direction of rotation signal (up/down) and the velocity event signals. The Quadrature Encoder Interface (QEI) decodes speed and motion sensor information. It can be used in any application that uses a quadrature encoder for feedback. The interface implements these features: • Three QEI inputs: two phase signals (QEA and QEB) and one index signal (INDX) • Direction of movement detection with a direction change interrupt (IC3DRIF) • 16-bit up/down position counter • Standard and high-precision position tracking modes • Two position update modes (x2 and x4) • Velocity measurement with a programmable postscaler for high-speed velocity measurement • Position counter interrupt (IC2QEIF in the PIR3 register) • Velocity control interrupt (IC1IF in the PIR3 register) The position counter acts as an integrator for tracking distance traveled. The QEA and QEB input edges serve as the stimulus to create the input clock which advances the Position Counter Register (POSCNT). The register is incremented on either the QEA input edge, or the QEA and QEB input edges, depending on the operating mode. It is reset either by a rollover on match to the Period Register, MAXCNT, or on the external index pulse input signal (INDX). An interrupt is generated on a reset of POSCNT if the position counter interrupt is enabled. The velocity postscaler down-samples the velocity pulses used to increment the velocity counter by a specified ratio. It essentially divides down the number of velocity pulses to one output per so many input, preserving the pulse width in the process. The QEI sub-module has three main components: the QEI control logic block, the position counter and velocity postscaler. FIGURE 16-8: A simplified block-diagram of the QEI module is shown in Figure 16-8. QEI BLOCK DIAGRAM Data Bus 16.2 QEI Module Direction change Set CHGIF Reset Timer5 Timer reset Velocity Event Velocity Capture Postscaler 8 Set UP/DOWN Filter QEB QEA Direction Clock 8 POSCNT/CAP2BUF Reset on match INDX CAP3/QEB Comparator Filter Set IC2QEIF CAP2/QEA Filter QEI Control Logic MAXCNT/CAP3BUF 8 Position Counter CAP1/INDX 8 8 DS39616B-page 170 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.2.1 QEI CONFIGURATION The QEI module shares its input pins with the Input Capture module. The inputs are mutually exclusive; only the IC module or the QEI module (but not both) can be enabled at one time. Also, because the IC and QEI are multiplexed to the same input pins, the programmable noise filters can be dedicated to one module only. REGISTER 16-2: The operation of the QEI is controlled by the QEICON configuration register. See Register 16-2. Note: In the event that both QEI and IC are enabled, QEI will take precedence and IC will remain disabled. QEICON: QUADRATURE ENCODER INTERFACE CONTROL REGISTER R/W-0 VELM bit 7 R/W-0 ERROR R-0 UP/DOWN R/W-0 QEIM2 R/W-0 QEIM1 R/W-0 QEIM0 R/W-0 PDEC1 bit 7 VELM: Velocity Mode bit 1 = Velocity mode disabled 0 = Velocity mode enabled bit 6 ERROR: QEI error bit(1) 1 = Position counter(4) overflow or underflow 0 = No overflow or underflow bit 5 UP/DOWN: Direction of Rotation Status bit(1) 1 = Forward 0 = Reverse bit 4-2 QEIM2:QEIM0: QEI Mode bits(2,3) 111 =Unused 110 =QEI enabled in 4x Update mode; position counter reset on period match (POSCNT = MAXCNT) 101 =QEI enabled in 4x Update mode; INDX resets the position counter 100 =Unused 010 =QEI enabled in 2x Update mode; position counter reset on period match (POSCNT = MAXCNT) 001 =QEI enabled in 2x Update mode; INDX resets the position counter 000 =QEI off bit 1-0 PDEC1:PDEC0: Velocity Pulse Reduction Ratio bit 11 =1:64 10 =1:16 01 =1:4 00 =1:1 R/W-0 PDEC0 bit 0 Note 1: QEI must be enabled and in Index mode. 2: QEI mode select must be cleared (= 000) to enable CAP1, CAP2 or CAP3 inputs. If QEI and IC modules are both enabled, QEI will take precedence. 3: Enabling one of the QEI operating modes remaps the IC buffer registers CAP1BUFH, CAP1BUFL, CAP2BUFH, CAP2BUFL, CAP3BUFH and CAP3BUFL as the VREGH, VREGL, POSCNTH, POSCNTL, MAXCNTH, and MAXCNTL registers (respectively) for the QEI. 4: ERROR bit must be cleared in software. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared 2003 Microchip Technology Inc. Preliminary x = bit is unknown DS39616B-page 171 PIC18F2331/2431/4331/4431 16.2.2 QEI MODES 16.2.3 Position measurement resolution depends on how often the Position Counter register, POSCNT, is incremented. There are two QEI update modes to measure the rotor’s position: QEI x2 and QEI x4. TABLE 16-4: QEIM2: QEIM0 QEI MODES Mode/ Reset Description QEI disabled(1) Two clocks per QEA pulse. INDX resets POSCNT. 010 Two clocks per QEA pulse. POSCNT reset by the period match (MAXCNT). 011 unused 100 unused 101 Four clocks per QEA and QEB pulse pair. INDX resets POSCNT. 110 x4 update/ Four clocks per QEA and period QEB pulse pair. match POSCNT reset by the period match (MAXCNT). 111 — unused Note 1: QEI module is disabled. The position counter and the velocity measurement functions are fully disabled in this mode. 000 001 16.2.2.1 — x2 update/ index pulse x2 update/ period match — — x4 update/ index QEI x2 Update Mode QEI x2 Update mode is selected by setting the QEI Mode Select bits (QEIM2:QEIM0) to ‘001’ or ‘010’. In this mode, the QEI logic detects every edge on the QEA input only. Every rising and falling edge on the QEA signal clocks the position counter. The position counter can be reset by either an input on the INDX pin (QEIM2:QEIM0 = 001), or by a period-match, even when the POSCNT register pair equals MAXCNT (QEIM2:QEIM0 = 010). 16.2.2.2 The Position Counter register pair (POSCNTH: POSCNTL) acts as an integrator, whose value is proportional to the position of the sensor rotor that corresponds to the number of active edges detected. POSCNT can either increment or decrement, depending on a number of selectable factors which are decoded by the QEI logic block. These include the Count mode selected, the phase relationship of QEA to QEB (“lead/lag”), the direction of rotation, and if a reset event occurs. The logic is detailed in the sections that follow. 16.2.3.1 Like QEI x2 mode, the position counter can be reset by an input on the pin (QEIM2:QEIM0 = 101), or by the period-match event (QEIM2:QEIM0 = 010). DS39616B-page 172 Edge and Phase Detect In the first step, the active edges of QEA and QEB are detected, and the phase relationship between them is determined. The position counter is changed based on the selected QEI mode. In QEI x2 Update mode, the position counter increments or decrements on every QEA edge based on the phase relationship of the QEA and QEB signals. In QEI x4 Update mode, the position counter increments or decrements on every QEA and QEB edge based on the phase relationship of the QEA and QEB signals. For example, if QEA leads QEB, the position counter is incremented by 1. If QEB lags QEA, the position counter is decremented by 1. 16.2.3.2 Direction of Count The QEI control logic generates a signal that sets the UP/DOWN bit (QEICON<5>); this in turn determines the direction of the count. When QEA leads QEB, UP/DOWN is set (= 1), and the position counter increments on every active edge. When QEA lags QEB, UP/DOWN is cleared, and the position counter decrements on every active edge. TABLE 16-5: Current Signal Detected QEI 4x Update Mode QEI x4 Update mode provides for a finer resolution of the rotor position, since the counter increments or decrements more frequently for each QEA/QEB input pulse pair than in QEI x2 mode. This mode is selected by setting the QEI Mode Select bits to 101 or 110. In QEI x4, the phase measurement is made on the rising and the falling edges of both QEA and QEB inputs. The position counter is clocked on every QEA and QEB edge. QEI OPERATION DIRECTION OF ROTATION Previous Signal Detected Rising Falling Pos. Cntrl.(1) QEA QEB QEA QEB QEA rising x x QEA falling x x QEB rising x x x QEB falling x Note 1: Preliminary INC DEC DEC INC INC DEC INC DEC When UP/DOWN = 1, the position counter is incremented; when UP/DOWN = 0, the position counter is decremented. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 16.2.4 16.2.3.3 The position counter interrupt occurs, and the interrupt flag (IC2QEIF) is set, based on the following events: Reset and Update Events The position counter will continue to increment or decrement until one of the following events takes place. The type of event and the direction of rotation when it happens determines if a register reset or update occurs. 1. An index pulse is detected on the INDX input (QEIM2:QEIM0 = 001). If the encoder is traveling in the forward direction, POSCNT is reset (00h) on the next clock edge after the index marker, INDX, has been detected. The position counter resets on the QEA or QEB edge once the INDX rising edge has been detected. If the encoder is traveling in the reverse direction, the value in the MAXCNT register is loaded into POSCNT on the next quadrature pulse edge (QEA or QEB) after the falling edge on INDX has been detected. 2. A POSTCNT/MAXCNT period match occurs (QEIM2:QEIM0 = 010). If the encoder is traveling in the forward direction, POSCNT is reset (00h) on the next clock edge when POSCNT = MAXCNT. An interrupt event is triggered on the next TCY after the reset (see Figure 16-10) If the encoder is traveling in the reverse direction and the value of POSCNT reaches 00h, POSCNT is loaded with the contents of MAXCNT register on the next clock edge. An interrupt event is triggered on the next TCY after the load operation (see Figure 16-10). The value of the position counter is not affected during QEI mode changes, nor when the QEI is disabled altogether. 2003 Microchip Technology Inc. QEI INTERRUPTS • A POSCNT/MAXCNT period match event (QEIM2:QEIM0 = 010 or 110) • A POSCNT rollover (FFFFh to 0000h) in Period mode only (QEIM2:QEIM0 = 010 or 110) • An index pulse detected on INDX. The interrupt timing diagrams for IC2QEIF are shown in Figure 16-10 and Figure 16-11. When the direction has changed, the direction change Interrupt flag (IC3DRIF) is set on the following TCY clock (see Figure 16-10). If the position counter rolls over in Index mode, the ERROR bit will be set. 16.2.5 QEI SAMPLE TIMING The quadrature input signals, QEA and QEB, may vary in quadrature frequency. The minimum quadrature input period TQEI is 16TCY. The position count rate, FPOS, is directly proportional to the rotor’s RPM, line count D and QEI Update mode (x2 vs. x4); that is, 4D ⋅ RPM F POS = -----------------------60 Note: The number of incremental lines in the position encoder is typically set at D = 1024 and the QEI Update mode = x4. The maximum position count rate (i.e., 4x QEI Update mode, D = 1024) with F CY = 10 MIPS is equal to 2.5 MHz, which corresponds to FQEI of 625 kHz. Figure 16-9 shows QEA and QEB quadrature inputs timing when sampled by the noise filter. Preliminary DS39616B-page 173 PIC18F2331/2431/4331/4431 FIGURE 16-9: QEI INPUTS WHEN SAMPLED BY THE FILTER (DIVIDE RATIO = 1:1) TCY QEA pin TQEI = 16TCY(1) QEB pin QEA input TGD = 3TCY QEB input Note 1: The module design allows a quadrature frequency of up to FQEI = FCY/16. FIGURE 16-10: QEI MODULE RESET TIMING ON PERIOD MATCH Forward Reverse QEA QEB count (+/-) +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 MAXCNT 1516 1515 1514 1517 1519 1518 1521 1520 1523 1522 1525 1524 0000 1527 1526 0001 0003 0002 0003 0004 0001 0002 0000 1524 1525 1526 1527 1520 1521 1522 1523 POSCNT(1) MAXCNT=1527 Note 6 IC2QEIF Note 2 Note 2 UP/DOWN Q4(3) Q4(3) position counter load Q1(5) Q1(4) IC3DRIF Q1(5) Note 1: POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge of QEA and QEB input signals). Asynchronous external QEA and QEB input are synchronized to TCY clock by the input sampling FF in the noise filter (see Figure 16-14). 2: When POSCNT = MAXCNT, POSCNT is reset to ‘0’ on the next QEA rising edge. POSCNT is set to MAXCNT when POSCNT = 0 (when decrementing), which occurs on the next QEA falling edge. 3: IC2QEI is generated on Q4 rising edge. 4: Position counter is loaded with ‘0’ (which is a rollover event in this case) on POSCNT = MAXCNT. 5: Position counter is loaded with MAXCNT value (1527h) on underflow. 6: IC2QEIF must be cleared in software. DS39616B-page 174 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 16-11: QEI MODULE RESET TIMING WITH THE INDEX INPUT Forward Reverse Note 2 Note 2 QEA QEB count (+/-) +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 MAXCNT 1516 1515 1514 1517 1519 1518 1521 1520 1523 1522 1525 1524 0000 1527 1526 0001 0003 0002 0003 0004 0001 0002 0000 1524 1525 1526 1527 1520 1521 1522 1523 POSCNT(1) MAXCNT=1527 INDX Note 6 IC2QEIF UP/DOWN Q4(3) Q4(3) Position counter load Q1(5) Q1(4) Note 1: POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge of QEA and QEB input signals) 2: When INDX Reset pulse is detected, POSCNT is reset to ‘0’ on the next QEA or QEB edge. POSCNT is set to MAXCNT when POSCNT = 0 (when decrementing), which occurs on the next QEA or QEB edge. Similar Reset sequence occurs for the reverse direction except that the INDX signal is recognized on its falling edge. The Reset is generated on the next QEA or QEB edge. 16.2.6 3: IC2QEI is enabled for one TCY clock cycle. 4: Position counter is loaded with ‘0000h’ (i.e., Reset) on the next QEA or QEB edge when INDX is high. 5: Position counter is loaded with MAXCNT value (e.g., 1527h) on the next QEA or QEB edge following the INDX falling edge input signal detect). 6: IC2QEIF must be cleared in software. TABLE 16-6: VELOCITY MEASUREMENT The velocity pulse generator, in conjunction with the IC1 and the synchronous TMR5 (in synchronous operation), provides a method for high accuracy speed measurements at both low and high mechanical motor speeds. The Velocity mode is enabled when the VELM bit is cleared (= 0) and QEI is set to one of its operating modes (see Table 16-6). VELOCITY PULSES QEIM<2:0> Velocity Event Mode 001 010 x2 Velocity Event mode. The velocity pulse is generated on every QEA edge. x4 Velocity Event mode. The velocity pulse is generated on every QEA and QEB active edge. 101 110 To optimize register space, the input capture channel one (IC1) is used to capture TMR5 counter values. Input capture buffer register, CAP1BUF, is redefined in Velocity Measurement mode, VELM = 0, as the Velocity Register buffer (VREGH, VREGL). 2003 Microchip Technology Inc. Preliminary DS39616B-page 175 PIC18F2331/2431/4331/4431 16.2.6.1 Velocity Event Timing Each velocity pulse serves as a capture pulse. With the TMR5 in Synchronous Timer mode, the value of TMR5 is captured on every output pulse of the postscaler. The counter is subsequently reset to ‘0’. TMR5 is reset upon a capture event. The event pulses are reduced by a fixed ratio by the velocity pulse divider. The divider is useful for high-speed measurements where the velocity events happen frequently. By producing a single output pulse for a given number of input event pulses, the counter can track larger pulse counts (i.e., distance travelled) for a given time interval. Time is measured by utilizing the TMR5 time base. FIGURE 16-12: Figure 16-13 shows the velocity measurement timing diagram. VELOCITY MEASUREMENT BLOCK DIAGRAM Reset Logic QEI Control Logic TMR5 Reset Clock TMR5 TCY 16 CAP3/QEB Noise Filters Velocity Mode Velocity Event IC1 (VELR Register) QEB QEA CAP2/QEA Velocity Capture Postscaler Direction INDX Clock Position Counter CAP1/INDX DS39616B-page 176 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 16-13: VELOCITY MEASUREMENT TIMING(1) Forward Reverse QEA QEB vel_out velcap VELR(2) Old Value 0002 0003 0004 0001 0009 0000 0007 0008 0006 0005 0003 0004 0001 0002 1536 0000 1531 1532 1533 1534 1535 1530 1528 1529 1525 1526 1527 1520 1521 1522 1523 1524 TMR5(2) 1537 1529 cnt_reset(3) Q1 Q1 Q1 IC1IF(4) CAP1REN Instr. Execution BCF TMR5CON, VELM BCF PIE2, IC1IE MOVWF QEICON(5) BSF PIE2, IC1IE Note 1: Timing shown is for QEIM<2:0> = 101, 110 or 111 (x4 Update mode enabled) and the velocity postscaler divide ratio is set to divide by 4 (PDEC<1:0> = 01). 2: VELR register latches the TMR5 count on the “velcap” capture pulse. Timer5 must be set to the synchronous timer or Counter mode. In this example, it is set to the Synchronous Timer mode where the TMR5 prescaler divide ratio = 1 (i.e., Timer5 clock = TCY). 3: The TMR5 counter is reset on the next Q1 clock cycle following the “velcap” pulse. TMR5 value is unaffected when the Velocity Measurement mode is first enabled (VELM = 0). The velocity postscaler values must be reconfigured to their previous settings when re-entering Velocity Measurement mode. While making speed measurements of very slow rotational speeds (e.g., servo-controller applications), the Velocity Measurement mode may not provide sufficient precision. The Pulse Width Measurement mode may have to be used to provide the additional precision. In this case, the input pulse is measured on the CAP1 input pin. 4: IC1IF interrupt is enabled by setting IC1IE as follows, BSF PIE2, IC1IE. Assume IC1E bit is placed in PIE2 Peripheral Interrupt Enable register in the target device. The actual IC1IF bit is written on Q2 rising edge. 5: Post decimation value is changed from PDEC = 01 (decimate by 4) to PDEC = 00 (decimate by 1). 16.2.6.2 16.2.6.3 Velocity Postscaler The velocity event pulse (velcap, see Figure 16-12) serves as the TMR5 capture trigger to IC1 while in the Velocity mode. The number of velocity events are reduced by the velocity postscaler before they are used as the input capture clock. The velocity event reduction ratio can be set with the PDEC1:PDEC0 control bits (QEICON<1:0>) to 1:4, 1:16, 1:64 or no reduction (1:1). CAP1REN in Velocity Mode The TMR5 value can be reset (TMR5 register pair = 0000h) on a velocity event capture by setting the CAP1REN bit (CAP1CON<6>). When CAP1REN is cleared, the TMR5 time base will not be reset on any velocity event capture pulse. The VELR register pair, however, will continue to be updated with the current TMR5 value. The velocity postscaler settings are automatically reloaded from their previous values as the Velocity mode is re-enabled. 2003 Microchip Technology Inc. Preliminary DS39616B-page 177 PIC18F2331/2431/4331/4431 16.3 Noise Filters The Motion Feedback module includes three noise rejection filters on CAP1/INDX, CAP2/QEA and CAP3/QEB. The filter block also includes a fourth filter for the T5CKI pin. They are intended to help reduce spurious noise spikes which may cause the input signals to become corrupted at the inputs. The filter ensures that the input signals are not permitted to change until a stable value has been registered for three consecutive sampling clock cycles. The filters are controlled using the Digital Filter Control (DFLTCON) register (see Register 16-3). The filters can be individually enabled or disabled by setting or clearing the corresponding FLTxEN bit in the DFLTCON register. The sampling frequency, which must be the same for all three noise filters, can be REGISTER 16-3: programmed by the FLTCK2:FLTCK0 configuration bits. TCY is used as the clock reference to the clock divider block. The noise filters can either be added or removed from the input capture or QEI signal path by setting or clearing the appropriate FLTxEN bit, respectively. Each capture channel provides for individual enable control of the filter output. The FLT4EN bit enables or disabled the noise filter available on TMR5CKI input in the Timer5 module. The filter network for all channels is disabled on POR and BOR resets , as the DFLTCON register is cleared on resets. The operation of the filter is shown in the timing diagram in Figure 16-14. DFLTCON: DIGITAL FILTER CONTROL REGISTER U-0 — bit 7 R/W-0 FLT4EN R/W-0 FLT3EN R/W-0 FLT2EN R/W-0 FLT1EN bit 7 Unimplemented: Read as ‘0’ bit 6 FLT4EN: Noise Filter Output Enable bit, T5CKI input 1 = Enabled 0 = Disabled bit 5 FLT3EN: Noise Filter Output Enable bit, CAP3/QEB input(1) 1 = Enabled 0 = Disabled bit 4 FLT2EN: Noise Filter Output Enable bit, CAP2/QEA input(1) 1 = Enabled 0 = Disabled bit 3 FLT1EN: Noise Filter Output Enable bit, CAP1/INDX input(1) 1 = Enabled 0 = Disabled bit 2-0 FLTCK<2:0>: Noise Filter Clock Divider Ratio bits 111 =Unused 110 =1:128 101 =1:64 100 =1:32 011 =1:16 010 =1:4 001 =1:2 000 =1:1 R/W-0 FLTCK2 R/W-0 FLTCK1 R/W-0 FLTCK0 bit 0 Note 1: Noise Filter Output Enables are functional in both QEI and IC operating modes Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared Note: DS39616B-page 178 x = bit is unknown The Noise Filter is intended for random high-frequency filtering and not continuous high-frequency filtering. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 16-14: FILTER TIMING DIAGRAM (CLOCK DIVIDER = 1:1) TQEI = 16TCY TCY Noise glitch(3) Noise glitch(3) CAP1/INDX pin(1) (input to filter) TGD = 3TCY CAP1/INDX input(2) (output from filter) Note 1: 16.4 Only CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on CAP2/QEA and CAP3/QEB pins. 2: Noise filtering occurs in shaded portions of CAP1 input. 3: Filter’s group delay: TGD = 3 TCY. IC and QEI Shared Interrupts 16.5 The IC and QEI sub-modules can each generate three distinct interrupt signals; however, they share the use of the same three interrupt flags in register PIR3. The meaning of a particular interrupt flag at any given time depends on which module is active at the time the interrupt is set. The meaning of the flags in context are summarized in Table 16-7. When the IC submodule is active, the three flags (IC1IF, IC2QEIF and IC3DRIF) function as interrupt-on-capture event flags for their respective input capture channels. The channel must be configured for one of the events that will generate an interrupt (see Section 16.1.7 “IC Interrupts” for more information). When the QEI is enabled, the IC1IF interrupt flag indicates an interrupt caused by a velocity measurement event, usually an update of the VELR register. The IC2QEIF interrupt indicates that a position measurement event has occurred. IC3DRIF indicates that a direction change has been detected. TABLE 16-7: Interrupt Flag IC1IF IC2QEIF IC3DRIF 16.5.1 Operation in Sleep Mode 3X INPUT CAPTURE IN SLEEP MODE Since the input capture can operate only when its time base is configured in a Synchronous mode, the input capture will not capture any events. This is because the device’s internal clock has been stopped, and any internal timers in synchronous modes will not increment. The prescaler will continue to count the events (not synchronized). When the specified capture event occurs, the CAPxIF interrupt will be set. The Capture Buffer register will be updated upon wake-up from sleep to the current TMR5 value. If the CAPxIF interrupt is enabled, the device will wake-up from sleep. This effectively enables all input capture channels to be used as the external interrupts. 16.5.2 QEI IN SLEEP MODE All QEI functions are halted in Sleep mode. MEANING OF IC AND QEI INTERRUPT FLAGS Meaning IC Mode QEI Mode IC1 capture event IC2 capture event IC3 capture event Velocity register update Position measurement update Direction change 2003 Microchip Technology Inc. Preliminary DS39616B-page 179 PIC18F2331/2431/4331/4431 TABLE 16-8: Name INTCON REGISTERS ASSOCIATED WITH THE MOTION FEEDBACK MODULE Bit 7 GIE/GIEH Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u IPR3 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP ---1 1111 ---1 1111 PIE3 — — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000 ---0 0000 PIR3 — — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000 ---0 0000 TMR5H Timer5 Register High Byte (Buffer) xxxx xxxx uuuu uuuu TMR5L Timer5 Register Low Byte xxxx xxxx uuuu uuuu PR5H Timer5 Period Register High Byte 1111 1111 1111 1111 PR5L Timer5 Period Register Low Byte 1111 1111 1111 1111 T5CON T5SEN RESEN T5MOD T5PS1 T5PS0 T5SYNC TMR5CS TMR5ON 0000 0000 0000 0000 CAP1BUFH/ VELRH Capture 1 Register, High Byte / Velocity Register, High Byte(1) xxxx xxxx uuuu uuuu CAP1BUFL/ VELRL Capture 1 Register Low Byte / Velocity Register, Low Byte(1) xxxx xxxx uuuu uuuu CAP2BUFH/ POSCNTH Capture 2 Register, High Byte / QEI Position Counter Register, High Byte(1) xxxx xxxx uuuu uuuu CAP2BUFL/ POSCNTL Capture 2 Register, Low Byte / QEI Position Counter Register, Low Byte(1) xxxx xxxx uuuu uuuu CAP3BUFH/ MAXCNTH Capture 3 Register, High Byte / QEI Max. Count Limit Register, High Byte(1) xxxx xxxx uuuu uuuu CAP3BUFL/ MAXCNTL Capture 3 Register, Low Byte / QEI Max. Count Limit Register, Low Byte(1) xxxx xxxx uuuu uuuu CAP1CON — CAP1REN — — CAP1M3 CAP1M2 CAP1M1 CAP1M0 -0-- 0000 -0-- 0000 CAP2CON — CAP2REN — — CAP2M3 CAP2M2 CAP2M1 CAP2M0 -0-- 0000 -0-- 0000 CAP3CON — CAP3REN — — CAP3M3 CAP3M2 CAP3M1 CAP3M0 -0-- 0000 -0-- 0000 DFLTCON — FLT4EN FLT3EN FLT2EN FLT1EN FLTCK2 FLTCK1 FLTCK0 -000 0000 -000 0000 VELM ERROR UP/DOWN QEIM2 QEIM1 QEIM0 PDEC1 PDEC0 0000 0000 0000 0000 QEICON Legend: Note 1: x = unknown, u = unchanged, – = unimplemented, q = value depends on condition. Shaded cells are not used by the Motion Feedback module. Register name and function determined by which submodule is selected (IC/QEI, respectively). See Section 16.1.10 “Other Operating Modes” for more information. DS39616B-page 180 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.0 POWER CONTROL PWM MODULE The PWM module has the following features: The Power Control PWM module simplifies the task of generating multiple, synchronized pulse width modulated (PWM) outputs for use in the control of motor controllers and power conversion applications. In particular, the following power and motion control applications are supported by the PWM module: • Three-phase and Single-phase AC Induction Motors • Switched Reluctance Motors • Brushless DC (BLDC) Motors • Uninterruptible Power Supplies (UPS) • Multiple DC Brush Motors • Up to eight PWM I/O pins with four duty cycle generators. Pins can be paired to get a complete half-bridge control. • Up to 14-bit resolution, depending upon the PWM period. • “On-the-fly” PWM frequency changes. • Edge- and Center-aligned Output modes. • Single-pulse Generation mode. • Programmable dead time control between paired PWMs. • Interrupt support for asymmetrical updates in Center-aligned mode. • Output override for Electrically Commutated Motor (ECM) operation; for example, BLDC. • Special Event comparator for scheduling other peripheral events. • PWM outputs disable feature sets PWM outputs to their inactive state when in Debug mode. The Power Control PWM module supports three PWM generators and six output channels on PIC18F2X31 devices, and four generators and eight channels on PIC18F4X31 devices. A simplified block diagram of the module is shown in Figure 17-1. Figure 17-2 and Figure 17-3 show how the module hardware is configured for each PWM output pair for the complementary and independent output modes. Each functional unit of the PWM module will be discussed in subsequent sections. 2003 Microchip Technology Inc. Preliminary DS39616B-page 181 PIC18F2331/2431/4331/4431 FIGURE 17-1: POWER CONTROL PWM MODULE BLOCK DIAGRAM Internal Data Bus 8 PWMCON0 PWM Enable and Mode 8 PWMCON1 8 DTCON Dead Time Control FLTCON Fault Pin Control 8 8 OVDCON<D/S> PWM Manual Control PWM Generator #3(1) 8 PDC3 Buffer PDC3 Comparator 8 PWM Generator #2 PTMR Channel 3 Dead Time Generator and Override Logic(2) PWM7(2) Channel 2 Dead Time Generator and Override Logic PWM5 Comparator PWM Generator #1 Channel 1 Dead Time Generator and Override Logic PTPER PWM Generator #0 8 PWM6(2) Output Driver Block Channel 0 Dead Time Generator and Override Logic PTPER Buffer PWM4 PWM3 PWM2 PWM1 PWM0 8 FLTA PTCON FLTB(2) Comparator SEVTDIR 8 SEVTCMP Special Event Postscaler Special Event Trigger PTDIR Note 1: Only PWM Generator #3 is shown in detail. The other generators are identical; their details are omitted for clarity. 2: PWM Generator #3 and its logic, PWM channels 6 and 7, and FLTB and its associated logic are not implemented on PIC18F2X31 devices. DS39616B-page 182 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 17-2: PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY MODE VDD Dead-Band Generator PWM1 Duty Cycle Comparator HPOL PWM Duty Cycle Register PWM0 LPOL Fault Override Values Channel Override Values Fault A pin Fault B pin FIGURE 17-3: Fault Pin Assignment Logic Note: In the Complementary mode, the even channel cannot be forced active by a fault or override event when the odd channel is active. The even channel is always the complement of the odd channel and is inactive, with dead time inserted, before the odd channel is driven to its active state. PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, INDEPENDENT MODE VDD PWM Duty Cycle Register PWM1 Duty Cycle Comparator VDD HPOL PWM0 LPOL Fault Override Values Channel Override Values Fault A pin Fault Pin Assignment Logic Fault B pin This module contains four duty-cycle generators, numbered 0 through 3. The module has eight PWM output pins, numbered 0 through 7. The eight PWM outputs are grouped into output pairs of even and odd numbered outputs. In complimentary modes, the even PWM pins must always be the complement of the corresponding odd PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the complement of PWM3, and so on. The dead time 2003 Microchip Technology Inc. generator inserts an “off” period called “dead time” between the going off of one pin to the going on of the complementary pin of the paired pins. This is to prevent damage to the power switching devices that will be connected to the PWM output pins. The time base for the PWM module is provided by its own 12-bit timer, which also incorporates selectable prescaler and postscaler options. Preliminary DS39616B-page 183 PIC18F2331/2431/4331/4431 17.1 Control Registers 17.2 The operation of the PWM module is controlled by a total of 22 registers. Eight of these are used to configure the features of the module: • • • • • • • • PWM Timer Control register 0 (PTCON0) PWM Timer Control register 1 (PTCON1) PWM Control register 0 (PWMCON0) PWM Control register 1 (PWMCON1) Dead Time Control register (DTCON) Output Override Control register (OVDCOND) Output State register (OVDCONS) Fault Configuration register (FLTCONFIG) The PWM module supports several modes of operation that are beneficial for specific power and motor control applications. Each mode of operation is described in subsequent sections. The PWM module is composed of several functional blocks. The operation of each is explained separately in relation to the several modes of operation: There are also 14 registers that are configured as seven register pairs of 16 bits. These are used for the configuration values of specific features. They are: • PWM Time Base Registers (PTMRH and PTMRL) • PWM Period Registers (PTPERH and PTPERL) • PWM Special Event Compare Registers (SEVTCMPH and SEVTCMPL) • PWM Duty Cycle #0 Registers (PDC0H and PDC0L) • PWM Duty Cycle #1 Registers (PDC1H and PDC1L) • PWM Duty Cycle #2 Registers (PDC2H and PDC2L) • PWM Duty Cycle #3 registers (PDC3H and PDC3L) • • • • • • • • PWM Time Base PWM Time Base Interrupts PWM Period PWM Duty Cycle Dead Time Generators PWM Output Overrides PWM Fault Inputs PWM Special Event Trigger 17.3 PWM Time Base The PWM time base is provided by a 12-bit timer with prescaler and postscaler functions. A simplified block diagram of the PWM time base is shown in Figure 17-4. The PWM time base is configured through the PTCON0 and PTCON1 registers. The time base is enabled or disabled by respectively setting or clearing the PTEN bit in the PTCON1 register. Note: All of these register pairs are double-buffered. DS39616B-page 184 Module Functionality Preliminary The PTMR register pair (PTMRL:PTMRH) is not cleared when the PTEN bit is cleared in software. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 17-4: PWM TIME BASE BLOCK DIAGRAM PTMR Clock PTMR Register Timer RESET Up/Down Comparator Zero match Period match Comparator Timer Direction Control PTDIR Duty Cycle Load PTMOD1 PTPER Period load PTPER Buffer Update disable (UDIS) FOSC/4 Prescaler 1:1, 1:4, 1:16, 1:64 Zero match Zero match Period match PTMOD1 PTMOD0 Clock Control PTMR clock PTEN Postscaler 1:1 - 1:16 Interrupt Control PTIF Period match PTMOD1 PTMOD0 The PWM time base can be configured for four different modes of operation: • • • • Free Running mode Single-shot mode Continuous Up/Down Count mode Continuous Up/Down Count mode with interrupts for double updates These four modes are selected by the PTMOD1:PTMOD0 bits in the PTCON0 register. The Free Running mode produces edge-aligned PWM generation. The up/down counting modes produce center-aligned PWM generation. The Single-shot mode allows the PWM module to support pulse control of certain electronically commutated motors (ECMs) and produces edge-aligned operation. 2003 Microchip Technology Inc. Preliminary DS39616B-page 185 PIC18F2331/2431/4331/4431 REGISTER 17-1: PTCON0: PWM TIMER CONTROL REGISTER 0 R/W-0 PTOPS3 bit 7 R/W-0 PTOPS2 R/W-0 PTOPS1 R/W-0 PTOPS0 R/W-0 R/W-0 PTCKPS1 PTCKPS0 R/W-0 PTMOD1 R/W-0 PTMOD0 bit 0 bit 7-4 PTOPS3:PTOPS0: PWM Time Base Output Postscale Select bits 0000 =1:1 Postscale 0001 =1:2 Postscale . . . 1111 =1:16 Postscale bit 3-2 PTCKPS1:PTCKPS0: PWM Time Base Input Clock Prescale Select bits 00 =PWM time base input clock is Fosc/4 (1:1 prescale) 01 =PWM time base input clock is Fosc/16 (1:4 prescale) 10 =PWM time base input clock is Fosc/64 (1:16 prescale) 11 =PWM time base input clock is Fosc/256 (1:64 prescale) bit 1-0 PTMOD1:PTMOD0: PWM Time Base Mode Select bits 11 =PWM time base operates in a Continuous Up/Down mode with interrupts for double PWM updates. 10 =PWM time base operates in a Continuous Up/Down Counting mode. 01 =PWM time base configured for Single-shot mode. 00 =PWM time base operates in a Free Running mode. Legend: REGISTER 17-2: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown PTCON1: PWM TIMER CONTROL REGISTER 1 R/W-0 PTEN bit 7 R-0 PTDIR U-0 — U-0 — U-0 — bit 7 PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is ON 0 = PWM time base is OFF bit 6 PTDIR: PWM Time Base Count Direction Status bit 1 = PWM time base counts down. 0 = PWM time base counts up. bit 5-0 Unimplemented: Read as ‘0’. U-0 — U-0 — U-0 — bit 0 Legend: DS39616B-page 186 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’= bit is set ‘0’ = bit is cleared Preliminary x = bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 17-3: bit 7 PWMCON0: PWM CONTROL REGISTER 0 U-0 R/W-1(1) R/W-1(1) R/W-1(1) R/W-0 — PWMEN2 PWMEN1 PWMEN0 PMOD3(3) bit 7 Unimplemented: Read as ‘0’. R/W-0 PMOD2 R/W-0 PMOD1 R/W-0 PMOD0 bit 0 bit 6-4 PWMEN2:PWMEN0: PWM Module Enable bits(1) 111 =All odd PWM I/O pins enabled for PWM output(2). 110 =PWM1, PWM3 pins enabled for PWM output. 101 =All PWM I/O pins enabled for PWM output(2) . 100 =PWM0, PWM1, PWM2, PWM3, PWM4 and PWM5 pins enabled for PWM output. 011 =PWM0, PWM1, PWM2 and PWM3 I/O pins enabled for PWM output. 010 =PWM0 and PWM1 pins enabled for PWM output. 001 =PWM1 pin is enabled for PWM output. 000 =PWM module disabled. All PWM I/O pins are general purpose I/O. bit 3-0 PMOD3:PMOD0: PWM Output Pair Mode bits For PMOD0: 1 = PWM I/O pin pair (PWM0, PWM1) is in the Independent mode. 0 = PWM I/O pin pair (PWM0, PWM1) is in the Complementary mode. For PMOD1: 1 = PWM I/O pin pair (PWM2, PWM3) is in the Independent mode. 0 = PWM I/O pin pair (PWM2, PWM3) is in the Complementary mode. For PMOD2: 1 = PWM I/O pin pair (PWM4, PWM5) is in the Independent mode. 0 = PWM I/O pin pair (PWM4, PWM5) is in the Complementary mode. For PMOD3(3): 1 = PWM I/O pin pair (PWM6, PWM7) is in the Independent mode. 0 = PWM I/O pin pair (PWM6, PWM7) is in the Complementary mode. Note 1: Reset condition of PWMEN bits depends on PWMPIN device configuration bit. 2: When PWMEN2:PWMEN0 = 101, PWM[5:0] outputs are enabled for PIC18F2X31 devices; PWM[7:0] outputs are enabled for PIC18F4X31devices. When PWMEN2:PWMEN0 = 111, PWM outputs 1, 3 and 5 are enabled in PIC18F2X31devices; PWM outputs 1, 3, 5 and 7 are enabled in PIC18F4X31 devices. 3: Unimplemented in PIC18F2X31 devices; maintain these bits clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared 2003 Microchip Technology Inc. Preliminary x = bit is unknown DS39616B-page 187 PIC18F2331/2431/4331/4431 REGISTER 17-4: PWMCON1: PWM CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 — UDIS SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR bit 7 bit 7-4 SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits 0000 =1:1 Postscale 0001 =1:2 Postscale . . . 1111 =1:16 Postscale R/W-0 OSYNC bit 0 bit 3 SEVTDIR: Special Event Trigger Time Base Direction bit 1 = A special event trigger will occur when the PWM time base is counting downwards. 0 = A special event trigger will occur when the PWM time base is counting upwards. bit 2 Unimplemented: Read as ‘0’. bit 1 UDIS: PWM Update Disable bit 1 = Updates from duty cycle and period buffer registers are disabled. 0 = Updates from duty cycle and period buffer registers are enabled. bit 0 OSYNC: PWM Output Override Synchronization bit 1 = Output overrides via the OVDCON register are synchronized to the PWM time base. 0 = Output overrides via the OVDCON register are asynchronous. Legend: 17.3.1 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared FREE RUNNING MODE Note: In the Free Running mode, the PWM time base (PTMRL and PTMRH) will begin counting upwards until the value in the Time Base Period Register, PTPER (PTPERL and PTPERH), is matched. The PTMR registers will be reset on the following input clock edge and the time base will continue counting upwards as long as the PTEN bit remains set. 17.3.4 17.3.2 SINGLE-SHOT MODE In the Single-shot mode, the PWM time base will begin counting upwards when the PTEN bit is set. When the value in the PTMR register matches the PTPER register, the PTMR register will be reset on the following input clock edge and the PTEN bit will be cleared by the hardware to halt the time base. 17.3.3 CONTINUOUS UP/DOWN COUNTING MODES In continuous up/down counting modes, the PWM time base counts upwards until the value in the PTPER register matches with PTMR. On the following input clock edge, the timer counts downwards. The PTDIR bit in the PTCON1 register is read-only and indicates the counting direction. The PTDIR bit is set when the timer counts downwards. DS39616B-page 188 x = bit is unknown When the PWM timer is enabled in Up/Down Count mode, during the first half of the first period of the up/down counting modes, the PWM outputs are kept inactive. By doing this, PWM pins will output garbage duty cycle due to unknown value in the PTMR registers. PWM TIME BASE PRESCALER The input clock to PTMR (FOSC/4) has prescaler options of 1:1, 1:4, 1:16 or 1:64. These are selected by control bits PTCKPS<1:0> in the PTCON0 register. The prescaler counter is cleared when any of the following occurs: • Write to the PTMR register • Write to the PTCON (PTCON0 or PTCON1) register • Any device Reset Note: The PTMR register is not cleared when PTCON is written. Table 17-1 shows the minimum PWM frequencies that can be generated with the PWM time base and the prescaler. An operating frequency of 40 MHz (FCYC = 10 MHz) and PTPER = 0xFFF is assumed in the table. The PWM module must be capable of generating PWM signals at the line frequency (50 Hz or 60 Hz) for certain power control applications. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 17-1: MINIMUM PWM FREQUENCY 17.4 Minimum PWM Frequencies vs. Prescaler Value for FCYC = 10 MIPS, (PTPER = 0FFFh) Prescale PWM Frequency Edge-aligned PWM Frequency Center-aligned 1:1 1:4 1:16 1:64 2441 Hz 610 Hz 153 Hz 38 Hz 1221 Hz 305 Hz 76 Hz 19 Hz 17.3.5 PWM Time Base Interrupts The PWM timer can generate interrupts based on the modes of operation selected by PTMOD<1:0> bits and the postscaler bits (PTOPS<3:0>). 17.4.1 INTERRUPTS IN FREE RUNNING MODE When the PWM time base is in the Free Running mode (PTMOD<1:0> = 00), an interrupt event is generated each time a match with the PTPER register occurs. The PTMR register is reset to zero in the following clock edge. PWM TIME BASE POSTSCALER Using a postscaler selection other than 1:1 will reduce the frequency of interrupt events. The match output of PTMR can optionally be post-scaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate an interrupt. The postscaler counter is cleared when any of the following occurs: • Write to the PTMR register • Write to the PTCON register • Any device Reset The PTMR register is not cleared when PTCON is written. FIGURE 17-5: PWM TIME BASE INTERRUPT TIMING, FREE RUNNING MODE A: PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 1 PTMR FFEh FFFh 000h 001h 002h PTMR_INT_REQ PTIF bit B: PRESCALER = 1:4 Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc 1 PTMR FFEh FFFh 000h 001h 002h PTMR_INT_REQ PTIF bit Note 1: PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example. 2003 Microchip Technology Inc. Preliminary DS39616B-page 189 PIC18F2331/2431/4331/4431 17.4.2 INTERRUPTS IN SINGLE-SHOT MODE 17.4.3 When the PWM time base is in the Single-shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs. The PWM timer register (PTMR) is reset to zero on the following input clock edge, and the PTEN bit is cleared. The postscaler selection bits have no effect in this Timer mode. FIGURE 17-6: INTERRUPTS IN CONTINUOUS UP/DOWN COUNTING MODE In the Up/Down Counting mode (PTMOD<1:0> = 10), an interrupt event is generated each time the value of the PTMR register becomes zero and the PWM time base begins to count upwards. The postscaler selection bits may be used in this mode of the timer to reduce the frequency of the interrupt events. Figure 17-7 shows the interrupts in continuous Up/Down Counting mode. PWM TIME BASE INTERRUPT TIMING, SINGLE SHOT MODE A: PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 2 PTMR FFEh FFFh 000h 1 1 000h 000h 1 PTMR_INT_REQ PTIF bit B: PRESCALER = 1:4 Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Q4 Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc Qc 2 PTMR FFEh 1 FFFh 1 000h 000h 000h 1 PTMR_INT_REQ PTIF bit Note 1: 2: Interrupt flag bit PTIF is sampled here (every Q1). PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example. DS39616B-page 190 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 17-7: PWM TIME BASE INTERRUPTS, UP/DOWN COUNTING MODE PRESCALER = 1:1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC/4 PTMR 002h 001h 000h 001h 002h PTDIR bit PTMR_INT_REQ 1 1 1 1 PTIF bit PRESCALER = 1:4 Q4 Qc PTMR Qc Qc Qc Qc 002h Qc Qc Qc Qc 001h Q4 Qc Qc Qc Qc 000h Qc Qc 001h Qc Qc Qc Qc Qc 002h PTDIR bit 1 1 1 1 PTMR_INT_REQ PTIF bit Note 1: Interrupt flag bit PTIF is sampled here (every Q1). 2003 Microchip Technology Inc. Preliminary DS39616B-page 191 PIC18F2331/2431/4331/4431 17.4.4 INTERRUPTS IN DOUBLE UPDATE MODE Note: This mode is available in Up/Down Counting mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches with PTPER register. Figure 17-8 shows the interrupts in Up/Down Counting mode with double updates. Do not change PTMOD while PTEN is active. It will yield unexpected results. To change PWM Timer mode of operation, first clear PTEN bit, load PTMOD with required data and then set PTEN. The Double Update mode provides two additional functions to the user in Center-Aligned mode. 1. 2. The control loop bandwidth is doubled because the PWM duty cycles can be updated twice per period. Asymmetrical center-aligned PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications. FIGURE 17-8: PWM TIME BASE INTERRUPTS, UP/DOWN COUNTING MODE WITH DOUBLE UPDATES A: PRESCALER = 1:1 Case 1: PTMR Counting Upwards Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 2 PTMR 3FDh 3FEh 3FFh 3FEh 3FDh PTDIR bit PTMR_INT_REQ 1 1 1 1 PTIF bit Case 2: PTMR Counting Downwards Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 PTMR 002h 001h 000h 001h 002h PTDIR bit PTMR_INT_REQ PTIF bit Note 1: 2: 1 1 1 1 Interrupt flag bit PTIF is sampled here (every Q1). PWM Time Base Period register, PTPER, is loaded with the value 3FFh for this example. DS39616B-page 192 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.5 PWM Period The PWM period is defined by the PTPER register pair (PTPERL and PTPERH). The PWM period has 12-bit resolution by combining 4 LSBs of PTPERH and 8-bits of PTPERL. PTPER is a double-buffered register used to set the counting period for the PWM time base. The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula: EQUATION 17-3: Fosc/4 log Fpwm The PTPER buffer contents are loaded into the PTPER register at the following times: • Free Running and Single-shot modes: when the PTMR register is reset to zero after a match with the PTPER register. • Up/Down Counting modes: When the PTMR register is zero. The value held in the PTPER buffer is automatically loaded into the PTPER register when the PWM time base is disabled (PTEN = 0). Figure 17-9 and Figure 17-10 indicate the times when the contents of the PTPER buffer are loaded into the actual PTPER register. PWM RESOLUTION Resolution = log(2) The PWM resolutions and frequencies are shown for a selection of execution speeds and PTPER values in Table 17-2. The PWM frequencies in Table 17-2 are calculated for Edge-aligned PWM mode. For Center-aligned mode, the PWM frequencies will be approximately one-half the values indicated in this table. TABLE 17-2: The PWM period can be calculated from the following formulas: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS PWM Frequency = 1/TPWM EQUATION 17-1: PWM PERIOD FOR FREE RUNNING MODE TPWM = (PTPER + 1) Fosc/(PTMRPS/4) or TPWM = EQUATION 17-2: TPWM = (PTPER + 1) x PTMRPS Fosc/4 PWM PERIOD FOR UP/DOWN COUNTING MODE (2 x PTPER) Fosc/(PTMRPS/4) The PWM frequency is the inverse of period; or 1 PWM frequency = ------------------------------PWM period Fosc MIPS PTPER PWM PWM Value Resolution Frequency 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 25 MHz 25 MHz 25 MHz 10 MHz 10 MHz 10 MHz 5 MHz 5 MHz 5 MHz 4 MHz 4 MHz 4 MHz 10 10 10 10 10 10 10 10 10 6.25 6.25 6.25 2.5 2.5 2.5 1.25 1.25 1.25 1 1 1 0FFFh 07FFh 03FFh 01FFh FFh 7Fh 3Fh 1Fh 0Fh 0FFFh 03FFh FFh 0FFFh 03FFh FFh 0FFFh 03FFh FFh 0FFFh 03FFh FFh 14 bits 13 bits 12 bits 11 bits 10 bits 9 bits 8 bits 7 bits 6 bits 14 bits 12 bits 10 bits 14 bits 12 bits 10 bits 14 bits 12 bits 10 bits 14 bits 12 bits 10 bits 2.4 kHz 4.9 kHz 9.8 kHz 19.5 kHz 39.0 kHz 78.1 kHz 156.2 kHz 312.5 kHz 625 kHz 1.5 kHz 6.1 kHz 24.4 kHz 610 Hz 2.4 kHz 9.8 kHz 305 Hz 1.2 kHz 4.9 kHz 244 Hz 976 Hz 3.9 kHz Note: For center-aligned operation, PWM frequencies will be approximately 1/2 the value indicated in the table. 2003 Microchip Technology Inc. Preliminary DS39616B-page 193 PIC18F2331/2431/4331/4431 FIGURE 17-9: PWM PERIOD BUFFER UPDATES IN FREE RUNNING COUNT MODE Period value loaded from PTPER Buffer register 7 6 New PTPER value = 007 5 4 Old PTPER value = 004 4 4 3 3 3 2 2 2 1 1 1 0 0 0 New value written to PTPER buffer. FIGURE 17-10: PWM PERIOD BUFFER UPDATES IN UP/DOWN COUNTING MODES Period value loaded from PTPER Buffer register 7 New PTPER value = 007 6 5 4 Old PTPER value = 004 3 2 1 0 4 3 3 2 2 1 1 0 6 5 4 3 2 1 0 New value written to PTPER buffer. DS39616B-page 194 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.6 PWM Duty Cycle The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCn hold the actual duty cycle value from PTMRH/L<11:0>, while the lower 2 bits control which internal Q-clock the duty cycle match occurs. This 2-bit value is decoded from the Q-clocks as shown in Figure 17-11 (when the prescaler is 1:1 (PTCKPS = 00)). PWM duty cycle is defined by PDCx (PDCxL and PDCxH) registers. There are a total of 4 PWM Duty Cycle registers for 4 pairs of PWM channels. The Duty Cycle registers have 14-bit resolution by combining 6 LSbs of PDCxH with the 8 bits of PDCxL. PDCx is a double-buffered register used to set the counting period for the PWM time base. 17.6.1 In Edge-aligned mode, the PWM period starts at Q1 and ends when the Duty Cycle register matches the PTMR register as follows. The duty cycle match is considered when the upper 12 bits of the PDC is equal to the PTMR and the lower 2 bits are equal to Q1, Q2, Q3 or Q4, depending on the lower two bits of the PDC (when the prescaler is 1:1, or PTCKPS = 00). PWM DUTY CYCLE REGISTERS There are four 14-bit special function registers used to specify duty cycle values for the PWM module: • • • • PDC0 (PDC0L and PDC0H) PDC1 (PDC1L and PDC1H) PDC2 (PDC2L and PDC2H) PDC3 (PDC3L and PDC3H) Note: When prescaler is not 1:1 (PTCKPS ≠ ~00), the duty cycle match occurs at Q1 clock of the instruction cycle when the PTMR and PDC match occurs. Each compare unit has logic that allows override of the PWM signals. This logic also ensures that the PWM signals will complement each other (with dead time insertion) in Complementary mode (see Section 17.7 “Dead Time Generators”). FIGURE 17-11: DUTY CYCLE COMPARISON PTMRH<7:0> PTMRL<7:0> PTMR<11:0> PTMRH<3:0> PTMRL<7:0> Q-CLOCKS(1) <1:0> UNUSED COMPARATOR UNUSED PDCnH<5:0> PDCnL<7:0> PDCn<13:0> PDCnH<7:0> PDCnL<7:0> Note 1: This value is decoded from the Q-Clocks: 00 = duty cycle match occurs on Q1 01 = duty cycle match occurs on Q2 10 = duty cycle match occurs on Q3 11 = duty cycle match occurs on Q4 2003 Microchip Technology Inc. Preliminary DS39616B-page 195 PIC18F2331/2431/4331/4431 17.6.2 DUTY CYCLE REGISTER BUFFERS The four PWM Duty Cycle registers are double-buffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period. In edge-aligned PWM Output mode, a new duty cycle value will be updated whenever a PTMR match with the PTPER register occurs and PTMR is reset as shown in Figure 17-12. Also, the contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0). When the PWM time base is in the Up/Down Counting mode, new duty cycle values will be updated when the value of the PTMR register is zero and the PWM time base begins to count upwards. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0). Figure 17-13 shows the timings when the duty cycle update occur for the Up/Down Count mode. In this mode, up to one entire PWM period is available for calculating and loading the new PWM duty cycle before changes take effect. When the PWM time base is in the Up/Down Counting mode with double updates, new duty cycle values will be updated when the value of the PTMR register is zero and when the value of the PTMR register matches the value in the PTPER register. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers during both of the above said conditions. Figure 17-14 shows the duty cycle updates for Up/Down mode with double update. In this mode, only up to half of a PWM period is available for calculating and loading the new PWM duty cycle before changes take effect. FIGURE 17-13: 17.6.3 EDGE-ALIGNED PWM Edge-aligned PWM signals are produced by the module when the PWM time base is in the Free Running mode or the Single-shot mode. For edge-aligned PWM outputs, the output for a given PWM channel has a period specified by the value loaded in PTPER and a duty cycle specified by the appropriate Duty Cycle register (see Figure 17-12). The PWM output is driven active at the beginning of the period (PTMR = 0) and is driven inactive when the value in the Duty Cycle register matches PTMR. A new cycle is started when PTMR matches the PTPER as explained in the PWM period section. If the value in a particular Duty Cycle register is zero, then the output on the corresponding PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is greater than the value held in the PTPER register. FIGURE 17-12: EDGE-ALIGNED PWM New Duty Cycle Latched PTPER PDC PTMR (old) Value PDC (new) 0 Duty Cycle Active at beginning of period Period DUTY CYCLE UPDATE TIMES IN UP/DOWN COUNTING MODE Duty cycle value loaded from buffer register PWM output PTMR Value New value written to duty cycle buffer DS39616B-page 196 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 17-14: DUTY CYCLE UPDATE TIMES IN UP/DOWN COUNTING MODE WITH DOUBLE UPDATES Duty cycle value loaded from buffer register PWM output PTMR Value New values written to duty cycle buffer. 17.6.4 CENTER-ALIGNED PWM Center-aligned PWM signals are produced by the module when the PWM time base is configured in an Up/Down Counting mode (see Figure 17-15). The PWM compare output is driven to the active state when the value of the Duty Cycle register matches the value of PTMR and the PWM time base is counting downwards (PTDIR = 1). The PWM compare output will be driven to the inactive state when the PWM time base is counting upwards (PTDIR = 0) and the value in the PTMR register matches the duty cycle value. If the value in a particular Duty Cycle register is zero, then the output on the corresponding PWM pin will be FIGURE 17-15: inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register. Note: When the PWM is started in Center-aligned mode, the period register (PTPER) is loaded into the PWM Timer register (PTMR) and the PTMR is configured automatically to start down-counting. This is done to ensure that all the PWM signals don’t start at the same time. START OF CENTER-ALIGNED PWM Period/2 PTPER PTMR Value Duty Cycle 0 Start of first PWM Period Duty Cycle Period 2003 Microchip Technology Inc. Preliminary Period DS39616B-page 197 PIC18F2331/2431/4331/4431 FIGURE 17-16: • • • • PDC0 register controls PWM1/PWM0 outputs PDC1 register controls PWM3/PWM2 outputs PDC2 register controls PWM5/PWM4 outputs PDC3 register controls PWM7/PWM6 outputs PWM1/3/5/7 are the main PWMs that are controlled by the PDC registers and PWM0/2/4/6 are the complemented outputs. When using the PWMs to control the half bridge, the odd number PWMs can be used to control the upper power switch and the even numbered PWMs for the lower switches. DS39616B-page 198 TYPICAL LOAD FOR COMPLEMENTARY PWM OUTPUTS PWM5 3 Phase Load PWM4 PWM3 +V PWM2 The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration as shown in Figure 17-16. This inverter topology is typical for a 3-phase induction motor, brushless DC motor or a 3-phase Uninterruptible Power Supply (UPS) control applications. Each upper/lower power switch pair is fed by a complementary PWM signal. Dead time may be optionally inserted during device switching where both outputs are inactive for a short period (see Section 17.7 “Dead Time Generators”). In Complementary mode, the duty cycle comparison units are assigned to the PWM outputs as follows: PWM1 COMPLEMENTARY PWM OPERATION PWM0 17.6.5 The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to Complementary mode by default upon all kinds of device resets. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.7 17.7.1 Dead Time Generators In power inverter applications where the PWMs are used in Complementary mode to control the upper and lower switches of a half-bridge, a dead time insertion is highly recommended. The dead time insertion keeps both outputs in inactive state for a brief time. This avoids any overlap in the switching during the state change of the power devices due to TON and TOFF characteristics. Because the power output devices cannot switch instantaneously, some amount of time must be provided between the turn-off event of one PWM output in a complementary pair and the turn-on event of the other transistor. The PWM module allows dead time to be programmed. Following sections explain the dead time block in detail. FIGURE 17-17: Each complementary output pair for the PWM module has a 6-bit down counter used to produce the dead time insertion. As shown in Figure 17-17, each dead time unit has a rising and falling edge detector connected to the duty cycle comparison output. The dead time is loaded into the timer on the detected PWM edge event. Depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the timer counts down to zero. A timing diagram indicating the dead time insertion for one pair of PWM outputs is shown in Figure 17-18. DEAD TIME CONTROL UNIT BLOCK DIAGRAM FOR ONE PWM OUTPUT PAIR Dead Time Select Bits FOSC DEAD TIME INSERTION Zero Compare Clock Control and Prescaler 6-Bit Down Counter Odd PWM Signal To Output Control Block Dead Time Prescale Even PWM Signal To Output Control Block Dead Time Register Duty Cycle Compare Input FIGURE 17-18: DEAD TIME INSERTION FOR COMPLEMENTARY PWM td td PDC1 compare output PWM1 PWM0 2003 Microchip Technology Inc. Preliminary DS39616B-page 199 PIC18F2331/2431/4331/4431 REGISTER 17-5: DTCON – DEAD TIME CONTROL REGISTER R/W-0 DTPS1 bit 7 R/W-0 DTPS0 R/W-0 DT5 R/W-0 DT4 R/W-0 DT3 R/W-0 DT2 bit 7-6 DTPS1:DTPS0: Dead Time Unit A Prescale Select bits 11 = Clock source for Dead Time Unit is FOSC/16. 10 = Clock source for Dead Time Unit is FOSC/8. 01 = Clock source for Dead Time Unit is FOSC/4. 00 = Clock source for Dead Time Unit is FOSC/2. bit 5-0 DT5:DT0: Unsigned 6-bit dead time value bits for Dead Time Unit. R/W-0 DT1 R/W-0 DT0 bit 0 Legend: 17.7.2 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared 3. DEAD TIME RANGES The amount of dead time provided by the dead time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value defined in the DTCON register. Four input clock prescaler selections have been provided to allow a suitable range of dead times based on the device operating frequency. FOSC/2, FOSC/4, FOSC/8 and FOSC/16 are the clock prescaler options available using the DTPS1:DTPS0 control bits in the DTCON register. 4. After selecting an appropriate prescaler value, the dead time is adjusted by loading a 6-bit unsigned value into DTCON<5:0>. The dead time unit prescaler is cleared on any of the following events: • On a load of the down timer due to a duty cycle comparison edge event; • On a write to the DTCON register; or • On any device Reset. 17.7.3 2. The dead time counter is clocked using every other Q-clock depending on the two LSbs in the Duty Cycle registers: • If the PWM duty cycle match occurs on Q1 or Q3, then the dead time counter is clocked using every Q1 and Q3. • If the PWM duty cycles match occurs on Q2 or Q4, then the dead time counter is clocked using every Q2 and Q4. When the DTPS1:DTPS0 bits are set to any of the other dead time prescaler settings, (i.e., FOSC/4, FOSC/8 or FOSC/16) and the PWM Time Base Prescaler is set to 1:1, the dead time counter is clocked by the Q-clock corresponding to the Q-clocks on which the PWM duty cycle match occurs. The actual dead time is calculated from the DTCON register as follows: Dead Time = Dead time value / (FOSC/prescaler) DECREMENTING THE DEAD TIME COUNTER The dead time counter is clocked from any of the Q clocks based on the following conditions. 1. x = bit is unknown Table 17-3 shows example dead time ranges as a function of the input clock prescaler selected and the device operating frequency. The dead time counter is clocked on Q1 when: • The DTPS bits are set to any of the following dead time prescaler settings: Fosc/4, FOSC/8, FOSC/16 • The PWM Time Base Prescale bits (PTCKPS) are set to any of the following prescale ratios: FOSC/16, FOSC/64, FOSC/256. The dead time counter is clocked by a pair of Q-clocks when the PWM Time Base Prescale bits are set to 1:1 (PTCKPS1:PTCKPS0 = 00, FOSC/4) and the dead time counter is clocked by the FOSC/2 (DTPS1:DTPS0 = 00). DS39616B-page 200 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 17-3: Fosc (MHz) 40 40 40 40 32 32 32 32 25 25 25 25 20 20 20 20 10 10 10 10 5 5 5 5 4 4 4 4 EXAMPLE DEAD TIME RANGES 17.7.4 MIPS Prescaler Selection Dead Time Min Dead Time Max 10 10 10 10 8 8 8 8 6.25 6.25 6.25 6.25 5 5 5 5 2.5 2.5 2.5 2.5 1.25 1.25 1.25 1.25 1 1 1 1 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 50 ns 100 ns 200 ns 400 ns 62.5 ns 125 ns 250 ns 500 ns 80 ns 160 ns 320 ns 640 ns 100 ns 200 ns 400 800 200 ns 400 ns 800 ns 1.6 µs 400 ns 800 ns 1.6 µs 3.2 µs 0.5 µs 1 µs 2 µs 4 µs 3.2 µs 6.4 µs 12.8 µs 25.6 µs 4 µs 8 µs 16 µs 32 µs 5.12 vs 10.2 µs 20.5 µs 41 µs 6.4 µs 12.8 µs 25.6 vs 51.2 µs 12.8 µs 25.6 µs 51.2 µs 102.4 µs 25.6 µs 51.2 µs 102.4 µs 204.8 µs 32 µs 64 µs 128 µs 256 µs DEAD TIME DISTORTION Note 1: For small PWM duty cycles, the ratio of dead time to the active PWM time may become large. In this case, the inserted dead time will introduce distortion into waveforms produced by the PWM module. The user can ensure that dead time distortion is minimized by keeping the PWM duty cycle at least three times larger than the dead time. A similar effect occurs for duty cycles at or near 100%. The maximum duty cycle used in the application should be chosen such that the minimum inactive time of the signal is at least three times larger than the dead time. If the dead time is greater or equal to the duty cycle of one of the PWM outputs pairs, then that PWM pair will be inactive for the whole period. 2: Changing the dead time values in DTCON when the PWM is enabled may result in undesired situation. Disable the PWM (PTEN = 0) before changing the dead time value 17.8 Independent PWM Output Independent PWM mode is used for driving the loads as shown in Figure 17-19 for driving one winding of a switched reluctance motor. A particular PWM output pair is configured in the Independent Output mode when the corresponding PMOD bit in the PWMCON0 register is set. No dead time control is implemented between the PWM I/O pins when the module is operating in the Independent mode and both I/O pins are allowed to be active simultaneously. This mode can also be used to drive stepper motors. 17.8.1 DUTY CYCLE ASSIGNMENT IN THE INDEPENDENT MODE In the Independent mode, each duty cycle generator is connected to both PWM output pins in a given PWM output pair. The odd and the even PWM output pins are driven with a single PWM duty cycle generator. PWM1 and PWM0 are driven by the PWM channel which uses PDC0 register to set the duty cycle, PWM3 and PWM2 with PDC1, PWM5 and PWM4 with PDC2, PWM7 and PWM6 with PDC3, see Figure 17-3 and Register 17-3. 2003 Microchip Technology Inc. Preliminary DS39616B-page 201 PIC18F2331/2431/4331/4431 17.8.2 PWM CHANNEL OVERRIDE PWM output may be manually overridden for each PWM channel by using the appropriate bits in the OVDCOND and OVDCONS registers. The user may select the following signal output options for each PWM output pin operating in the Independent mode: • I/O pin outputs PWM signal • I/O pin inactive • I/O pin active Refer to Section 17.10 “PWM Output Override” for details for all the override functions. FIGURE 17-19: CENTER-CONNECTED LOAD +V PWM1 OVDCOND and OVDCONS registers are used to define the PWM override options. The OVDCOND register contains eight bits, POVD7:POVD0, that determine which PWM I/O pins will be overridden. The OVDCONS register contains eight bits, POUT7:POUT0, that determine the state of the PWM I/O pins when a particular output is overridden via the POVD bits. The POVD bits are active-low control bits. When the POVD bits are set, the corresponding POUT bit will have no effect on the PWM output. In other words, the pins corresponding to POVD bits that are set will have the duty PWM cycle set by the PDC registers. When one of the POVD bits is cleared, the output on the corresponding PWM I/O pin will be determined by the state of the POUT bit. When a POUT bit is set, the PWM pin will be driven to its active state. When the POUT bit is cleared, the PWM pin will be driven to its inactive state. LOAD 17.10.1 PWM0 17.9 Single-Pulse PWM Operation The single pulse PWM operation is available only in Edge-aligned mode. In this mode, the PWM module will produce single pulse output. Single-pulse operation is configured when the PTMOD1:PTMOD0 bits are set to ‘01’ in PTCON0 register. This mode of operation is useful for driving certain types of ECMs. In Single-pulse mode, the PWM I/O pin(s) are driven to the active state when the PTEN bit is set. When the PWM timer match with Duty Cycle register occurs, the PWM I/O pin is driven to the inactive state. When the PWM timer match with the PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated, if the corresponding interrupt bit is set. Note: PTPER and PDC values are held as it is after the single pulse output. To have another cycle of single pulse, only PTEN has to be enabled. 17.10 PWM Output Override 17.10.2 OVERRIDE SYNCHRONIZATION If the OSYNC bit in the PWMCON1 register is set, all output overrides performed via the OVDCOND and OVDCONS registers will be synchronized to the PWM time base. Synchronous output overrides will occur on following conditions: • When the PWM is in Edge-aligned mode, synchronization occurs when PTMR is zero. • When the PWM is in Center-aligned mode, synchronization occurs when PTMR is zero and when the value of PTMR matches PTPER. Note 1: In the Complementary mode, the even channel cannot be forced active by a fault or override event when the odd channel is active. The even channel is always the complement of the odd channel with dead time inserted, before the odd channel can be driven to its active state as shown in Figure 17-20. The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states independent of the duty cycle comparison units. The PWM override bits are useful when controlling various types of ECMs like a BLDC motor. DS39616B-page 202 COMPLEMENTARY OUTPUT MODE The even-numbered PWM I/O pin has override restrictions when a pair of PWM I/O pins are operating in the Complementary mode (PMODx = 0). In Complementary mode, if the even-numbered pin is driven active by clearing the corresponding POVD bit and by setting POUT bits in OVDCOND and OVDCONS registers, the output signal is forced to be the complement of the odd-numbered I/O pin in the pair (see Figure 17-2 for details). Preliminary 2: Dead time inserted to the PWM channels even when they are in Override mode. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 17-20: OVERRIDE BITS IN COMPLEMENTARY MODE 1 POUT0 POUT1 4 5 PWM1 2 7 3 PWM0 6 Assume: PVOD0 = 0; PVOD1 = 0; PMOD0 = 0 1. Even override bits have no effect in Complementary mode. 2. Odd override bit is activated, which causes the even PWM to deactivate. 3. Dead time insertion. 4. Odd PWM activated after the dead time. 5. Odd override bit is deactivated, which causes the odd PWM to deactivate. 6. Dead time insertion. 7. Even PWM is activated after the dead time. 17.10.3 OUTPUT OVERRIDE EXAMPLES Figure 17-21 shows an example of a waveform that might be generated using the PWM output override feature. The figure shows a six-step commutation sequence for a BLDC motor. The motor is driven through a 3-phase inverter as shown in Figure 17-16. When the appropriate rotor position is detected, the PWM outputs are switched to the next commutation state in the sequence. In this example, the PWM outputs are driven to specific logic states. The OVDCOND and OVDCONS register values used to generate the signals in Figure 17-21 are given in Table 17-4. REGISTER 17-6: The PWM Duty Cycle registers may be used in conjunction with the OVDCOND and OVDCONS registers. The Duty Cycle registers control the average voltage across the load and the OVDCOND and OVDCONS registers control the commutation sequence. Figure 17-22 shows the waveforms, while Table 17-4 and Table 17-5 show the OVDCOND and OVDCONS register values used to generate the signals. OVDCOND: OUTPUT OVERRIDE CONTROL REGISTER R/W-1 R/W-1 POVD7(1) POVD6(1) bit 7 bit 7-0 R/W-1 POVD5 R/W-1 POVD4 R/W-1 POVD3 R/W-1 POVD2 R/W-1 POVD1 R/W-1 POVD0 bit 0 POVD7:POVD0: PWM Output Override bits(1) 1 = Output on PWM I/O pin is controlled by the value in the Duty Cycle register and the PWM time base. 0 = Output on PWM I/O pin is controlled by the value in the corresponding POUT bit. Note 1: Unimplemented in PIC18F2X31 devices; maintain these bits clear. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared 2003 Microchip Technology Inc. Preliminary x = bit is unknown DS39616B-page 203 PIC18F2331/2431/4331/4431 REGISTER 17-7: OVDCONS: OUTPUT STATE REGISTER R/W-0 POUT7(1) bit 7 R/W-0 POUT6(1) R/W-0 POUT5 R/W-0 POUT4 R/W-0 POUT3 R/W-0 POUT2 R/W-0 POUT1 R/W-0 POUT0 bit 0 POUT7:POUT0: PWM Manual Output bits(1) 1 = Output on PWM I/O pin is ACTIVE when the corresponding PWM output override bit is cleared. 0 = Output on PWM I/O pin is INACTIVE when the corresponding PWM output override bit is cleared. bit 7-0 Note 1: Unimplemented in PIC18F2X31 devices; maintain these bits clear. Legend: FIGURE 17-21: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared PWM OUTPUT OVERRIDE EXAMPLE #1 1 2 3 4 5 FIGURE 17-22: 6 x = bit is unknown PWM OUTPUT OVERRIDE EXAMPLE #2 1 2 3 4 PWM5 PWM4 PWM7 PWM3 PWM2 PWM6 PWM1 PWM5 PWM0 PWM4 TABLE 17-4: State PWM OUTPUT OVERRIDE EXAMPLE #1 PWM3 OVDCOND(POVD) OVDCONS(POUT) 1 2 3 4 5 6 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b TABLE 17-5: PWM2 00100100b 00100001b 00001001b 00011000b 00010010b 00000110b PWM1 PWM0 PWM OUTPUT OVERRIDE EXAMPLE #2 State OVDCOND (POVD) OVDCONS (POUT) 1 2 3 4 11000011b 11110000b 00111100b 00001111b 00000000b 00000000b 00000000b 00000000b DS39616B-page 204 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.11 PWM Output and Polarity Control 17.11.1 OUTPUT PIN CONTROL There are three device configuration bits associated with the PWM module that provide PWM output pin control defined in CONFIG3L configuration register. The PWMEN2:PWMEN0 control bits enable each PWM output pin as required in the application. All PWM I/O pins are general purpose I/O. When a pair of pins are enabled for PWM output, the PORT and TRIS registers controlling the pin are disabled. Refer to Figure 17-23 for details. • HPOL configuration bit • LPOL configuration bit • PWMPIN configuration bit These three configuration bits work in conjunction with the three PWM enable bits (PWMEN2:PWMEN0) in the PWMCON0 register. The configuration bits and PWM enable bits ensure that the PWM pins are in the correct states after a device Reset occurs. FIGURE 17-23: PWM I/O PIN BLOCK DIAGRAM PWM signal from module 1 0 PWM Pin Enable Data Bus D Q VDD WR PORT CK Q P Data Latch I/O Pin WR TRIS D Q CK Q N VSS TRIS Latch TTL or Schmitt Trigger RD TRIS Q D EN RD PORT Note: 17.11.2 I/O pin has protection diodes to VDD and VSS. PWM polarity selection logic not shown for clarity. OUTPUT POLARITY CONTROL The polarity of the PWM I/O pins is set during device programming via the HPOL and LPOL configuration bits in the CONFIG3L device configuration register. The HPOL configuration bit sets the output polarity for the high-side PWM outputs, PWM1, PWM3, PWM5 and PWM7. The polarity is active-high when HPOL is cleared (= 0), and active-low when it is set (= 1). The LPOL configuration bit sets the output polarity for the low-side PWM outputs, PWM0, PWM2, PWM4 and PWM6. As with HPOL, they are active-high when LPOL is cleared, and active-low when set. All output signals generated by the PWM module are referenced to the polarity control bits, including those generated by fault inputs or manual override (see Section 17.10 “PWM Output Override”). The default polarity configuration bits have the PWM I/O pins in active-high output polarity. 2003 Microchip Technology Inc. Preliminary DS39616B-page 205 PIC18F2331/2431/4331/4431 17.11.3 PWM OUTPUT PIN RESET STATES The PWMPIN configuration bit determines the PWM output pins to be PWM output pins or digital I/O pins, after the device comes out of reset. If the PWMPIN configuration bit is unprogrammed (default), the PWMEN2:PWMEN0 control bits will be cleared on a device Reset. Consequently, all PWM outputs will be tri-stated and controlled by the corresponding PORT and TRIS registers. If the PWMPIN configuration bit is programmed low, the PWMEN2:PWMEN0 control bits will be set as follows on a device Reset: • PWMEN2:PWMEN0 = 101 if device has 8 PWM pins (PIC18F4X31 devices) • PWMEN2:PWMEN0 = 100 if device has 6 PWM pins (PIC18F2X31 devices) All PWM pins will be enabled for PWM output and will have the output polarity defined by the HPOL and LPOL configuration bits. 17.12.2 MFAULT INPUT MODES The FLTAMOD and FLTBMOD bits in the FLTCONFIG register determine the modes of PWM I/O pins that are deactivated when they are overridden by fault input. FLTAS and FLTBS bits in the FLTCONFIG register give the status of FaultA and FaultB inputs. Each of the fault inputs have two modes of operation: • Inactive Mode (FLTxMOD = 0) This is a catastrophic Fault Management mode. When the fault occurs in this mode, the PWM outputs are deactivated. The PWM pins will remain in Inactivated mode until the fault is cleared (fault input is driven high) and the corresponding fault status bit has been cleared in software. The PWM outputs are enabled immediately at the beginning of the following PWM period, after Fault Status bit (FLTxS) is cleared. • Cycle-by-Cycle Mode (FLTxMOD = 1) 17.12 PWM Fault Inputs There are two fault inputs associated with the PWM module. The main purpose of the input fault pins is to disable the PWM output signals and drive them into an inactive state. The action of the fault inputs is performed directly in hardware so that when a fault occurs, it can be managed quickly and the PWMs outputs are put into an inactive state to save the power devices connected to the PWMs. When the fault occurs in this mode, the PWM outputs are deactivated. The PWM outputs will remain in the defined fault states (all PWM outputs inactive) for as long as the fault pin is held low. After the fault pin is driven high, the PWM outputs will return to normal operation at the beginning of the following PWM period, and the FLTS bit is automatically cleared. The PWM fault inputs are FLTA and FLTB, which can come from I/O pins, the CPU or another module. The FLTA and FLTB pins are active-low inputs so it is easy to “OR” many sources to the same input. The FLTCONFIG register (Register 17-8) defines the settings of FLTA and FLTB inputs. Note: 17.12.1 The inactive state of the PWM pins are dependent on the HPOL and LPOL configuration bit settings, which defines the active and inactive state for PWM outputs. FAULT PIN ENABLE BITS By setting the bits FLTAEN and FLTBEN in the FLTCONFIG register, the corresponding fault inputs are enabled. If both bits are cleared, then the fault inputs have no effect on the PWM module. DS39616B-page 206 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.12.3 PWM OUTPUTS WHILE IN FAULT CONDITION Note: While in the fault state (i.e., one or both FLTA and FLTB inputs are active), the PWM output signals are driven into their inactive states. The selection of which PWM outputs are deactivated (while in the fault state) is determined by the FLTCON bit in the FLTCONFIG register as follows: It is highly recommended to enable the fault condition on breakpoint if a debugging tool is used, while developing the firmware and the high-power circuitry is used. When the device is ready to program after debugging the firmware, BRFEN bit can be disabled. • FLTCON = 1. When FLTA or FLTB is asserted, the PWM outputs (i.e., PWM[7:0]) are driven into their inactive state • FLTCON = 0. When FLTA or FLTB is asserted, only PWM[5:0] outputs are driven inactive, leaving PWM[7:6] activated. Note: 17.12.4 Disabling only three PWM channels and leaving one PWM channel enabled when in the fault state, allows the flexibility to have at least one PWM channel enabled. None of the PWM outputs can be enabled (driven with the PWM Duty Cycle registers) while FLTCON = 1 and the fault condition is present. PWM OUTPUTS IN DEBUG MODE The BRFEN bit in the FLTCONFIG register controls the simulation of fault condition when a breakpoint is hit, while debugging the application using a In-Circuit Emulator (ICE) or a In-Circuit Debugger (ICD). Setting the BRFEN to high, enables the fault condition on breakpoint, thus driving the PWM outputs to inactive state. This is done to avoid any continuous keeping of status on the PWM pin, which may result in damage of the power devices connected to the PWM outputs. If BRFEN = 0, the fault condition on breakpoint is disabled. 2003 Microchip Technology Inc. Preliminary DS39616B-page 207 PIC18F2331/2431/4331/4431 REGISTER 17-8: FLTCONFIG: FAULT CONFIGURATION REGISTER R/W-0 BRFEN bit 7 R/W-0 FLTBS(1) R/W-0 R/W-0 FLTBMOD(1) FLTBEN(1) R/W-0 FLTCON R/W-0 FLTAS R/W-0 FLTAMOD R/W-0 FLTAEN bit 0 bit 7 BRFEN: Breakpoint Fault Enable bit 1 = Enable fault condition on a breakpoint (i.e., only when HDMIN = 1) 0 = Disable fault condition bit 6 FLTBS: Fault B Status bit(1) 1 = FLTB is asserted; if FLTBMOD = 0, cleared by the user if FLTBMOD = 1, cleared automatically at beginning of the new period when FLTB is deasserted 0 = No Fault bit 5 FLTBMOD: Fault B Mode bit(1) 1 = Cycle-by-cycle mode: Pins are inactive for the remainder of the current PWM period, or until FLTB is deasserted. FLTBS is cleared automatically when FLTB is inactive (no fault present). 0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTB is deasserted and FLTBS is cleared by the user only. bit 4 FLTBEN: Fault B Enable bit(1) 1 = Enable Fault B 0 = Disable Fault B bit 3 FLTCON: Fault Configuration bit 1 = FLTA , FLTB or both deactivates all PWM outputs 0 = FLTA or FLTB deactivates PWM[5:0] bit 2 FLTAS: Fault A Status bit 1 = FLTA is asserted; If FLTAMOD = 0, cleared by the user If FLTAMOD = 1, cleared automatically at beginning of the new period when FLTA is deasserted. 0 = No Fault bit 1 FLTAMOD: Fault A Mode bit 1 = Cycle-by-cycle mode: Pins are inactive for the remainder of the current PWM period, or until FLTA is deasserted. FLTAS is cleared automatically. 0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTA is deasserted and FLTAS is cleared by the user only. bit 0 FLTAEN: Fault A Enable bit 1 = Enable Fault A 0 = Disable Fault A Note 1: Unimplemented in PIC18F2X31 devices; maintain these bits clear. Legend: DS39616B-page 208 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared Preliminary x = bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 17.13 PWM Update Lockout 17.14.1 For a complex PWM application, the user may need to write up to four Duty Cycle registers and the Time Base Period Register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. The PWM module will always produce special event trigger pulses. This signal may optionally be used by the A/D module. Refer to Chapter 20.0 "10-bit High-Speed Analog-to-Digital Converter (A/D) Module" for details. A PWM update lockout feature may optionally be enabled so the user may specify when new duty cycle buffer values are valid. The PWM update lockout feature is enabled by setting the control bit UDIS in the PWMCON1 register. This bit affects all Duty Cycle Buffer registers and the PWM time base period buffer, PTPER. To perform a PWM update lockout: 1. 2. 3. 4. Set the UDIS bit. Write all Duty Cycle registers and PTPER, if applicable. Clear the UDIS bit to re-enable updates. With this, when UDIS bit is cleared, the buffer values will be loaded to the actual registers. This makes a synchronous loading of the registers. 17.14.2 SPECIAL EVENT TRIGGER ENABLE SPECIAL EVENT TRIGGER POSTSCALER The PWM special event trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS3:SEVOPS0 control bits in the PWMCON1 register. The special event output postscaler is cleared on any write to the SEVTCMP register pair, or on any device Reset. 17.14 PWM Special Event Trigger The PWM module has a special event trigger capability that allows A/D conversions to be synchronized to the PWM time base. The A/D sampling and conversion time may be programmed to occur at any point within the PWM period. The special event trigger allows the user to minimize the delay between the time when A/D conversion results are acquired and the time when the duty cycle value is updated. The PWM 16-bit Special Event Trigger register SEVTCMP (high and low), and five control bits in PWMCON1 register are used to control its operation. The PTMR value for which a special event trigger should occur is loaded into the SEVTCMP register pair. SEVTDIR bit in PWMCON1 register specifies the counting phase when the PWM time base is in an Up/Down Counting mode. If the SEVTDIR bit is cleared, the special event trigger will occur on the upward counting cycle of the PWM time base. If SEVTDIR is set, the special event trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR bit has effect only when PWM timer is in the Up/Down Counting mode. 2003 Microchip Technology Inc. Preliminary DS39616B-page 209 PIC18F2331/2431/4331/4431 TABLE 17-6: Name REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE Bit 7 INTCON Bit 6 GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u ---1 1111 ---1 1111 IPR3 — — — PTIP IC3DRIP IC2QEIP IC1IP TMR5IP PIE3 — — — PTIE IC3DRIE IC2QEIE IC1IE TMR5IE ---0 0000 ---0 0000 PIR3 — — — PTIF IC3DRIF IC2QEIF IC1IF TMR5IF ---0 0000 ---0 0000 PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTMOD1 PTMOD0 0000 0000 0000 0000 PTEN PTDIR — — PTCON0 PTCON1 PTMRL(1) PTCKPS1 PTCKPS0 — — — — 00-- ---- 00-- ---- 0000 0000 0000 0000 ---- 0000 ---- 0000 1111 1111 1111 1111 PWM Time Base Period (upper 4 bits) ---- 1111 ---- 1111 0000 0000 0000 0000 PWM Special Event Compare (upper 4 bits) ---- 0000 ---- 0000 PWM Time Base (lower 8 bits) PTMRH(1) — PTPERL(1) — — — PWM Time Base (upper 4 bits) PWM Time Base Period (lower 8 bits) PTPERH(1) — SEVTCMPL(1) — — — PWM Special Event Compare (lower 8 bits) SEVTCMPH(1) — — — PWMCON0 — PWMEN2 PWMEN1 PWMEN0 PMOD3(2) PMOD2 PMOD1 PMOD0 -101 0000 -101 0000 SEVOPS1 SEVOPS0 SEVTDIR — UDIS OSYNC 0000 0-00 0000 0-00 0000 0000 0000 0000 PWMCON1 DTCON SEVOPS3 SEVOPS2 DTPS1 DTPS0 (2) — Dead Time A Value register FLTBMOD(2) FLTBEN(2) FLTCON FLTAS 0000 0000 0000 0000 OVDCOND POVD7(2) POVD6(2) POVD5 POVD4 POVD3 POVD2 POVD1 POVD0 1111 1111 1111 1111 OVDCONS POUT7(2) POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 0000 0000 0000 0000 PDC0L(1) PWM Duty Cycle #0L register (lower 8 bits) FLTCONFIG PDC0H(1) PDC1L(1) PDC1H(1) PDC2L(1) PDC2H(1) PDC3L(1,2) PDC3H(1,2) Legend: Note 1: 2: BRFEN — FLTBS POUT6(2) — PWM Duty Cycle #0H register (upper 6 bits) PWM Duty Cycle #1L register (lower 8 bits) — — PWM Duty Cycle #1H register (upper 6 bits) PWM Duty Cycle #2L register (Lower 8 bits) — — PWM Duty Cycle #2H register (Upper 6 bits) PWM Duty Cycle #3L register (Lower 8 bits) — — PWM Duty Cycle #3H register (Upper 6 bits) FLTAMOD FLTAEN --00 0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 --00 0000 --00 0000 0000 0000 0000 0000 --00 0000 --00 0000 0000 0000 0000 0000 --00 0000 --00 0000 - = Unimplemented, u = Unchanged. Shaded cells are not used with the power control PWM. Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to. Unimplemented in PIC18F2X31 devices; maintain these bits clear. Reset values shown are for PIC18F4X31 devices. DS39616B-page 210 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.0 18.1 SYNCHRONOUS SERIAL PORT (SSP) MODULE SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI™) • Inter-Integrated Circuit (I2C™) An overview of I2C operations and additional information on the SSP module can be found in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023). Refer to Application Note AN578, “Use of the SSP module in the I 2C™ Multi-Master Environment” (DS00578). 18.2 SPI Mode This section contains register definitions and operational characteristics of the SPI module. Additional information on the SPI module can be found in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023A). SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: • Serial Data Out (SDO) – RC7/RX/DT/SDO • Serial Data In (SDI) – RC4/INT1/SDI/SDA • Serial Clock (SCK) – RC5/INT2/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SS) – RC6/TX/CK/SS When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: • • • • Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock polarity (Idle state of SCK) Clock edge (output data on rising/falling edge of SCK) • Clock rate (Master mode only) • Slave Select mode (Slave mode only) 2003 Microchip Technology Inc. Preliminary DS39616B-page 211 PIC18F2331/2431/4331/4431 REGISTER 18-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire®) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 C mode: This bit must be maintained clear CKE: SPI Clock Edge Select bit (Figure 18-2, Figure 18-3, and Figure 18-4) SPI mode, CKP = 0: 1 = Data transmitted on rising edge of SCK (Microwire® alternate) 0 = Data transmitted on falling edge of SCK SPI mode, CKP = 1: 1 = Data transmitted on falling edge of SCK (Microwire® default) 0 = Data transmitted on rising edge of SCK I2 C mode: This bit must be maintained clear D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. SSPEN is cleared. 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last S: Start bit (I2C mode only) This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. SSPEN is cleared. 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last R/W: Read/Write bit Information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or ACK bit. 1 = Read 0 = Write UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty Legend: DS39616B-page 212 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 18-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received, while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In SPI mode: 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level (Microwire® default) 0 = Idle state for clock is a low level (Microwire® alternate) In I2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1011 = I2C Firmware Controlled Master mode (slave Idle) 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 213 PIC18F2331/2431/4331/4431 FIGURE 18-1: SSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read Write SSPBUF reg • SDI must have TRISC<4> set • SDO must have TRISC<5> cleared • SCK (Master mode) must have TRISC<3> cleared • SCK (Slave mode) must have TRISC<3> set • SS must have TRISA<5> set and ADCON must be configured such that RA5 is a digital I/O SSPSR reg RC4/SDI/SDA RC5/SDO Shift Clock bit0 To enable the serial port, SSP enable bit SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, reinitialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: Peripheral OE . SS Control Enable RA5/SS/AN4 Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. Edge Select 2: If the SPI is used in Slave mode with CKE = 1, then the SS pin control must be enabled. 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TMR2 Output 2 Prescaler TCY 4, 16, 64 TRISC<3> DS39616B-page 214 Preliminary 3: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the state of the SS pin can affect the state read back from the TRISC<5> bit. The Peripheral OE signal from the SSP module into PORTC controls the state that is read back from the TRISC<5> bit (see Section 10.3 “PORTC, TRISC and LATC Registers” for information on PORTC). If ReadModify-Write instructions, such as BSF, are performed on the TRISC register while the SS pin is high, this will cause the TRISC<5> bit to be set, thus disabling the SDO output. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 18-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit7 SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 18-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit7 SDO bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF 2003 Microchip Technology Inc. Preliminary DS39616B-page 215 PIC18F2331/2431/4331/4431 FIGURE 18-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0) SCK (CKP = 1) SDO bit7 bit6 bit5 bit2 bit3 bit4 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF TABLE 18-1: Name INTCON REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 TMR0IE INTE Bit 3 Bit 2 Bit 1 Bit 0 INTF RBIF Value on: POR, BOR Value on all other Resets GIE PEIE RBIE TMR0IF PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 TRISC PORTC Data Direction Register SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register SSPCON TRISA SSPSTAT WCOL SSPOV SSPEN — — SMP CKE 1111 1111 1111 1111 CKP SSPM3 SSPM2 xxxx xxxx uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 PORTA Data Direction Register D/A 0000 000x 0000 000u P S R/W --11 1111 --11 1111 UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear. DS39616B-page 216 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 18.3 SSP I2 C Operation The SSP module in I2C mode, fully implements all slave functions, except general call support, and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the SCK/ SCL pin, which is the clock (SCL), and the SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<5:4> or TRISD<3:2> bits. The SSP module functions are enabled by setting SSP enable bit SSPEN (SSPCON<5>). FIGURE 18-5: SSP BLOCK DIAGRAM (I2C MODE) Internal Data Bus Read Write LSb Match Detect Addr Match SSPADD reg Start and Stop bit Detect Note 1: Set, RESET S, P bits (SSPSTAT reg) The SSP module has five registers for I2C operation. These are the: 2003 Microchip Technology Inc. There are certain conditions that will cause the SSP module not to give this ACK pulse. They include (either or both): b) When SSPMX = 0 in CONFIG3H: SCK/SCL is multiplexed to pin RD3, SDA/SDI is multiplexed to pin RD2, and SDO is multiplexed to pin RD1. SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) – Not directly accessible • SSP Address Register (SSPADD) When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. a) When SSPMX = 1 in CONFIG3H: SCK/SCL is multiplexed to pin RC5, SDA/SDI is multiplexed to pin RC4, and SDO is multiplexed to pin RC7. • • • • SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<5:4> or TRISD<3:2> set). The SSP module will override the input state with the output data when required (slave-transmitter). SSPSR reg MSb Selection of any I 2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate TRISC or TRISD bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. 18.3.1 Shift Clock SDI/ SDA(1) • I 2C Slave mode (7-bit address) • I 2C Slave mode (10-bit address) • I 2C Slave mode (7-bit address), with Start and Stop bit interrupts enabled to support Firmware Master mode • I 2C Slave mode (10-bit address), with Start and Stop bit interrupts enabled to support Firmware Master mode • I 2C Start and Stop bit interrupts enabled to support Firmware Master mode; Slave is Idle Additional information on SSP I 2C operation can be found in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023A). SSPBUF reg SCK/SCL(1) The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received. In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 18-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirements of the SSP module, are shown in timing parameter #100 and parameter #101. Preliminary DS39616B-page 217 PIC18F2331/2431/4331/4431 18.3.1.1 Addressing Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>), is set (interrupt is generated if enabled) on the falling edge of the ninth SCL pulse. In 10-bit Address mode, two address bytes need to be received by the slave (Figure 18-7). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. TABLE 18-2: The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. 2. 3. 4. 5. 6. 7. 8. 9. Receive first (high) byte of address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated Start condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received SSPSR → SSPBUF Generate ACK Pulse Set bit SSPIF (SSP Interrupt occurs if enabled) BF SSPOV 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 Note: 18.3.1.2 1 No No Yes Shaded cells show the conditions where the user software did not properly clear the overflow condition. Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error condition due to the user’s firmware. An SSP interrupt is generated for each data transfer byte. Flag bit, SSPIF (PIR1<3>), must be cleared in software. The SSPSTAT register is used to determine the status of the byte. DS39616B-page 218 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 18-6: Receiving Address SCL R/W = 0 ACK A7 A6 A5 A4 A3 A2 A1 SDA 1 S 2 3 4 5 6 7 9 8 Receiving Data Receiving Data ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 SSPIF (PIR1<3>) 3 4 5 6 7 8 9 1 2 3 5 4 8 7 6 9 Cleared in software BF (SSPSTAT<0>) P Bus Master terminates transfer SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. 18.3.1.3 Transmission An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 18-7). I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) FIGURE 18-7: Receiving Address SDA SCL A7 S As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin SCK/SCL should be enabled by setting bit CKP. A6 1 2 Data in sampled R/W = 1 A5 A4 A3 A2 A1 3 4 5 6 7 ACK 8 9 ACK Transmitting Data D7 1 SCL held low while CPU responds to SSPIF D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 P Cleared in software SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPBUF is written in software From SSP Interrupt Service Routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) 2003 Microchip Technology Inc. Preliminary DS39616B-page 219 PIC18F2331/2431/4331/4431 18.3.2 MASTER MODE 18.3.3 Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle and both the S and P bits are clear. In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC<5:4> or TRISD<3:2> bits. The output level is always low, irrespective of the value(s) in PORTC<5:4> or PORTD<3:2>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<4> or TRISD<2> bit. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. The following events will cause SSP interrupt flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled): • Start condition • Stop condition • Data transfer byte transmitted/received Master mode of operation can be done with either the Slave mode Idle (SSPM3:SSPM0 = 1011), or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. TABLE 18-3: MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions, allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is Idle and both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<5:4> or TRISD<3:2> ). There are two stages where this arbitration can be lost, these are: • Address Transfer • Data Transfer When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to retransfer the data at a later time. REGISTERS ASSOCIATED WITH I2C OPERATION Name Bit 7 Bit 6 INTCON GIE PEIE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u Bit 5 PIR1 (1) PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SSPADD Synchronous Serial Port (I SSPCON WCOL SSPSTAT (2) SMP 2C SSPOV SSPEN CKE(2) mode) Address Register CKP D/A P SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF (3) PORTC Data Direction Register 1111 1111 1111 1111 (3) PORTD Data Direction Register 1111 1111 1111 1111 TRISC TRISD Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by SSP module in I2C mode. Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear. 2: Maintain these bits clear in I2C mode. 3: Depending upon the setting of SSPMX in CONFIG3H, these pins are multiplexed to PORTC or PORTD. DS39616B-page 220 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules available in the PIC18F2331/2431/4331/ 4431 family of microcontrollers. EUSART is also known as a Serial Communications Interface or SCI. The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a halfduplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The EUSART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on sync break reception and 12-bit break character transmit. These make it ideally suited for use in Local Interconnect Network (LIN) bus systems. The USART can be configured in the following modes: • Asynchronous (full-duplex) with: - Auto-Wake-up on character reception - Auto-Baud calibration - 12-bit break character transmission • Synchronous – Master (half-duplex) with selectable clock polarity • Synchronous – Slave (half-duplex) with selectable clock polarity 19.1 Asynchronous Operation in Power-Managed Modes The USART may operate in Asynchronous mode, while the peripheral clocks are being provided by the internal oscillator block. This makes it possible to remove the crystal or resonator that is commonly connected as the primary clock on the OSC1 and OSC2 pins. The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz (see Table 25-6). However, this frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output back to 8 MHz. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source (see Section 3.6 “INTOSC Frequency Drift” for more information). The other method adjusts the value in the baud rate generator. There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. In order to configure pins RC6/TX/CK/SS and RC7/RX/ DT/SDO as the Universal Synchronous Asynchronous Receiver Transmitter: • SPEN (RCSTA<7>) bit must be set ( = 1), • TRISC<6> bit must be set ( = 1), and • TRISC<1> bit must be set ( = 1). Note: The USART control will automatically reconfigure the pin from input to output as needed. The operation of the enhanced USART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCTL) These are detailed in on the following pages in Register 19-1, Register 19-2 and Register 19-3, respectively. 2003 Microchip Technology Inc. Preliminary DS39616B-page 221 PIC18F2331/2431/4331/4431 REGISTER 19-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC R/W-0 SENDB bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 SREN/CREN overrides TXEN in Sync mode. bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. Legend: DS39616B-page 222 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 19-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 SPEN bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave: Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 223 PIC18F2331/2431/4331/4431 REGISTER 19-3: BAUDCTL: BAUD RATE CONTROL REGISTER U-0 R-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 — RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 RCIDL: Receive Operation Idle Status bit 1 = Receiver is Idle 0 = Receive in progress bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: Unused in this mode Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level bit 3 BRG16: 16-bit Baud Rate Register Enable bit 1 = 16-bit baud rate generator – SPBRGH and SPBRG 0 = 8-bit baud rate generator – SPBRG only (Compatible mode), SPBRGH value ignored bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = USART will continue to sample the RX pin – interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode Legend: DS39616B-page 224 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary x = Bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.2 19.2.1 USART Baud Rate Generator (BRG) The BRG is a dedicated 8-bit or 16-bit generator, that supports both the Asynchronous and Synchronous modes of the USART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 also control the baud rate. In Synchronous mode, bit BRGH is ignored. Table 19-1 shows the formula for computation of the baud rate for different USART modes, which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 19-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 19-1. Typical baud rates and error values for the various asynchronous modes are shown in Table 19-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. POWER-MANAGED MODE OPERATION The system clock is used to generate the desired baud rate; however, when a power-managed mode is entered, the clock source may be operating at a different frequency than in PRI_RUN mode. In Sleep mode, no clocks are present and in PRI_IDLE, the primary clock source continues to provide clocks to the baud rate generator; however, in other powermanaged modes, the clock frequency will probably change. This may require the value in SPBRG to be adjusted. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit and make sure that the receive operation is Idle before changing the system clock. 19.2.2 SAMPLING The data on the RC7/RX/DT/SDO pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. TABLE 19-1: BAUD RATE FORMULAS Configuration Bits BRG/USART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 FOSC/[16 (n+1)] FOSC/[4 (n+1)] Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair 2003 Microchip Technology Inc. Preliminary DS39616B-page 225 PIC18F2331/2431/4331/4431 EXAMPLE 19-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate= FOSC / (64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((Fosc / Desired Baud Rate)/64) – 1 = ((16000000 / 9600) / 64) – 1 = [25.042] = 25 Calculated Baud Rate=16000000 / (64 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) / Desired Baud Rate = (9615 – 9600) / 9600 = 0.16% TABLE 19-2: Name REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 -010 0000 -010 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x — RCIDL — SCKP BRG16 — WUE ABDEN BAUDCTL -1-1 0-00 -1-1 0-00 Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG. SPBRGH TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — — — 1.221 2.441 1.73 255 Actual Rate (K) % Error 0.3 — — 1.2 — 2.4 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — — — 1.73 255 1.202 2.404 0.16 129 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error — — — — 0.16 129 1201 -0.16 103 2.404 0.16 64 2403 -0.16 51 SPBRG value SPBRG value (decimal) 9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9615 -0.16 12 19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — — 57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — — 115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 207 300 -0.16 0.16 51 1201 Actual Rate (K) % Error 0.3 0.300 0.16 1.2 1.202 SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error 103 300 -0.16 51 -0.16 25 1201 -0.16 12 SPBRG value SPBRG value (decimal) 2.4 2.404 0.16 25 2403 -0.16 12 — — — 9.6 8.929 -6.99 6 — — — — — — 19.2 20.833 8.51 2 — — — — — — 57.6 62.500 8.51 0 — — — — — — 115.2 62.500 -45.75 0 — — — — — — DS39616B-page 226 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error — — — 1.73 255 9.615 Actual Rate (K) % Error 2.4 — — 9.6 9.766 SPBRG value SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error — 2.441 1.73 0.16 129 9.615 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error SPBRG value 255 2403 -0.16 207 0.16 64 9615 -0.16 51 25 (decimal) 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) % Error FOSC = 2.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate (K) % Error SPBRG value (decimal) 0.3 — — — — — — 300 -0.16 207 1.2 1.202 0.16 207 1201 -0.16 103 1201 -0.16 51 2.4 2.404 0.16 103 2403 -0.16 51 2403 -0.16 25 9.6 9.615 0.16 25 9615 -0.16 12 — — — 19.2 19.231 0.16 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 8332 0.300 0.02 0.02 2082 1.200 2.402 0.06 1040 Actual Rate (K) % Error 0.3 0.300 0.00 1.2 1.200 2.4 SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 4165 0.300 0.02 -0.03 1041 1.200 2.399 -0.03 520 SPBRG value FOSC = 8.000 MHz (decimal) Actual Rate (K) % Error 2082 300 -0.04 -0.03 520 1201 -0.16 415 2.404 0.16 259 2403 -0.16 207 SPBRG value SPBRG value (decimal) 1665 9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9615 -0.16 51 19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19230 -0.16 25 57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55555 3.55 8 115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error (decimal) % Error 832 300 -0.16 415 300 -0.16 0.16 207 1201 207 -0.16 103 1201 -0.16 51 2.404 0.16 103 9.615 0.16 25 2403 -0.16 51 2403 -0.16 25 9615 -0.16 12 — — 19.2 19.231 0.16 — 12 — — — — — — 57.6 62.500 8.51 3 — — — — — — 115.2 125.000 8.51 1 — — — — — — % Error 0.3 0.300 0.04 1.2 1.202 2.4 9.6 SPBRG value 2003 Microchip Technology Inc. SPBRG value FOSC = 1.000 MHz Actual Rate (K) Actual Rate (K) Preliminary SPBRG value (decimal) DS39616B-page 227 PIC18F2331/2431/4331/4431 TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) % Error 0.3 0.300 0.00 1.2 1.200 0.00 FOSC = 20.000 MHz (decimal) Actual Rate (K) % Error 33332 0.300 0.00 8332 1.200 SPBRG value SPBRG value FOSC = 10.000 MHz (decimal) Actual Rate (K) % Error 16665 0.300 0.00 0.02 4165 1.200 FOSC = 8.000 MHz SPBRG value (decimal) Actual Rate (K) % Error SPBRG value 8332 300 -0.01 6665 0.02 2082 1200 -0.04 1665 832 (decimal) 2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2400 -0.04 9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9615 -0.16 207 19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19230 -0.16 103 57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57142 0.79 34 115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117647 -2.12 16 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) 0.3 1.2 FOSC = 4.000 MHz Actual Rate (K) % Error 0.300 1.200 0.01 0.04 FOSC = 2.000 MHz (decimal) Actual Rate (K) % Error 3332 832 300 1201 SPBRG value FOSC = 1.000 MHz (decimal) Actual Rate (K) % Error -0.04 -0.16 1665 415 300 1201 -0.04 -0.16 832 207 SPBRG value SPBRG value (decimal) 2.4 2.404 0.16 415 2403 -0.16 207 2403 -0.16 103 9.6 9.615 0.16 103 9615 -0.16 51 9615 -0.16 25 19.2 19.231 0.16 51 19230 -0.16 25 19230 -0.16 12 57.6 58.824 2.12 16 55555 3.55 8 — — — 115.2 111.111 -3.55 8 — — — — — — DS39616B-page 228 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.2.3 AUTO-BAUD RATE DETECT The enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 19-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is selfaveraging. carry occurred for 8-bit modes, by checking for 00h in the SPBRGH register. Refer to Table 19-4 for counter clock rates to the BRG. While the ABD sequence takes place, the USART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud rate detection will occur on the byte following the Break character (see Section 19.3.4 “Auto-Wake-up on SYNC BREAK Character”). In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Detect must receive a byte with the value 55h (ASCII “U”, which is also the LIN bus Sync character), in order to calculate the proper bit rate. The measurement takes over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin, or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG registers. Once the 5th edge is seen (should correspond to the Stop bit), the ABDEN bit is automatically cleared. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and USART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. TABLE 19-4: While calibrating the baud rate period, the BRG registers are clocked at 1/8th the pre-configured clock rate. Note that the BRG clock will be configured by the BRG16 and BRGH bits. Independent of the BRG16 bit setting, both the SPBRG and SPBRGH will be used as a 16-bit counter. This allows the user to verify that no FIGURE 19-1: BRG16 BRGH BRG Counter Clock 0 0 FOSC/512 0 1 FOSC/256 1 0 FOSC/128 1 1 FOSC/32 Note: During the ABD sequence, SPBRG and SPBRGH are both used as a 16-bit counter, independent of BRG16 setting. AUTOMATIC BAUD RATE CALCULATION XXXXh BRG Value BRG COUNTER CLOCK RATES RX pin 0000h 001Ch Start Edge #1 Bit 1 Bit 0 Edge #2 Bit 3 Bit 2 Edge #3 Bit 5 Bit 4 Edge #4 Bit 7 Bit 6 Edge #5 Stop Bit BRG Clock Auto-Cleared Set by User ABDEN bit RCIF bit (Interrupt) Read RCREG SPBRG SPBRGH Note 1: XXXXh 1Ch XXXXh 00h The ABD sequence requires the USART module to be configured in Asynchronous mode and WUE = 0. 2003 Microchip Technology Inc. Preliminary DS39616B-page 229 PIC18F2331/2431/4331/4431 19.3 USART Asynchronous Mode The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the USART uses standard non-return-to-zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART’s transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCTL<3>). Parity is not supported by the hardware, but can be implemented in software and stored as the 9th data bit. Asynchronous mode is available in all low-power modes; it is available in Sleep mode only when AutoWake-up on Sync Break is enabled. When in PRI_IDLE mode, no changes to the baud rate generator values are required; however, other low-power mode clocks may operate at another frequency than the primary clock. Therefore, the baud rate generator values may need to be adjusted. becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a readonly bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. To set up an Asynchronous Transmission: 1. 2. 3. 4. When operating in Asynchronous mode, the USART module consists of the following important elements: 5. • • • • • • • 6. Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-bit Break Character Transmit Auto-Baud Rate Detection 19.3.1 7. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in Figure 19-2. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. Flag bit TXIF is not cleared immediately upon loading the transmit buffer register TXREG. TXIF DS39616B-page 230 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 19-2: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG Register TXIE 8 MSb RC6/TX/CK/SS pin LSb • • • (8) Pin Buffer and Control 0 TSR Register Interrupt Baud Rate CLK TXEN TRMT BRG16 SPBRGH SPEN SPBRG TX9 Baud Rate Generator TX9D FIGURE 19-3: ASYNCHRONOUS TRANSMISSION Write to TXREG BRG Output (Shift Clock) Word 1 RC6/TX/CK/SS (pin) Start bit FIGURE 19-4: bit 1 bit 7/8 Stop bit Word 1 TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) bit 0 1 TCY Word 1 Transmit Shift Reg ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG BRG Output (Shift Clock) Word 1 RC6/TX/CK/SS (pin) TXIF bit (Interrupt Reg. Flag) Word 2 Start bit bit 0 1 TCY bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. 2003 Microchip Technology Inc. Preliminary DS39616B-page 231 PIC18F2331/2431/4331/4431 TABLE 19-5: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 000u GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 INTCON IPR1 RCSTA TXREG TXSTA BAUDCTL USART Transmit Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Transmission. DS39616B-page 232 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.3.2 USART ASYNCHRONOUS RECEIVER 19.3.3 The receiver block diagram is shown in Figure 19-5. The data is received on the RC7/RX/DT/SDO pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. To set up an Asynchronous Reception: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 19-5: SETTING UP 9-BIT MODE WITH ADDRESS DETECT USART RECEIVE BLOCK DIAGRAM CREN OERR FERR x64 Baud Rate CLK BRG16 SPBRGH SPBRG Baud Rate Generator ÷ 64 or ÷ 16 or ÷4 RSR Register MSb Stop (8) 7 • • • 1 LSb 0 Start RX9 RC7/RX/DT/SDO Pin Buffer and Control Data Recovery RX9D RCREG Register FIFO SPEN 8 Interrupt RCIF Data Bus RCIE 2003 Microchip Technology Inc. Preliminary DS39616B-page 233 PIC18F2331/2431/4331/4431 To set up an Asynchronous Transmission: 1. 2. 3. 4. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (see Section 19.2 “USART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). 5. 6. 7. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. FIGURE 19-6: ASYNCHRONOUS RECEPTION Start bit RX (pin) bit0 bit1 bit7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit7/8 bit0 Start bit bit7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG Stop bit RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. TABLE 19-6: Name INTCON REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x IPR1 RCSTA RCREG TXSTA BAUDCTL USART Receive Register 0000 0000 0000 0000 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception. DS39616B-page 234 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.3.4 AUTO-WAKE-UP ON SYNC BREAK CHARACTER During Sleep mode, all clocks to the USART are suspended. Because of this, the baud rate generator is inactive and a proper byte reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line, while the USART is operating in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit (BAUDCTL<1>). Once set, the typical receive sequence on RX/DT is disabled, and the USART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN protocol.) Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 19-7), and asynchronously if the device is in Sleep mode (Figure 19-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-tohigh transition is observed on the RX line, following the wake-up event. At this point, the USART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over. 19.3.4.1 Special Considerations Using Auto-Wake-up Since Auto-Wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false end-ofcharacter and cause data or framing errors. To work FIGURE 19-7: properly, therefore, the initial character in the transmission must be all ‘0’s. This can be 00h (8 bytes) for standard RS-232 devices, or 000h (12 bits) for LIN bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer startup intervals (i.e., LP, XT or HS/PLL mode). The sync break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the USART. 19.3.4.2 Special Considerations Using the WUE Bit The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the USART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/ DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto-Cleared Bit Set by User WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The USART remains in Idle while the WUE bit is set. FIGURE 19-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto-Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Cleared due to User Read of RCREG Sleep Ends Sleep Command Executed Note 1: 2: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The USART remains in Idle while the WUE bit is set. 2003 Microchip Technology Inc. Preliminary DS39616B-page 235 PIC18F2331/2431/4331/4431 19.3.5 BREAK CHARACTER SEQUENCE The enhanced USART module has the capability of sending the special break character sequences that are required by the LIN bus standard. The break character transmit consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. The frame break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set, while the transmit shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the break character (typically, the sync character in the LIN specification). Note that the data value written to the TXREG for the break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 19-9 for the timing of the break character sequence. 19.3.5.1 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. Configure the USART for the desired mode. Set the TXEN and SENDB bits to setup the break character. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. After the break has been sent, the SENDB bit is reset by hardware. The sync character now transmits in the Pre-Configured mode. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. 19.3.6 RECEIVING A BREAK CHARACTER The enhanced USART module can receive a break character in two ways. The first method forces to configure the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 19.3.4 “Auto-Wake-up on SYNC BREAK Character”. By enabling this feature, the USART will sample the next two transitions on RX/ DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a break character, the user will typically want to enable the auto-baud rate detect feature. For both methods, the user can set the ABD bit before placing the USART in its Sleep mode. FIGURE 19-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start Bit Bit 0 Bit 1 Bit 11 Stop Bit Break TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto-Cleared SENDB (Transmit Shift Reg. Empty Flag) DS39616B-page 236 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.4 USART Synchronous Master Mode Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/ CK/SS and RC7/RX/DT/SDO I/O pins to CK (clock) and DT (data) lines, respectively. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user must poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCTL<5>); setting SCKP sets the Idle state on CK as high, while clearing the bit, sets the Idle state low. This option is provided to support Microwire® devices with this module. 19.4.1 To set up a Synchronous Master Transmission: 1. USART SYNCHRONOUS MASTER TRANSMISSION 2. The USART transmitter block diagram is shown in Figure 19-2. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). 3. 4. 5. 6. 7. 8. FIGURE 19-10: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT/ SDO pin bit 0 bit 1 bit 2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 Write Word 1 bit 0 bit 1 bit 7 Word 2 Word 1 RC6/TX/CK/ SS pin (SCKP = 0) RC6/TX/CK/ SS pin (SCKP = 1) Write to TXREG Reg Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: '1' '1' Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words. 2003 Microchip Technology Inc. Preliminary DS39616B-page 237 PIC18F2331/2431/4331/4431 FIGURE 19-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT/SDO pin bit0 bit2 bit1 bit6 bit7 RC6/TX/CK/SS pin Write to TXREG reg TXIF bit TRMT bit TXEN bit TABLE 19-7: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 GIE/GIEH PEIE/GIEL TMR0IE Bit 4 Bit 3 Bit 2 Bit 1 Value on POR, BOR Bit 0 Value on all other Resets INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -000 -000 -000 -000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 IPR1 RCSTA TXREG TXSTA BAUDCTL USART Transmit Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission. DS39616B-page 238 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.4.2 USART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT/SDO pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. FIGURE 19-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT/SDO pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK/SS pin (SCKP = 0) RC6/TX/CK/SS pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. 2003 Microchip Technology Inc. Preliminary DS39616B-page 239 PIC18F2331/2431/4331/4431 TABLE 19-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 INTCON RCSTA RCREG TXSTA BAUDCTL GIE/GIEH PEIE/GIEL USART Receive Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for Synchronous Master Reception. DS39616B-page 240 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 19.5 USART Synchronous Slave Mode To set up a Synchronous Slave Transmission: 1. Synchronous Slave mode is entered by clearing bit CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the RC6/TX/CK/SS pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode. 19.5.1 Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 2. 3. 4. 5. USART SYNCHRONOUS SLAVE TRANSMIT 6. The operation of the Synchronous Master and Slave modes are identical, except in the case of the Sleep mode. 7. 8. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) e) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector. TABLE 19-9: Name INTCON REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF -000 -000 -000 -000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 -000 -000 -000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -000 -000 -000 -000 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 RCSTA TXREG TXSTA BAUDCTL USART Transmit Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission. 2003 Microchip Technology Inc. Preliminary DS39616B-page 241 PIC18F2331/2431/4331/4431 19.5.2 USART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a “don't care” in Slave mode. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 2. 3. 4. 5. If receive is enabled by setting the CREN bit prior to entering Sleep or any idle mode, then a word may be received while in this Low-Power mode. Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from Low-Power mode. If the global interrupt is enabled, the program will branch to the interrupt vector. 6. 7. 8. 9. TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 000u GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x PIR1 — ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 — ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 — ADIP RCIP TXIP — CCP1IP TMR2IP TMR1IP -111 -111 -111 -111 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x INTCON RCSTA RCREG TXSTA BAUDCTL USART Receive Register 0000 0000 0000 0000 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 — RCIDL — SCKP BRG16 — WUE ABDEN -1-1 0-00 -1-1 0-00 SPBRGH Baud Rate Generator Register, High Byte 0000 0000 0000 0000 SPBRG Baud Rate Generator Register, Low Byte 0000 0000 0000 0000 Legend: x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. DS39616B-page 242 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.0 10-BIT HIGH-SPEED ANALOGTO-DIGITAL CONVERTER (A/D) MODULE The high-speed Analog-to-Digital (A/D) Converter module allows conversion of an analog signal to a corresponding 10-bit digital number. The A/D module supports up to 5 input channels on PIC18F2X31 devices, and up to 9 channels on the PIC18F4X31 devices. This high-speed 10-bit A/D module offers the following features: • Up to 200K samples per second • Two sample and hold inputs for dual-channel simultaneous sampling • Selectable simultaneous or sequential sampling modes • 4-word data buffer for A/D results • Selectable data acquisition timing • Selectable A/D event trigger • Operation in Sleep using internal oscillator 2003 Microchip Technology Inc. These features lend themselves to many applications including motor control, sensor interfacing, data acquisition and process control. In many cases, these features will reduce the software overhead associated with standard A/D modules. The module has 9 registers: • • • • • • • • • A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) A/D Control Register 3 (ADCON3) A/D Channel Select Register (ADCHS) Analog I/O Select Register 0 (ANSEL0) Analog I/O Select Register 1 (ANSEL1) Preliminary DS39616B-page 243 PIC18F2331/2431/4331/4431 REGISTER 20-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 — — R/W-0 ACONV R/W-0 ACSCH R/W-0 ACMOD1 R/W-0 R/W-0 ACMOD0 GO/DONE bit 7 R/W-0 ADON bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 ACONV: Auto-Conversion Continuous Loop or Single-shot Mode Select bit 1 = Continuous Loop mode Enabled 0 = Single-shot mode Enabled bit 4 ACSCH: Auto-Conversion Single or Multi-Channel mode bit 1 = Multi-Channel mode Enabled, Single Channel mode Disabled 0 = Single Channel mode Enabled, Multi-Channel mode Disabled bit 3-2 ACMOD: Auto-Conversion mode Sequence Select bits If ACSCH = 1: 00 =Sequential Mode1 (SEQM1). Two samples are taken in sequence: 1st sample: Group A 2nd sample: Group B 01 =Sequential Mode2 (SEQM2). Four samples are taken in sequence: 1st sample: Group A 2nd sample: Group B 3rd sample: Group C 4th sample: Group D 10 =Simultaneous Mode1 (STNM1). Two samples are taken simultaneously: 1st sample: Group A and Group B 11 =Simultaneous Mode2 (STNM2). Two samples are taken simultaneously: 1st sample: Group A and Group B 2nd sample: Group C and Group D If ACSCH = 0, Auto-Conversion Single Channel Sequence mode enabled: 00 =Single Ch Mode1 (SCM1). Group A is taken and converted 01 =Single Ch Mode2 (SCM2). Group B is taken and converted 10 =Single Ch Mode3 (SCM3). Group C is taken and converted 11 =Single Ch Mode4 (SCM4). Group D is taken and converted bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts the A/D conversion cycle. If AutoConversion Single-shot mode is enabled (ACONV = 0), this bit is automatically cleared by hardware when the A/D conversion (single or multi-channel depending on ACMOD settings) has completed. If Auto-Conversion Continuous Loop mode is enabled (ACONV = 1), this bit remains set after the user/trigger has set it (continuous conversions). It may be cleared manually by the user to stop the conversions. 0 = A/D conversion or multiple conversions completed/not in progress bit 0 ADON: A/D On bit 1 = A/D converter module is enabled (after brief power-up delay, starts continuous sampling) 0 = A/D converter module is disabled Note: Group A, B, C, D refer to the ADCHS register. Legend: DS39616B-page 244 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = bit is set ‘0’ = bit is cleared Preliminary x = bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 20-2: ADCON1: A/D CONTROL REGISTER 1 R/W-0 VCFG1 bit 7 R/W-0 VCFG0 U-0 — R/W-0 FIFOEN R-0 BFEMT R-0 BFOVFL R-0 ADPNT1 R-0 ADPNT0 bit 0 bit 7-6 VCFG<1:0>: A/D VREF+ and A/D VREF- Source Selection bits 00 =VREF+ = AVDD, VREF- = AVSS, (AN2 and AN3 are Analog inputs or Digital I/O) 01 =VREF+ = External VREF+, VREF- = AVSS, (AN2 is an Analog input or Digital I/O) 10 =VREF+ = AVDD, VREF- = External VREF-, (AN3 is an Analog input or Digital I/O) 11 =VREF+ = External VREF-, VREF- = External VREFbit 5 Unimplemented: Read as ‘0’ bit 4 FIFOEN: FIFO Buffer Enable bit 1 = FIFO is enabled 0 = FIFO is disabled bit 3 BFEMT: Buffer Empty bit 1 = FIFO is empty 0 = FIFO is not empty (at least one of four locations has unread A/D result data) bit 2 BFOVFL: Buffer Overflow bit 1 = A/D result has overwritten a buffer location that has unread data 0 = A/D result has not overflowed bit 1-0 ADPNT<1:0>: Buffer Read Pointer Locations bits Designates the location to be read next. 00 = Buffer address 0 01 = Buffer address 1 10 = Buffer address 2 11 = Buffer address 3 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = bit is set ‘0’ = bit is cleared 2003 Microchip Technology Inc. Preliminary x = bit is unknown DS39616B-page 245 PIC18F2331/2431/4331/4431 REGISTER 20-3: ADCON2 – A/D CONTROL REGISTER 2 R/W-0 ADFM bit 7 R/W-0 ACQT3 R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified bit 6-3 ACQT<3:0>: A/D Acquisition Time Select bits 0000 = No Delay(1) (Conversion starts immediately when GO/DONE is set) 0001 = 2 TAD 0010 = 4 TAD 0011 = 6 TAD 0100 = 8 TAD 0101 = 10 TAD 0110 = 12 TAD 0111 = 16 TAD 1000 = 20 TAD 1001 = 24 TAD 1010 = 28 TAD 1011 = 32 TAD 1100 = 36 TAD 1101 = 40 TAD 1110 = 48 TAD 1111 = 64 TAD bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC/4(2) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (Internal A/D RC Oscillator) R/W-0 ADCS0 bit 0 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before sampling/ conversion starts. 2: Due to an increased frequency of the internal A/D RC oscillator, FRC/4 provides clock frequencies compatible with previous A/D modules. 3: In sequential mode TACQ should be 12 TAD or greater. Legend: DS39616B-page 246 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = bit is set ‘0’ = bit is cleared Preliminary x = bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 20-4: ADCON3: A/D CONTROL REGISTER 3 R/W-0 ADRS1 bit 7 R/W-0 ADRS0 U-0 — R/W-0 SSRC4 R/W-0 SSRC3 R/W-0 SSRC2 R/W-0 SSRC1 R/W-0 SSRC0 bit 0 bit 7-6 ADRS<1:0>: A/D Result Buffer Depth Interrupt Select Control bits for Continuous Loop mode The ADRS bits are ignored in Single-shot mode. 00 =Interrupt is generated when each word is written to the buffer 01 =Interrupt is generated when the 2nd & 4th words are written to the buffer 10 =Interrupt is generated when the 4th word is written to the buffer 11 =Unimplemented bit 5 Unimplemented: Read as ‘0’ bit 4:0 SSRCx<4:0>: A/D Trigger Source Select bits 00000 =All triggers disabled xxxx1 =External interrupt RC3/INT0 starts A/D sequence xxx1x =Timer5 starts A/D sequence xx1xx =Input Capture 1 (IC1) starts A/D sequence x1xxx =CCP2 compare match starts A/D sequence 1xxxx =Power Control PWM module rising edge starts A/D sequence Note 1: SSRCx<4:0> bits can be set such that any of the triggers will start conversion (e.g. SSRCx<4:0)> = 00101, will trigger the A/D conversion sequence when RC3/INT0 or Input Capture 1 event occurs). Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = bit is set ‘0’ = bit is cleared 2003 Microchip Technology Inc. Preliminary x = bit is unknown DS39616B-page 247 PIC18F2331/2431/4331/4431 REGISTER 20-5: ADCHS: A/D CHANNEL SELECT REGISTER R/W-0 GDSEL1 bit 7 R/W-0 GDSEL0 R/W-0 GBSEL1 R/W-0 GBSEL0 bit 7-6 GDSEL1:GDSEL0: Group D Select bits S/H-2 positive input 00 =AN3 01 =AN7(1) 1x =Reserved bit 5-4 GBSEL1:GBSEL0: Group B Select bits S/H-2 positive input 00 =AN1 01 =AN5(1) 1x =Reserved bit 3-2 GCSEL1:GCSEL0: Group C Select bits S/H-1 positive input 00 =AN2 01 =AN6(1) 1x =Reserved bit 1-0 GASEL1:GASEL0: Group A Select bits S/H-1 positive input 00 =AN0 01 =AN4 10 =AN8(1) 11 =Reserved R/W-0 R/W-0 R/W-0 GCSEL1 GCSEL0 GASEL1 R/W-0 GASEL0 bit 0 Note 1: AN5 through AN8 are available only in PIC18F4X31 devices. Legend: DS39616B-page 248 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = bit is set ‘0’ = bit is cleared Preliminary x = bit is unknown 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 20-6: ANSEL0: ANALOG SELECT REGISTER 0(1) R/W-1 ANS7(2) bit 7 bit 7-0 R/W-1 ANS6(2) R/W-1 ANS5(2) R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0 ANS<7:0>: Analog Input Function Select bits Correspond to pins AN<7:0> 1 = Analog Input 0 = Digital I/O Note 1: Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should be set for an input and cleared for an output (analog or digital). The ANSx bits directly correspond to the ANx pins (e.g., ANS0 = AN0, ANS1 = AN1, etc.) Unused ANSx bits are to be read as ‘0’. 2: ANS7 through ANS5 are available only on PIC18F4X31 devices. Legend: REGISTER 20-7: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown ANSEL1: ANALOG SELECT REGISTER 1(1) U-0 — bit 15 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-1 ANS8(2) bit 8 bit 15-9 Unimplemented: Read as ‘0’ bit 8 ANS8: Analog Input Function Select bit 1 = Analog Input 0 = Digital I/O Note 1: Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should be set for an input and cleared for an output (analog or digital). The ANSx bits directly correspond to the ANx pins (e.g., ANS8 = AN8, ANS9 = AN9, etc.) Unused ANSx bits are to be read as ‘0’. 2: ANS8 is available only on PIC18F4X31 devices. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at Reset ‘1’ = bit is set ‘0’ = bit is cleared 2003 Microchip Technology Inc. Preliminary x = bit is unknown DS39616B-page 249 PIC18F2331/2431/4331/4431 The A/D channels are grouped into four sets of 2 or 3 channels. For the PIC18F2X31 devices, AN0 and AN4 are in Group A, AN1 is in Group B, AN2 is in Group C and AN3 is in Group D. For the PIC18F4X31 devices, AN0, AN4 and AN8 are in Group A, AN1 and AN5 are in Group B, AN2 and AN6 are in Group C and AN3 and AN7 are in Group D. The selected channel in each group is selected by configuring the A/D Channel Select Register, ADCHS. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D converter can individually be configured as an analog input or digital I/O using the ANSEL0 and ANSEL1 registers. The ADRESH and ADRESL registers contain the value in the result buffer pointed to by ADPNT<1:0> (ADCON1<1:0>). The result buffer is a 4-deep circular buffer that has an empty status bit, BEMT (ADCON1<3>), and an overflow status bit, BOVFL (ADCON1<2>). The analog voltage reference is software selectable to either the device’s positive and negative analog supply voltage (AVDD and AVSS), or the voltage level on the RA3/AN3/VREF+/CAP2/QEA and RA2/AN2/VREF-/ CAP1/INDX, or some combination of supply and external sources. Register ADCON1 controls the voltage reference settings. FIGURE 20-1: A/D BLOCK DIAGRAM VCFG<1:0> AVDD AVSS VREF+ VREF- VREFL VREFH ADC AN0 AN4 ADRESH, ADRESL AN8(1) 10 Analog Mux AN2/VREFAN6(1) MUX ACMOD, GxSEL<1:0> 00 01 10 11 1 2 3 4 S/H-1 + S/H - ADPNT<1:0> 4x10-bit FIFO AVSS ACONV ACSCM ACMOD AN1 AN5(1) Analog Mux AN3/VREF+ S/H-2 AN7(1) + ACMOD, GxSEL<1:0> S/H AVSS Seq. Cntrl. Note 1: AN5 through AN8 are available only on PIC18F4X31 devices. DS39616B-page 250 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.1 Configuring the A/D Converter ACMOD<1:0> bits (ADCON0<3:2>). In addition, the A/D channels are divided into four groups as defined in the ADCHS register. Table 20-1 shows the sequence configurations as controlled by ACSCH and ACMOD<1:0>. The A/D converter has two types of conversion, two modes of operation and eight different sequencing modes. These features are controlled by the ACONV bit (ADCON0<5>), ACSH bit (ADCON0<4>) and TABLE 20-1: AUTO-CONVERSION SEQUENCE CONFIGURATIONS Mode ACSCH ACMOD Multi-Channel Sequential Mode1 (SEQM1) Multi-Channel Sequential Mode2 (SEQM2) Multi-Channel Simultaneous Mode1 (STNM1) Multi-Channel Simultaneous Mode2 (STNM2) 1 00 1 01 1 10 1 11 Single Channel Mode1 (SCM1) Single Channel Mode2 (SCM2) Single Channel Mode3 (SCM3) Single Channel Mode4 (SCM4) 0 0 0 0 00 01 10 11 20.1.1 CONVERSION TYPE Description Group A and B are sampled and converted sequentially Group A, B, C and D are sampled and converted sequentially Group A and B are sampled simultaneously and converted sequentially Group A and B are sampled simultaneously, then converted sequentially. Then, Group C and D are sampled simultaneously, then converted sequentially. Group A is sampled and converted Group B is sampled and converted Group C is sampled and converted Group D is sampled and converted 20.1.2 Two types of conversions exist in the high-speed 10-bit A/D converter module that are selected using the ACONV bit. Single-shot mode allows a single conversion or sequence to be when ACONV = ‘0’. At the end of the sequence, the GO/DONE bit will be automatically cleared and the interrupt flag, ADIF, will be set. When using Single-shot mode and configured for Simultaneous mode, STNM2, acquisition time must be used to ensure proper conversion of the analog input signals. CONVERSION MODE The ACSCH bit (ADCON0<4>) controls how many channels are used in the configured sequence. When clear, the A/D is configured for single channel conversion and will convert the group selected by ACMOD<1:0> and channel selected by GxSEL<1:0> (ADCHS). When ACSCH = ‘1’, the A/D is configured for multiple channel conversion and the sequence is defined by ACMOD<1:0>. Continuous Loop mode allows the defined sequence to be executed in a continuous loop when ACONV = ‘1’. In this mode, either the user can trigger the start of conversion by setting the GO/DONE bit or one of the A/D triggers can start the conversion. The interrupt flag ADIF is set based on the configuration of the bits ADRS<1:0> (ADCON3<7:6>). In simultaneous modes, STNM1 and STNM2, acquisition time must be configured to ensure proper conversion of the analog input signals. 2003 Microchip Technology Inc. Preliminary DS39616B-page 251 PIC18F2331/2431/4331/4431 20.1.3 CONVERSION SEQUENCING 20.1.5 The ACMOD<1:0> bits control the sequencing of the A/D conversions. When ACSCH = 0, the A/D is configured to sample and convert a single channel. The ACMOD bits select which group to perform the conversions and the GxSEL<1:0> bits select which channel in the group is to be converted. If Single-shot mode is enabled, the A/D interrupt flag will be set after the channel is converted. If Continuous Loop mode is enabled, the A/D interrupt flag will be set according to the ADRS<1:0> bits. When ACSHC = 1, multiple channel sequencing is enabled and two sub-modes can be selected. The first mode is Sequential mode with two settings. The first setting is called SEQM1 and first samples and converts the selected Group A channel and then samples and converts the selected Group B channel. The second mode is called SEQM2, and it samples and converts a Group A channel, Group B channel, Group C channel and finally a Group D channel. The second multiple channel sequencing sub-mode is Simultaneous Sampling mode. In this mode, there are also two settings. The first setting is called STNM1 and uses the two sample and hold circuits on the A/D module. The selected Group A and B channels are simultaneously sampled and then the Group A channel is converted followed by the conversion of the Group B channel. The second setting is called STNM2 and starts the same as STNM1 but follows it with a simultaneous sample of Group C and D channels. The A/D module will then convert the Group C channel followed by the Group D channel. 20.1.4 • • • • • The following steps should be followed to initialize the A/D module: 1. 2. 3. 4. TRIGGERING A/D CONVERSIONS The PIC18F2331/2431/4331/4431 devices are capable of triggering conversions from many different sources. The same method used by all other microcontrollers of setting the GO/DONE bit still works. The other trigger sources are: 5. RC3/INT0 pin Timer5 Overflow Input Capture 1 (IC1) CCP2 Compare Match Power Control PWM rising edge These triggers are enabled using the SSRC<4:0> bits (ADCON3<4:0>). Any combination of the five sources can trigger a conversion by simply setting the corresponding bit in ADCON3. When the trigger occurs, the GO/DONE bit is automatically set by the hardware and then cleared once the conversion completes. DS39616B-page 252 A/D MODULE INITIALIZATION STEPS 6. Preliminary Configure the A/D module: a) Configure analog pins, voltage reference and digital I/O b) Select A/D input channels c) Select A/D Auto-conversion mode (Single-shot or Continuous Loop) d) Select A/D conversion clock e) Select A/D conversion trigger Configure A/D interrupt (if required): a) Set GIE bit b) Set PEIE bit c) Set ADIE bit d) Clear ADIF bit e) Select A/D trigger setting f) Select A/D interrupt priority Turn On ADC: a) Set ADON bit in ADCON0 register b) Wait the required power-up setup time, about 5-10 µs Start sample/conversion sequence: a) Sample for a minimum of 2TAD and start conversion by setting the GO/DONE bit. The GO/DONE bit is set by the user in software or by the module if initiated by a trigger. b) If TACQ is assigned a value (multiple of TAD), then setting the GO/DONE bit starts a sample period of the TACQ value, then starts a conversion. Wait for A/D conversion/conversions to complete using one of the following options: a) Poll for the GO/DONE bit to be cleared if in Single-shot mode. b) Wait for the A/D interrupt flag (ADIF) to be set. c) Poll for the BFEMT bit to be cleared to signify that at least the first conversion has completed. Read A/D results, clear ADIF flag, reconfigure trigger. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.2 A/D Result Buffer 20.3 The A/D module has a 4-level result buffer with an address range of 0 to 3, enabled by setting the FIFOEN bit in the ADCON1 register. This buffer is implemented in a circular fashion where the A/D result is stored in one location and the address is incremented. If the address is greater than 3, the pointer is wrapped back around to 0. The result buffer has a buffer empty flag, BEMT, indicating when any data is in the buffer. It also has an overflow flag, BOVFL, which indicates when a new sample has overwritten a location that was not previously read. Associated with the buffer is a pointer to the address for the next read operation. The ADPNT<1:0> bits configure the address for the next read operation. These bits are read-only. The Result Buffer also has a configurable interrupt trigger level that is configured by the ADRS<1:0> bits. The user has three selections: interrupt flag set on every write to the buffer, interrupt on every second write to the buffer, or interrupt on every fourth write to the buffer. ADPNT<1:0> is reset to ‘00’ every time a conversion sequence is started (either by setting the GO/DONE bit, or on a trigger). Note: When right justified, reading ADRESL increments ADPNT. When left justified, reading ADRESH increments ADPNT. A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 20-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 kΩ. After the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 20-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 20-1 shows the calculation of the minimum required acquisition time TACQ. In this case, the converter module is fully powered up at the outset and therefore the amplifier settling time, TAMP, is negligible. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature VHOLD EQUATION 20-1: TACQ 9 pF 100 Ω 1/2 LSb 5V → Rss = 6 kΩ 50°C (system max.) 0V @ time = 0 ACQUISITION TIME = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient = TAMP + TC + TCOFF EQUATION 20-2: VHOLD or TC = = ≤ = = = MINIMUM A/D HOLDING CAPACITOR CHARGING TIME = (VREF – (VREF/2048)) • (1 – e(-Tc/CHOLD(RIC + RSS + RS))) = -(CHOLD)(RIC + RSS + RS) ln(1/2048) 2003 Microchip Technology Inc. Preliminary DS39616B-page 253 PIC18F2331/2431/4331/4431 EXAMPLE 20-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TAMP + TC + TCOFF TAMP = negligible TCOFF = (Temp – 25°C)(0.005 µs/°C) (50°C – 25°C)(0.005 µs/°C) = .13 µs Temperature coefficient is only required for temperatures > 25°C. Below 25°C, TCOFF = 0 µs. TC – -(CHOLD) (RIC + RSS + RS) ln(1/2047) µs -(9 pF) (1 kΩ + 6 kΩ + 100 Ω) ln(0.0004883) µs = .49 µs + .13 µs = .62 µs TACQ = 0 + .62 µs + .13 µs = .75 µs Note: If the converter module has been in Sleep mode, TAMP is 2.0 µs from the time the part exits Sleep mode. FIGURE 20-2: ANALOG INPUT MODEL VDD Sampling Switch VT = 0.6V Rs VAIN RIC ≤ 1k ANx CPIN 5 pF VT = 0.6V SS RSS I leakage ± 500 nA CHOLD = 9 pF VSS Legend: CPIN = input capacitance VT = threshold voltage I LEAKAGE = leakage current at the pin due to various junctions = interconnect resistance RIC = sampling switch SS = sample/hold capacitance (from DAC) CHOLD RSS = sampling switch resistance Note: VDD 6V 5V 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch (kΩ) For VDD < 2.7V and temperatures below 0ºC, VAIN should be restricted to range: VAIN < VDD/2. DS39616B-page 254 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.4 A/D Voltage References 20.6 If external voltage references are used instead of the internal AVDD and AVSS sources, the source impedance of the VREF+ and VREF- voltage sources must be considered. During acquisition, currents supplied by these sources are insignificant. However, during conversion, the A/D module sinks and sources current through the reference sources. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are eight possible options for TAD: • • • • • • • • In order to maintain the A/D accuracy, the voltage reference source impedances should be kept low to reduce voltage changes. These voltage changes occur as reference currents flow through the reference source impedance. Note: 20.5 When using external references, the source impedance of the external voltage references must be less than 75Ω in order to achieve the specified ADC resolution. A higher reference source impedance will increase the ADC offset and gain errors. Resistive voltage dividers will not provide a low enough source impedance. To ensure the best possible ADC performance, external VREF inputs should be buffered with an op-amp or other low impedance circuit. Selecting the A/D Conversion Clock 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator Internal RC Oscillator/4 For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (approximately 416 µs, see parameter 130 for more information). Table 20-2 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. Selecting and Configuring Automatic Acquisition Time The ADCON2 register allows the user to select an acquisition time that occurs each time an A/D conversion is triggered. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and the start of conversion. This occurs when the ACQT3:ACQT0 bits (ADCON2<6:3>) remain in their Reset state (‘0000’). If desired, the ACQT bits can be set to select a programmable acquisition time for the A/D module. When triggered, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and triggering the A/D. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended, or if the conversion has begun. 2003 Microchip Technology Inc. Preliminary DS39616B-page 255 PIC18F2331/2431/4331/4431 TABLE 20-2: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Note 1: 2: 3: 4: 20.7 Maximum Device Frequency Operation ADCS2:ADCS0 PIC18FXX31 PIC18LFXX31(4) 2 TOSC 000 4.8 MHz 666 kHz 4 TOSC 100 9.6 MHz 1.33 MHz 8 TOSC 001 19.2 MHz 2.66 MHz 16 TOSC 101 38.4 MHz 5.33 MHz 32 TOSC 010 40.0 MHz 10.65 MHz 64 TOSC 110 40.0 MHz 21.33 MHz RC/4(3) 011 1.00 MHz(1) 1.00 MHz(2) RC(3) 111 4.0 MHz(2) 4.0 MHz(2) The RC source has a typical TAD time of 2-6 µs. The RC source has a typical TAD time of 0.5-1.5 µs. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification, unless in Single-shot mode. Low-power devices only. Operation in Power-Managed Modes Note: The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT3:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the power-managed mode clock that will be used. After the power-managed mode is entered (either of the power-managed run modes), an A/D acquisition or conversion may be started. Once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. If desired, the device may be placed into the corresponding power-managed Idle mode during the conversion. If the power-managed mode clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in Sleep mode requires the A/D RC clock to be selected. If bits ACQT3:ACQT0 are set to ‘0000’, and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN and SCS bits in the OSCCON register must have already been cleared prior to starting the conversion. DS39616B-page 256 20.8 The A/D can operate in Sleep mode only when configured for Single-shot operation. If the part is in Sleep mode, and it is possible for a source other than the A/D module to wake the part, the user must poll ADCON<GO/DONE> to ensure it is clear before reading the result. Configuring Analog Port Pins The ANSEL0, ANSEL1, TRISA and TRISE registers all configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the ANSEL0, ANSEL1 and the TRIS bits. Note 1: When reading the Port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will be accurately converted. Preliminary 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device’s specification limits. 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 20.9 A/D Conversions Figure 20-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. The internal A/D RC oscillator must be selected to perform a conversion in Sleep. Figure 20-4 shows the operation of the A/D converter after the GO bit has been set and the ACQT3:ACQT0 bits are set to ‘010’, and selecting a 4 TAD acquisition time before the conversion starts. FIGURE 20-3: Clearing the GO/DONE bit during a conversion will abort the current conversion. The resulting buffer location will contain the partially completed A/D conversion sample. This will not set the ADIF flag, therefore, the user must read the buffer location before a conversion sequence overwrites it. After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0) GO bit is set, and holding cap is disconnected from analog input TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b6 b3 b2 b8 b9 b4 b5 b7 b0 b1 Conversion Starts Go bit cleared on the rising edge of Q1 after the first Q3 following TAD11(1), and result buffer is loaded. Conversion time is a minimum of 11 TAD + 2 TCY, and a maximum of 11 TAD + 6 TCY. Note 1: A/D CONVERSION TAD CYCLES (ACQT<3:0> = 0010, TACQ = 4 TAD) FIGURE 20-4: TAD Cycles TACQT Cycles 1 2 3 4 Automatic Acquisition Time TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b6 b3 b2 b8 b9 b4 b5 b7 b0 b1 Conversion Starts (Holding capacitor is disconnected) A/D triggered Go bit cleared on the rising edge of Q1 after the first Q3 following TAD11(1) and result buffer is loaded. Note 1: In continuous modes, next conversion starts at the end of TAD12. 2003 Microchip Technology Inc. Preliminary DS39616B-page 257 PIC18F2331/2431/4331/4431 20.9.1 A/D RESULT REGISTER The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the flexibility to left- or rightjustify the 10-bit result in the 16-bit result register. The FIGURE 20-5: A/D Format Select bit (ADFM) controls this justification. Figure 20-5 shows the operation of the A/D result justification. The extra bits are loaded with ‘0’s. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers. A/D RESULT JUSTIFICATION 10-bit Result ADFM = 0 ADFM = 1 7 0 2107 7 0765 0000 00 0000 00 ADRESH ADRESH ADRESL 10-bit Result ADRESL 10-bit Result Left Justified Right Justified EQUATION 20-3: 0 CONVERSION TIME FOR MULTICHANNEL MODES Sequential Mode: T = (TACQ)A + (TCON)A + [(TACQ)B - 12TAD] + (TCON)B + [(TACQ)C - 12TAD] + (TCON)C + [(TACQ)D - 12TAD] + (TCON)D Simultaneous Mode: T = TACQ + (TCON)A + (TCON)B + TACQ + (TCON)C + (TCON)D DS39616B-page 258 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 20-3: SUMMARY OF A/D REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 0000 0000 0000 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111 PIR2 OSCFIF CMIF — EEIF BCLIF LVDIF TMR3IF CCP2IF 00-0 0000 00-0 0000 PIE2 OSCFIE CMIE — EEIE BCLIE LVDIE TMR3IE CCP2IE 00-0 0000 00-0 0000 IPR2 OSCFIP CMIP — EEIP BCLIP LVDIP TMR3IP CCP2IP ADRESH A/D Result Register High Byte ADRESL A/D Result Register Low Byte ADCON0 — — ACONV ADCON1 VCFG1 VCFG0 — FIFOEN 11-1 1111 11-1 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CHS0 GO/DONE ADON 00-1 0000 00-1 0000 BFEMT BFOVFL ADPNT1 ADPNT0 --00 qqqq --00 qqqq ACMOD1 ACMOD0 ADCON2 ADFM ACQT3 ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 0-00 0000 0-00 0000 ADCON3 ADRS1 ADRS0 — SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 00-0 0000 00-0 0000 ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GASEL1 GASEL0 0000 0000 0000 0000 ANSEL0 ANS7(6) ANS6(6) ANS5(6) ANS4 ANS1 ANS0 1111 1111 1111 1111 ---- ---1 ---- ---1 --0x 0000 --0u 0000 GCSEL1 GCSEL0 ANS3 ANS2 ANSEL1 — — — — — — — PORTA RA7(4) RA6(4) RA5 RA4 RA3 RA2 RA1 TRISA — — — — TRISE(3) IBF OBE IBOV PSPMODE LATE(3) — — — — Note 1: 2: 3: 4: 5: 6: RA0 TRISA7(4) TRISA6(4) Data Direction Control Register for PORTA PORTE(2) Legend: ANS8 (5) RE3(1) — --11 1111 --11 1111 Read PORTE Pins, Write Late(4) ---- xxxx ---- uuuu PORTE Data Direction 0000 -111 0000 -111 ---- -xxx ---- -uuu PORTE Output Data Latch x = unknown, u = unchanged, – = unimplemented, read as ‘0’, q = value depends on condition. Shaded cells are not used for A/D conversion. RE3 port bit is available only as an input pin when MCLRE bit in configuration register is ‘0’. This register is not implemented on PIC18F2X31 devices. These bits are not implemented on PIC18F2X31 devices. These pins may be configured as port pins depending on the Oscillator mode selected. ANS5 through ANS8 are available only on the PIC18F4X31 devices. Not available on 28-pin devices. 2003 Microchip Technology Inc. Preliminary DS39616B-page 259 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 260 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 21.0 LOW-VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low-Voltage Detect module (LVD). This module is a software programmable circuitry, where a device voltage trip point can be specified. When the voltage of the device becomes lower then the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low-Voltage Detect circuitry is completely under software control. This allows the circuitry to be turned off by the software, which minimizes the current consumption for the device. Figure 21-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, The block diagram for the LVD module is shown in Figure 21-2. A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit is set. Each node in the resistor divider represents a “trip point” voltage. The “trip point” voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the 1.2V internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (see Figure 21-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). TYPICAL LOW-VOLTAGE DETECT APPLICATION Voltage FIGURE 21-1: until the device voltage is no longer in valid operating range, to shut down the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. The difference TB – TA is the total time for shutdown. VA VB Legend: VA = LVD trip point VB = Minimum valid device operating voltage Time 2003 Microchip Technology Inc. TA TB Preliminary DS39616B-page 261 PIC18F2331/2431/4331/4431 FIGURE 21-2: LOW-VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD Control Register 16 to 1 MUX VDD Internally Generated Reference Voltage 1.2V LVDEN The LVD module has an additional feature that allows the user to supply the sense voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to ‘1111’. In this state, the comparator input is multiplexed from the external input FIGURE 21-3: LVDIF pin, LVDIN (Figure 21-3). This gives users flexibility, because it allows them to configure the low-voltage detect interrupt to occur at any voltage in the valid operating range. LOW-VOLTAGE DETECT (LVD) WITH EXTERNAL INPUT BLOCK DIAGRAM VDD VDD 16 to 1 MUX LVD Control Register LVDIN Externally Generated Trip Point LVDEN LVD VxEN BODEN EN BGAP DS39616B-page 262 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 21.1 Control Register The Low-Voltage Detect Control register controls the operation of the Low-Voltage Detect circuitry. REGISTER 21-1: LVDCON REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — IRVST LVDEN LVDL3 LVDL2 LVDL1 LVDL0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL3:LVDL0: Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.23V - 4.96V 1101 = 3.93V - 4.62V 1100 = 3.75V - 4.40V 1011 = 3.56V - 4.18V 1010 = 3.38V - 3.96V 1001 = 3.29V - 3.86V 1000 = 3.09V - 3.63V 0111 = 2.82V - 3.31V 0110 = 2.64V - 3.10V 0101 = 2.55V - 2.99V 0100 = 2.35V - 2.76V 0011 = 2.26V - 2.65V 0010 = 2.08V - 2.44V 0001 = Reserved 0000 = Reserved Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared 2003 Microchip Technology Inc. Preliminary x = Bit is unknown DS39616B-page 263 PIC18F2331/2431/4331/4431 21.2 Operation Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. The following steps are needed to set up the LVD module: 1. 2. 3. 4. 5. 6. Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD Trip Point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits). Figure 21-4 shows typical waveforms that the LVD module may be used to detect. FIGURE 21-4: LOW-VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable TIVRST LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists DS39616B-page 264 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 21.2.1 REFERENCE VOLTAGE SET POINT The internal reference voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low-voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter 36. The low-voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 21-4. 21.2.2 CURRENT CONSUMPTION 21.3 Operation During Sleep When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 21.4 Effects of a Reset A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off. When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. 2003 Microchip Technology Inc. Preliminary DS39616B-page 265 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 266 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 22.0 SPECIAL FEATURES OF THE CPU PIC18F2331/2431/4331/4431 devices include several features intended to maximize system reliability and minimize cost through elimination of external components. These are: • Oscillator Selection • Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • Interrupts • Watchdog Timer (WDT) • Fail-Safe Clock Monitor • Two-Speed Start-up • Code Protection • ID Locations • In-Circuit Serial Programming™ (ICSP™) The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 2.0 “Oscillator Configurations”. 22.1 Configuration Bits The configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes. Programming the configuration registers is done in a manner similar to programming the Flash memory. The EECON1 register WR bit starts a self-timed write to the Configuration register. In normal Operation mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and the data for the configuration register write. Setting the WR bit starts a long write to the Configuration register. The configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a ‘1’ or a ‘0’ into the cell. For additional details on Flash programming, refer to Section 6.5 “Writing to Flash Program Memory”. A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator start-up timers provided for Resets, PIC18F2331/2431/4331/4431 devices have a Watchdog Timer, which is either permanently enabled via the configuration bits, or software controlled (if configured as disabled). The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate configuration register bits. 2003 Microchip Technology Inc. Preliminary DS39616B-page 267 PIC18F2331/2431/4331/4431 TABLE 22-1: CONFIGURATION BITS AND DEVICE IDS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value 300000h CONFIG1L — — — — — — — — ---- ---- 300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 11-- 1111 300002h CONFIG2L — — — — BORV1 BORV0 BOREN PWRTEN ---- 1111 300003h CONFIG2H — — WINEN WDPS3 WDPS2 WDPS1 WDPS0 WDTEN ---1 1111 HPOL LPOL PWMPIN — — --11 11-- SSPMX — FLTAMX 1--1 1-11 300004h CONFIG3L — — T1OSCMX 300005h CONFIG3H MCLRE — — 300006h CONFIG4L DEBUG — — — — LVP — STVREN 1--- -1-1 300007h CONFIG4H — — — — — — — — ---- ---- EXCLKMX PWM4MX 300008h CONFIG5L — — — — CP3 CP2 CP1 CP0 ---- 1111 300009h CONFIG5H CPD CPB — — — — — — 11-- ---- 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 ---- 1111 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 111- ---- 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 ---- 1111 30000Dh CONFIG7H — EBTRB — — — — — — -1-- ---- 3FFFFEh DEVID1(1) DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 xxxx xxxx(1) DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0101 3FFFFFh DEVID2 Legend: Note 1: (1) x = unknown, u = unchanged, – = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’. See Register 22-13 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user. REGISTER 22-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h) R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7 IESO: Internal External Switch Over bit 1 = Internal External Switch Over mode enabled 0 = Internal External Switch Over mode disabled bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 FOSC<3:0>: Oscillator Selection bits 11xx= External RC oscillator, CLKO function on RA6 1001= Internal oscillator block, CLKO function on RA6, and port function on RA7 1000= Internal oscillator block, port function on RA6, and port function on RA7 0111= External RC oscillator, port function on RA6 0110= HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) 0101= EC oscillator, port function on RA6 0100= EC oscillator, CLKO function on RA6 0010= HS oscillator 0001= XT oscillator 0000= LP oscillator Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed DS39616B-page 268 Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 22-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — BORV1 BORV0 BOREN PWRTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 BORV1:BORV0: Brown-out Reset Voltage bits 11 = Reserved 10 = VBOR set to 2.7V 01 = VBOR set to 4.2V 00 = VBOR set to 4.5V bit 1 BOREN: Brown-out Reset Enable bit(1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled bit 0 PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: Having BOREN = 1 does not automatically override the PWRTEN to ‘0’ nor automatically enable the Power-up Timer. Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed 2003 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state DS39616B-page 269 PIC18F2331/2431/4331/4431 REGISTER 22-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h) U-0 — bit 7 bit 7-6 bit 5 bit 4-1 bit 0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — WINEN WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 0 Unimplemented: Read as ‘0’ WINEN: Watchdog Timer Window Enable bit 1 = WDT Window disabled 0 = WDT Window enabled WDPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed DS39616B-page 270 Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 22-4: CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300004h) U-0 — bit 7 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1-0 U R/P-1 R/P-1 R/P-1 R/P-1 U U — T1OSCMX HPOL LPOL PWMPIN — — bit 0 Unimplemented: Read as ‘0’ T1OSCMX: Timer1 Oscillator Mode bit 1 = Low power Timer1 operation when microcontroller is in Sleep mode. 0 = Standard (legacy) Timer1 oscillator operation. HPOL(1): High-Side Transistors Polarity bit (i.e., odd PWM output polarity control bit ) 1 = PWM 1, 3, 5 and 7 are active-high (default) 0 = PWM 1, 3, 5 and 7 are active-low LPOL(1): Low-Side Transistors Polarity bit (i.e., even PWM output polarity control bit) 1 = PWM 0, 2, 4 and 6 are active-high (default) 0 = PWM 0, 2, 4 and 6 are active-low PWMPIN(2): PWM output pins Reset state control bit 1 = PWM outputs disabled upon Reset (default) 0 = PWM outputs drive active states upon Reset(3) Unimplemented: Read as ‘0’ Note 1: Polarity control bits HPOL and LPOL define PWM signal output active and inactive states; PWM states generated by the fault inputs or PWM manual override. 2: PWM6 and PWM7 output channels are only available on the PIC18F4X21 devices. 3: When PWMPIN = 0, PWMEN<2:0> = 101 if device has eight PWM output pins (40 and 44-pin devices) and PWMEN<2:0> = 100 if the device has six PWM output pins (28-pin device). PWM output polarity is defined by HPOL and LPOL. Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed 2003 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state DS39616B-page 271 PIC18F2331/2431/4331/4431 REGISTER 22-5: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h) R/P-1 U U MCLRE — — R/P-1 R/P-1 (1) EXCLKMX R/P-1 (1) PWM4MX SSPMX (1) U R/P-1 — FLTAMX(1) bit 7 bit 0 bit 7 MCLRE: MCLR Pin Enable bit 1 = RE3 input pin enabled; MCLR disabled. 0 = MCLR pin enabled: RE3 input pin disabled. bit 6-5 Unimplemented: Read as ‘0’ bit 4 EXCLKMX: TMR0/T5CKI External Clock Mux bit 1 = TMR0/T5CKI external clock input is multiplexed with RC3 0 = TMR0/T5CKI external clock input is multiplexed with RD0 bit 3 PWM4MX: PWM4 Mux bit 1 = PWM4 output is multiplexed with RB5 0 = PWM4 output is multiplexed with RD5 bit 2 SSPMX: SSP I/O Mux bit 1 = SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4 respectively. SDO output is multiplexed with RC7. 0 = SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2 respectively. SDO output is multiplexed with RD1. bit 1 Unimplemented: Read as ‘0’ bit 0 FLTAMX: FLTA Mux bit 1 = FLTA input is multiplexed with RC1 0 = FLTA input is multiplexed with RD4 Note 1: Unimplemented in PIC18F2X31 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed DS39616B-page 272 Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 22-6: CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h) R/P-1 U-0 U-0 U-0 U-0 R/P-1 U-0 R/P-1 DEBUG — — — — LVP — STVREN bit 7 bit 0 bit 7 DEBUG: Background Debugger Enable bit 1 = Background Debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background Debugger enabled, RB6 and RB7 are dedicated to in-circuit debug bit 6-3 Unimplemented: Read as ‘0’ bit 2 LVP: Low-Voltage ICSP Enable bit 1 = Low-Voltage ICSP enabled 0 = Low-Voltage ICSP disabled bit 1 Unimplemented: Read as ‘0’ bit 0 STVREN: Stack Full/Underflow Reset Enable bit 1 = Stack Full/Underflow will cause Reset 0 = Stack Full/Underflow will not cause Reset Legend: R = Readable bit C = Clearable bit - n = Value when device is unprogrammed 2003 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state DS39616B-page 273 PIC18F2331/2431/4331/4431 REGISTER 22-7: CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h) U-0 U-0 U-0 U-0 R/C-1 R/C-1 R/C-1 R/C-1 — — — — CP3(1) CP2(1) CP1 CP0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 CP3: Code Protection bit 1 = Block 3 (001800-001FFFh) not code-protected 0 = Block 3 (001800-001FFFh) code-protected bit 2 CP2: Code Protection bit 1 = Block 2 (001000-0017FFh) not code-protected 0 = Block 2 (001000-0017FFh) code-protected bit 1 CP1: Code Protection bit 1 = Block 1 (000800-000FFFh) not code-protected 0 = Block 1 (000800-000FFFh) code-protected bit 0 CP0: Code Protection bit 1 = Block 0 (000200-0007FFh) not code-protected 0 = Block 0 (000200-0007FFh) code-protected Note 1: Unimplemented in PIC18F2X31 devices; maintain this bit set. Legend: R = Readable bit C = Clearable bit - n = Value when device is unprogrammed REGISTER 22-8: U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h) R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot block (000000-0001FFh) not code-protected 0 = Boot block (000000-0001FFh) code-protected bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit C = Clearable bit - n = Value when device is unprogrammed DS39616B-page 274 Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 22-9: CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — WRT3(1) WRT2(1) WRT1 WRT0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 WRT3: Write Protection bit(1) 1 = Block 3 (001800-001FFFh) not write-protected 0 = Block 3 (001800-001FFFh) write-protected bit 2 WRT2: Write Protection bit(1) 1 = Block 2 (001000-0017FFh) not write-protected 0 = Block 2 (001000-0017FFh) write-protected bit 1 WRT1: Write Protection bit 1 = Block 1 (000800-000FFFh) not write-protected 0 = Block 1 (000800-000FFFh) write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 (000200-0007FFh) not write-protected 0 = Block 0 (000200-0007FFh) write-protected Note 1: Unimplemented in PIC18F2X31 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state REGISTER 22-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh) R/P-1 R/P-1 R-1 U-0 U-0 U-0 U-0 U-0 WRTD WRTB WRTC — — — — — bit 7 bit 0 bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot block (000000-0001FFh) not write-protected 0 = Boot block (000000-0001FFh) write-protected bit 5 WRTC: Configuration Register Write Protection bit 1 = Configuration registers (300000-3000FFh) not write-protected 0 = Configuration registers (300000-3000FFh) write-protected Note: bit 4-0 This bit is read-only in normal Execution mode; it can be written only in Program mode. Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed 2003 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state DS39616B-page 275 PIC18F2331/2431/4331/4431 REGISTER 22-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — EBTR3(1) EBTR2(1) EBTR1 EBTR0 bit 7 bit 0 bit 7-4 Unimplemented: Read as ‘0’ bit 3 EBTR3: Table Read Protection bit(1) 1 = Block 3 (001800-001FFFh) not protected from table reads executed in other blocks 0 = Block 3 (001800-001FFFh) protected from table reads executed in other blocks bit 2 EBTR2: Table Read Protection bit(1) 1 = Block 2 (001000-0017FFh) not protected from table reads executed in other blocks 0 = Block 2 (001000-0017FFh) protected from table reads executed in other blocks bit 1 EBTR1: Table Read Protection bit 1 = Block 1 (000800-000FFFh) not protected from table reads executed in other blocks 0 = Block 1 (000800-000FFFh) protected from table reads executed in other blocks bit 0 EBTR0: Table Read Protection bit 1 = Block 0 (000200-0007FFh) not protected from table reads executed in other blocks 0 = Block 0 (000200-0007FFh) protected from table reads executed in other blocks Note 1: Unimplemented in PIC18F2X31 devices; maintain this bit set. Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state REGISTER 22-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh) U-0 R/P-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot block (000000-0001FFh) not protected from table reads executed in other blocks 0 = Boot block (000000-0001FFh) protected from table reads executed in other blocks bit 5-0 Unimplemented: Read as ‘0’ Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed DS39616B-page 276 Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 REGISTER 22-13: DEVICE ID REGISTER 1 FOR PIC18F2331/2431/4331/4431 DEVICES R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 bit 7-5 DEV<2:0>: Device ID bits These bits are used with the DEV<10:3> bits in the Device ID register 2 to identify the part number. 000 = PIC18F4331 001 = PIC18F4431 100 = PIC18F2331 101 = PIC18F2431 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision. Legend: R = Read-only bit P = Programmable bit - n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state REGISTER 22-14: DEVICE ID REGISTER 2 FOR PIC18F2331/2431/4331/4431 DEVICES R R R R R R R R DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 bit 7 bit 7-0 bit 0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the part number 0000 0101 = PIC18F2331/2431/4331/4431 devices Note 1: These values for DEV10:DEV3 may be shared with other devices. The specific device is always identified by using the entire DEV10:DEV0 bit sequence. Legend: R = Read-only bit P = Programmable bit - n = Value when device is unprogrammed 2003 Microchip Technology Inc. Preliminary U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state DS39616B-page 277 PIC18F2331/2431/4331/4431 22.2 Watchdog Timer (WDT) Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. For PIC18F2331/2431/4331/4431 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. 2: Changing the setting of the IRCF bits (OSCCON<6:4> clears the WDT and postscaler counts. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H (see Register 22-3). Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: execute a SLEEP or CLRWDT instruction, the IRCF bits (OSCCON<6:4>) are changed, or a clock failure has occurred (see Section 22.4.1 “FSCM and the Watchdog Timer”). 3: When a CLRWDT instruction is executed the postscaler count will be cleared. 4: If WINEN = 0, then CLRWDT must be executed only when WDTW = 1; otherwise, a device reset will result. 22.2.1 Register 22-15 shows the WDTCON register. This is a readable and writable register. The SWDTEN bit allows software to enable or disable the WDT, but only if the configuration bit has disabled the WDT. The WDTW bit is a read-only bit that indicates when the WDT count is in the fourth quadrant (i.e., when the 8-bit WDT value is b’11000000’ or greater). Adjustments to the internal oscillator clock period using the OSCTUNE register also affect the period of the WDT by the same factor. For example, if the INTRC period is increased by 3%, then the WDT period is increased by 3%. FIGURE 22-1: CONTROL REGISTER WDT BLOCK DIAGRAM Enable WDT SWDTEN WDTEN INTRC Control WDT Counter ÷125 INTRC Source Wake-up from Sleep Change on IRCF Bits Programmable Postscaler 1:1 to 1:32,768 CLRWDT All Device Resets WDT Reset Reset WDT 4 WDTPS<3:0> Sleep REGISTER 22-15: WDTCON REGISTER R-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 WDTW — — — — — — SWDTEN bit 7 bit 0 bit 7 WDTW: Watchdog Timer Window bit 1 = WDT count is in fourth quadrant 0 = WDT count is not in fourth quadrant bit 6 Unimplemented bit 0 SWDTEN: Software Enable / Disable for Watch Dog Timer bit (1) 1 = WDT is turned on 0 = WDT is turned off Note 1: If WDTEN configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTEN configuration bit = 0, then it is possible to turn WDT on/off with this control bit. Legend: DS39616B-page 278 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 22-2: Name CONFIG2H RCON WDTCON SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — WINEN WDTPS3 WDTPS2 WDTPS2 WDTPS0 WDTEN IPEN — — RI TO PD POR BOR WDTW — — — — — — SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. 22.3 22.3.1 Two-Speed Start-up The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTRC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO bit in Configuration Register 1H (CONFIG1H<7>). Two-Speed Start-up is available only if the primary Oscillator mode is LP, XT, HS or HSPLL (crystal-based modes). Other sources do not require a OST start-up delay; for these, Two-Speed Start-up is disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer after a POR Reset is enabled. This allows almost immediate code execution, while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP While using the INTRC oscillator in Two-Speed Startup, the device still obeys the normal command sequences for entering power-managed modes, including serial SLEEP instructions (refer to Section 3.1.3 “Multiple Sleep Commands”). In practice, this means that user code can change the SCS1:SCS0 bit settings and issue SLEEP commands before the OST times out. This would allow an application to briefly wake-up, perform routine “housekeeping” tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the system clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the system clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode. Because the OSCCON register is cleared on Reset events, the INTOSC (or postscaler) clock source is not initially available after a Reset event; the INTRC clock is used directly at its base frequency. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IFRC2:IFRC0 immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode. In all other power-managed modes, Two-Speed Startup is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored. 2003 Microchip Technology Inc. Preliminary DS39616B-page 279 PIC18F2331/2431/4331/4431 FIGURE 22-2: TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL) Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) PLL Clock Output 1 2 3 4 5 6 Clock Transition 7 8 CPU Clock Peripheral Clock Program Counter PC Wake from Interrupt Event Note 1: PC + 4 PC + 2 PC + 6 OSTS bit Set TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39616B-page 280 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 22.4 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure, by automatically switching the system clock to the internal oscillator block. The FSCM function is enabled by setting the Fail-Safe Clock Monitor Enable bit, FCMEN (CONFIG1H<6>). When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide an instant backup clock in the event of a clock failure. Clock monitoring (shown in Figure 22-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral system clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the system clock source, but cleared on the rising edge of the sample clock. FIGURE 22-3: FSCM BLOCK DIAGRAM Clock Monitor Latch (CM) (edge-triggered) Peripheral Clock INTRC Source (32 µs) ÷ 64 S Q C Q Adjustments to the internal oscillator block using the OSCTUNE register also affect the period of the FSCM by the same factor. This can usually be neglected, as the clock frequency being monitored is generally much higher than the sample clock frequency. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible. 22.4.1 FSCM AND THE WATCHDOG TIMER Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur, and a subsequent device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out. 488 Hz (2.048 ms) Clock Failure Detected Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 22-4). This causes the following: • the FSCM generates an oscillator fail interrupt by setting bit OSCFIF (PIR2<7>); • the system clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source – this is the fail-safe condition); and • the WDT is reset. Since the postscaler frequency from the internal oscillator block may not be sufficiently stable, it may be desirable to select another clock configuration and enter an alternate power-managed mode (see Section 22.3.1 “Special Considerations for Using Two-Speed Start-up” and Section 3.1.3 “Multiple Sleep Commands” for more details). This can be done to attempt a partial recovery or execute a controlled shutdown. 2003 Microchip Technology Inc. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits IFRC2:IFRC0 immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting IFRC2:IFRC0 prior to entering Sleep mode. 22.4.2 EXITING FAIL-SAFE OPERATION The fail-safe condition is terminated by either a device Reset, or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the Oscillator mode, such as OST or PLL timer). The INTOSC multiplexer provides the system clock until the primary clock source becomes ready (similar to a Two-Speed Start-up). The clock system source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power-managed mode is entered. Entering a power-managed mode by loading the OSCCON register and executing a SLEEP instruction will clear the fail-safe condition. When the fail-safe condition is cleared, the clock monitor will resume monitoring the peripheral clock. Preliminary DS39616B-page 281 PIC18F2331/2431/4331/4431 FIGURE 22-4: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output CM Output (Q) Failure Detected OSCFIF CM Test Note: 22.4.3 CM Test CM Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 22.4.4 FSCM INTERRUPTS IN POWERMANAGED MODES As previously mentioned, entering a power-managed mode clears the fail-safe condition. By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-safe monitoring of the power-managed clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, the device will not exit the power-managed mode on oscillator failure. Instead, the device will continue to operate as before, but clocked by the INTOSC multiplexer. While in Idle mode, subsequent interrupts will cause the CPU to begin executing instructions while being clocked by the INTOSC multiplexer. The device will not transition to a different clock source until the fail-safe condition is cleared. POR OR WAKE FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or Low-Power Sleep mode. When the primary system clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on POR or wake from Sleep will also prevent the detection of the oscillator’s failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged. As noted in Section 22.3.1 “Special Considerations for Using Two-Speed Start-up”, it is also possible to select another clock configuration and enter an alternate power-managed mode, while waiting for the primary system clock to become stable. When the new Powered Managed mode is selected, the primary clock is disabled. DS39616B-page 282 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 22.5 Program Verification and Code Protection Each of the five blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PICmicro® devices. • Code-Protect bit (CPn) • Write-Protect bit (WRTn) • External Block Table Read bit (EBTRn) The user program memory is divided into five blocks. One of these is a boot block of 512 bytes. The remainder of the memory is divided into four blocks on binary boundaries. Figure 22-5 shows the program memory organization for 8- and 16-Kbyte devices, and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 22-3. FIGURE 22-5: CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2331/2431/4331/4431 MEMORY SIZE/DEVICE Block Code Protection Controlled By: 8 Kbytes (PIC18FX331) Boot Block Address Range 16 Kbytes (PIC18FX431) 0000h 0FFFh Address Range 0000h 01FFh Boot Block 0200h CPB, WRTB, EBTRB 0200h Block 0 Block 0 CP0, WRT0, EBTR0 0FFFh 0FFFh 1000h 1000h Block 1 Block 1 CP1, WRT1, EBTR1 1FFFh 1FFFh 2000h CP2, WRT2, EBTR2 Block 2 2FFFh Unimplemented Read 0’s 3000h Block 3 CP3, WRT3, EBTR3 3FFFh TABLE 22-3: 3FFFh SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CP3 CP2 CP1 CP0 300008h CONFIG5L — — — — 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — WRT3 WRT2 WRT1 WRT0 30000Bh CONFIG6H WRTD WRTB WRTC — — — — — 30000Ch CONFIG7L — — — — EBTR3 EBTR2 EBTR1 EBTR0 CONFIG7H — EBTRB — — — — — — 30000Dh Legend: Shaded cells are unimplemented. 2003 Microchip Technology Inc. Preliminary DS39616B-page 283 PIC18F2331/2431/4331/4431 22.5.1 PROGRAM MEMORY CODE PROTECTION Note: The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The configuration registers may be read and written with the table read and table write instructions. In normal Execution mode, the CPn bits have no direct effect. CPn bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTn configuration bit is ‘0’. The EBTRn bits control table reads. For a block of user memory with the EBTRn bit set to ‘0’, a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read, and will result in reading ‘0’s. Figures 22-6 through 22-8 illustrate table write and table read protection. FIGURE 22-6: Code protection bits may only be written to a ‘0’ from a ‘1’ state. It is not possible to write a ‘1’ to a bit in the ‘0’ state. Code protection bits are only set to ‘1’ by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP or an external programmer. TABLE WRITE (WRTn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0001FFh 000200h WRTB,EBTRB = 11 TBLPTR = 0002FFh WRT0,EBTR0 = 01 PC = 0007FEh TBLWT * 0007FFh 000800h WRT1,EBTR1 = 11 000FFFh 001000h PC = 0017FEh WRT2,EBTR2 = 11 TBLWT * 0017FFh 001800h WRT3,EBTR3 = 11 001FFFh Results: All table writes disabled to Blockn whenever WRTn = ‘0’. DS39616B-page 284 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 22-7: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB,EBTRB = 11 0001FFh 000200h TBLPTR = 0002FFh WRT0,EBTR0 = 10 0007FFh 000800h PC = 000FFEh TBLRD * WRT1,EBTR1 = 11 000FFFh 001000h WRT2,EBTR2 = 11 0017FFh 001800h WRT3,EBTR3 = 11 001FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = ‘0’. TABLAT register returns a value of ‘0’. FIGURE 22-8: EXTERNAL BLOCK TABLE READ (EBTRn) ALLOWED Register Values Program Memory Configuration Bit Settings 000000h WRTB,EBTRB = 11 0001FFh 000200h TBLPTR = 0002FFh PC = 0007FEh WRT0,EBTR0 = 10 TBLRD * 0007FFh 000800h WRT1,EBTR1 = 11 000FFFh 001000h WRT2,EBTR2 = 11 0017FFh 001800h WRT3,EBTR3 = 11 001FFFh Results: Table reads permitted within Blockn, even when EBTRBn = ‘0’. TABLAT register returns the value of the data at the location TBLPTR. 2003 Microchip Technology Inc. Preliminary DS39616B-page 285 PIC18F2331/2431/4331/4431 22.5.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits external writes to data EEPROM. The CPU can continue to read and write data EEPROM regardless of the protection bit settings. 22.5.3 CONFIGURATION REGISTER PROTECTION The configuration registers can be write-protected. The WRTC bit controls protection of the configuration registers. In normal Execution mode, the WRTC bit is readable only. WRTC can only be written via ICSP or an external programmer. 22.6 ID Locations Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions, or during program/verify. The ID locations can be read when the device is code-protected. 22.7 22.9 In-Circuit Debugger When the DEBUG bit in configuration register CONFIG4L is programmed to a ‘0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB® IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 22-4 shows which resources are required by the background debugger. TABLE 22-4: Low-Voltage ICSP Programming The LVP bit in Configuration Register 4L (CONFIG4L<2>) enables Low-Voltage ICSP Programming (LVP). When LVP is enabled, the microcontroller can be programmed without requiring high voltage being applied to the MCLR/VPP pin, but the RB5/PGM pin is then dedicated to controlling Program mode entry and is not available as a general purpose I/O pin. LVP is enabled in erased devices. While programming using LVP, VDD is applied to the MCLR/VPP pin as in normal Execution mode. To enter Programming mode, VDD is applied to the PGM pin. Note 1: High voltage programming is always available, regardless of the state of the LVP bit or the PGM pin, by applying VIHH to the MCLR pin. 2: When Low-Voltage Programming is enabled, the RB5 pin can no longer be used as a general purpose I/O pin. In-Circuit Serial Programming PIC18F2331/2431/4331/4431 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 22.8 To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, VSS, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies. 3: When LVP is enabled, externally pull the PGM pin to VSS to allow normal program execution. If Low-Voltage ICSP Programming mode will not be used, the LVP bit can be cleared and RB5/PGM becomes available as the digital I/O pin RB5. The LVP bit may be set or cleared only when using standard high voltage programming (VIHH applied to the MCLR/VPP pin). Once LVP has been disabled, only the standard high voltage programming is available and must be used to program the device. Memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required. If a block erase is to be performed when using low-voltage programming, the device must be supplied with VDD of 4.5V to 5.5V. DEBUGGER RESOURCES I/O pins: RB6, RB7 Stack: 2 levels Program Memory: 512 bytes Data Memory: 10 bytes DS39616B-page 286 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 23.0 INSTRUCTION SET SUMMARY The PIC18 instruction set adds many enhancements to the previous PICmicro instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16-bits), but there are three instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Byte-oriented operations Bit-oriented operations Literal operations Control operations The PIC18 instruction set summary in Table 23-2 lists byte-oriented, bit-oriented, literal and control operations. Table 23-1 shows the OPCODE field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by ‘f’) The destination of the result (specified by ‘d’) The accessed memory (specified by ‘a’) The file register designator 'f' specifies which file register is to be used by the instruction. The destination designator ‘d’ specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by ‘f’) The bit in the file register (specified by ‘b’) The accessed memory (specified by ‘a’) • A program memory address (specified by ‘n’) • The mode of the Call or Return instructions (specified by ‘s’) • The mode of the table read and table write instructions (specified by ‘m’) • No operand required (specified by ‘—’) All instructions are a single word, except for three double word instructions. These three instructions were made double word instructions so that all the required information is available in these 32 bits. In the second word, the 4 MSbs are 1’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs. Twoword branch instructions (if true) would take 3 µs. Figure 23-1 shows the general formats that the instructions can have. All examples use the format ‘nnh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 23-2, lists the instructions recognized by the Microchip Assembler (MPASMTM assembler). Section 23.2 “Instruction Set” provides a description of each instruction. 23.1 READ-MODIFY-WRITE OPERATIONS The bit field designator 'b' selects the number of the bit affected by the operation, while the file register designator 'f' represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: • A literal value to be loaded into a file register (specified by ‘k’) • The desired FSR register to load the literal value into (specified by ‘f’) • No operand required (specified by ‘—’) 2003 Microchip Technology Inc. The control instructions may use some of the following operands: Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. For example, a "BCF PORTB,1" instruction will read PORTB, clear bit 1 of the data, then write the result back to PORTB. The read operation would have the unintended result that any condition that sets the RBIF flag would be cleared. The R-M-W operation may also copy the level of an input pin to its corresponding output latch. Preliminary DS39616B-page 287 PIC18F2331/2431/4331/4431 TABLE 23-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit: a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit: d = 0: store result in WREG d = 1: store result in file register f dest Destination either the WREG register or the specified register file location. f 8-bit register file address (0x00 to 0xFF). fs 12-bit register file address (0x000 to 0xFFF). This is the source address. fd 12-bit register file address (0x000 to 0xFFF). This is the destination address. k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label Label name. mm The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: * No Change to register (such as TBLPTR with table reads and writes). *+ Post-Increment register (such as TBLPTR with table reads and writes). *- Post-Decrement register (such as TBLPTR with table reads and writes). Pre-Increment register (such as TBLPTR with table reads and writes). +* n The relative address (2’s complement number) for relative branch instructions, or the direct address for Call/ Branch and Return instructions. PRODH Product of Multiply high byte. PRODL Product of Multiply low byte. s Fast Call/Return Mode Select bit: s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or Unchanged. WREG Working register (accumulator). x Don't care (0 or 1) . The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location). TABLAT 8-bit Table Latch. TOS Top-of-Stack. PC Program Counter. PCL Program Counter Low Byte. PCH Program Counter High Byte. PCLATH Program Counter High Byte Latch. PCLATU Program Counter Upper Byte Latch. GIE Global Interrupt Enable bit. WDT Watchdog Timer. TO Time-out bit. PD Power-down bit. C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative. [ ] Optional. ( ) Contents. → Assigned to. < > Register bit field. ∈ In the set of. italics User defined term (font is courier). DS39616B-page 288 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 23-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 8 7 OPCODE b (BIT #) a 0 BSF MYREG, bit, B f (FILE #) b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 8 7 OPCODE 0 MOVLW 0x7F k (literal) k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 8 7 OPCODE 15 0 GOTO Label n<7:0> (literal) 12 11 0 n<19:8> (literal) 1111 n = 20-bit immediate value 15 8 7 OPCODE 15 S 0 CALL MYFUNC n<7:0> (literal) 12 11 0 n<19:8> (literal) S = Fast bit 15 OPCODE 15 OPCODE 2003 Microchip Technology Inc. 11 10 0 BRA MYFUNC n<10:0> (literal) 8 7 0 n<7:0> (literal) Preliminary BC MYFUNC DS39616B-page 289 PIC18F2331/2431/4331/4431 TABLE 23-2: PIC18FXXX INSTRUCTION SET Mnemonic, Operands 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a SUBWF SUBWFB f, d, a f, d, a SWAPF TSTFSZ XORWF f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1 1 1 1 1 1 1 1 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff 1 1 0101 11da 0101 10da ffff ffff ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N 1, 2 1 0011 10da 1 (2 or 3) 0110 011a 1 0001 10da ffff ffff ffff ffff None ffff None ffff Z, N 4 1, 2 1 1 1 (2 or 3) 1 (2 or 3) 1 ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1, 2 1, 2 3, 4 3, 4 1, 2 None None C, DC, Z, OV, N 1, 2 C, Z, N Z, N 1, 2 C, Z, N Z, N None C, DC, Z, OV, N 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS BTG Note 1: 2: 3: 4: 5: f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39616B-page 290 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 23-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL n n n n n n n n n n, s CLRWDT DAW GOTO — — n NOP NOP POP PUSH RCALL RESET RETFIE — — — — n RETLW RETURN SLEEP Note 1: 2: 3: 4: 5: 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 s Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable k s — Return with literal in WREG Return from Subroutine Go into Standby mode 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 2 2 1 0000 1100 0000 0000 0000 0000 kkkk 0001 0000 1 1 2 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None TO, PD C, DC None None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD 4 When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. 2003 Microchip Technology Inc. Preliminary DS39616B-page 291 PIC18F2331/2431/4331/4431 TABLE 23-2: PIC18FXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSRx 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 None None None None None None None None None None None None C, DC, Z, OV, N Z, N DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: 2: 3: 4: 5: Table Read 2 Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write 2 (5) Table Write with post-increment Table Write with post-decrement Table Write with pre-increment When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction. If the table write starts the write cycle to internal memory, the write will continue until terminated. DS39616B-page 292 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 23.2 Instruction Set ADDLW ADD literal to W Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (W) + k → W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 k kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W ADDLW 0x15 Before Instruction W = ADDWF ADD W to f Syntax: [ label ] ADDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) + (f) → dest Status Affected: N, OV, C, DC, Z Encoding: 0010 01da f [,d [,a]] ffff ffff Description: Add W to register ‘f’. If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected. If ‘a’ is 1, the BSR is used. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 0x10 Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination After Instruction W = 0x25 Example: ADDWF REG, W Before Instruction W REG = = 0x17 0xC2 After Instruction W REG 2003 Microchip Technology Inc. Preliminary = = 0xD9 0xC2 DS39616B-page 293 PIC18F2331/2431/4331/4431 ADDWFC ADD W and Carry bit to f ANDLW AND literal with W Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] Operation: (W) + (f) + (C) → dest Status Affected: N, OV, C, DC, Z Encoding: 0010 Description: 1 Cycles: 1 0 ≤ k ≤ 255 Operation: (W) .AND. k → W Status Affected: N, Z Encoding: ffff ffff Add W, the Carry Flag and data memory location ‘f’. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed in data memory location ‘f’. If ‘a’ is 0, the Access Bank will be selected. If ‘a’ is 1, the BSR will not be overridden. Words: 0000 kkkk kkkk The contents of W are ANDed with the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W ANDLW 0x5F Before Instruction Q2 Q3 Q4 Read register 'f' Process Data Write to destination ADDWFC REG, W W = 0xA3 After Instruction W Example: 1011 Description: Example: Q Cycle Activity: Q1 Decode 00da Operands: k = 0x03 Before Instruction Carry bit = REG = W = 1 0x02 0x4D After Instruction Carry bit = REG = W = DS39616B-page 294 0 0x02 0x50 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] f [,d [,a]] Operation: (W) .AND. (f) → dest Status Affected: N, Z Encoding: 0001 ffff ffff [ label ] BC Operands: -128 ≤ n ≤ 127 Operation: if carry bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None nnnn nnnn Words: 1 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write to destination ANDWF = = Q Cycle Activity: If Jump: Q1 REG, W Before Instruction 0x17 0xC2 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation If No Jump: Q1 Decode After Instruction = = 0010 1 Cycles: W REG 1110 n If the Carry bit is 1, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: W REG Syntax: Description: The contents of W are AND’ed with register ‘f’. If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected. If ‘a’ is 1, the BSR will not be overridden (default). Example: Branch if Carry Encoding: 01da Description: Decode BC Q2 Q3 Q4 Read literal ‘n’ Process Data No operation 0x02 0xC2 Example: HERE BC JUMP Before Instruction PC = address (HERE) = = = = 1; address (JUMP) 0; address (HERE+2) After Instruction If Carry PC If Carry PC 2003 Microchip Technology Inc. Preliminary DS39616B-page 295 PIC18F2331/2431/4331/4431 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 0 → f<b> Status Affected: None Encoding: 1001 Description: Branch if Negative Syntax: [ label ] BN Operands: -128 ≤ n ≤ 127 Operation: if negative bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Encoding: bbba ffff ffff 1110 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: BCF FLAG_REG, FLAG_REG = 0xC7 FLAG_REG = 0x47 0110 nnnn nnnn If the Negative bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation 7 Before Instruction After Instruction n Description: Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: Decode f,b[,a] BN If No Jump: Q1 Decode Q2 Q3 Q4 Read literal ‘n’ Process Data No operation Example: HERE BN Jump Before Instruction PC = address (HERE) = = = = 1; address (Jump) 0; address (HERE+2) After Instruction If Negative PC If Negative PC DS39616B-page 296 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if carry bit is ‘0’ (PC) + 2 + 2n → PC Operation: if negative bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 n 0011 nnnn nnnn Encoding: 1110 n 0111 nnnn nnnn Description: If the Carry bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Description: If the Negative bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q2 Q3 Q4 Read literal ‘n’ Process Data No operation If No Jump: Q1 Decode Example: HERE BNC Jump If No Jump: Q1 Decode Q4 No operation HERE BNN Jump Before Instruction = address (HERE) PC After Instruction If Carry PC If Carry PC Q3 Process Data Example: Before Instruction PC Q2 Read literal ‘n’ = address (HERE) = = = = 0; address (Jump) 1; address (HERE+2) After Instruction = = = = 0; address (Jump) 1; address (HERE+2) 2003 Microchip Technology Inc. If Negative PC If Negative PC Preliminary DS39616B-page 297 PIC18F2331/2431/4331/4431 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 ≤ n ≤ 127 Operands: -128 ≤ n ≤ 127 Operation: if overflow bit is ‘0’ (PC) + 2 + 2n → PC Operation: if zero bit is ‘0’ (PC) + 2 + 2n → PC Status Affected: None Status Affected: None Encoding: 1110 n 0101 nnnn nnnn Encoding: 1110 n 0001 nnnn nnnn Description: If the Overflow bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Description: If the Zero bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Words: 1 Cycles: 1(2) Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation No operation No operation No operation No operation Q2 Q3 Q4 Read literal ‘n’ Process Data No operation If No Jump: Q1 Decode Example: HERE BNOV Jump If No Jump: Q1 Decode Example: Before Instruction PC DS39616B-page 298 Q3 Q4 Process Data No operation HERE BNZ Jump Before Instruction = address (HERE) PC After Instruction If Overflow PC If Overflow PC Q2 Read literal ‘n’ = address (HERE) = = = = 0; address (Jump) 1; address (HERE+2) After Instruction = = = = 0; address (Jump) 1; address (HERE+2) If Zero PC If Zero PC Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 ≤ n ≤ 1023 Operands: Operation: (PC) + 2 + 2n → PC Status Affected: None 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operation: 1 → f<b> Status Affected: None Encoding: Description: 1101 1 Cycles: 2 Q Cycle Activity: Q1 No operation 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a twocycle instruction. Words: Decode n Q2 Q3 Q4 Read literal ‘n’ Process Data Write to PC No operation No operation No operation Encoding: HERE BRA 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q3 Q4 Process Data Write register ‘f’ BSF = address (Jump) 2003 Microchip Technology Inc. FLAG_REG, 7 Before Instruction = 0x0A = 0x8A After Instruction FLAG_REG After Instruction PC Q2 Read register ‘f’ FLAG_REG address (HERE) ffff Words: Jump = ffff Bit ‘b’ in register 'f' is set. If ‘a’ is 0, Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value. Before Instruction PC bbba Description: Example: Example: 1000 f,b[,a] Preliminary DS39616B-page 299 PIC18F2331/2431/4331/4431 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 ≤ f ≤ 255 0≤b≤7 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is 0, then the next instruction is skipped. If bit ‘b’ is 0, then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a twocycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Description: If bit ‘b’ in register ‘f’ is 1, then the next instruction is skipped. If bit ‘b’ is 1, then the next instruction fetched during the current instruction execution, is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register ‘f’ Process Data No operation If skip: Q Cycle Activity: Q1 Decode 3 cycles if skip and followed by a 2-word instruction. Q2 Q3 Q4 Read register ‘f’ Process Data No operation If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE FALSE TRUE BTFSC : : FLAG, 1 Example: Before Instruction PC DS39616B-page 300 BTFSS : : FLAG, 1 Before Instruction = address (HERE) PC After Instruction If FLAG<1> PC If FLAG<1> PC HERE FALSE TRUE = address (HERE) = = = = 0; address (FALSE) 1; address (TRUE) After Instruction = = = = 0; address (TRUE) 1; address (FALSE) If FLAG<1> PC If FLAG<1> PC Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 ≤ f ≤ 255 0≤b<7 a ∈ [0,1] Operands: -128 ≤ n ≤ 127 Operation: if overflow bit is ‘1’ (PC) + 2 + 2n → PC Status Affected: None Operation: (f<b>) → f<b> Status Affected: None Encoding: Description: bbba ffff ffff 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: BTG PORTC, = 0111 0101 [0x75] PORTC = 0110 0101 [0x65] nnnn nnnn If the Overflow bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation 4 After Instruction: 0100 Description: Before Instruction: PORTC 1110 Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: Decode Encoding: 0111 n If No Jump: Q1 Decode Q2 Q3 Q4 Read literal ‘n’ Process Data No operation Example: HERE BOV JUMP Before Instruction PC = address (HERE) = = = = 1; address (JUMP) 0; address (HERE+2) After Instruction If Overflow PC If Overflow PC 2003 Microchip Technology Inc. Preliminary DS39616B-page 301 PIC18F2331/2431/4331/4431 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 ≤ n ≤ 127 Operands: Operation: if Zero bit is ‘1’ (PC) + 2 + 2n → PC 0 ≤ k ≤ 1048575 s ∈ [0,1] Operation: (PC) + 4 → TOS, k → PC<20:1>, if s = 1 (W) → WS, (STATUS) → STATUSS, (BSR) → BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. Words: 1 Cycles: 1(2) Q Cycle Activity: If Jump: Q1 Q2 Q3 Q4 Decode Read literal ‘n’ Process Data Write to PC No operation No operation No operation No operation Q2 Q3 Q4 Read literal ‘n’ Process Data No operation If No Jump: Q1 Decode Example: HERE BZ Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k19kkk k7kkk kkkk Description: Subroutine call of entire 2 Mbyte memory range. First, return address (PC+ 4) is pushed onto the return stack. If ‘s’ = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If ‘s’ = 0, no update occurs (default). Then, the 20-bit value ‘k’ is loaded into PC<20:1>. CALL is a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Jump Q2 Q3 Q4 Decode Read literal ‘k’<7:0>, Push PC to stack Read literal ‘k’<19:8>, Write to PC No operation No operation No operation No operation Before Instruction PC = address (HERE) = = = = 1; address (Jump) 0; address (HERE+2) After Instruction If Zero PC If Zero PC kkkk0 kkkk8 Example: HERE CALL THERE,FAST Before Instruction PC = address (HERE) After Instruction PC = TOS = WS = BSRS = STATUSS= DS39616B-page 302 Preliminary address (THERE) address (HERE + 4) W BSR STATUS 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 CLRF Clear f Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: 000h → f 1→Z Status Affected: Z Encoding: Description: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h → WDT, 000h → WDT postscaler, 1 → TO, 1 → PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Clears the contents of the specified register. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Description: CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Decode Example: Example: CLRF FLAG_REG Q4 No operation CLRWDT WDT Counter = 0x5A = 0x00 2003 Microchip Technology Inc. = ? = = = = 0x00 0 1 1 After Instruction After Instruction FLAG_REG Q3 Process Data Before Instruction Before Instruction FLAG_REG Q2 No operation WDT Counter WDT Postscaler TO PD Preliminary DS39616B-page 303 PIC18F2331/2431/4331/4431 COMF Complement f Syntax: [ label ] COMF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: ( f ) → dest Status Affected: N, Z Encoding: 0001 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] CPFSEQ Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None Encoding: 0110 001a f [,a] ffff ffff Description: Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If ‘f’ = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Q2 Q3 Q4 Words: 1 Process Data Write to destination Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. COMF Before Instruction = 0x13 After Instruction REG W ffff Compare f with W, skip if f = W Read register ‘f’ Example: REG ffff The contents of register ‘f’ are complemented. If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: Decode 11da f [,d [,a]] CPFSEQ = = 0x13 0xEC REG, W Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register ‘f'’ Process Data No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NEQUAL EQUAL CPFSEQ REG : : Before Instruction PC Address W REG = = = HERE ? ? = = ≠ = W; Address (EQUAL) W; Address (NEQUAL) After Instruction If REG PC If REG PC DS39616B-page 304 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f) − (W), skip if (f) > (W) (unsigned comparison) Operation: (f) – (W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 010a f [,a] ffff ffff Compares the contents of data memory location ‘f’ to the contents of the W by performing an unsigned subtraction. If the contents of ‘f’ are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Encoding: Q2 Q3 Q4 Process Data No operation Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Q4 No operation If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q4 No operation No operation No operation No operation No operation HERE NLESS LESS CPFSLT REG : : No operation No operation No operation No operation No operation HERE NGREATER GREATER CPFSGT REG : : Example: Before Instruction PC W Before Instruction = = Address (HERE) ? > = ≤ = W; Address (GREATER) W; Address (NGREATER) = = Address (HERE) ? < = ≥ = W; Address (LESS) W; Address (NLESS) After Instruction If REG PC If REG PC After Instruction 2003 Microchip Technology Inc. Q3 Process Data No operation No operation If REG PC If REG PC Q2 Read register ‘f’ No operation No operation PC W ffff No operation No operation Example: ffff Compares the contents of data memory location ‘f’ to the contents of W by performing an unsigned subtraction. If the contents of ‘f’ are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If ‘a’ is 0, the Access Bank will be selected. If ‘a’ is 1, the BSR will not be overridden (default). If skip: Q1 000a Description: Decode Read register ‘f’ 0110 f [,a] Preliminary DS39616B-page 305 PIC18F2331/2431/4331/4431 DAW Decimal Adjust W Register DECF Decrement f Syntax: [ label ] DAW Syntax: [ label ] DECF f [,d [,a]] Operands: None Operands: Operation: If [W<3:0> >9] or [DC = 1] then (W<3:0>) + 6 → W<3:0>; else (W<3:0>) → W<3:0>; 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest Status Affected: C, DC, N, OV, Z Encoding: If [W<7:4> >9] or [C = 1] then (W<7:4>) + 6 → W<7:4>; else (W<7:4>) → W<7:4>; Status Affected: Encoding: 0000 0000 0000 Words: 1 Cycles: 1 Q2 Q3 Q4 Read register W Process Data Write W Example1: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination CNT Z CNT, = = 0x01 0 After Instruction DAW = = = DECF Before Instruction CNT Z Before Instruction W C DC ffff Words: Example: Q Cycle Activity: Q1 ffff Decrement register ‘f’. If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). 0111 DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. The carry bit may be set by DAW regardless of its setting prior to the DAW instruction. 01da Description: C, DC Description: Decode 0000 = = 0x00 1 0xA5 0 0 After Instruction W C DC = = = 0x05 1 0 Example 2: Before Instruction W C DC = = = 0xCE 0 0 After Instruction W C DC = = = DS39616B-page 306 0x34 1 0 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [ label ] DCFSNZ Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – 1 → dest, skip if result = 0 Operation: (f) – 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da f [,d [,a]] ffff ffff Description: The contents of register ‘f’ are decremented. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’ (default). If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Description: The contents of register ‘f’ are decremented. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’ (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a twocycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination If skip: Decode Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE DECFSZ GOTO CNT LOOP Example: CONTINUE Before Instruction PC = = = = ≠ = DCFSNZ : : TEMP Before Instruction Address (HERE) TEMP After Instruction CNT If CNT PC If CNT PC HERE ZERO NZERO = ? = = = ≠ = TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) After Instruction CNT - 1 0; Address (CONTINUE) 0; Address (HERE+2) 2003 Microchip Technology Inc. TEMP If TEMP PC If TEMP PC Preliminary DS39616B-page 307 PIC18F2331/2431/4331/4431 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 1048575 Operands: Operation: k → PC<20:1> Status Affected: None 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range. The 20-bit value ‘k’ is loaded into PC<20:1>. GOTO is always a two-cycle instruction. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’<7:0>, No operation Read literal ‘k’<19:8>, Write to PC No operation No operation No operation No operation Example: GOTO THERE Encoding: f [,d [,a]] 10da ffff ffff Description: The contents of register ‘f’ are incremented. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination Example: After Instruction PC = 0010 INCF INCF CNT, Before Instruction Address (THERE) CNT Z C DC = = = = 0xFF 0 ? ? After Instruction CNT Z C DC DS39616B-page 308 Preliminary = = = = 0x00 1 1 1 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) + 1 → dest, skip if result = 0 Operation: (f) + 1 → dest, skip if result ≠ 0 Status Affected: None Status Affected: None Encoding: 0011 INCFSZ 11da f [,d [,a]] ffff ffff Encoding: 0100 INFSNZ 10da f [,d [,a]] ffff ffff Description: The contents of register ‘f’ are incremented. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’. (default) If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a two-cycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Description: The contents of register ‘f’ are incremented. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’ (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead, making it a twocycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode Q Cycle Activity: Q1 Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination If skip: Decode Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination If skip: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 Q4 No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO INCFSZ : : CNT Example: Before Instruction PC = = = = ≠ = INFSNZ REG Before Instruction Address (HERE) PC After Instruction CNT If CNT PC If CNT PC HERE ZERO NZERO = Address (HERE) After Instruction CNT + 1 0; Address (ZERO) 0; Address (NZERO) 2003 Microchip Technology Inc. REG If REG PC If REG PC Preliminary = ≠ = = = REG + 1 0; Address (NZERO) 0; Address (ZERO) DS39616B-page 309 PIC18F2331/2431/4331/4431 IORLW Inclusive OR literal with W IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .OR. (f) → dest Status Affected: N, Z IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → W Status Affected: N, Z Encoding: 0000 Description: kkkk kkkk The contents of W are OR’ed with the eight-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W IORLW Before Instruction W 1001 = 0x9A 0x35 Encoding: = 00da f [,d [,a]] ffff ffff Description: Inclusive OR W with register ‘f’. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 After Instruction W 0001 IORWF Decode 0xBF Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination Example: IORWF RESULT, W Before Instruction RESULT = W = 0x13 0x91 After Instruction RESULT = W = DS39616B-page 310 Preliminary 0x13 0x93 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 LFSR Load FSR MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0≤f≤2 0 ≤ k ≤ 4095 Operands: Operation: k → FSRf 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Status Affected: None Operation: f → dest Status Affected: N, Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the file select register pointed to by ‘f’. Words: 2 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ MSB Process Data Write literal ‘k’ MSB to FSRfH Decode Read literal ‘k’ LSB Process Data Write literal ‘k’ to FSRfL Example: LFSR 2, 0x3AB After Instruction FSR2H FSR2L = = Encoding: MOVF 0101 00da f [,d [,a]] ffff ffff Description: The contents of register ‘f’ are moved to a destination dependent upon the status of ‘d’. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’ (default). Location ‘f’ can be anywhere in the 256 byte bank. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 0x03 0xAB Example: Q2 Q3 Q4 Read register ‘f’ Process Data Write W MOVF REG, W Before Instruction REG W = = 0x22 0xFF = = 0x22 0x22 After Instruction REG W 2003 Microchip Technology Inc. Preliminary DS39616B-page 311 PIC18F2331/2431/4331/4431 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ fs ≤ 4095 0 ≤ fd ≤ 4095 Operands: 0 ≤ k ≤ 255 Operation: k → BSR None MOVFF fs,fd Operation: (fs) → fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’. Location of source ‘fs’ can be anywhere in the 4096 byte data space (000h to FFFh) and location of destination ‘fd’ can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). MOVLB k 0000 0001 kkkk kkkk Description: The 8-bit literal ‘k’ is loaded into the Bank Select Register (BSR). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read literal ‘k’ Process Data Write literal ‘k’ to BSR MOVLB 5 Before Instruction BSR register = 0x02 = 0x05 After Instruction BSR register The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. The MOVFF instruction should not be used to modify interrupt settings while any interrupt is enabled (see the note on page 91). Words: 2 Cycles: 2 (3) Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register ‘f’ (src) Process Data No operation Decode No operation No operation Write register ‘f’ (dest) No dummy read Example: MOVFF REG1, REG2 Before Instruction REG1 REG2 = = 0x33 0x11 = = 0x33, 0x33 After Instruction REG1 REG2 DS39616B-page 312 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 MOVLW Move literal to W MOVWF Move W to f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: Operation: k→W 0 ≤ f ≤ 255 a ∈ [0,1] Status Affected: None Operation: (W) → f Status Affected: None Encoding: 0000 Description: MOVLW k 1110 kkkk The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W MOVLW 0x5A After Instruction W kkkk = Encoding: 0110 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 111a f [,a] ffff ffff Move data from W to register ‘f’. Location ‘f’ can be anywhere in the 256 byte bank. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). Words: 0x5A MOVWF Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: MOVWF REG Before Instruction W REG = = 0x4F 0xFF After Instruction W REG 2003 Microchip Technology Inc. Preliminary = = 0x4F 0x4F DS39616B-page 313 PIC18F2331/2431/4331/4431 MULLW Multiply Literal with W MULWF Multiply W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (W) x (f) → PRODH:PRODL Status Affected: None MULLW k Operands: 0 ≤ k ≤ 255 Operation: (W) x k → PRODH:PRODL Status Affected: None Encoding: Description: 0000 1 Cycles: 1 Q Cycle Activity: Q1 Example: kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. Words: Decode 1101 Q2 Q3 Q4 Read literal ‘k’ Process Data Write registers PRODH: PRODL MULLW 0xC4 Before Instruction W PRODH PRODL = = = 0xE2 ? ? = = = 0xE2 0xAD 0x08 Encoding: Description: 0000 001a 1 Cycles: 1 Q Cycle Activity: Q1 Example: ffff ffff Q2 Q3 Q4 Read register ‘f’ Process Data Write registers PRODH: PRODL After Instruction W PRODH PRODL f [,a] An unsigned multiplication is carried out between the contents of W and the register file location ‘f’. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and ‘f’ are unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’= 1, then the bank will be selected as per the BSR value (default). Words: Decode MULWF MULWF REG Before Instruction W REG PRODH PRODL = = = = 0xC4 0xB5 ? ? = = = = 0xC4 0xB5 0x8A 0x94 After Instruction W REG PRODH PRODL DS39616B-page 314 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 NEGF Negate f Syntax: [ label ] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] NEGF Operation: (f)+1→f Status Affected: N, OV, C, DC, Z Encoding: 0110 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff Description: 1 Cycles: 1 Decode 0000 xxxx 0000 xxxx No operation. Words: Q Cycle Activity: Q1 0000 xxxx Q2 Q3 Q4 No operation No operation No operation Example: Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ Example: No Operation Encoding: ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value. Words: Decode 110a f [,a] NOP NEGF None. REG, 1 Before Instruction REG = 0011 1010 [0x3A] After Instruction REG = 1100 0110 [0xC6] 2003 Microchip Technology Inc. Preliminary DS39616B-page 315 PIC18F2331/2431/4331/4431 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) → bit bucket Operation: (PC+2) → TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode POP Encoding: Q2 Q3 Q4 POP TOS value No operation 1 Cycles: 1 = = DS39616B-page 316 = = Q3 Q4 No operation No operation PUSH TOS PC 0x0031A2 0x014332 = = 0x00345A 0x000124 = = = 0x000126 0x000126 0x00345A After Instruction PC TOS Stack (1 level down) After Instruction TOS PC Q2 PUSH PC+2 onto return stack Before Instruction NEW Before Instruction TOS Stack (1 level down) 0101 Words: Example: POP GOTO 0000 The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows to implement a software stack by modifying TOS, and then push it onto the return stack. Q Cycle Activity: Q1 No operation 0000 Description: Decode Example: 0000 PUSH 0x014332 NEW Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL Syntax: [ label ] Operands: Operation: -1024 ≤ n ≤ 1023 Operands: None (PC) + 2 → TOS, (PC) + 2 + 2n → PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: Description: 1101 nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Decode 1nnn n Encoding: 0000 RESET 0000 1111 1111 Description: This instruction provides a way to execute a MCLR Reset in software. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Start reset No operation No operation RESET After Instruction Registers = Flags* = Q2 Q3 Q4 Read literal ‘n’ Process Data Write to PC No operation No operation Reset Value Reset Value Push PC to stack No operation Example: No operation HERE RCALL Jump Before Instruction PC = Address (HERE) After Instruction PC = TOS = Address (Jump) Address (HERE+2) 2003 Microchip Technology Inc. Preliminary DS39616B-page 317 PIC18F2331/2431/4331/4431 RETFIE Return from Interrupt RETLW Return Literal to W Syntax: [ label ] Syntax: [ label ] RETFIE [s] RETLW k Operands: s ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (TOS) → PC, 1 → GIE/GIEH or PEIE/GIEL, if s = 1 (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged. Operation: k → W, (TOS) → PC, PCLATU, PCLATH are unchanged Status Affected: None Status Affected: 0000 Description: 0000 0001 1 Cycles: 2 Q Cycle Activity: Q1 kkkk kkkk W is loaded with the eight-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read literal ‘k’ Process Data pop PC from stack, Write to W No operation No operation No operation No operation Example: Q2 Q3 Q4 No operation No operation pop PC from stack Set GIEH or GIEL No operation Example: 1100 Description: 000s Return from Interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If ‘s’ = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: No operation 0000 GIE/GIEH, PEIE/GIEL. Encoding: Decode Encoding: RETFIE No operation No operation 1 CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; W contains table offset value W now has table value W = offset Begin table End of table After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL DS39616B-page 318 = = = = = Before Instruction TOS WS BSRS STATUSS 1 W = 0x07 After Instruction W Preliminary = value of kn 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] RETURN [s] RLCF f [,d [,a]] Operands: s ∈ [0,1] Operands: Operation: (TOS) → PC, if s = 1 (WS) → W, (STATUSS) → STATUS, (BSRS) → BSR, PCLATU, PCLATH are unchanged 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n+1>, (f<7>) → C, (C) → dest<0> Status Affected: C, N, Z None Encoding: Status Affected: Encoding: 0000 0000 0001 001s Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If ‘s’= 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, W, STATUS and BSR. If ‘s’ = 0, no update of these registers occurs (default). Words: 1 Cycles: 2 Q Cycle Activity: Q1 0011 Description: Q2 Q3 Q4 No operation Process Data pop PC from stack No operation No operation No operation No operation Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode ffff register f Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination Example: RETURN ffff The contents of register ‘f’ are rotated one bit to the left through the Carry Flag. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is stored back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ = 1, then the bank will be selected as per the BSR value (default). C Decode Example: 01da RLCF REG, W Before Instruction REG C After Interrupt PC = TOS = = 1110 0110 0 After Instruction REG W C 2003 Microchip Technology Inc. Preliminary = = = 1110 0110 1100 1100 1 DS39616B-page 319 PIC18F2331/2431/4331/4431 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<n>) → dest<n+1>, (f<7>) → dest<0> Operation: Status Affected: N, Z (f<n>) → dest<n-1>, (f<0>) → C, (C) → dest<7> Status Affected: C, N, Z Encoding: 0100 Description: RLNCF 01da f [,d [,a]] ffff ffff The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is stored back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). Encoding: 0011 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q3 Q4 Read register ‘f’ Process Data Write to destination Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode RLNCF REG ffff ffff register f C Q2 Example: 00da f [,d [,a]] The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). register f Words: RRCF Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination Before Instruction REG = 1010 1011 Example: After Instruction REG = RRCF REG, W Before Instruction REG C 0101 0111 = = 1110 0110 0 After Instruction REG W C DS39616B-page 320 Preliminary = = = 1110 0110 0111 0011 0 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] SETF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operation: (f<n>) → dest<n-1>, (f<0>) → dest<7> FFh → f Operation: Status Affected: None Status Affected: N, Z Encoding: 0100 Description: RRNCF 00da f [,d [,a]] Encoding: ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). 1 Cycles: 1 ffff ffff The contents of the specified register are set to FFh. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q2 Q3 Q4 Read register ‘f’ Process Data Write register ‘f’ SETF REG Before Instruction Q Cycle Activity: Q1 Decode 100a Description: register f Words: 0110 f [,a] REG Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination Example 1: RRNCF = 0x5A = 0xFF After Instruction REG REG, 1, 0 Before Instruction REG = 1101 0111 After Instruction REG = Example 2: 1110 1011 RRNCF REG, W Before Instruction W REG = = ? 1101 0111 After Instruction W REG = = 1110 1011 1101 0111 2003 Microchip Technology Inc. Preliminary DS39616B-page 321 PIC18F2331/2431/4331/4431 SLEEP Enter Sleep mode SUBFWB Subtract f from W with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB Operands: None Operands: Operation: 00h → WDT, 0 → WDT postscaler, 1 → TO, 0 → PD 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) – (f) – (C) → dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The power-down status bit (PD) is cleared. The time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 No operation Process Data Go to sleep Example: TO = PD = ? ? ffff ffff Subtract register ‘f’ and carry flag (borrow) from W (2’s complement method). If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination Example 1: SUBFWB REG Before Instruction After Instruction TO = PD = 01da Description: SLEEP Before Instruction 0101 f [,d [,a]] REG W C 1† 0 = = = 0x03 0x02 0x01 After Instruction † If WDT causes wake-up, this bit is cleared. REG W C Z N = = = = = Example 2: 0xFF 0x02 0x00 0x00 0x01 SUBFWB ; result is negative REG, 0, 0 Before Instruction REG W C = = = 2 5 1 After Instruction REG W C Z N = = = = = Example 3: 2 3 1 0 0 ; result is positive SUBFWB REG, 1, 0 Before Instruction REG W C = = = 1 2 0 After Instruction REG W C Z N DS39616B-page 322 Preliminary = = = = = 0 2 1 1 0 ; result is zero 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 SUBLW Subtract W from literal SUBWF Subtract W from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF Operands: 0 ≤ k ≤ 255 Operands: Operation: k – (W) → W Status Affected: N, OV, C, DC, Z 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) → dest Status Affected: N, OV, C, DC, Z Encoding: 0000 1000 kkkk kkkk Description: W is subtracted from the eight-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example 1: SUBLW 0x02 Before Instruction W C = = 1 ? = = = = Example 2: 1 1 0 0 SUBLW = = Example 3: 0 1 1 0 SUBLW 1 Cycles: 1 Decode ; result is positive = = = = = = Q3 Q4 Process Data Write to destination SUBWF REG Before Instruction 0x02 REG W C = = = 3 2 ? After Instruction REG W C Z N ; result is zero 0x02 = = = = = Example 2: 1 2 1 0 0 ; result is positive SUBWF REG, W Before Instruction REG W C 3 ? After Instruction W C Z N Q2 Read register ‘f’ Example 1: Before Instruction W C ffff Words: 2 ? = = = = ffff Subtract W from register ‘f’ (2’s complement method). If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored back in register ‘f’ (default). If = ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). After Instruction W C Z N 11da Description: Before Instruction W C 0101 Q Cycle Activity: Q1 After Instruction W C Z N Encoding: f [,d [,a]] = = = 2 2 ? After Instruction FF ; (2’s complement) 0 ; result is negative 0 1 REG W C Z N = = = = = Example 3: 2 0 1 1 0 ; result is zero SUBWF REG Before Instruction REG W C = = = 0x01 0x02 ? After Instruction REG W C Z N 2003 Microchip Technology Inc. Preliminary = = = = = 0xFFh ;(2’s complement) 0x02 0x00 ; result is negative 0x00 0x01 DS39616B-page 323 PIC18F2331/2431/4331/4431 SUBWFB Subtract W from f with Borrow Syntax: [ label ] SUBWFB Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f) – (W) – (C) → dest Status Affected: N, OV, C, DC, Z Encoding: Description: 0101 1 Cycles: 1 Q Cycle Activity: Q1 Decode SUBWFB REG, 1, 0 Before Instruction f [,d [,a]] REG W C = = = 0x19 0x0D 0x01 (0001 1001) (0000 1101) 0x0C 0x0D 0x01 0x00 0x00 (0000 1011) (0000 1101) After Instruction 10da ffff REG W C Z N ffff Subtract W and the carry flag (borrow) from register ‘f’ (2’s complement method). If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored back in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). Words: Example 1: = = = = = Example 2: ; result is positive SUBWFB REG, 0, 0 Before Instruction REG W C = = = 0x1B 0x1A 0x00 (0001 1011) (0001 1010) 0x1B 0x00 0x01 0x01 0x00 (0001 1011) After Instruction REG W C Z N = = = = = Example 3: SUBWFB ; result is zero REG, 1, 0 Before Instruction Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination DS39616B-page 324 Preliminary REG W C = = = 0x03 0x0E 0x01 (0000 0011) (0000 1101) (1111 0100) ; [2’s comp] (0000 1101) After Instruction REG = 0xF5 W C Z N = = = = 0x0E 0x00 0x00 0x01 ; result is negative 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 SWAPF Swap f Syntax: [ label ] SWAPF f [,d [,a]] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (f<3:0>) → dest<7:4>, (f<7:4>) → dest<3:0> Status Affected: None Encoding: 0011 Description: ffff ffff The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is 0, the result is placed in W. If ‘d’ is 1, the result is placed in register ‘f’ (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 10da Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination Example: SWAPF REG Before Instruction REG = 0x53 After Instruction REG = 0x35 2003 Microchip Technology Inc. Preliminary DS39616B-page 325 PIC18F2331/2431/4331/4431 TBLRD Table Read TBLRD Table Read (cont’d) Syntax: [ label ] Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) → TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) +1 → TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) → TABLAT; (TBLPTR) -1 → TBLPTR; if TBLRD +*, (TBLPTR) +1 → TBLPTR; (Prog Mem (TBLPTR)) → TABLAT; TBLRD ( *; *+; *-; +*) Before Instruction TABLAT TBLPTR MEMORY(0x00A356) Description: 0000 0000 0000 = = = 0x55 0x00A356 0x34 = = 0x34 0x00A357 After Instruction TABLAT TBLPTR Example2: Status Affected:None Encoding: *+ ; 10nn nn=0 * =1 *+ =2 *=3 +* TBLRD +* ; Before Instruction TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358) = = = = 0xAA 0x01A357 0x12 0x34 = = 0x34 0x01A358 After Instruction TABLAT TBLPTR This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read Program Memory) DS39616B-page 326 No No operation operation (Write TABLAT) Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] Words: 1 TBLWT ( *; *+; *-; +*) Operands: None Cycles: 2 Operation: if TBLWT*, (TABLAT) → Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) → Holding Register; (TBLPTR) +1 → TBLPTR; if TBLWT*-, (TABLAT) → Holding Register; (TBLPTR) -1 → TBLPTR; if TBLWT+*, (TBLPTR) +1 → TBLPTR; (TABLAT) → Holding Register; Q Cycle Activity: Description: 0000 Q2 Q3 Q4 Decode No operation No operation No operation No operation No operation (Read TABLAT) No operation No operation (Write to Holding Register ) Example1: TBLWT *+; Before Instruction Status Affected: None Encoding: Q1 0000 0000 This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 “Flash Program Memory” for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: • no change • post-increment • post-decrement • pre-increment 2003 Microchip Technology Inc. TABLAT TBLPTR HOLDING REGISTER (0x00A356) 11nn nn=0 * =1 *+ =2 *=3 +* = = 0x55 0x00A356 = 0xFF After Instructions (table write completion) TABLAT TBLPTR HOLDING REGISTER (0x00A356) Example 2: Preliminary TBLWT = = 0x55 0x00A357 = 0x55 +*; Before Instruction TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) = = 0x34 0x01389A = 0xFF = 0xFF After Instruction (table write completion) TABLAT TBLPTR HOLDING REGISTER (0x01389A) HOLDING REGISTER (0x01389B) = = 0x34 0x01389B = 0xFF = 0x34 DS39616B-page 327 PIC18F2331/2431/4331/4431 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 255 a ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: Operation: skip if f = 0 (W) .XOR. k → W Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: 011a ffff ffff If ‘f’ = 0, the next instruction, fetched during the current instruction execution, is discarded and a NOP is executed, making this a twocycle instruction. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q Cycle Activity: Q1 Decode 0000 1010 kkkk kkkk Description: The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: XORLW 0xAF Before Instruction W = 0xB5 After Instruction Q2 Q3 Q4 Read register ‘f’ Process Data No operation W = 0x1A If skip: Q1 Q2 Q3 Q4 No operation No operation No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 Q4 No operation No operation No operation No operation No operation No operation No operation No operation Example: HERE NZERO ZERO TSTFSZ : CNT : Before Instruction PC = Address (HERE) After Instruction If CNT PC If CNT PC DS39616B-page 328 = = ≠ = 0x00, Address (ZERO) 0x00, Address (NZERO) Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 XORWF Exclusive OR W with f Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] a ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: N, Z Encoding: 0001 10da f [,d [,a]] ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is 0, the result is stored in W. If ‘d’ is 1, the result is stored back in the register ‘f' (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value. If ‘a’ is 1, then the bank will be selected as per the BSR value (default). Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Q2 Q3 Q4 Read register ‘f’ Process Data Write to destination Example: XORWF REG Before Instruction REG W = = 0xAF 0xB5 After Instruction REG W = = 0x1A 0xB5 2003 Microchip Technology Inc. Preliminary DS39616B-page 329 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 330 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 24.0 DEVELOPMENT SUPPORT 24.1 The PICmicro® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PRO MATE® II Universal Device Programmer - PICSTART® Plus Development Programmer • Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board • Evaluation Kits - KEELOQ® - PICDEM MSC - microID® - CAN - PowerSmart® - Analog MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® based application that contains: • An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) • A full-featured editor with color coded context • A multiple project manager • Customizable data windows with direct edit of contents • High level source code debugging • Mouse over variable inspection • Extensive on-line help The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) • Debug using: - source files (assembly or C) - absolute listing file (mixed assembly and C) - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power. 24.2 MPASM Assembler The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process 2003 Microchip Technology Inc. Preliminary DS39616B-page331 PIC18F2331/2431/4331/4431 24.3 MPLAB C17 and MPLAB C18 C Compilers 24.6 The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 24.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of pre-compiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 24.5 MPLAB C30 C Compiler MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping, and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high level source debugging with the MPLAB IDE. DS39616B-page 332 MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it’s object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 24.7 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-step, Execute-UntilBreak or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 24.8 The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many commandline options and language extensions to take full advantage of the dsPIC30F device hardware capabilities, and afford fine control of the compiler code generator. MPLAB ASM30 Assembler, Linker, and Librarian MPLAB SIM30 Software Simulator The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 24.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator 24.11 MPLAB ICD 2 In-Circuit Debugger The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 24.10 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory, and the ability to view variables in real-time. Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface. This tool is based on the Flash PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real-time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices. 24.12 PRO MATE II Universal Device Programmer The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-alone mode, the PRO MATE II device programmer can read, verify, and program PICmicro devices without a PC connection. It can also set code protection in this mode. 24.13 PICSTART Plus Development Programmer The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 2003 Microchip Technology Inc. Preliminary DS39616B-page333 PIC18F2331/2431/4331/4431 24.14 PICDEM 1 PICmicro Demonstration Board 24.17 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer, or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs. The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs. 24.15 PICDEM.net Internet/Ethernet Demonstration Board The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface, and a 16 x 2 LCD display. Also included is the book and CD-ROM “TCP/IP Lean, Web Servers for Embedded Systems,” by Jeremy Bentham 24.16 PICDEM 2 Plus Demonstration Board The PICDEM 2 Plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs, and sample PIC18F452 and PIC16F877 Flash microcontrollers. DS39616B-page 334 24.18 PICDEM 4 8/14/18-Pin Demonstration Board The PICDEM 4 can be used to demonstrate the capabilities of the 8-, 14-, and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low-power operation with the supercapacitor circuit, and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2x16 liquid crystal display, PCB footprints for H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide. 24.19 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion. Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 24.20 PICDEM 18R PIC18C601/801 Demonstration Board 24.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/De-multiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801. The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products. In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. 24.21 PICDEM LIN PIC16C43X Demonstration Board The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 Flash microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication. 24.22 PICkitTM 1 Flash Starter Kit A complete "development system in a box", the PICkit Flash Starter Kit includes a convenient multi-section board for programming, evaluation, and development of 8/14-pin Flash PIC® microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the user's guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB® IDE (Integrated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin Flash PIC® Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. 2003 Microchip Technology Inc. 24.24 Evaluation and Programming Tools • KEELOQ evaluation and programming tools for Microchip’s HCS Secure Data Products • CAN developers kit for automotive network applications • Analog design boards and filter design software • PowerSmart battery charging evaluation/ calibration kits • IrDA® development kit • microID development and rfLabTM development software • SEEVAL® designer kit for memory evaluation and endurance calculations • PICDEM MSC demo boards for Switching mode power supply, high power IR driver, delta sigma ADC, and flow rate sensor Check the Microchip web page and the latest Product Line Card for the complete list of demonstration and evaluation kits. Preliminary DS39616B-page335 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 336 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2003 Microchip Technology Inc. Preliminary DS39616B-page 337 PIC18F2331/2431/4331/4431 FIGURE 25-1: PIC18F2331/2431/4331/4431 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V 5.0V PIC18F2X31/4X31 Voltage 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz Frequency FIGURE 25-2: PIC18LF2331/2431/4331/4431 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V PIC18LF2X31/4X31 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 40 MHz 4 MHz Frequency FMAX = (16.36 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. DS39616B-page 338 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.1 DC Characteristics: Supply Voltage PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Symbol VDD D001 Characteristic Min Typ Max Units Supply Voltage PIC18LF2X31/4X31 2.0 — 5.5 V PIC18F2X31/4X31 4.2 — 5.5 V D002 VDR RAM Data Retention Voltage(1) 1.5 — — V D003 VPOR VDD Start Voltage to ensure internal Poweron Reset signal — — 0.7 V D004 SVDD VDD Rise Rate to ensure internal Poweron Reset signal 0.05 — — BORV1:BORV0 = 10 2.45 — 2.99 V BORV1:BORV0 = 01 3.80 — 4.64 V BORV1:BORV0 = 00 4.09 — 4.99 V VBOR D005 Conditions HS, XT, RC and LP Osc mode See section on Power-on Reset for details V/ms See section on Power-on Reset for details Brown-out Reset Voltage Legend: Shading of rows is to assist in readability of the table. Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. 2003 Microchip Technology Inc. Preliminary DS39616B-page 339 PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Typ Max Units Conditions 0.1 0.5 µA -40°C 0.1 0.5 µA 25°C 0.2 1.9 µA 85°C 0.1 0.5 µA -40°C 0.1 0.5 µA 25°C 0.3 1.9 µA 85°C 0.1 2.0 µA -40°C 0.1 2.0 µA 25°C 0.4 6.5 µA 85°C Power-down Current (IPD)(1) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: VDD = 2.0V, (Sleep mode) VDD = 3.0V, (Sleep mode) VDD = 5.0V, (Sleep mode) Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39616B-page 340 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Typ Max Units Conditions 8 40 µA -40°C 9 40 µA 25°C Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: 11 40 µA 85°C 25 68 µA -40°C 25 68 µA 25°C 20 68 µA 85°C 55 180 µA -40°C 55 180 µA 25°C 50 180 µA 85°C 140 220 µA -40°C 145 220 µA 25°C 155 220 µA 85°C 215 330 µA -40°C 225 330 µA 25°C 235 330 µA 85°C 385 550 µA -40°C 390 550 µA 25°C 405 550 µA 85°C VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 2003 Microchip Technology Inc. Preliminary DS39616B-page 341 PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: Typ Max Units 410 600 µA Conditions -40°C 425 600 µA 25°C 435 600 µA 85°C 650 900 µA -40°C 670 900 µA 25°C 680 900 µA 85°C 1.2 1.8 mA -40°C 1.2 1.8 mA 25°C 1.2 1.8 mA 85°C VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39616B-page 342 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: 4.7 8 µA -40°C 5.0 8 µA 25°C 5.8 11 µA 85°C 7.0 11 µA -40°C 7.8 11 µA 25°C 8.7 15 µA 85°C 12 16 µA -40°C 14 16 µA 25°C 14 22 µA 85°C 75 150 µA -40°C 85 150 µA 25°C 95 150 µA 85°C 110 180 µA -40°C 125 180 µA 25°C 135 180 µA 85°C 180 300 µA -40°C 195 300 µA 25°C 200 300 µA 85°C VDD = 2.0V VDD = 3.0V FOSC = 31 kHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 2003 Microchip Technology Inc. Preliminary DS39616B-page 343 PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: Typ Max Units 175 275 µA Conditions -40°C 185 275 µA 25°C 195 275 µA 85°C 265 375 µA -40°C 280 375 µA 25°C 300 375 µA 85°C 475 800 µA -40°C 500 800 µA 25°C 505 800 µA 85°C VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (RC_IDLE mode, Internal oscillator source) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39616B-page 344 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices All devices All devices Legend: Note 1: 2: 3: 4: 150 250 µA -40°C 150 250 µA 25°C 160 250 µA 85°C 340 350 µA -40°C 300 350 µA 25°C 280 350 µA 85°C 0.72 1.0 mA -40°C 0.63 1.0 mA 25°C 0.57 1.0 mA 85°C 440 600 µA -40°C 450 600 µA 25°C 460 600 µA 85°C 0.80 1.0 mA -40°C 0.78 1.0 mA 25°C 0.77 1.0 mA 85°C -40°C 1.6 2.0 mA 1.5 2.0 mA 25°C 1.5 2.0 mA 85°C 9.5 12 mA -40°C 9.7 12 mA 25°C 9.9 12 mA 85°C -40°C 11.9 15 mA 12.1 15 mA 25°C 12.3 15 mA 85°C VDD = 2.0V VDD = 3.0V FOSC = 1 MHZ (PRI_RUN, EC oscillator) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (PRI_RUN, EC oscillator) VDD = 5.0V VDD = 4.2V FOSC = 40 MHZ (PRI_RUN, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 2003 Microchip Technology Inc. Preliminary DS39616B-page 345 PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices All devices All devices Legend: Note 1: 2: 3: 4: 35 50 µA -40°C 35 50 µA 25°C 35 60 µA 85°C 55 80 µA -40°C 50 80 µA 25°C 60 100 µA 85°C 105 150 µA -40°C 110 150 µA 25°C 115 150 µA 85°C 135 180 µA -40°C 140 180 µA 25°C 140 180 µA 85°C 215 280 µA -40°C 225 280 µA 25°C 230 280 µA 85°C 410 525 µA -40°C 420 525 µA 25°C 430 525 µA 85°C -40°C 3.2 4.1 mA 3.2 4.1 mA 25°C 3.3 4.1 mA 85°C -40°C 4.0 5.1 mA 4.1 5.1 mA 25°C 4.1 5.1 mA 85°C VDD = 2.0V VDD = 3.0V FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V VDD = 2.0V VDD = 3.0V FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V VDD = 4.2 V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39616B-page 346 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Typ Max Units Conditions Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices 5.1 9 µA -10°C 5.8 9 µA 25°C 7.9 11 µA 70°C 7.9 12 µA -10°C 8.9 12 µA 25°C 10.5 14 µA 70°C 12.5 20 µA -10°C 16.3 20 µA 25°C 18.9 25 µA 70°C VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) VDD = 5.0V Supply Current (IDD)(2,3) PIC18LF2X31/4X31 PIC18LF2X31/4X31 All devices Legend: Note 1: 2: 3: 4: 9.2 15 µA -10°C 9.6 15 µA 25°C 12.7 18 µA 70°C 22.0 30 µA -10°C 21.0 30 µA 25°C 20.0 35 µA 70°C 30 80 µA -10°C 45 80 µA 25°C 45 85 µA 70°C VDD = 2.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) VDD = 5.0V Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. 2003 Microchip Technology Inc. Preliminary DS39616B-page 347 PIC18F2331/2431/4331/4431 25.2 DC Characteristics: Power-Down and Supply Current PIC18F2331/2431/4331/4431 (Industrial, Extended) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) PIC18F2331/2431/4331/4431 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Typ Max Units Conditions Module Differential Currents (∆IWDT, ∆IBOR, ∆ILVD, ∆IOSCB, ∆IAD) D022 (∆IWDT) D022A Watchdog Timer Brown-out Reset (∆IBOR) D022B Low-Voltage Detect (∆ILVD) D025 Timer1 Oscillator (∆IOSCB) D026 (∆IAD) A/D Converter Legend: Note 1: 2: 3: 4: 1.5 4.0 µA -40°C 2.2 4.0 µA 25°C 3.1 5.0 µA 85°C 2.5 6.0 µA -40°C 3.3 6.0 µA 25°C 4.7 7.0 µA 85°C 3.7 10.0 µA -40°C 4.5 10.0 µA 25°C 6.1 13.0 µA 85°C 19 35.0 µA -40°C to +85°C VDD = 3.0V 24 45.0 µA -40°C to +85°C VDD = 5.0V 8.5 25.0 µA -40°C to +85°C VDD = 2.0V 16 35.0 µA -40°C to +85°C VDD = 3.0V 20 45.0 µA -40°C to +85°C VDD = 5.0V 1.7 3.5 µA -40°C 1.8 3.5 µA 25°C 2.1 4.5 µA 85°C 2.2 4.5 µA -40°C 2.6 4.5 µA 25°C 2.8 5.5 µA 85°C 3.0 6.0 µA -40°C 3.3 6.0 µA 25°C VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 2.0V 32 kHz on Timer1(4) VDD = 3.0V 32 kHz on Timer1(4) VDD = 5.0V 32 kHz on Timer1(4) 3.6 7.0 µA 85°C 1.0 3.0 µA -40°C to 85°C VDD = 2.0V 1.0 4.0 µA -40°C to 85°C VDD = 3.0V 2.0 10.0 µA -40°C to 85°C VDD = 5.0V A/D on, not converting Shading of rows is to assist in readability of the table. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ. Standard low cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature crystals are available at a much higher cost. DS39616B-page 348 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.3 DC Characteristics: PIC18F2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/4431 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Max Units Conditions VSS 0.15 VDD V VDD < 4.5V — 0.8 V 4.5V ≤ VDD ≤ 5.5V VSS VSS 0.2 VDD 0.3 VDD V V Input Low Voltage I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer RC3 and RC4 D032 MCLR VSS 0.2 VDD V D032A OSC1 and T1OSI VSS 0.3 VDD V LP, XT, HS, HSPLL modes(1) D033 OSC1 VSS 0.2 VDD V EC mode(1) 0.25 VDD + 0.8V VDD V VDD < 4.5V 4.5V ≤ VDD ≤ 5.5V VIH Input High Voltage I/O ports: D040 with TTL buffer D040A D041 with Schmitt Trigger buffer RC3 and RC4 2.0 VDD V 0.8 VDD 0.7 VDD VDD VDD V V D042 MCLR 0.8 VDD VDD V D042A OSC1 and T1OSI 0.7 VDD VDD V LP, XT, HS, HSPLL modes(1) D043 OSC1 0.8 VDD VDD V EC mode(1) IIL Input Leakage Current(2,3) D060 I/O ports — ±1 µA VSS ≤ VPIN ≤ VDD, Pin at hi-impedance D061 MCLR — ±1 µA Vss ≤ VPIN ≤ VDD OSC1 — ±1 µA Vss ≤ VPIN ≤ VDD 50 400 µA VDD = 5V, VPIN = VSS D063 D070 Note 1: 2: 3: 4: IPU Weak Pull-up Current IPURB PORTB weak pull-up current In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. 2003 Microchip Technology Inc. Preliminary DS39616B-page 349 PIC18F2331/2431/4331/4431 25.3 DC Characteristics: PIC18F2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/4431 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC CHARACTERISTICS Param Symbol No. VOL Characteristic Min Max Units Conditions Output Low Voltage D080 I/O ports — 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C D083 OSC2/CLKO (RC, RCIO, EC, ECIO modes) — 0.6 V IOL = 1.6 mA, VDD = 4.5V, -40°C to +85°C VOH Output High Voltage(3) D090 I/O ports VDD – 0.7 — V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C D092 OSC2/CLKO (RC, RCIO, EC, ECIO modes) VDD – 0.7 — V IOH = -1.3 mA, VDD = 4.5V, -40°C to +85°C — 8.5 V RA4 pin D150 VOD Open-Drain High Voltage Capacitive Loading Specs on Output Pins D100(4) COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 D101 CIO All I/O pins and OSC2 (in RC mode) — 50 pF To meet the AC Timing Specifications D102 CB SCL, SDA — 400 pF I2C™ Specification Note 1: 2: 3: 4: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Parameter is characterized but not tested. DS39616B-page 350 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 TABLE 25-1: MEMORY PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial DC Characteristics Param No. Sym Characteristic Min Typ† Max Units Conditions Internal Program Memory Programming Specifications(1) D110 VPP Voltage on MCLR/VPP pin 9.00 — 13.25 V (Note 3) D112 IPP Current into MCLR/VPP pin — — 300 µA D113 IDDP Supply Current during Programming — — 1 mA E/W -40°C to +85°C Data EEPROM Memory D120 ED Byte Endurance 100K 1M — D121 VDRW VDD for Read/Write VMIN — 5.5 V D122 TDEW Erase/Write Cycle Time — 4 — ms D123 TRETD Characteristic Retention 40 — — Year Provided no other specifications are violated D124 TREF 1M 10M — E/W -40°C to +85°C D130 EP Cell Endurance 10K 100K — E/W -40°C to +85°C D131 VPR VDD for Read VMIN — 5.5 V VMIN = Minimum operating voltage D132 VIE VDD for Block Erase 4.5 — 5.5 V Using ICSP port D132A VIW VDD for Externally Timed Erase or Write 4.5 — 5.5 V Using ICSP port D132B VPEW VDD for Self-timed Write VMIN — 5.5 V VMIN = Minimum operating voltage D133 ICSP Block Erase Cycle Time — 4 — ms VDD > 4.5V D133A TIW ICSP Erase or Write Cycle Time (externally timed) 1 — — ms VDD > 4.5V D133A TIW Self-timed Write Cycle Time — 2 — Characteristic Retention 40 100 — Number of Total Erase/Write Cycles before Refresh(2) Using EECON to read/write VMIN = Minimum operating voltage Program Flash Memory D134 TIE TRETD ms Year Provided no other specifications are violated † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of Table Write instructions. 2: Refer to Section 7.8 “Using the Data EEPROM” for a more detailed discussion on data EEPROM endurance. 3: Required only if low-voltage programming is disabled. 2003 Microchip Technology Inc. Preliminary DS39616B-page 351 PIC18F2331/2431/4331/4431 FIGURE 25-3: LOW-VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 25-2: LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol No. D420 Characteristic Min Typ† Max Units LVD Voltage on VDD LVV = 0010 Transition High to Low LVV = 0011 2.08 2.26 2.44 V 2.26 2.45 2.65 V LVV = 0100 2.35 2.55 2.76 V LVV = 0101 2.55 2.77 2.99 V LVV = 0110 2.64 2.87 3.10 V LVV = 0111 2.82 3.07 3.31 V LVV = 1000 3.09 3.36 3.63 V LVV = 1001 3.29 3.57 3.86 V LVV = 1010 3.38 3.67 3.96 V LVV = 1011 3.56 3.87 4.18 V LVV = 1100 3.75 4.07 4.40 V LVV = 1101 3.93 4.28 4.62 V LVV = 1110 4.23 4.60 4.96 V Conditions † Production tested at TAMB = 25°C. Specifications over temp. limits ensured by characterization. DS39616B-page 352 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.4 25.4.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low 2 I C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 2003 Microchip Technology Inc. 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only) T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid Hi-impedance High Low High Low SU Setup STO Stop condition Preliminary DS39616B-page 353 PIC18F2331/2431/4331/4431 25.4.2 TIMING CONDITIONS Note: The temperature and voltages specified in Table 25-3 apply to all timing specifications unless otherwise noted. Figure 25-4 specifies the load conditions for the timing specifications. TABLE 25-3: Because of space limitations, the generic terms “PIC18FXX31” and “PIC18LFXX31” are used throughout this section to refer to the PIC18F2331/2431/4331/4431 and PIC18LF2331/2431/4331/4431 families of devices specifically, and only those devices. TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC AC CHARACTERISTICS FIGURE 25-4: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Operating voltage VDD range as described in DC spec Section 25.1 and Section 25.3. LF parts operate for industrial temperatures only. LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 Load Condition 2 VDD/2 RL CL Pin VSS CL Pin RL = 464Ω VSS DS39616B-page 354 CL = 50 pF Preliminary for all pins except OSC2/CLKO and including D and E outputs as ports 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 25.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 25-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 25-4: Param. No. EXTERNAL CLOCK TIMING REQUIREMENTS Symbol Characteristic Min Max Units Conditions 1A FOSC External CLKI Frequency(1) Oscillator Frequency(1) DC DC 0.1 4 4 5 40 4 4 25 10 200 MHz MHz MHz MHz MHz kHz 1 TOSC External CLKI Period(1) 25 — ns EC, ECIO 250 250 25 100 25 — 10,000 250 250 — ns ns ns ns µs RC osc XT osc HS osc HS + PLL osc LP osc (1) Oscillator Period 2 3 4 Note 1: TCY TosL, TosH EC, ECIO RC osc XT osc HS osc HS + PLL osc LP Osc mode Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time 100 — ns TCY = 4/FOSC 30 — ns XT osc 2.5 — µs LP osc 10 — ns HS osc TosR, External Clock in (OSC1) — 20 ns XT osc TosF Rise or Fall Time — 50 ns LP osc — 7.5 ns HS osc Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 2003 Microchip Technology Inc. Preliminary DS39616B-page 355 PIC18F2331/2431/4331/4431 TABLE 25-5: Param No. PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V) Sym Characteristic Min Typ† Max Units Conditions F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only F11 FSYS On-chip VCO System Frequency 16 — 40 MHz HS mode only F12 TPLL PLL Start-up Time (Lock Time) — — 2 F13 ms ∆CLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 25-6: INTERNAL RC ACCURACY PIC18F2331/2431/4331/4431 (Industrial) PIC18LF2331/2431/4331/4431 (Industrial) PIC18F1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC18LF1220/1320 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Device Min Typ Max Units Conditions INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) F2 PIC18LF2331/2431/4331/4431 -15 +/-5 +15 % 25°C VDD = 3.0V F3 All devices -15 +/-5 +15 % 25°C VDD = 5.0V INTRC Accuracy @ Freq = 31 F5 kHz(2) PIC18LF2331/2431/4331/4431 26.562 F6 All devices — 35.938 kHz 25°C VDD = 3.0V 26.562 — 35.938 kHz 25°C VDD = 5.0V INTRC Stability(3) F8 PIC18LF2331/2431/4331/4431 TBD 1 TBD % 25°C VDD = 3.0V F9 All devices TBD 1 TBD % 25°C VDD = 5.0V Legend: Shading of rows is to assist in readability of the table. Note 1: Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift. 2: INTRC frequency after calibration. 3: Change of INTRC frequency as VDD changes. DS39616B-page 356 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 25-6: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) Note: 20, 21 Refer to Figure 25-4 for load conditions. TABLE 25-7: Param No. New Value Old Value CLKO AND I/O TIMING REQUIREMENTS Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1 ↑ to CLKO ↓ — 75 200 ns (1) 11 TosH2ckH OSC1 ↑ to CLKO ↑ — 75 200 ns (1) 12 TckR CLKO rise time — 35 100 ns (1) 13 TckF CLKO fall time — 35 100 ns (1) CLKO ↓ to Port out valid — — 0.5 TCY + 20 ns (1) 0.25 TCY + 25 — — ns (1) (1) 14 TckL2ioV 15 TioV2ckH Port in valid before CLKO ↑ 16 TckH2ioI 17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid 18 TosH2ioI 18A Port in hold after CLKO ↑ OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time) 0 — — ns — 50 150 ns PIC18FXX31 100 — — ns PIC18LFXX31 200 — — ns 19 TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20 TioR Port output rise time PIC18FXX31 — 10 25 ns PIC18LFXX31 — — 60 ns TioF Port output fall time PIC18FXX31 — 10 25 ns — — 60 ns 22†† TINP INT pin high or low time TCY — — ns 23†† TRBP RB7:RB4 change INT high or low time TCY — — 24†† TRCP RB7:RB4 change INT high or low time 20 20A 21 21A PIC18LFXX31 ns ns †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC. 2003 Microchip Technology Inc. Preliminary DS39616B-page 357 PIC18F2331/2431/4331/4431 FIGURE 25-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 25-4 for load conditions. FIGURE 25-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage Stable TABLE 25-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. 30 31 TmcL TWDT 32 33 TOST TPWRT 34 TIOZ 35 36 TBOR TIVRST 37 TLVD 36 Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Postscaler) Oscillation Start-up Timer Period Power-up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become stable Low-Voltage Detect Pulse Width DS39616B-page 358 Min Typ Max Units 2 — — 4.00 — TBD µs ms 1024 TOSC — 1024 TOSC — 65.5 TBD — ms Conditions TOSC = OSC1 period — 2 — µs 200 — — 20 — 50 µs µs VDD ≤ BVDD (see D005) 200 — — µs VDD ≤ VLVD Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 25-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 25-4 for load conditions. TABLE 25-9: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Symbol No. Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period 45 Tt1H Min No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler T1CKI Synchronous, no prescaler High Time Synchronous, PIC18FXX31 with prescaler PIC18LFXX31 Asynchronous 46 Tt1L T1CKI Low Time 47 Tt1P T1CKI Input Period 48 PIC18FXX31 PIC18LFXX31 Synchronous, no prescaler Synchronous, PIC18FXX31 with prescaler PIC18LFXX31 Asynchronous PIC18FXX31 PIC18LFXX31 Synchronous Asynchronous Ft1 T1CKI Oscillator Input Frequency Range Tcke2tmrI Delay from External T1CKI Clock Edge to Timer Increment 2003 Microchip Technology Inc. Max — 0.5 TCY + 20 10 — — 0.5 TCY + 20 10 — TCY + 10 — Greater of: — 20 ns or TCY + 40 N — 0.5 TCY + 20 10 — 25 — 30 — 50 — 0.5 TCY + 5 — 10 — 25 — 30 — TBD TBD Greater of: — 20 ns or TCY + 40 N 60 — DC 50 2 TOSC 7 TOSC Preliminary Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions N = prescale value (1, 2, 4,..., 256) N = prescale value (1, 2, 4, 8) ns kHz — DS39616B-page 359 PIC18F2331/2431/4331/4431 FIGURE 25-10: CAPTURE/COMPARE/PWM TIMINGS (ALL CCP MODULES) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: 54 Refer to Figure 25-4 for load conditions. TABLE 25-10: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param Symbol No. Characteristic 50 TccL 51 TccH 52 TccP No Prescaler With PIC18FXX31 Prescaler PIC18LFXX31 CCPx input high No Prescaler time With PIC18FXX31 Prescaler PIC18LFXX31 CCPx input period 53 TccR CCPx output fall time 54 TccF CCPx output fall time DS39616B-page 360 CCPx input low time PIC18FXX31 PIC18LFXX31 PIC18FXX31 PIC18LFXX31 Preliminary Min Max Units 0.5 TCY + 20 10 20 0.5 TCY + 20 10 20 3 TCY + 40 N — — — — — — — — — — — ns ns ns ns ns ns ns 25 45 25 45 ns ns ns ns Conditions N = prescale value (1,4 or 16) 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 25-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN bit6 - - - -1 LSb IN 74 73 Note: Refer to Figure 25-4 for load conditions. TABLE 25-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param No. 70 71 71A 72 72A 73 73A 74 Symbol TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TB2B 75 TscH2diL, TscL2diL TdoR 76 78 TdoF TscR Characteristic Min SS↓ to SCK↓ or SCK↑ input SCK input high time (Slave mode) Continuous Single Byte SCK input low time Continuous (Slave mode) Single Byte Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time PIC18FXX31 PIC18LFXX31 SDO data output fall time SCK output rise time (Master mode) PIC18FXX31 PIC18LFXX31 79 TscF SCK output fall time (Master mode) 80 TscH2doV, SDO data output valid after PIC18FXX31 TscL2doV SCK edge PIC18LFXX31 Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. 2003 Microchip Technology Inc. Preliminary Max Units TCY — ns 1.25 TCY + 30 40 1.25 TCY + 30 40 — — — — ns ns ns ns 100 — ns 1.5 TCY + 40 — ns 100 — ns — — — — — — — — 25 45 25 25 45 25 50 100 ns ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) (Note 2) DS39616B-page 361 PIC18F2331/2431/4331/4431 FIGURE 25-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO bit6 - - - - - -1 LSb 75, 76 SDI MSb IN bit6 - - - -1 LSb IN 74 Note: Refer to Figure 25-4 for load conditions. TABLE 25-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 71 71A 72 72A 73 73A 74 Symbol TscH TscL TdiV2scH, TdiV2scL TB2B 75 TscH2diL, TscL2diL TdoR 76 78 TdoF TscR Characteristic SCK input high time (Slave mode) Continuous Single Byte SCK input low time Continuous (Slave mode) Single Byte Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time PIC18FXX31 PIC18LFXX31 SDO data output fall time SCK output rise time (Master mode) PIC18FXX31 PIC18LFXX31 79 TscF SCK output fall time (Master mode) 80 TscH2doV, SDO data output valid after PIC18FXX31 TscL2doV SCK edge PIC18LFXX31 81 TdoV2scH, SDO data output setup to SCK edge TdoV2scL Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. DS39616B-page 362 Preliminary Min Max Units 1.25 TCY + 30 40 1.25 TCY + 30 40 — — — — ns ns ns ns 100 — ns 1.5 TCY + 40 — ns 100 — ns — 25 45 25 25 45 25 50 100 ns ns ns ns ns ns ns ns — ns — — — — TCY Conditions (Note 1) (Note 1) (Note 2) 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 25-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO bit6 - - - - - -1 LSb 77 75, 76 SDI MSb IN bit6 - - - -1 LSb IN 74 73 Note: Refer to Figure 25-4 for load conditions. TABLE 25-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)) Param No. 70 71 71A 72 72A 73 Symbol Characteristic TssL2scH, SS↓ to SCK↓ or SCK↑ input TssL2scL TscH SCK input high time (Slave mode) Continuous Single Byte TscL SCK input low time Continuous (Slave mode) Single Byte TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL Last clock edge of Byte1 to the first clock edge of Byte2 73A TB2B 74 TscH2diL, Hold time of SDI data input to SCK edge TscL2diL 75 TdoR SDO data output rise time PIC18FXX31 PIC18LFXX31 76 TdoF SDO data output fall time 77 TssH2doZ SS↑ to SDO output hi-impedance 78 TscR SCK output rise time (Master mode) PIC18FXX31 PIC18LFXX31 79 TscF SCK output fall time (Master mode) 80 TscH2doV, SDO data output valid after SCK edge PIC18FXX31 TscL2doV PIC18LFXX31 83 TscH2ssH, SS ↑ after SCK edge TscL2ssH Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. 2003 Microchip Technology Inc. Preliminary Min Max Units Conditions TCY — ns 1.25 TCY + 30 40 1.25 TCY + 30 40 100 — — — — — ns ns ns ns ns 1.5 TCY + 40 100 — — ns ns — 25 45 25 50 25 45 25 50 100 — ns ns ns ns ns ns ns ns ns ns — 10 — — — 1.5 TCY + 40 (Note 1) (Note 1) (Note 2) DS39616B-page 363 PIC18F2331/2431/4331/4431 FIGURE 25-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit6 - - - - - -1 LSb 75, 76 SDI Note: MSb IN 77 bit6 - - - -1 LSb IN 74 Refer to Figure 25-4 for load conditions. TABLE 25-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param No. 70 71 71A 72 72A 73A 74 Symbol TssL2scH, TssL2scL TscH TscL 75 TB2B TscH2diL, TscL2diL TdoR 76 77 78 TdoF TssH2doZ TscR Characteristic Min SS↓ to SCK↓ or SCK↑ input TCY Continuous 1.25 TCY + 30 Single Byte 40 SCK input low time Continuous 1.25 TCY + 30 (Slave mode) Single Byte 40 Last clock edge of Byte1 to the first clock edge of Byte2 1.5 TCY + 40 Hold time of SDI data input to SCK edge 100 SCK input high time (Slave mode) PIC18FXX31 PIC18LFXX31 — SDO data output fall time SS↑ to SDO output hi-impedance SCK output rise time PIC18FXX31 (Master mode) PIC18LFXX31 79 TscF SCK output fall time (Master mode) 80 TscH2doV, SDO data output valid after SCK PIC18FXX31 TscL2doV edge PIC18LFXX31 82 TssL2doV SDO data output valid after SS↓ PIC18FXX31 edge PIC18LFXX31 83 TscH2ssH, SS ↑ after SCK edge TscL2ssH Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. — 10 — — — — — — — DS39616B-page 364 Max Units Conditions SDO data output rise time Preliminary 1.5 TCY + 40 — ns — — — — — — ns ns ns ns ns ns 25 45 25 50 25 45 25 50 100 50 100 — ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 2) 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 25-15: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 25-4 for load conditions. TABLE 25-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No. 90 91 92 93 Characteristic TSU:STA Start condition Setup time THD:STA Start condition Hold time TSU:STO Stop condition Setup time THD:STO Stop condition Hold time FIGURE 25-16: 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min Max Units Conditions 4700 600 4000 600 4700 600 4000 600 — — — — — — — — ns Only relevant for repeated Start condition ns After this period, the first clock pulse is generated ns ns I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 25-4 for load conditions. 2003 Microchip Technology Inc. Preliminary DS39616B-page 365 PIC18F2331/2431/4331/4431 TABLE 25-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH Characteristic Clock high time Min Max Units Conditions 100 kHz mode 4.0 — µs PIC18FXX31 must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — µs PIC18FXX31 must operate at a minimum of 10 MHz SSP Module 101 TLOW Clock low time 1.5 TCY — 100 kHz mode 4.7 — µs PIC18FXX31 must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — µs PIC18FXX31 must operate at a minimum of 10 MHz 1.5 TCY — SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from 10 to 400 pF Start condition setup time 100 kHz mode 4.7 — µs 400 kHz mode 0.6 — µs Only relevant for repeated Start condition Start condition hold time 100 kHz mode 4.0 — µs 400 kHz mode 0.6 — µs Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 µs Data input setup time 100 kHz mode 250 — ns 400 kHz mode 100 — ns Stop condition setup time 100 kHz mode 4.7 — µs 400 kHz mode 0.6 — µs Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns Bus free time 100 kHz mode 4.7 — µs 400 kHz mode 1.3 — µs — 400 pF SSP Module 102 TR 103 TF 90 TSU:STA 91 THD:STA 106 THD:DAT 107 TSU:DAT 92 TSU:STO 109 TAA 110 TBUF D102 CB Note 1: 2: Bus capacitive loading CB is specified to be from 10 to 400 pF After this period, the first clock pulse is generated (Note 2) (Note 1) Time the bus must be free before a new transmission can start As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. DS39616B-page 366 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 25-17: SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 25-4 for load conditions. TABLE 25-17: SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic Start condition 100 kHz mode Setup time 91 THD:STA Start condition Hold time 92 TSU:STO Stop condition Setup time THD:STO Stop condition Hold time Note 1: Units 2(TOSC)(BRG + 1) — ns Only relevant for repeated Start condition ns After this period, the first clock pulse is generated 400 kHz mode 2(TOSC)(BRG + 1) — 2(TOSC)(BRG + 1) — 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — (1) 1 MHz mode 2(TOSC)(BRG + 1) — 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — (1) 2(TOSC)(BRG + 1) — 100 kHz mode 2(TOSC)(BRG + 1) — 400 kHz mode 2(TOSC)(BRG + 1) — 1 MHz mode(1) 2(TOSC)(BRG + 1) — 2C Maximum pin capacitance = 10 pF for all I FIGURE 25-18: Max 1 MHz mode(1) 1 MHz mode 93 Min Conditions ns ns pins. SSP I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out Note: Refer to Figure 25-4 for load conditions. 2003 Microchip Technology Inc. Preliminary DS39616B-page 367 PIC18F2331/2431/4331/4431 TABLE 25-18: SSP I2C BUS DATA REQUIREMENTS Param. Symbol No. 100 THIGH Characteristic Clock high time TLOW Clock low time 103 90 91 106 107 92 TR TF TSU:STA SDA and SCL rise time SDA and SCL fall time Start condition setup time THD:STA Start condition hold time THD:DAT Data input hold time TSU:DAT Data input setup time TSU:STO Stop condition setup time — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 2(TOSC)(BRG + 1) — ms 110 D102 Note 1: 2: TAA TBUF CB mode(1) 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms mode(1) ms 2(TOSC)(BRG + 1) — 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 300 ns 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1 CB 300 ns 1 MHz mode(1) — 100 ns 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 100 kHz mode 0 — ns 400 kHz mode 0 0.9 ms 1 MHz mode(1) TBD — ns 100 kHz mode 250 — ns 400 kHz mode 100 — ns 1 MHz mode(1) TBD — ns 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms mode(1) 2(TOSC)(BRG + 1) — ms — 3500 ns — 1000 ns (1) 1 MHz mode — — ns 100 kHz mode 4.7 — ms 400 kHz mode 1.3 — ms 1 MHz mode(1) TBD — ms — 400 pF 1 MHz 109 Output valid from 100 kHz mode clock 400 kHz mode Bus free time Units 2(TOSC)(BRG + 1) 1 MHz 102 Max 100 kHz mode 1 MHz 101 Min Bus capacitive loading Conditions CB is specified to be from 10 to 400 pF CB is specified to be from 10 to 400 pF Only relevant for Repeated Start condition After this period, the first clock pulse is generated (Note 2) Time the bus must be free before a new transmission can start Maximum pin capacitance = 10 pF for all I2C pins. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter #107 ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line is released. DS39616B-page 368 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 FIGURE 25-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 25-4 for load conditions. TABLE 25-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param Symbol No. 120 Characteristic TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock high to data out valid 121 Tckrf Clock out rise time and fall time (Master mode) 122 Tdtrf Data out rise time and fall time FIGURE 25-20: PIC18FXX31 PIC18LFXX31 PIC18FXX31 PIC18LFXX31 PIC18FXX31 PIC18LFXX31 Min Max Units — — — — — — 40 100 20 50 20 50 ns ns ns ns ns ns Conditions USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin 125 RC7/RX/DT pin 126 Note: Refer to Figure 25-4 for load conditions. TABLE 25-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. Symbol 125 TdtV2ckl 126 TckL2dtl Characteristic SYNC RCV (MASTER & SLAVE) Data hold before CK ↓ (DT hold time) Data hold after CK ↓ (DT hold time) 2003 Microchip Technology Inc. Preliminary Min Max Units 10 15 — — ns ns Conditions DS39616B-page 369 PIC18F2331/2431/4331/4431 TABLE 25-21: A/D CONVERTER CHARACTERISTICS: PIC18F2331/2431/4331/4431 (INDUSTRIAL) PIC18LF2331/2431/4331/4431 (INDUSTRIAL) Param No. Symbol Characteristic Min Typ Max Units — VDD+0.3 V Conditions Device Supply AVDD Analog VDD Supply VDD-0.3 AVSS Analog VSS Supply VSS-0.3 IAD Module Current (during conversion) IADO Module Current Off VSS+0.3 500 250 V µA µA VDD = 5V VDD = 2.5V 1.0 µA 200 75 ksps ksps 20,000 20,000 ns VDD = 5V VDD = 3V 500 750 10000 1500 2250 20000 ns ns ns PIC18F parts PIC18LF parts AVDD < 3.0V 12 12 TAD AC Timing Parameters A10 FTHR Throughput rate — — A11 TAD A/D Clock Period A12 TRC A/D Internal RC Oscillator Period A13 TCNV Conversion Time(1) (2) A14 TACQ Acquisition Time A16 TTC Conversion start from external 385 1000 12 2 (2) VDD = 5V, single channel VDD < 3V, single channel TAD 1/4 TCY 1Tcy Reference Inputs 1.5 1.8 — — AVDD-AVSS AVDD-AVSS V V VDD ≥ 3V VDD < 3V Reference voltage High (AVDD or VREF+) 1.5V — AVDD V VDD ≥ 3V Reference voltage Low (AVSS or VREF-) AVSS — VREFH-1.5V V A20 VREF Reference voltage for 10-bit resolution (VREF+ - VREF-) A21 VREFH A22 VREFL A23 IREF Reference Current 150µA 75µA VDD = 5V VDD = 2.5V Analog Input Characteristics A26 VAIN Input Voltage(3) AVSS-0.3 — AVDD+0.3 V A30 ZAIN Recommended impedance of analog voltage source — — 2.5 kΩ A31 ZCHIN Analog channel input impedance — 10.0 kΩ VDD = 3.0 V DC Performance A41 NR Resolution A42 EIL Integral Nonlinearity — — < ±1 LSb VDD ≥ 3.0V VREFH ≥ 3.0V A43 EIL Differential Nonlinearity — — < ±1 LSb VDD ≥ 3.0V VREFH ≥ 3.0V A45 EOFF Offset error — ±0.5 < ±1.5 LSb VDD ≥ 3.0V VREFH ≥ 3.0V A46 EGA Gain error — ±0.5 < ±1.5 LSb VDD ≥ 3.0V VREFH ≥ 3.0V A47 — — VDD ≥ 3.0V VREFH ≥ 3.0V Note 1: 2: 3: 4: Monotonicity(4) 10 bits guaranteed — Conversion time does not include acquisition time. See Section 20.0 “10-bit High-Speed Analog-to-Digital Converter (A/D) Module” for a full discussion of acquisition time requirements. In sequential modes, Tacq should be 12Tad or greater. For VDD < 2.7V and temperature below 0°C, VAIN should be limited to range < VDD/2. The A/D conversion result never decreases with an incraese in the input voltage, and has no missing codes. DS39616B-page 370 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 26.0 PRELIMINARY DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs are not available at this time. 2003 Microchip Technology Inc. Preliminary DS39616B-page 371 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 372 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC18F2331-I/SP 0317017 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN PIC18F2431-E/SO 0310017 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP PIC18F4331-I/P 0312017 Example PIC18F4431 -I/PT XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 0320017 44-Lead QFN Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: Note: * PIC18F4431 -I/ML 0320017 XX...X Y YY WW NNN Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2003 Microchip Technology Inc. Preliminary DS39616B-page 373 PIC18F2331/2431/4331/4431 27.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c β B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 8.26 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 Molded Package Width E1 .275 .285 .295 6.99 7.24 7.49 Overall Length D 1.345 1.365 1.385 34.16 34.67 35.18 Tip to Seating Plane L c .125 .130 .135 3.18 3.30 3.43 .008 .012 .015 0.20 0.29 0.38 B1 .040 .053 .065 1.02 1.33 1.65 Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom § 0.38 B .016 .019 .022 0.41 0.48 0.56 eB α .320 .350 .430 8.13 8.89 10.92 β 5 10 15 5 10 15 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 DS39616B-page 374 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E E1 p D B 2 1 n h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β A1 MIN .093 .088 .004 .394 .288 .695 .010 .016 0 .009 .014 0 0 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MAX .104 .094 .012 .420 .299 .712 .029 .050 8 .013 .020 15 15 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 MIN MAX 2.64 2.39 0.30 10.67 7.59 18.08 0.74 1.27 8 0.33 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 2003 Microchip Technology Inc. Preliminary DS39616B-page 375 PIC18F2331/2431/4331/4431 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) E1 D α 2 1 n E A2 A L c β B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .595 .600 .625 Molded Package Width E1 .530 .545 .560 Overall Length D 2.045 2.058 2.065 Tip to Seating Plane L .120 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .030 .050 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .620 .650 .680 α Mold Draft Angle Top 5 10 15 β Mold Draft Angle Bottom 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-011 Drawing No. C04-016 DS39616B-page 376 Preliminary MAX 4.83 4.06 15.88 14.22 52.45 3.43 0.38 1.78 0.56 17.27 15 15 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 ° α A c φ β L A1 A2 (F) Units Dimension Limits n p Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff § Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic n1 A A2 A1 L (F) φ E D E1 D1 c B CH α β MIN .039 .037 .002 .018 0 .463 .463 .390 .390 .004 .012 .025 5 5 INCHES NOM 44 .031 11 .043 .039 .004 .024 .039 3.5 .472 .472 .394 .394 .006 .015 .035 10 10 MAX .047 .041 .006 .030 7 .482 .482 .398 .398 .008 .017 .045 15 15 MILLIMETERS* NOM 44 0.80 11 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.09 0.15 0.30 0.38 0.64 0.89 5 10 5 10 MIN MAX 1.20 1.05 0.15 0.75 7 12.25 12.25 10.10 10.10 0.20 0.44 1.14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-076 2003 Microchip Technology Inc. Preliminary DS39616B-page 377 PIC18F2331/2431/4331/4431 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) EXPOSED METAL PAD E p D D2 2 1 B n PIN 1 INDEX ON EXPOSED PAD OPTIONAL PIN 1 INDEX ON TOP MARKING E2 L TOP VIEW BOTTOM VIEW A A1 A3 Number of Pins Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length Units Dimension Limits n p A A1 A3 E E2 D D2 B L MIN .031 .000 .262 .262 .012 .014 INCHES NOM 44 .026 BSC .035 .001 .010 REF .315 BSC .268 .315 BSC .268 .013 .016 MAX .039 .002 .274 .274 .013 .018 MILLIMETERS* NOM 44 0.65 BSC 0.90 0.80 0.02 0 0.25 REF 8.00 BSC 6.65 6.80 8.00 BSC 6.65 6.80 0.30 0.33 0.35 0.40 MIN MAX 1.00 0.05 6.95 6.95 0.35 0.45 *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: M0-220 Drawing No. C04-103 DS39616B-page 378 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (June 2003) Original data sheet for PIC18F2331/2431/4331/4431 devices. DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1. Revision B (December 2003) The Electrical Specifications in Section 25.0 “Electrical Characteristics” have been updated and there have been minor corrections to the data sheet text. TABLE B-1: DEVICE DIFFERENCES Features PIC18F2331 PIC18F2431 PIC18F4331 PIC18F4431 Program Memory (Bytes) 4096 8192 4096 8192 Program Memory (Instructions) 2048 4096 2048 4096 22 22 34 34 Interrupt Sources I/O Ports Ports A, B, C, D, E Ports A, B, C, D, E Ports A, B, C, D, E Ports A, B, C, D, E Capture/Compare/PWM Modules 2 2 2 2 Enhanced Capture/Compare/ PWM Modules 1 1 1 1 Parallel Communications (PSP) No No Yes Yes 10-bit Analog-to-Digital Module 5 input channels 5 input channels 9 input channels 9 input channels 28-pin SDIP 28-pin SOIC 40-pin DIP 44-pin TQFP 44-pin QFN 40-pin DIP 44-pin TQFP 44-pin QFN Packages 2003 Microchip Technology Inc. 28-pin SDIP 28-pin SOIC Preliminary DS39616B-page 379 PIC18F2331/2431/4331/4431 APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39616B-page 380 MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a baseline device (i.e., PIC16C5X) to an enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18F442.” The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the enhanced devices (i.e., PIC18FXXX) is provided in AN726, “PIC17CXXX to PIC18FXXX Migration.” This Application Note is available on Microchip’s web site; www.Microchip.com. This Application Note is available on Microchip’s web site; www.Microchip.com. 2003 Microchip Technology Inc. Preliminary DS39616B-page 381 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 382 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 INDEX A A/D ................................................................................... 243 Associated Registers ............................................... 259 Calculating the Minimum Required Acquisition Time ............................................... 254 Special Event Trigger (CCP) .................................... 154 Absolute Maximum Ratings ............................................. 337 AC (Timing) Characteristics ............................................. 353 Load Conditions for Device Timing Specifications ....................................... 354 Parameter Symbology ............................................. 353 Temperature and Voltage Specifications ................. 354 Timing Conditions .................................................... 354 Access Bank ...................................................................... 70 ACK Pulse ................................................................ 217, 218 ADDLW ............................................................................ 293 ADDWF ............................................................................ 293 ADDWFC ......................................................................... 294 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 294 ANDWF ............................................................................ 295 Application Notes AN578 (Use of the SSP Module in the I2C Multi-Master Environment) ............................... 211 Assembler MPASM Assembler .................................................. 331 Auto-Wake-up on Sync Break Character ......................... 235 B Bank Select Register (BSR) ............................................... 70 BC .................................................................................... 295 BCF .................................................................................. 296 BF bit ................................................................................ 212 Block Diagrams Analog Input Model .................................................. 254 Capture Mode Operation ......................................... 153 Compare Mode Operation ....................................... 154 External Power-on Reset Circuit (Slow VDD Power-up) ......................................... 46 Fail-Safe Clock Monitor ............................................ 281 Generic I/O Port ....................................................... 107 Interrupt Logic ............................................................ 92 Low-Voltage Detect (LVD) ....................................... 262 Low-Voltage Detect (LVD) with External Input ......... 262 On-Chip Reset Circuit ................................................ 45 PIC18F2331/2431 ...................................................... 10 PIC18F4331/4431 ...................................................... 11 PLL ............................................................................. 22 PWM (Standard) ...................................................... 156 RA0 Pin .................................................................... 108 RA1 Pin .................................................................... 108 RA3:RA2 Pins .......................................................... 108 RA4 Pin .................................................................... 109 RA5 Pin .................................................................... 110 RA6 Pin .................................................................... 110 RB3:RB0 Pins .......................................................... 113 RB4 Pin .................................................................... 114 RB5 Pin ............................................................ 115, 121 RB7:RB6 Pins .......................................................... 116 RC0 Pin .................................................................... 118 RC1 Pin .................................................................... 119 RC2 Pin .................................................................... 119 2003 Microchip Technology Inc. RC3 Pin ................................................................... 120 RC4 Pin ................................................................... 120 RC6 Pin ................................................................... 121 RC7 Pin ................................................................... 122 RD0 Pin ................................................................... 127 RD1 Pin ................................................................... 127 RD2 Pin ................................................................... 126 RD3 Pin ................................................................... 126 RD4 Pin ................................................................... 125 RD5 Pin ................................................................... 125 RD7:RD6 Pins ......................................................... 124 RE2:RE0 Pins .......................................................... 130 RE3 Pin ................................................................... 130 Reads from Flash Program Memory .......................... 79 SSP (I2C Mode) ....................................................... 217 SSP (SPI Mode) ...................................................... 214 System Clock ............................................................. 27 Table Read Operation ............................................... 75 Table Write Operation ................................................ 76 Table Writes to Flash Program Memory .................... 81 Timer0 in 16-bit Mode .............................................. 134 Timer0 in 8-bit Mode ................................................ 134 Timer1 ..................................................................... 138 Timer1 (16-bit Read/Write Mode) ............................ 138 Timer2 ..................................................................... 144 Timer5 ..................................................................... 146 USART Receive ....................................................... 233 USART Transmit ...................................................... 231 Watchdog Timer ...................................................... 278 BN .................................................................................... 296 BNC ................................................................................. 297 BNN ................................................................................. 297 BNOV ............................................................................... 298 BNZ .................................................................................. 298 BOR. See Brown-out Reset. BOV ................................................................................. 301 BRA ................................................................................. 299 Break Character (12-bit) Transmit and Receive .............. 236 Brown-out Reset (BOR) ..............................................46, 267 BSF .................................................................................. 299 BTFSC ............................................................................. 300 BTFSS ............................................................................. 300 BTG ................................................................................. 301 BZ .................................................................................... 302 C C Compilers MPLAB C17 ............................................................. 332 MPLAB C18 ............................................................. 332 MPLAB C30 ............................................................. 332 CALL ................................................................................ 302 Capture (CCP Module) .................................................... 153 Associated Registers ............................................... 155 CCP Pin Configuration ............................................. 153 CCPR1H:CCPR1L Registers ................................... 153 Software Interrupt .................................................... 153 Timer1 Mode Selection ............................................ 153 Capture/Compare/PWM (CCP) ....................................... 151 Capture Mode. See Capture. CCP1 ....................................................................... 152 CCPR1H Register ........................................... 152 CCPR1L Register ............................................ 152 DS39616B-page 383 PIC18F2331/2431/4331/4431 CCP2 ........................................................................ 152 CCPR2H Register ............................................ 152 CCPR2L Register ............................................ 152 Compare Mode. See Compare. PWM Mode. See PWM. Timer Resources ...................................................... 152 CKE bit ............................................................................. 212 CKP bit ............................................................................. 213 Clock Sources .................................................................... 26 Selection Using OSCCON Register ........................... 26 Clocking Scheme/Instruction Cycle .................................... 61 CLRF ................................................................................ 303 CLRWDT .......................................................................... 303 Code Examples 16 x 16 Signed Multiply Routine ................................. 90 16 x 16 Unsigned Multiply Routine ............................. 90 8 x 8 Signed Multiply Routine ..................................... 89 8 x 8 Unsigned Multiply Routine ................................. 89 Changing Between Capture Prescalers ................... 153 Computed GOTO Using an Offset Value ................... 63 Data EEPROM Read ................................................. 87 Data EEPROM Refresh Routine ................................ 88 Data EEPROM Write .................................................. 87 Erasing a Flash Program Memory Row ..................... 80 Fast Register Stack .................................................... 60 How to Clear RAM (Bank 1) Using Indirect Addressing ......................................................... 71 Implementing a Real-Time Clock Using a Timer1 Interrupt Service .................................. 141 Initializing PORTA .................................................... 107 Initializing PORTB .................................................... 112 Initializing PORTC .................................................... 118 Initializing PORTD .................................................... 124 Initializing PORTE .................................................... 129 Reading a Flash Program Memory Word ................... 79 Saving Status, WREG and BSR Registers in RAM ..................................... 106 Writing to Flash Program Memory ....................... 82–83 Code Protection ....................................................... 267, 283 COMF ............................................................................... 304 Compare (CCP Module) ................................................... 154 Associated Registers ............................................... 155 CCP Pin Configuration ............................................. 154 CCPR1 Register ....................................................... 154 Software Interrupt ..................................................... 154 Special Event Trigger ............................................... 154 Timer1 Mode Selection ............................................ 154 Computed GOTO ............................................................... 63 Configuration Bits ............................................................. 267 Configuration Register Protection .................................... 286 Context Saving During Interrupts ..................................... 106 Control Registers EECON1 and EECON2 .............................................. 76 Conversion Considerations .............................................. 380 CPFSEQ .......................................................................... 304 CPFSGT ........................................................................... 305 CPFSLT ........................................................................... 305 Crystal Oscillator/Ceramic Resonator ................................ 21 D D/A Bit .............................................................................. 212 Data EEPROM Code Protection ...................................... 286 Data EEPROM Memory ..................................................... 85 Associated Registers ................................................. 88 EEADR Register ........................................................ 85 EECON1 and EECON2 Registers ............................. 85 DS39616B-page 384 Operation During Code-Protect ................................. 88 Protection Against Spurious Write ............................. 87 Reading ..................................................................... 87 Using .......................................................................... 88 Write Verify ................................................................ 87 Writing ........................................................................ 87 Data Memory ..................................................................... 63 General Purpose Registers ....................................... 63 Map for PIC18F2X31/4X31 ........................................ 64 Special Function Registers ........................................ 65 Data/Address Bit (D/A) ..................................................... 212 DAW ................................................................................ 306 DC and AC Characteristics Graphs and Tables (Preliminary) ............................. 371 DC Characteristics ............................................339, 340, 349 DCFSNZ .......................................................................... 307 DECF ............................................................................... 306 DECFSZ .......................................................................... 307 Demonstration Boards PICDEM 1 ................................................................ 334 PICDEM 17 .............................................................. 334 PICDEM 18R PIC18C601/801 ................................. 335 PICDEM 2 Plus ........................................................ 334 PICDEM 3 PIC16C92X ............................................ 334 PICDEM 4 ................................................................ 334 PICDEM LIN PIC16C43X ........................................ 335 PICDEM USB PIC16C7X5 ...................................... 335 PICDEM.net Internet/Ethernet ................................. 334 Development Support ...................................................... 331 Device Differences ........................................................... 379 Device Overview .................................................................. 7 Features (table) ........................................................... 9 New Core Features ...................................................... 7 Other Special Features ................................................ 8 Direct Addressing ............................................................... 72 E Effects of Power Managed Modes on Various Clock Sources ............................................................ 29 Electrical Characteristics .................................................. 337 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................ 221 Equations 16 x 16 Signed Multiplication Algorithm ..................... 90 16 x 16 Unsigned Multiplication Algorithm ................. 90 A/D Acquisition Time ............................................... 253 A/D Minimum Charging Time ................................... 253 Errata ................................................................................... 6 Evaluation and Programming Tools ................................. 335 External Clock Input ........................................................... 23 F Fail-Safe Clock Monitor .............................................267, 281 Interrupts in Power-Managed Modes ....................... 282 POR or Wake from Sleep ........................................ 282 WDT During Oscillator Failure ................................. 281 Fast Register Stack ............................................................ 60 Firmware Instructions ....................................................... 287 Flash Program Memory ..................................................... 75 Associated Registers ................................................. 83 Control Registers ....................................................... 76 Erase Sequence ........................................................ 80 Erasing ....................................................................... 80 Operation During Code-Protect ................................. 83 Reading ..................................................................... 79 TABLAT Register ....................................................... 78 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Table Pointer .............................................................. 78 Boundaries Based on Operation ........................ 78 Table Pointer Boundaries .......................................... 78 Table Reads and Table Writes .................................. 75 Unexpected Termination of Write Operation .............. 83 Write Verify ................................................................ 83 Writing to .................................................................... 81 FSCM. See Fail-Safe Clock Monitor. G GOTO ............................................................................... 308 H Hardware Multiplier ............................................................ 89 Introduction ................................................................ 89 Operation ................................................................... 89 Performance Comparison .......................................... 89 HSPLL ................................................................................ 22 I I/O Ports ........................................................................... 107 I2C Mode Addressing ............................................................... 218 Associated Registers ............................................... 220 Master Mode ............................................................ 220 Mode Selection ........................................................ 217 Multi-Master Mode ................................................... 220 Operation ................................................................. 217 Reception ................................................................. 218 Slave Mode SCL and SDA Pins ........................................... 217 Transmission ............................................................ 219 ID Locations ............................................................. 267, 286 INCF ................................................................................. 308 INCFSZ ............................................................................ 309 In-Circuit Debugger .......................................................... 286 In-Circuit Serial Programming (ICSP) ...................... 267, 286 Indirect Addressing INDF and FSR Registers ........................................... 71 Operation ................................................................... 71 Indirect Addressing Operation ............................................ 72 Indirect File Operand .......................................................... 63 INFSNZ ............................................................................ 309 Initialization Conditions for all Registers ...................... 48–51 Instruction Cycle ................................................................. 61 Instruction Flow/Pipelining ................................................. 61 Instruction Format ............................................................ 289 Instruction Set .................................................................. 287 ADDLW .................................................................... 293 ADDWF .................................................................... 293 ADDWFC ................................................................. 294 ANDLW .................................................................... 294 ANDWF .................................................................... 295 BC ............................................................................ 295 BCF .......................................................................... 296 BN ............................................................................ 296 BNC ......................................................................... 297 BNN ......................................................................... 297 BNOV ....................................................................... 298 BNZ .......................................................................... 298 BOV ......................................................................... 301 BRA .......................................................................... 299 BSF .......................................................................... 299 BTFSC ..................................................................... 300 BTFSS ..................................................................... 300 BTG .......................................................................... 301 2003 Microchip Technology Inc. BZ ............................................................................ 302 CALL ........................................................................ 302 CLRF ....................................................................... 303 CLRWDT ................................................................. 303 COMF ...................................................................... 304 CPFSEQ .................................................................. 304 CPFSGT .................................................................. 305 CPFSLT ................................................................... 305 DAW ........................................................................ 306 DCFSNZ .................................................................. 307 DECF ....................................................................... 306 DECFSZ .................................................................. 307 GOTO ...................................................................... 308 INCF ........................................................................ 308 INCFSZ .................................................................... 309 INFSNZ .................................................................... 309 IORLW ..................................................................... 310 IORWF ..................................................................... 310 LFSR ....................................................................... 311 MOVF ...................................................................... 311 MOVFF .................................................................... 312 MOVLB .................................................................... 312 MOVLW ................................................................... 313 MOVWF ................................................................... 313 MULLW .................................................................... 314 MULWF .................................................................... 314 NEGF ....................................................................... 315 NOP ......................................................................... 315 POP ......................................................................... 316 PUSH ....................................................................... 316 RCALL ..................................................................... 317 RESET ..................................................................... 317 RETFIE .................................................................... 318 RETLW .................................................................... 318 RETURN .................................................................. 319 RLCF ....................................................................... 319 RLNCF ..................................................................... 320 RRCF ....................................................................... 320 RRNCF .................................................................... 321 SETF ....................................................................... 321 SLEEP ..................................................................... 322 SUBFWB ................................................................. 322 SUBLW .................................................................... 323 SUBWF .................................................................... 323 SUBWFB ................................................................. 324 SWAPF .................................................................... 325 TBLRD ..................................................................... 326 TBLWT .................................................................... 327 TSTFSZ ................................................................... 328 XORLW ................................................................... 328 XORWF ................................................................... 329 Summary Table ....................................................... 290 Instructions in Program Memory ........................................ 62 Two-Word Instructions ............................................... 62 INTCON Register RBIF Bit ................................................................... 112 INTCON Registers ............................................................. 93 Inter-Integrated Circuit (I2C). See I2C Mode. Internal Oscillator Block ..................................................... 24 Adjustment ................................................................. 24 INTIO Modes ............................................................. 24 INTRC Output Frequency .......................................... 24 OSCTUNE Register ................................................... 24 Internal RC Oscillator Use with WDT .......................................................... 278 DS39616B-page 385 PIC18F2331/2431/4331/4431 Interrupt Sources .............................................................. 267 Capture Complete (CCP) ......................................... 153 Compare Complete (CCP) ....................................... 154 Interrupt-on-Change (RB7:RB4) .............................. 112 INTn Pin ................................................................... 106 PORTB, Interrupt-on-Change .................................. 106 TMR0 ....................................................................... 106 TMR1 Overflow ........................................................ 137 TMR2 to PR2 Match ................................................. 144 TMR2 to PR2 Match (PWM) ............................ 143, 156 Interrupts ............................................................................ 91 Interrupts, Enable Bits CCP1 Enable (CCP1IE Bit) ...................................... 153 Interrupts, Flag Bits CCP1 Flag (CCP1IF Bit) .......................................... 153 CCP1IF Flag (CCP1IF Bit) ....................................... 154 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ...... 112 INTOSC Frequency Drift .................................................... 42 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 310 IORWF ............................................................................. 310 IPR Registers ................................................................... 102 L LFSR ................................................................................ 311 Look-up Tables .................................................................. 63 Low-Voltage Detect .......................................................... 261 Low-Voltage Detect Characteristics ......................................................... 352 Effects of a Reset ..................................................... 265 Operation ................................................................. 264 Current Consumption ....................................... 265 Reference Voltage Set Point ............................ 265 Operation During Sleep ............................................ 265 Low-Voltage ICSP Programming ..................................... 286 LVD. See Low-Voltage Detect. M Memory Organization ......................................................... 57 Data Memory .............................................................. 63 Program Memory ....................................................... 57 Memory Programming Requirements .............................. 351 Migration from Baseline to Enhanced Devices ................ 380 Migration from High-End to Enhanced Devices ............... 381 Migration from Mid-Range to Enhanced Devices ............. 381 MOVF ............................................................................... 311 MOVFF ............................................................................. 312 MOVLB ............................................................................. 312 MOVLW ............................................................................ 313 MOVWF ........................................................................... 313 MPLAB ASM30 Assembler, Linker, Librarian .................. 332 MPLAB ICD 2 In-Circuit Debugger ................................... 333 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator ................................................... 333 MPLAB ICE 4000 High Performance Universal I n-Circuit Emulator .................................................... 333 MPLAB Integrated Development Environment Software .............................................. 331 MPLINK Object Linker/MPLIB Object Librarian ............... 332 MULLW ............................................................................ 314 MULWF ............................................................................ 314 N NEGF ............................................................................... 315 NOP ................................................................................. 315 DS39616B-page 386 O Opcode Field Descriptions ............................................... 288 OPTION_REG Register PSA Bit .................................................................... 135 T0CS Bit .................................................................. 135 T0PS2:T0PS0 Bits ................................................... 135 T0SE Bit ................................................................... 135 Oscillator Configuration ...................................................... 21 EC .............................................................................. 21 ECIO .......................................................................... 21 HS .............................................................................. 21 HSPLL ....................................................................... 21 Internal Oscillator Block ............................................. 24 INTIO1 ....................................................................... 21 INTIO2 ....................................................................... 21 LP .............................................................................. 21 RC .............................................................................. 21 RCIO .......................................................................... 21 XT .............................................................................. 21 Oscillator Selection .......................................................... 267 Oscillator Start-up Timer (OST) ....................................29, 46 Oscillator Switching ............................................................ 26 Oscillator Transitions ......................................................... 28 Oscillator, Timer1 ............................................................. 137 P P (Stop) bit ....................................................................... 212 Packaging Information ..................................................... 373 Marking .................................................................... 373 PICkit 1 Flash Starter Kit .................................................. 335 PICSTART Plus Development Programmer .................... 333 PIE Registers ..................................................................... 99 Pin Functions MCLR/VPP/RE3 ....................................................12, 15 OSC1/CLKI/RA7 ...................................................12, 15 OSC2/CLKO/RA6 .................................................12, 15 RA0/AN0 ...............................................................12, 15 RA1/AN1 ...............................................................12, 15 RA2/AN2/VREF-/CAP1/INDX ................................12, 15 RA3/AN3/VREF+/CAP2/QEA .................................12, 15 RA4/AN4/CAP3/QEB ................................................. 15 RA4/CAP3/QEB ......................................................... 12 RA5/AN5/LVDIN ........................................................ 15 RB0/PWM0 ...........................................................13, 16 RB1/PWM1 ...........................................................13, 16 RB2/PWM2 ...........................................................13, 16 RB3/PWM3 ...........................................................13, 16 RB4/KBI0/PWM5 ....................................................... 16 RB4/PWM5 ................................................................ 13 RB5/KBI1/PWM4/PGM .........................................13, 16 RB6/KBI2/PGC .....................................................13, 16 RB7/KBI3/PGD .....................................................13, 16 RC0/T1OSO/T1CKI ..............................................14, 17 RC1/T1OSI/CCP2/FLTA .......................................14, 17 RC2/CCP1/FLTB ..................................................14, 17 RC3/T0CKI/T5CKI/INT0 .......................................14, 17 RC4/INT1/SDI/SDA ..............................................14, 17 RC5/INT2/SCK/SCL .............................................14, 17 RC6/TX/CK/SS .....................................................14, 17 RC7/RX/DT/SDO ..................................................14, 17 RD0/T0CKI/T5CKI ..................................................... 18 RD1/SDO ................................................................... 18 RD2/SDI/SDA ............................................................ 18 RD3/SCK/SCL ........................................................... 18 RD4/FLTA .................................................................. 18 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 RD5/PWM4 ................................................................ 18 RD6/PWM6 ................................................................ 18 RD7/PWM7 ................................................................ 18 RE0/AN6 .................................................................... 19 RE1/AN7 .................................................................... 19 RE2/AN8 .................................................................... 19 VDD ....................................................................... 14, 19 VSS ....................................................................... 14, 19 Pinout I/O Descriptions PIC18F2331/2431 ...................................................... 12 PIC18F4331/4431 ...................................................... 15 PIR Registers ..................................................................... 96 PLL Lock Time-out ............................................................. 46 Pointer, FSRn ..................................................................... 71 POP .................................................................................. 316 POR. See Power-on Reset. PORTA Associated Registers ............................................... 111 LATA Register .......................................................... 107 PORTA Register ...................................................... 107 TRISA Register ........................................................ 107 PORTB Associated Registers ............................................... 117 LATB Register .......................................................... 112 PORTB Register ...................................................... 112 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 112 TRISB Register ........................................................ 112 PORTC Associated Registers ............................................... 123 LATC Register ......................................................... 118 PORTC Register ...................................................... 118 TRISC Register ........................................................ 118 PORTD Associated Registers ............................................... 128 LATD Register ......................................................... 124 PORTD Register ...................................................... 124 TRISD Register ........................................................ 124 PORTE Associated Registers ............................................... 132 LATE Register .......................................................... 129 PORTE Register ...................................................... 129 TRISE Register ........................................................ 129 Postscaler, WDT Assignment (PSA Bit) .............................................. 135 Rate Select (T0PS2:T0PS0 Bits) ............................. 135 Power-Managed Modes ..................................................... 31 Entering ...................................................................... 32 Idle Modes ................................................................. 33 Run Modes ................................................................. 38 Selecting .................................................................... 31 Sleep Mode ................................................................ 33 Summary (table) ........................................................ 31 Wake from .................................................................. 40 Power-on Reset (POR) .............................................. 46, 267 Oscillator Start-up Timer (OST) ......................... 46, 267 Power-up Timer (PWRT) ................................... 46, 267 Time-out Sequence .................................................... 46 Power-up Delays ................................................................ 29 Power-up Timer (PWRT) .............................................. 29, 46 Prescaler, Capture ........................................................... 153 Prescaler, Timer0 ............................................................. 135 Assignment (PSA Bit) .............................................. 135 Rate Select (T0PS2:T0PS0 Bits) ............................. 135 Prescaler, Timer2 ............................................................. 157 PRO MATE II Universal Device Programmer .................. 333 2003 Microchip Technology Inc. Program Counter PCL Register ............................................................. 60 PCLATH Register ...................................................... 60 PCLATU Register ...................................................... 60 Program Memory Interrupt Vector .......................................................... 57 Map and Stack PIC18F2331/4331 ............................................. 57 PIC18F2431/4431 ............................................. 57 Reset Vector .............................................................. 57 Program Memory Code Protection .................................. 284 Program Verification ........................................................ 283 Program Verification and Code Protection Associated Registers ............................................... 283 Programming, Device Instructions ................................... 287 Pulse Width Modulation. See PWM (CCP Module) and PWM (ECCP Module). PUSH ............................................................................... 316 PUSH and POP Instructions .............................................. 59 PWM (CCP Module) ........................................................ 156 Associated Registers ............................................... 157 CCPR1H:CCPR1L Registers ................................... 156 Duty Cycle ............................................................... 156 Example Frequencies/Resolutions .......................... 157 Period ...................................................................... 156 Set-up for PWM Operation ...................................... 157 TMR2 to PR2 Match .........................................143, 156 Q Q Clock ............................................................................ 157 QEI Sampling Modes ....................................................... 172 R R/W bit .............................................................. 212, 218, 219 RAM. See Data Memory. RC Oscillator ...................................................................... 23 RCIO Oscillator Mode ................................................ 23 RCALL ............................................................................. 317 RCON Register Bit Status During Initialization .................................... 47 Bits and Positions ...................................................... 47 RCSTA Register SPEN Bit .................................................................. 221 Receive Overflow Indicator Bit (SSPOV) ......................... 213 Register File ....................................................................... 63 Registers BAUDCTL (Baud Rate Control) ............................... 224 CCPxCON (Capture/Compare/PWM Control) ......... 151 CONFIG1H (Configuration 1 High) .......................... 268 CONFIG2H (Configuration 2 High) ...................270, 271 CONFIG2L (Configuration 2 Low) ........................... 269 CONFIG3H (Configuration 3 High) .......................... 272 CONFIG4L (Configuration 4 Low) ........................... 273 CONFIG5H (Configuration 5 High) .......................... 274 CONFIG6H (Configuration 6 High) .......................... 275 CONFIG6L (Configuration 6 Low) ........................... 275 CONFIG7H (Configuration 7 High) .......................... 276 CONFIG7L (Configuration 7 Low) ........................... 276 Device ID Register 1 ................................................ 277 Device ID Register 2 ................................................ 277 EECON1 (Data EEPROM Control 1) ....................77, 86 INTCON (Interrupt Control) ........................................ 93 INTCON2 (Interrupt Control 2) ................................... 94 INTCON3 (Interrupt Control 3) ................................... 95 IPR1 (Peripheral Interrupt Priority 1) ....................... 102 IPR2 (Peripheral Interrupt Priority 2) ....................... 103 DS39616B-page 387 PIC18F2331/2431/4331/4431 LVDCON (LVD Control) ........................................... 263 OSCCON (Oscillator Control) .................................... 28 OSCTUNE (Oscillator Tuning) ................................... 25 PIE1 (Peripheral Interrupt Enable 1) .......................... 99 PIE2 (Peripheral Interrupt Enable 2) ........................ 100 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 96 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 97 RCON (Reset Control) ....................................... 74, 105 RCSTA (Receive Status and Control) ...................... 223 SSPCON (Sync Serial Port Control) Register .......... 213 SSPSTAT (Sync Serial Port Status) Register .......... 212 Status ......................................................................... 73 STKPTR (Stack Pointer) ............................................ 59 Summary .............................................................. 66–68 T0CON (Timer0 Control) .......................................... 133 T1CON (Timer 1 Control) ......................................... 137 T2CON (Timer 2 Control) ......................................... 143 TRISE ....................................................................... 131 TXSTA (Transmit Status and Control) ..................... 222 WDTCON (Watchdog Timer Control) ....................... 278 Reset .......................................................................... 45, 317 Resets .............................................................................. 267 RETFIE ............................................................................ 318 RETLW ............................................................................. 318 RETURN .......................................................................... 319 Return Address Stack ........................................................ 58 Return Stack Pointer (STKPTR) ........................................ 58 Revision History ............................................................... 379 RLCF ................................................................................ 319 RLNCF ............................................................................. 320 RRCF ............................................................................... 320 RRNCF ............................................................................. 321 S S (Start) bit ....................................................................... 212 SCK .................................................................................. 211 SCL .................................................................................. 217 SDI ................................................................................... 211 SDO ................................................................................. 211 Serial Clock (SCK) Pin ..................................................... 211 Serial Data In (SDI) Pin .................................................... 211 Serial Data Out (SDO) Pin ............................................... 211 SETF ................................................................................ 321 Slave Select (SS) Pin ....................................................... 211 Sleep ................................................................................ 322 OSC1 and OSC2 Pin States ...................................... 29 SMP bit ............................................................................. 212 Software Simulator (MPLAB SIM) .................................... 332 Software Simulator (MPLAB SIM30) ................................ 332 Special Event Trigger. See Compare (CCP Module). Special Features of the CPU ............................................ 267 Special Function Registers ................................................ 65 Map ............................................................................ 65 SPI Mode ......................................................................... 211 Associated Registers ............................................... 216 Serial Clock .............................................................. 211 Serial Data In ........................................................... 211 Serial Data Out ......................................................... 211 Slave Select ............................................................. 211 SS .................................................................................... 211 SSP Overview TMR2 Output for Clock Shift ............................ 143, 144 SSP I2C Operation ........................................................... 217 Slave Mode .............................................................. 217 SSPEN Bit ........................................................................ 213 DS39616B-page 388 SSPM<3:0> Bits .............................................................. 213 SSPOV Bit ....................................................................... 213 Stack Full/Underflow Resets .............................................. 59 SUBFWB ......................................................................... 322 SUBLW ............................................................................ 323 SUBWF ............................................................................ 323 SUBWFB ......................................................................... 324 SWAPF ............................................................................ 325 Synchronous Serial Port Enable Bit (SSPEN) ................. 213 Synchronous Serial Port Mode Select Bits (SSPM<3:0>) ........................................................... 213 Synchronous Serial Port. See SSP. T TABLAT Register ............................................................... 78 Table Pointer Operations (table) ........................................ 78 Table Reads/Table Writes ................................................. 63 TBLPTR Register ............................................................... 78 TBLRD ............................................................................. 326 TBLWT ............................................................................. 327 Time-out in Various Situations (table) ................................ 47 Timer0 .............................................................................. 133 16-bit Mode Timer Reads and Writes ...................... 135 Associated Registers ............................................... 135 Clock Source Edge Select (T0SE Bit) ..................... 135 Clock Source Select (T0CS Bit) ............................... 135 Interrupt ................................................................... 135 Operation ................................................................. 135 Prescaler. See Prescaler, Timer0. Switching Prescaler Assignment ............................. 135 Timer1 .............................................................................. 137 16-bit Read/Write Mode ........................................... 140 Associated Registers ............................................... 141 Interrupt ................................................................... 140 Operation ................................................................. 138 Oscillator ...........................................................137, 139 Oscillator Layout Considerations ............................. 139 Overflow Interrupt .................................................... 137 Resetting, Using a Special Event Trigger Output (CCP) ................................................... 140 Special Event Trigger (CCP) ................................... 154 TMR1H Register ...................................................... 137 TMR1L Register ....................................................... 137 Use as a Real-Time Clock ....................................... 140 Timer2 .............................................................................. 143 Associated Registers ............................................... 144 Operation ................................................................. 143 Postscaler. See Postscaler, Timer2. PR2 Register ....................................................143, 156 Prescaler. See Prescaler, Timer2. SSP Clock Shift ................................................143, 144 TMR2 Register ......................................................... 143 TMR2 to PR2 Match Interrupt ...................143, 144, 156 Timer5 Block Diagram ......................................................... 146 Timing Diagrams Asynchronous Reception ......................................... 234 Asynchronous Transmission .................................... 231 Asynchronous Transmission (Back to Back) ........... 231 Auto-Wake-up Bit (WUE) During Normal Operation ............................................ 235 Auto-Wake-up Bit (WUE) During Sleep ................... 235 Brown-out Reset (BOR) ........................................... 358 Capture/Compare/PWM (CCP) ............................... 360 CLKO and I/O .......................................................... 357 Clock, Instruction Cycle ............................................. 61 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 Example SPI Master Mode (CKE = 0) ..................... 361 Example SPI Master Mode (CKE = 1) ..................... 362 Example SPI Slave Mode (CKE = 0) ....................... 363 Example SPI Slave Mode (CKE = 1) ....................... 364 External Clock (All Modes except PLL) .................... 355 Fail-Safe Clock Monitor ............................................ 282 I2C Bus Data ............................................................ 365 I2C Bus Start/Stop Bits ............................................. 365 I2C Reception (7-bit Address) .................................. 219 I2C Transmission (7-bit Address) ............................. 219 Low-Voltage Detect .................................................. 264 Low-Voltage Detect Characteristics ......................... 352 Master SSP I2C Bus Data ........................................ 367 Master SSP I2C Bus Start/Stop Bits ........................ 367 PWM Output ............................................................ 156 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST), Power-up Timer (PWRT) ........... 358 Send Break Character Sequence ............................ 236 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 55 SPI Mode (Master Mode) ......................................... 215 SPI Mode (Slave Mode with CKE = 0) ..................... 215 SPI Mode (Slave Mode with CKE = 1) ..................... 216 Synchronous Reception (Master Mode, SREN) ...... 239 Synchronous Transmission ...................................... 237 Synchronous Transmission (Through TXEN) .......... 238 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ........................................... 55 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 1 .......................................... 54 Time-out Sequence on Power-up (MCLR Not Tied to VDD): Case 2 .......................................... 54 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ........................ 54 Timer0 and Timer1 External Clock .......................... 359 Transition for Entry to SEC_IDLE Mode .................... 36 Transition for Entry to SEC_RUN Mode .................... 38 Transition for Entry to Sleep Mode ............................ 34 Transition for Two-Speed Start-up (INTOSC to HSPLL) ......................................... 280 Transition for Wake from RC_RUN Mode (RC_RUN to NFP) ............................................. 37 Transition for Wake from SEC_RUN Mode (Secondary Clock to HSPLL) ............................. 36 Transition for Wake from Sleep (HSPLL) ................... 34 Transition Timing For Wake From PRI_IDLE Mode ... 35 Transition Timing to PRI_IDLE Mode ........................ 35 Transition to RC_IDLE Mode ..................................... 37 Transition to RC_RUN Mode ..................................... 39 USART Synchronous Receive ( Master/Slave) ........ 369 USART SynchronousTransmission (Master/Slave) .................................................. 369 Timing Diagrams and Specifications ................................ 355 Capture/Compare/PWM Requirements ................... 360 CLKO and I/O Requirements ................................... 357 DC Characteristics - Internal RC Accuracy .............. 356 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 361 Example SPI Mode Requirements (Master Mode, CKE = 1) .................................. 362 Example SPI Mode Requirements (Slave Mode, CKE = 0) .................................... 363 Example SPI Slave Mode Requirements (CKE = 1) ......................................................... 364 External Clock Requirements .................................. 355 2003 Microchip Technology Inc. I2C Bus Data Requirements (Slave Mode) .............. 366 Master SSP I2C Bus Data Requirements ................ 368 Master SSP I2C Bus Start/Stop Bits Requirements .................................................. 367 PLL Clock ................................................................ 356 RESET, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ........................................ 358 Timer0 and Timer1 External Clock Requirements ... 359 USART Synchronous Receive Requirements ......... 369 USART Synchronous Transmission Requirements .................................................. 369 Top-of-Stack Access .......................................................... 58 TSTFSZ ........................................................................... 328 Two-Speed Start-up ..................................................267, 279 Two-Word Instructions Example Cases .......................................................... 62 TXSTA Register BRGH Bit ................................................................. 225 U UA .................................................................................... 212 Update Address bit, UA ................................................... 212 USART Asynchronous Mode ................................................ 230 12-bit Break Transmit and Receive ................. 236 Associated Registers, Receive ........................ 234 Associated Registers, Transmit ....................... 232 Auto-Wake-up on Sync Break ......................... 235 Receiver .......................................................... 233 Setting up 9-bit Mode with Address Detect ..... 233 Transmitter ...................................................... 230 Baud Rate Generator (BRG) ................................... 225 Associated Registers ....................................... 226 Auto-Baud Rate Detect .................................... 229 Baud Rate Error, Calculating ........................... 225 Baud Rates, Asynchronous Modes ................. 226 High Baud Rate Select (BRGH Bit) ................. 225 Power-Managed Mode Operation ................... 225 Sampling .......................................................... 225 Serial Port Enable (SPEN Bit) ................................. 221 Synchronous Master Mode ...................................... 237 Associated Registers, Reception ..................... 240 Associated Registers, Transmit ....................... 238 Reception ........................................................ 239 Transmission ................................................... 237 Synchronous Slave Mode ........................................ 241 Associated Registers, Receive ........................ 242 Associated Registers, Transmit ....................... 241 Reception ........................................................ 242 Transmission ................................................... 241 W Watchdog Timer (WDT) ............................................267, 278 Associated Registers ............................................... 279 Control Register ....................................................... 278 During Oscillator Failure .......................................... 281 Programming Considerations .................................. 278 WCOL bit ......................................................................... 213 Write Collision Detect bit (WCOL) ................................... 213 WWW, On-Line Support ...................................................... 6 X XORLW ............................................................................ 328 XORWF ........................................................................... 329 DS39616B-page 389 PIC18F2331/2431/4331/4431 NOTES: DS39616B-page 390 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site 042003 The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2003 Microchip Technology Inc. Preliminary DS39616B-page 391 PIC18F2331/2431/4331/4431 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC18F2331/2431/4331/4431 Literature Number: DS39616B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39616B-page 392 Preliminary 2003 Microchip Technology Inc. PIC18F2331/2431/4331/4431 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX XXX Device Temperature Range Package Pattern Examples: a) b) Device PIC18F2331/2431/4331/4431(1), PIC18F2331/2431/4331/4431T(1,2); VDD range 4.2V to 5.5V c) PIC18LF4431-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF2331-I/SO = Industrial temp., SOIC package, Extended VDD limits. PIC18F4331-I/P = Industrial temp., PDIP package, normal VDD limits. PIC18LF2331/2431/4331/4431(1), PIC18LF2331/2431/4331/44310T(1,2); VDD range 2.0V to 5.5V Temperature Range I = -40°C to +85°C (Industrial) Package PT SO SP P ML Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) Note 1: = = = = = TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP PDIP QFN 2: F = Standard Voltage range LF = Wide Voltage Range T = in tape and reel - SOIC and TQFP packages only. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2003 Microchip Technology Inc. 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Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 India Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Japan Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 DS39616B-page 394 Preliminary Singapore 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Austria Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910 France Parc d’Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands P. A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 11/24/03 2003 Microchip Technology Inc.