Self-protected FET with Temperature and Current Limit 42 V, 14 A, Single N-Channel, SOT-223

NIF5003N
Preferred Device
Self-Protected FET
with Temperature and
Current Limit
42 V, 14 A, Single N−Channel, SOT−223
HDPlus™ devices are an advanced series of power MOSFETs which
utilize ON Semiconductors latest MOSFET technology process to
achieve the lowest possible on−resistance per silicon area while
incorporating smart features. Integrated thermal and current limits
work together to provide short circuit protection. The devices feature
an integrated Drain−to−Gate Clamp that enables them to withstand
high energy in the avalanche mode. The Clamp also provides
additional safety margin against unexpected voltage transients.
Electrostatic Discharge (ESD) protection is provided by an integrated
Gate−to−Source Clamp.
Features
•
•
•
•
•
•
•
Short Circuit Protection/Current Limit
Thermal Shutdown with Automatic Restart
IDSS Specified at Elevated Temperature
Avalanche Energy Specified
Slew Rate Control for Low Noise Switching
Overvoltage Clamped Protection
Pb−Free Packages are Available
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VDSS
(Clamped)
RDS(on) TYP
ID MAX
(Limited)
42 V
53 mW @ 10 V
14 A
Drain
Gate
Input
Overvoltage
Protection
RG
ESD Protection
Temperature
Limit
4
Symbol
Value
Unit
Drain−to−Source Voltage Internally Clamped
VDSS
42
Vdc
Gate−to−Source Voltage
VGS
"14
Vdc
Drain Current
Continuous
Total Power Dissipation
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
Single Pulse Drain−to−Source Avalanche Energy
(VDD = 25 Vdc, VGS = 5.0 Vdc,
IL = 7.0 Apk, L = 9.5 mH, RG = 25 W)
Operating and Storage Temperature Range
(Note 3)
Current
Sense
ID
Internally Limited
PD
W
1.25
1.9
°C/W
RqJC
RqJA
RqJA
12
100
65
EAS
233
mJ
TJ, Tstg
−55 to 150
°C
1
2
3
MARKING DIAGRAM
GATE
1
4
2
DRAIN
3
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings
are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended
Operating Conditions may affect device reliability.
1. Surface mounted onto minimum pad size (0.412″ square) FR4 PCB, 1 oz cu.
2. Mounted onto 1″ square pad size (1.127″ square) FR4 PCB, 1 oz cu.
3. Normal pre−fault operating range. See thermal limit range conditions.
SOT−223
CASE 318E
STYLE 3
AYW
5003N G
G
Thermal Resistance
Junction−to−Case
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Current
Limit
Source
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
MPWR
DRAIN
SOURCE
A
= Assembly Location
Y
= Year
W
= Work Week
5003N = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2008
September, 2008 − Rev. 5
1
Publication Order Number:
NIF5003N/D
NIF5003N
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
42
40
46
45
51
51
Vdc
mV/°C
−
−
0.6
2.5
5.0
−
−
50
125
mAdc
1.0
−
1.7
5.0
2.2
−
Vdc
mV/°C
−
−
53
95
68
123
−
−
63
105
76
135
VSD
−
0.95
1.1
V
OFF CHARACTERISTICS
Drain−to−Source Clamped Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
(VGS = 0 Vdc, ID = 250 mAdc, TJ = −40°C to 150°C)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 32 Vdc, VGS = 0 Vdc)
(VDS = 32 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate Input Current
(VGS = 5.0 Vdc, VDS = 0 Vdc)
IGSS
mAdc
ON CHARACTERISTICS
Gate Threshold Voltage
(VDS = VGS, ID = 1.2 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 4)
(VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 25°C)
(VGS = 10 Vdc, ID = 3.0 Adc, TJ @ 150°C)
RDS(on)
Static Drain−to−Source On−Resistance (Note 4)
(VGS = 5.0 Vdc, ID = 3.0 Adc, TJ @ 25°C)
(VGS = 5.0 Vdc, ID = 3.0 Adc, TJ @ 150°C)
RDS(on)
Source−Drain Forward On Voltage
(IS = 7.0 A, VGS = 0 V)
mW
mW
SWITCHING CHARACTERISTICS
Turn−on Time
(Vin to 90% ID)
RL = 4.7 W, Vin = 0 to 10 V, VDD = 12 V
T(on)
−
16
20
ms
Turn−off Time
(Vin to 10% ID)
RL = 4.7 W, Vin = 10 to 0 V, VDD = 12 V
T(off)
−
80
100
ms
Slew Rate On
RL = 4.7 W,
Vin = 0 to 10 V, VDD = 12 V
−dVDS/dton
−
1.4
−
V/ms
Slew Rate Off
RL = 4.7 W,
Vin = 10 to 0 V, VDD = 12 V
dVDS/dtoff
−
0.5
−
V/ms
SELF PROTECTION CHARACTERISTICS (TJ = 25°C unless otherwise noted) (Note 5)
Current Limit
(VGS = 5.0 Vdc)
VDS = 10 V (VGS = 5.0 Vdc, TJ = 150°C)
ILIM
12
7.0
18
13
24
18
Adc
Current Limit
(VGS = 10 Vdc)
VDS = 10 V (VGS = 10 Vdc, TJ = 150°C)
ILIM
18
13
22
18
30
25
Adc
Temperature Limit (Turn−off)
VGS = 5.0 Vdc
TLIM(off)
150
175
200
°C
Thermal Hysteresis
VGS = 5.0 Vdc
DTLIM(on)
−
15
−
°C
Temperature Limit (Turn−off)
VGS = 10 Vdc
TLIM(off)
150
165
185
°C
Thermal Hysteresis
VGS = 10 Vdc
DTLIM(on)
−
15
−
°C
ESD ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Electro−Static Discharge Capability
Human Body Model (HBM)
ESD
4000
−
−
V
Electro−Static Discharge Capability
Machine Model (MM)
ESD
400
−
−
V
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
5. Fault conditions are viewed as beyond the normal operating range of the part.
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2
NIF5003N
TYPICAL PERFORMANCE CURVES
VGS = 7 V
25
VGS = 10 V
VGS = 6 V
VGS = 8 V
20
15
VGS = 5 V
10
VGS = 4 V
5
0.5
0
1.5
1
2
2.5
3
3.5
4
4.5
12
10
6
4
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3
5
4
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
10
1
4
0.075
TJ = 25°C
0.07
VGS = 5 V
0.065
0.06
0.055
VGS = 10 V
0.05
0.045
0.04
0.035
0.03
2
3
4
6
5
7
8
9
10
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
100000
ID = 3 A
VGS = 5 V
VGS = 0 V
TJ = 150°C
10000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
100°C
8
0
5
ID = 3 A
TJ = 25°C
1.6
25°C
14
1.5
3.5
2
3
2.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.9
1.8
TJ = −55°C
16
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1.0
2
VDS ≥ 10 V
18
2
VGS = 3 V
TJ = 25°C
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
30
20
Current Limit
Inception Region
VGS = 9 V
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (AMPS)
35
1.4
1.2
1.0
1000
TJ = 100°C
100
0.8
0.6
−50 −30 −10
10
30
50
70
90
110 130 150
10
0
5
10
15
20
25
30
35
40
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
45
NIF5003N
TYPICAL PERFORMANCE CURVES
IS, SOURCE CURRENT (AMPS)
10
VGS = 0 V
TJ = 25°C
1
0.1
0.4
0.5
0.6
0.7
0.8
0.9
1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 7. Diode Forward Voltage vs. Current
ORDERING INFORMATION
Package
Shipping†
NIF5003NT1
SOT−223
1000 / Tape & Reel
NIF5003NT1G
SOT−223
(Pb−Free)
1000 / Tape & Reel
NIF5003NT3
SOT−223
4000 / Tape & Reel
NIF5003NT3G
SOT−223
(Pb−Free)
4000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
NIF5003N
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE L
D
b1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
4
HE
E
1
2
3
b
e1
e
0.08 (0003)
C
q
A
A1
L1
DIM
A
A1
b
b1
c
D
E
e
e1
L1
HE
MILLIMETERS
NOM
MAX
1.63
1.75
0.06
0.10
0.75
0.89
3.06
3.20
0.29
0.35
6.50
6.70
3.50
3.70
2.30
2.40
0.94
1.05
1.75
2.00
7.00
7.30
10°
−
q
MIN
1.50
0.02
0.60
2.90
0.24
6.30
3.30
2.20
0.85
1.50
6.70
0°
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
MIN
0.060
0.001
0.024
0.115
0.009
0.249
0.130
0.087
0.033
0.060
0.264
0°
INCHES
NOM
0.064
0.002
0.030
0.121
0.012
0.256
0.138
0.091
0.037
0.069
0.276
−
MAX
0.068
0.004
0.035
0.126
0.014
0.263
0.145
0.094
0.041
0.078
0.287
10°
SOLDERING FOOTPRINT*
3.8
0.15
2.0
0.079
2.3
0.091
2.3
0.091
6.3
0.248
2.0
0.079
1.5
0.059
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
HDPlus is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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For additional information, please contact your local
Sales Representative
NIF5003N/D