MMSF7N03Z Power MOSFET 7 Amps, 30 Volts N−Channel SO−8 EZFETst are an advanced series of Power MOSFETs which contain monolithic back−to−back zener diodes. These zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain−to−source diode has a very low reverse recovery time. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc−dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. • Zener Protected Gates Provide Electrostatic Discharge Protection • Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life • Designed to withstand 200V Machine Model and 2000V Human Body Model • Logic Level Gate Drive − Can Be Driven by Logic ICs • Miniature SO−8 Surface Mount Package − Saves Board Space • Diode Is Characterized for Use In Bridge Circuits • Diode Exhibits High Speed, With Soft Recovery • IDSS Specified at Elevated Temperature • Mounting Information for SO−8 Package Provided http://onsemi.com 7 AMPERES 30 VOLTS RDS(on) = 30 mW N−Channel D G S MARKING DIAGRAM SO−8 CASE 751 STYLE 12 8 7N03Z LYWW 1 7N03Z L Y WW = Device Code = Location Code = Year = Work Week PIN ASSIGNMENT Source 1 8 Drain Source 2 7 Drain Source 3 6 Drain Gate 4 5 Drain Top View ORDERING INFORMATION © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 2 1 Device Package MMSF7N03ZR2 SO−8 Shipping 2500 Tape & Reel Publication Order Number: MMSF7N03Z/D MMSF7N03Z MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 30 Vdc Drain−to−Gate Voltage (RGS = 1.0 MΩ) VDGR 30 Vdc Gate−to−Source Voltage − Continuous VGS ± 15 Vdc Drain Current − Continuous @ TA = 25°C (Note 1) − Continuous @ TA = 70°C (Note 1) − Pulsed Drain Current (Note 3) ID ID 7.5 5.6 60 Adc Total Power Dissipation @ TA = 25°C (Note 1) Linear Derating Factor (Note 1) PD 2.5 20 Watts mW/°C Total Power Dissipation @ TA = 25°C (Note 2) Linear Derating Factor (Note 2) PD 1.6 12 Watts mW/°C TJ, Tstg − 55 to 150 IDM Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 Ω) Thermal Resistance − Junction to Ambient (Note 1) − Junction to Ambient (Note 2) 1. When mounted on 1″ square FR−4 or G−10 board (VGS = 10 V, @ 10 Seconds) 2. When mounted on 1″ square FR−4 or G−10 board (VGS = 10 V, @ Steady State) 3. Repetitive rating; pulse width limited by maximum junction temperature. http://onsemi.com 2 EAS RθJA Apk °C mJ 450 50 80 °C/W MMSF7N03Z ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 30 − − 35 − − − − 0.03 0.15 2.0 10 − 1.3 5.0 1.0 − 2.0 5.5 3.0 − − − 22 30 30 40 gFS 4.0 9.5 − Mhos Ciss − 750 1500 pF Coss − 340 680 Crss − 45 90 td(on) − 40 80 tr − 90 180 td(off) − 470 940 tf − 170 340 td(on) − 120 240 OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 μAdc) Temperature Coefficient (Positive) (Cpk ≥ 2.0) (Notes 4 & 6) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0) IGSS Vdc mV/°C μAdc μAdc ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (Cpk ≥ 2.0) (VDS = VGS, ID = 250 μAdc) Threshold Temperature Coefficient (Negative) (Notes 4 & 6) Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 7.5 Adc) (VGS = 4.5 Vdc, ID = 3.8 Adc) (Cpk ≥ 2.0) (Notes 4 & 6) Forward Transconductance (VDS = 3.0 Vdc, ID = 3.8 Adc) (Note 4) VGS(th) RDS(on) Vdc mV/°C mΩ DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDS = 15 Vdc, ID = 5.0 Adc, VGS = 10 Vdc, RG = 6 Ω) (Note 4) Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 15 Vdc, ID = 5.0 Adc, VGS = 4.5 Vdc, RG = 6 Ω) (Note 4) Fall Time Gate Charge (VDS = 24 Vdc, ID = 5.0 Adc, VGS = 10 Vdc) (Note 4) tr − 350 700 td(off) − 430 860 tf − 140 280 QT − 34 48 Q1 − 3.5 − Q2 − 9.5 − Q3 − 6.5 − − − 0.83 0.67 1.6 − trr − 110 − ta − 22 − tb − 90 − QRR − 0.17 − ns ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 4) (IS = 7.5 Adc, VGS = 0 Vdc) (Note 4) (IS = 7.5 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 7.5 Adc, VGS = 0 Vdc, dIS/dt = 100 A/μs) (Note 4) Reverse Recovery Storage Charge 4. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. Max limit − Typ 6. Reflects typical values. Cpk = 3 x SIGMA http://onsemi.com 3 VSD Vdc ns μC MMSF7N03Z TYPICAL ELECTRICAL CHARACTERISTICS 10 10 TJ = 25°C VDS ≥ 10 V I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 3.5 V VGS = 10 V 8 4.5 V 3.8 V 6 3.3 V 4 3.1 V 2 8 6 4 100°C 25°C 2 2.7 V 0 0.4 0.8 TJ = −55°C 1.6 1.2 0 2 2.6 3 3.4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 2.5 A TJ = 25°C 0.08 0.06 0.04 0.02 0 2 4 6 8 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 10 3.8 0.05 TJ = 25°C 0.04 VGS = 4.5 0.03 10 V 0.02 0.01 0 0 2 4 8 6 10 ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 1000 2.0 VGS = 0 V VGS = 10 V ID = 2.5 A 1.5 I DSS , LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2.2 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.1 0 1.8 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS) 0 1.0 TJ = 125°C 100 100°C 10 0.5 0 −50 −25 0 25 50 75 100 125 1 150 0 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 30 MMSF7N03Z POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Δt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 2500 TJ = 25°C VGS = 0 V C, CAPACITANCE (pF) 2000 Ciss 1500 1000 Coss 500 Crss 0 0 6 12 18 24 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 5 30 12 24 QT 20 10 16 8 VDS VGS 12 6 Q1 4 Q2 8 ID = 5 A TJ = 25°C 2 4 Q3 0 0 5 10 15 20 25 30 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) t, TIME (ns) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) MMSF7N03Z 0 35 1000 VDD = 15 V ID = 7.5 A VGS = 10 V TJ = 25°C td(off) tf 100 tr td(on) 10 1 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by http://onsemi.com 6 MMSF7N03Z 5 VGS = 0 V TJ = 25°C I S , SOURCE CURRENT (AMPS) 4 3 2 1 0 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current di/dt = 300 A/μs Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta t, TIME Figure 11. Reverse Recovery Time (trr) SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 μs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RθJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 7 MMSF7N03Z 500 10 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) VGS = 15 V SINGLE PULSE TC = 25°C 100 μs 1 ms 10 ms 1 0.1 0.01 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 ID = 15 A 400 300 200 100 0 10 100 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 12. Maximum Rated Forward Biased Safe Operating Area Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature TYPICAL ELECTRICAL CHARACTERISTICS 10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE I D , DRAIN CURRENT (AMPS) 100 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 Normalized to θja at 10s. Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.0307 F 0.1668 F 0.5541 F 0.6411 Ω 0.9502 Ω 0.01 0.01 1.9437 F 72.416 F SINGLE PULSE 0.001 1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 t, TIME (s) 1.0E+00 1.0E+01 Figure 14. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 15. Diode Reverse Recovery Waveform http://onsemi.com 8 1.0E+02 Ambient 1.0E+03 MMSF7N03Z INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self−align when subjected to a solder reflow process. 0.060 1.52 0.275 7.0 0.155 4.0 0.024 0.6 0.050 1.270 inches mm SO−8 POWER DISSIPATION into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 2.5 Watts. The power dissipation of the SO−8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO−8 package, PD can be calculated as follows: PD = PD = 150°C − 25°C = 2.5 Watts 50°C/W The 50°C/W for the SO−8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.5 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Cladt. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint. TJ(max) − TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values SOLDERING PRECAUTIONS • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. * * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 9 MMSF7N03Z TYPICAL SOLDER HEATING PROFILE temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 −189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 16 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows STEP 1 PREHEAT ZONE 1 “RAMP” 200°C STEP 2 STEP 3 VENT HEATING “SOAK” ZONES 2 & 5 “RAMP” DESIRED CURVE FOR HIGH MASS ASSEMBLIES STEP 4 HEATING ZONES 3 & 6 “SOAK” 160°C STEP 5 STEP 6 STEP 7 HEATING VENT COOLING ZONES 4 & 7 205° TO 219°C “SPIKE” PEAK AT 170°C SOLDER JOINT 150°C 150°C 100°C 140°C 100°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 5°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile http://onsemi.com 10 MMSF7N03Z PACKAGE DIMENSIONS SO−8 CASE 751−07 ISSUE V −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 STYLE 12: PIN 1. 2. 3. 4. 5. 6. 7. 8. INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN EZFET is a trademark of Semiconductor Components Industries, LLC (SCILLC). Thermal Clad is a registered trademark of the Bergquist Company. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 11 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MMSF7N03Z/D