Si2333DS Datasheet

Si2333DS
Vishay Siliconix
P-Channel 12-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
- 12
RDS(on) (Ω)
ID (A)
0.032 at VGS = - 4.5 V
- 5.3
0.042 at VGS = - 2.5 V
- 4.6
0.059 at VGS = - 1.8 V
- 3.9
• Halogen-free According to IEC 61249-2-21
Available
• TrenchFET® Power MOSFET
APPLICATIONS
• Load Switch
• PA Switch
TO-236
(SOT-23)
G
1
3
S
D
2
Top View
Si2333DS (E3)*
* Marking Code
Ordering Information: Si2333DS-T1-E3 (Lead (Pb)-free)
Si2333DS-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
5s
Steady State
Drain-Source Voltage
VDS
- 12
Gate-Source Voltage
VGS
±8
Continuous Drain Current (TJ = 150 °C)a, b
TA = 25 °C
TA = 70 °C
Continuous Source Current (Diode Conduction)a, b
IS
TA = 25 °C
TA = 70 °C
PD
- 4.1
- 4.2
- 3.3
- 20
- 1.0
- 0.6
1.25
0.75
0.8
0.48
TJ, Tstg
Operating Junction and Storage Temperature Range
V
- 5.3
IDM
Pulsed Drain Current
Maximum Power Dissipationa, b
ID
Unit
- 55 to 150
A
W
°C
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
Symbol
t≤5s
Steady State
Steady State
RthJA
RthJF
Typical
Maximum
75
100
120
166
40
50
Unit
°C/W
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. Pulse width limited by maximum junction temperature.
Document Number: 72023
S09-0130-Rev. C, 02-Feb-09
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Si2333DS
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Limits
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Drain-Source Breakdown Voltage
Gate-Threshold Voltage
Gate-Body Leakage
V(BR)DSS
VGS = 0 V, ID = - 250 µA
- 12
VGS(th)
VDS = VGS, ID = - 250 µA
- 0.40
IGSS
VDS = 0 V, VGS = ± 8 V
± 100
VDS = - 9.6 V, VGS = 0 V
-1
VDS = - 9.6 V, VGS = 0 V, TJ = 55 °C
- 10
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-Resistancea
RDS(on)
VDS ≤ - 5 V, VGS = - 4.5 V
- 1.0
- 20
V
nA
µA
A
VGS = - 4.5 V, ID = - 5.3 A
0.025
0.032
VGS = - 2.5 V, ID = - 4.6 A
0.033
0.042
VGS = - 1.8 V, ID = - 2.0 A
0.046
0.059
Forward Transconductancea
gfs
VDS = - 5 V, ID = - 5.3 A
17
Diode Forward Voltage
VSD
IS = - 1.0 A, VGS = 0 V
- 0.7
- 1.2
11.5
18
Ω
S
V
b
Dynamic
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
VDS = - 6 V, VGS = - 4.5 V
ID ≅ - 5.3 A
nC
1.5
3.2
1100
VDS = - 6 V, VGS = 0 V, f = 1 MHz
pF
390
300
Switchingc
Turn-On Time
Turn-Off Time
td(on)
tr
td(off)
tf
VDD = - 6 V, RL = 6 Ω
ID ≅ - 1.0 A, VGEN = - 4.5 V
RG = 6 Ω
25
40
45
70
72
110
60
90
ns
Notes:
a. Pulse test: PW ≤ 300 µs, duty cycle ≤ 2 %.
b. For design aid only, not subject to production testing.
c. Switching time is essentially independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 72023
S09-0130-Rev. C, 02-Feb-09
Si2333DS
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
20
20
VGS = 5 V thru 2.5 V
TC = - 55 °C
2V
25 °C
16
ID - Drain Current (A)
ID - Drain Current (A)
16
12
8
1.5 V
4
125 °C
12
8
4
1V
0
0
1
2
3
4
0
0.0
5
0.5
VDS - Drain-to-Source Voltage (V)
1.5
2.0
2.5
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
0.15
1800
1500
0.12
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
1.0
0.09
VGS = 1.8 V
0.06
VGS = 2.5 V
0.03
1200
Ciss
900
600
Coss
Crss
300
VGS = 4.5 V
0.00
0
0
4
8
12
16
20
0
6
9
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
5
12
1.4
VDS = 6 V
ID = 5.3 A
4
1.3
RDS(on) - On-Resistance
(Normalized)
VGS - Gate-to-Source Voltage (V)
3
ID - Drain Current (A)
3
2
1
VGS = 4.5 V
ID = 5.3 A
1.2
1.1
1.0
0.9
0
0
3
6
9
12
Qg - Total Gate Charge (nC)
Gate Charge
Document Number: 72023
S09-0130-Rev. C, 02-Feb-09
15
0.8
- 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
On-Resistance vs. Junction Temperature
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Si2333DS
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.15
20
TJ = 150 °C
R DS(on) - On-Resistance (Ω)
IS - Source Current (A)
10
TJ = 25 °C
1
0.12
0.09
ID = 5.3 A
ID = 2 A
0.06
0.03
0.00
0.1
0.0
0.2
0.4
0.6
0.8
1.0
0
1.2
2
3
4
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.4
5
12
ID = 140 µA
0.3
10
8
0.2
Power (W)
V GS(th) Variance (V)
1
0.1
6
4
0.0
TA = 25 °C
2
- 0.1
- 0.2
- 50
0
- 25
0
25
50
75
100
125
150
0.01
0.1
1
10
100
600
Time (s)
TJ - Temperature (°C)
Single Pulse Power
Threshold Voltage
100
IDM Limited
Limited by RDS(on)*
P(t) = 0.0001
ID - Drain Current (A)
10
P(t) = 0.001
1
P(t) = 0.01
ID(on)
Limited
P(t) = 0.1
0.1
P(t) = 1
P(t) = 10
DC
TA = 25 °C
Single Pulse
BVDSS Limited
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
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Document Number: 72023
S09-0130-Rev. C, 02-Feb-09
Si2333DS
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
t1
0.05
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 120 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
4. Surface Mounted
Single Pulse
0.01
10- 4
10- 3
10- 2
10- 1
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72023.
Document Number: 72023
S09-0130-Rev. C, 02-Feb-09
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Package Information
Vishay Siliconix
SOT-23 (TO-236): 3-LEAD
b
3
E1
1
E
2
e
S
e1
D
0.10 mm
C
0.004"
A2
A
C
q
Gauge Plane
Seating Plane
Seating Plane
C
A1
Dim
0.25 mm
L
L1
MILLIMETERS
Min
INCHES
Max
Min
Max
0.044
A
0.89
1.12
0.035
A1
0.01
0.10
0.0004
0.004
A2
0.88
1.02
0.0346
0.040
b
0.35
0.50
0.014
0.020
c
0.085
0.18
0.003
0.007
D
2.80
3.04
0.110
0.120
E
2.10
2.64
0.083
0.104
E1
1.20
1.40
0.047
e
0.95 BSC
e1
L
1.90 BSC
0.40
L1
q
0.0748 Ref
0.60
0.016
0.64 Ref
S
0.024
0.025 Ref
0.50 Ref
3°
0.055
0.0374 Ref
0.020 Ref
8°
3°
8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
Document Number: 71196
09-Jul-01
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AN807
Vishay Siliconix
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
ambient air. This pattern uses all the available area underneath the
body for this purpose.
0.114
2.9
0.081
2.05
0.150
3.8
0.059
1.5
0.0394
1.0
0.037
0.95
FIGURE 1. Footprint With Copper Spreading
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
Document Number: 70739
26-Nov-03
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
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Application Note 826
Vishay Siliconix
0.049
(1.245)
0.029
0.022
(0.559)
(0.724)
0.037
(0.950)
(2.692)
0.106
RECOMMENDED MINIMUM PADS FOR SOT-23
0.053
(1.341)
0.097
(2.459)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index Return to Index
APPLICATION NOTE
Document Number: 72609
Revision: 21-Jan-08
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Revision: 02-Oct-12
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Document Number: 91000