Si2306BDS Vishay Siliconix N-Channel 30-V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 30 RDS(on) (Ω) ID (A) 0.047 at VGS = 10 V 4.0 0.065 at VGS = 4.5 V 3.5 • Halogen-free Option Available • TrenchFET® Power MOSFET • 100 % Rg Tested Qg (Typ.) 3.0 RoHS COMPLIANT TO-236 (SOT-23) G 1 3 S D 2 Top View Si2306BDS (L6 )* * Marking Code Ordering Information: Si2306BDS-T1-E3 (Lead (Pb)-free) Si2306BDS-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol 5s Steady State Drain-Source Voltage VDS 30 Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C)a, b TA = 25 °C TA = 70 °C Continuous Source Current (Diode Conduction)a, b IS TA = 25 °C TA = 70 °C PD 3.16 3.5 2.7 20 1.04 0.62 1.25 0.75 0.8 0.48 TJ, Tstg Operating Junction and Storage Temperature Range V 4.0 IDM Pulsed Drain Current Maximum Power Dissipationa, b ID Unit - 55 to 150 A W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Foot (Drain) Symbol t≤5s Steady State Steady State RthJA RthJF Typical Maximum 80 100 130 166 60 75 Unit °C/W Notes: a. Surface Mounted on FR4 board, t ≤ 5 s. b. Pulse width limited by maximum junction temperature. c. Surface Mounted on FR4 board. For SPICE model information via the Worldwide Web: http://www.vishay.com/www/product/spice.htm Document Number: 73234 S-80642-Rev. B, 24-Mar-08 www.vishay.com 1 Si2306BDS Vishay Siliconix SPECIFICATIONS TA = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. Static Drain-Source Breakdown Voltage Gate-Threshold Voltage Gate-Body Leakage V(BR)DSS VGS(th) IGSS 30 1.0 Zero Gate Voltage Drain Current IDSS On-State Drain Currenta ID(on) VGS = 0 V, ID = 250 µA VDS = VGS, ID = 250 µA VDS = 0 V, VGS = ± 20 V VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 0 V, TJ = 55 °C VDS ≥ 4.5 V, VGS = 10 V VGS = 10 V, ID = 3.5 A VGS = 4.5 V, ID = 2.8 A VDS = 4.5 V, ID = 2.5 A IS = 1.25 A, VGS = 0 V Drain-Source On-Resistancea RDS(on) gfs Forward Transconductancea VSD Diode Forward Voltage Dynamic Qg Gate Charge Qgt Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge Rg Gate Resistance Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time trr Reverse Recovery Time Qrr Body Diode Reverse Recovery Charge Notes: a. Pulse test: Pulse width ≤ 300 µs, duty cycle ≤ 2 %. Limits Typ. Unit Max. V 3.0 ± 100 0.5 10 nA µA 6 A VDS = 15 V, VGS = 5 V, ID = 2.5 A VDS = 15 V, VGS = 10 V, ID = 2.5 A f = 1.0 MHz 2.5 VDS = 15 V, VGS = 0 V, f = 1 MHz VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω IF = 1.25 A, di/dt = 100 A/µs 0.038 0.052 7.0 0.8 0.047 0.065 3.0 6 1.6 0.6 5 305 65 29 4.5 9 7 12 14 6 14 6 11 18 25 10 21 10 Ω S V 1.2 nC Ω 7.5 pF ns nC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 20 20 VGS = 10 thru 5 V 16 4V I D - Drain Current (A) I D - Drain Current (A) 16 12 8 12 8 TC = 125 °C 4 4 25 °C 3V - 55 °C 0 0 www.vishay.com 2 1 2 3 4 5 6 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 4.0 4.5 Document Number: 73234 S-80642-Rev. B, 24-Mar-08 Si2306BDS Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.10 400 Ciss 300 0.06 C - Capacitance (pF) R DS(on) - On-Resistance (Ω) 350 0.08 VGS = 4.5 V VGS = 10 V 0.04 250 200 150 100 Coss 0.02 Crss 50 0.00 0 0 2 4 6 8 10 12 14 16 0 15 20 25 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) Capacitance 30 1.6 VDS = 15 V ID = 3.5 A VGS = 10 V ID = 3.5 A 8 6 4 (Normalized) 1.4 R DS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 10 On-Resistance vs. Drain Current 10 2 1.2 1.0 0.8 0 0 1 2 3 4 5 0.6 - 50 6 0 25 50 75 100 125 TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature 150 0.5 R DS(on) - On-Resistance (Ω) TJ = 150 °C TJ = 25 °C 1 0.1 0.0 - 25 Qg - Total Gate Charge (nC) 10 I S - Source Current (A) 5 0.4 ID = 3.5 A 0.3 0.2 0.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage Document Number: 73234 S-80642-Rev. B, 24-Mar-08 10 www.vishay.com 3 Si2306BDS Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.4 10 0.2 8 0.0 - 0.2 TA = 25 °C Single Pulse 6 Power (W) V GS(th) Variance (V) ID = 250 µA 4 - 0.4 2 - 0.6 - 0.8 - 50 - 25 0 25 50 75 100 TJ - Temperature (°C) 125 0 0.01 150 1 0.1 10 100 600 Time (s) Threshold Voltage Single Pulse Power 100 Limited by RDS(on)* IDM Limited 10 µs I D - Drain Current (A) 10 100 µs 1 1 ms 10 ms TA = 25 °C Single Pulse 0.1 100 ms DC, 100 s, 10 s, 1 s 0.01 0.1 BVDSS Limited 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which R DS(on) is specified Safe Operating Area 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 PDM 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = R thJA = 130 °C/W 3. T JM - T A = PDMZthJA(t) Single Pulse 0.01 10- 4 10- 3 4. Surface Mounted 10- 2 10- 1 1 Square Wave Pulse Duration (s) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?73234. www.vishay.com 4 Document Number: 73234 S-80642-Rev. B, 24-Mar-08 Package Information Vishay Siliconix SOT-23 (TO-236): 3-LEAD b 3 E1 1 E 2 e S e1 D 0.10 mm C 0.004" A2 A C q Gauge Plane Seating Plane Seating Plane C A1 Dim 0.25 mm L L1 MILLIMETERS Min INCHES Max Min Max 0.044 A 0.89 1.12 0.035 A1 0.01 0.10 0.0004 0.004 A2 0.88 1.02 0.0346 0.040 b 0.35 0.50 0.014 0.020 c 0.085 0.18 0.003 0.007 D 2.80 3.04 0.110 0.120 E 2.10 2.64 0.083 0.104 E1 1.20 1.40 0.047 e 0.95 BSC e1 L 1.90 BSC 0.40 L1 q 0.0748 Ref 0.60 0.016 0.64 Ref S 0.024 0.025 Ref 0.50 Ref 3° 0.055 0.0374 Ref 0.020 Ref 8° 3° 8° ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 Document Number: 71196 09-Jul-01 www.vishay.com 1 AN807 Vishay Siliconix Mounting LITTLE FOOTR SOT-23 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET footprint . In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. ambient air. This pattern uses all the available area underneath the body for this purpose. 0.114 2.9 0.081 2.05 0.150 3.8 0.059 1.5 0.0394 1.0 0.037 0.95 FIGURE 1. Footprint With Copper Spreading The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board. Figure 1 shows the footprint with copper spreading for the SOT-23 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the Document Number: 70739 26-Nov-03 Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device. www.vishay.com 1 Application Note 826 Vishay Siliconix 0.049 (1.245) 0.029 0.022 (0.559) (0.724) 0.037 (0.950) (2.692) 0.106 RECOMMENDED MINIMUM PADS FOR SOT-23 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72609 Revision: 21-Jan-08 www.vishay.com 25 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Material Category Policy Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000