PIC24FXXKAXXX PIC24FJXXGAXXX to PIC24FXXKAXXX Migration Guide INTRODUCTION CONTENTS The PIC24FXXKAXXX (PIC24F ‘K’) device family includes many new features and is the low-power extension of Microchip’s PIC24FJXXGAXXX (PIC24F ‘J’) device family, with standby current as low as 20 nA. PIC24F ‘K’ Family Overview .......................................2 New PIC24F ‘K’ Family Features ........................3 Unsupported PIC24F ‘J’ Family Features................3 Migration Considerations.....................................3 Memory Organization, Program Memory and Data EEPROM Memory ......................................................4 New PIC24F ‘K’ Family Features ........................5 Unsupported PIC24F ‘J’ Family Features................5 Migration Considerations.....................................5 Power-Managed Modes/Oscillator Configurations .....6 New PIC24F ‘K’ Family Features ........................7 Unsupported PIC24F ‘J’ Family Features................7 Migration Considerations.....................................7 The distinguishing features of the PIC24FJXXKAXXX devices include: • Supply Voltage (VDD and VDDCORE) • Internal MCLR Option - MCLR pin can be configured as an input pin • CodeGuard™ Security Features with the Boot Segment • Data EEPROM Memory • Programmable Brown-out Reset (BOR) • 500 kHz LPFRC Oscillator • Dedicated Memory Block for Configuration Bits This document highlights the similarities and differences between the PIC24F ‘J’ and PIC24F ‘K’ device families. It also covers the general principles for migrating PIC24F ‘J’ applications to PIC24F ‘K’ devices. Each section of this document describes one peripheral or major feature of the PIC24F ‘K’ device family. The sections are organized with the following information, as applicable: Programmable Brown-out Reset (BOR) .....................7 New PIC24F ‘K’ Family Features ........................7 Unsupported PIC24F ‘J’ Family Features................7 Migration Considerations.....................................7 Summary ....................................................................8 References .................................................................8 Document Revision History ........................................9 • Comparison of PIC24F ‘K’ and PIC24F ‘J’ Peripheral Features • List of new PIC24F ‘K’ Features • List of any Unsupported PIC24F ‘J’ Features • Summary of Migration Considerations For more information on new or modified modules, refer to the specific PIC24F ‘K’ device data sheet (see References). 2011 Microchip Technology Inc. Preliminary DS39990A-page 1 PIC24FXXKAXXX PIC24F ‘K’ FAMILY OVERVIEW Table 1 compares different features of the PIC24F ‘J’ and PIC24F ‘K’ device families. The PIC24F ‘K’ is a device family with low-power features and nanoWatt XLP technology. This family of devices is available in 14-pin, 20-pin, 28-pin and 44-pin packages and is largely pin compatible with other PIC24F products for easy migration. TABLE 1: COMPARISON BETWEEN PIC24F ‘J’ AND PIC24F ‘K’ Feature Description Operating Voltage Internal MCLR Option Option to Configure MCLR Program Memory Data EEPROM Memory BOR Device Configuration Bit Locations Device Programming Modes Packages DS39990A-page 2 • • • • • PIC24F ‘J’ PIC24F ‘K’ 2V to 3.6V 1.8V to 3.6V or 2V to 5.5V No Yes No Yes; as an input pin Only General Segment (16 Kbytes to 256 Kbytes) General Segment and Configurable Boot Segment with CodeGuard™ Security Feature (4 Kbytes to 32 Kbytes) Emulated Yes Fixed BOR Programmable BOR End of User Program Memory Dedicated Memory Locations in Configuration Memory Space Supports only Low-Voltage Programming Supports both Low-Voltage and High-Voltage Programming 28-pin SPDIP, SSOP, SOIC, QFN 44-pin TQFP, QFN 64-pin TQFP, QFN 80-pin TQFP, QFN 100-pin TQFP, QFN Preliminary • • • • • 14-pin PDIP, TSSOP 20-pin PDIP, SSOC, SOIC, QFN 28-pin SPDIP, SSOP, SOIC, QFN 44-pin TQFP, QFN 48-pin UQFN 2011 Microchip Technology Inc. PIC24FXXKAXXX New PIC24F ‘K’ Family Features Migration Considerations In addition to the rich feature set of the PIC24F ‘J’ device families, the following new features are available to improve flexibility. Consider the following when migrating from the PIC24F ‘J’ to the PIC24F ‘K’ family: • Supply Voltage – The PIC24F ‘K’ devices are available in either 5V or 3.3V devices. The 5V devices have an on-chip 3.3V regulator to power the core, whereas the 3.3V devices have no regulator. • Low-Power Technology – The standby power consumption of this device family is reduced to around 20 nA. • Program Memory with Boot Segment – The program memory of this device family is divided into a General Segment (GS) and Boot Segment (BS). If a Boot Segment is enabled, then the CodeGuard security feature is available. • Data EEPROM – The dedicated data EEPROM module can save and retrieve data, even when the power cycle occurs. • Programmable BOR – The BOR trip voltage can be selected, and also, the BOR can be enabled or disabled. Unsupported PIC24F ‘J’ Family Features • Supply Voltage – The PIC24F ‘J’ parts require a voltage regulator to operate between 2.75V and 3.6V. PIC24F ‘K’ parts do not require a voltage regulator to operate at these voltages. PIC24F ‘J’ VDDCORE and regulator enable pins are available as general purpose I/O for the PIC24F ‘K’ devices. PIC24F ‘FV’ devices are available that support 5V operation. These devices use an internal regulator similar to PIC24F ‘J’ parts. • MCLR Pin – No changes are needed to MCLR when migrating from PIC24F ‘J’ to ‘K’ device families. An additional feature for the PIC24F ‘K’ devices is that MCLR can be configured as an input pin. High-Voltage Programming Entry mode must be used to disable the MCLR function by its respective Configuration bit. Note that the LowVoltage Programming entry is then no longer available. • I/O Ports – The PIC24F ‘J’ devices pins are grouped as 3.3V and 5.5V tolerant inputs. Only PIC24 ‘FV’ families support 5.5V input voltages. If input voltages greater than 3.3V are needed, PIC24 ‘FV’ devices must be used. The I/O pins of the PIC24F ‘K’ device family cannot have an input of more than VDD + 0.3V. 2011 Microchip Technology Inc. Preliminary DS39990A-page 3 PIC24FXXKAXXX MEMORY ORGANIZATION, PROGRAM MEMORY AND DATA EEPROM MEMORY Table 2 compares different features of the PIC24F ‘J’ and PIC24F ‘K’ memory organization. The program memory of the PIC24F ‘K’ device family can be divided into two segments: Boot Segment and General Segment. Both the segments have dedicated protection bits. The length of the Boot Segment can be configured. TABLE 2: COMPARISON BETWEEN PIC24F ‘J’ AND PIC24F ‘K’ MEMORY ORGANIZATION Feature Description Program Memory Size PIC24F ‘J’ PIC24F ‘K’ 16 Kbytes to 256 Kbytes 4 Kbytes to 32 Kbytes Only General Segment General Segment and Boot Segment with CodeGuard™ Security Feature Erase Size 512 Instructions Programmable, 32/64/128 Instructions Write Size 64 Instructions 32 Instructions Emulated Yes Last Few Locations of User Program Memory Specific Memory Locations in Configuration Space Program Memory Segment Data EEPROM Device Configuration Bit Locations DS39990A-page 4 Preliminary 2011 Microchip Technology Inc. PIC24FXXKAXXX New PIC24F ‘K’ Family Features Unsupported PIC24F ‘J’ Family Features In addition to program memory with the General Segment of the PIC24F ‘J’ device family, the following new features are available to improve flexibility. None. PROGRAM MEMORY WITH BOOT SEGMENT Consider the following when migrating from the PIC24F ‘J’ to the PIC24F ‘K’ family: The Boot Segment option, along with the CodeGuard security feature, are available in the PIC24F ‘K’ device family. The size and security level of the Boot Segment are determined by Configuration bits, BSS<2:0>, of the FBS Configuration Word. When the Boot Segment is configured, it starts from the 0x0200 location and the size is defined by the bits, BSS<2:0>. The General Segment follows the Boot Segment. The Boot Segment is equipped with enhanced securities. The code or data in the Boot Segment cannot be accessed from outside of the Boot Segment. The basic restricted operation includes: • Read, write and erase operations on the Boot Segment space from outside the Boot Segment are not allowed when standard or high security is enabled. • Program flow change into the Boot Segment from outside the Boot Segment is not allowed when high security is enabled. • While executing in the Boot Segment, a special code sequence is required to handle the interrupts and traps. DATA EEPROM MEMORY Migration Considerations • The PIC24F ‘K’ device family has 4 Kbytes to 32 Kbytes of program memory. Therefore, the applications that require more than 32 Kbytes of memory cannot be migrated to PIC24F ‘K’ devices at this time. • In PIC24F ‘J’ devices, the erase size is 512 instructions and the write size is 64 instructions. While in PIC24F ‘K’ devices, the erase size is configurable for 32, 64 or 128 instructions and the write size is 32 instructions. • By default, the program memory of the PIC24F ‘K’ device family is configured as a single General Segment. Therefore, migrating an application from the PIC24F ‘J’ family does not require any changes. • If the application uses an emulated data EEPROM to save data, the dedicated data EEPROM available on PIC24F ‘K’ devices can be used. • If the device Configuration bits are defined in the source file, then the Configuration register names need to be changed to match the registers of the PIC24F ‘K’ device family. Refer to the respective data sheet for the device Configuration register details. In addition to the program memory and volatile data RAM, the PIC24F ‘K’ device family also includes nonvolatile, on-chip data EEPROM. This memory segment allows users to store application information, such as identification, calibration constants, etc. 2011 Microchip Technology Inc. Preliminary DS39990A-page 5 PIC24FXXKAXXX POWER-MANAGED MODES/ OSCILLATOR CONFIGURATIONS In addition to the PIC24F ‘J’ oscillator features, the PIC24F ‘K’ devices support an on-chip, 500 kHz LPRC oscillator. TABLE 3: COMPARISON OF PIC24F ‘J’ AND PIC24F ‘K’ OSCILLATOR Feature Description PIC24F ‘J’ PIC24F ‘K’ Primary Oscillator with PLL Off (HS, XT, EC) Yes Yes Primary Oscillator with PLL On (HSPLL, XTPLL, ECPLL) Yes Yes Secondary Oscillator Yes Yes 8 MHz FRC Yes Yes 8 MHz FRC with Postscaler Yes Yes 8 MHz FRC with Postscaler and PLL Yes Yes 500 kHz LPFRC with Postscaler No Yes 31 kHz LPRC Yes Yes FIGURE 1: PIC24F ‘K’ OSCILLATOR BLOCK DIAGRAM Primary Oscillator REFOCON<15:8> XT, HS, EC OSCO OSCI 4 x PLL 8 MHz 4 MHz Postscaler 8 MHz FRC Oscillator Reference Clock Generator XTPLL, HSPLL, ECPLL,FRCPLL REFO FRCDIV Peripherals 500 kHz LPFRC Oscillator CLKDIV<10:8> FRC CLKO LPRC Postscaler LPRC Oscillator 31 kHz (nominal) Secondary Oscillator CPU SOSC SOSCO SOSCI CLKDIV<14:12> SOSCEN Enable Oscillator Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT, DSWDT Clock Source Option for Other Modules DS39990A-page 6 Preliminary 2011 Microchip Technology Inc. PIC24FXXKAXXX New PIC24F ‘K’ Family Features New PIC24F ‘K’ Family Features In addition to the 8 MHz FRC and 31 kHz LPRC internal RC oscillators, a 500 kHz LPFRC oscillator is added to the PIC24F ‘K’ device family. This oscillator shares the postscaler of 8 MHz FRC. Therefore, the operating frequency can be reduced to 1.95 kHz. The BOR can be enabled or disabled, regardless of using or not using an on-chip regulator. The BOR trip point is programmable and one of the four trip points can be selected. Unsupported PIC24F ‘J’ Family Features Unsupported PIC24F ‘J’ Family Features None. None. Migration Considerations Migration Considerations To migrate the 2V BOR feature to the PIC24F ‘K’ family, select the appropriate BOR trip point using the BOR<1:0> bits from the FPOR register. None. PROGRAMMABLE BROWN-OUT RESET (BOR) The PIC24F ‘J’ device family has a fixed-point BOR circuitry, while the PIC24F ‘K’ device family has a BOR circuitry with four programmable trip points. REGISTER 1: FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 R/P-1 R/P-1 MCLRE BORV1(1) BORV0(1) I2C1SEL PWRTEN — BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit bit 6-5 BORV<1:0>: Brown-out Reset Enable bits(1) 11 = Brown-out Reset is set to the first trip voltage 10 = Brown-out Reset is set to the second trip voltage 01 = Brown-out Reset is set to the third trip voltage 00 = Low-power Brown-out Reset re-arms the POR circuit bit 4 I2C1SEL: Alternate I2C1 Pin Mapping bit bit 3 PWRTEN: Power-up Timer Enable bit bit 2 Unimplemented: Read as ‘0’ bit 1-0 BOREN<1:0>: Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled 10 = Brown-out Reset is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled 01 = Brown-out Reset is controlled with the SBOREN bit setting 00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled Note 1: Refer to the electrical specifications in the specific device data sheet for BOR voltages. Note that the BOR voltages differ by device. 2011 Microchip Technology Inc. Preliminary DS39990A-page 7 PIC24FXXKAXXX SUMMARY REFERENCES The preceding sections represent the most important considerations in migrating a PIC24F ‘J’ application to a PIC24F ‘K’ device. Although it is impractical to list every possible code to hardware implementation, this document should be considered as a check list of the most important differences and similarities. For more specific information on the device families referenced in this document, refer to the following data sheets and PIC24F reference manual: Additional features, such as data EEPROM, provide new applications for the PIC24F ‘K’ family that were not possible with PIC24F ‘J’ device families. It is important to review an application, before migration, to decide how the code and hardware design must be changed to work on the PIC24F ‘K’ device family. • “PIC24F16KA102 Family Data Sheet” (DS39927) • “PIC24F04KA201 Family Data Sheet” (DS39937) • “PIC24FJ64GA004 Family Data Sheet” (DS39881) • “PIC24FJ64GA104 Family Data Sheet” (DS39951) • “PIC24F Family Reference Manual”, Section 2. CPU (DS39703) • “PIC24F Family Reference Manual”, Section 5. Data EEPROM (DS39720) • “PIC24F Family Reference Manual”, Section 6. Oscillator (DS39700) • “PIC24F Family Reference Manual”, Section 7. Reset (DS39712) • “PIC24F Family Reference Manual”, Section 38. Oscillator with 500 kHz Low-Power FRC (DS39726) • “PIC24F Family Reference Manual”, Section 40. Reset with Programmable Brown-out Reset (DS39728) There are other Microchip data sheets and reference materials available for PIC24F devices that may be helpful in planning the migration of an application. For a complete list of available materials, visit the Microchip corporate web site at: www.microchip.com DS39990A-page 8 Preliminary 2011 Microchip Technology Inc. PIC24FXXKAXXX DOCUMENT REVISION HISTORY Revision A Document (2/2011) This is the initial release of this document. This revision includes introduction to the PIC24F ‘K’ device family, the differences from the PIC24F ‘J’ device family and the migration considerations. 2011 Microchip Technology Inc. Preliminary DS39990A-page 9 PIC24FXXKAXXX NOTES: DS39990A-page 10 Preliminary 2011 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-890-0 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2011 Microchip Technology Inc. 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