Key Sheet AD7790 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Highlights of the AD7790—Low Power, 16-Bit, Buffered Sigma-Delta ADC GND VDD REFIN VDD INTERNAL CLOCK GND 16-BIT ADC DIGITAL PGA SERIAL INTERFACE 11264-001 BUF AIN AD7790 Figure 1. Functional Block Diagram GENERAL DESCRIPTION FEATURES AND BENEFITS This key sheet provides users with an overview of the AD7790. Key attributes of the part include the following: The AD7790 offers the following features and benefits: 1 • • • • • • 1 Designed for the measurement of wide dynamic range, low frequency signals, such as those in pressure transducers, weigh scales, and temperature measurement applications. Low power, flexible, high performance, low noise, 16-bit sigma-delta (Σ-Δ) ADC suitable for converting low input bandwidth analog signals with a fully flexible output data rate (ODR) between 9.5 SPS and 120 SPS. Single fully differential analog channel with ultralow power consumption. With an ODR of 9.5 SPS, the AD7790 boasts an rms noise of 1.1 µV. User friendly, with the part being fully configurable over a 4-wire serial interface. Available in a 10-lead MSOP package, allowing a reduced board size. • • • • • • • Simultaneous 50 Hz and 60 Hz rejection at 16.6 SPS ODR Optional internal rail-to-rail input buffer Three MCLK divide options, allowing further reduction in power dissipation Ultralow noise performance across the ODR range Fully compatible with SPI, QSPI™, MICROWIRE®, and DSP SPI configuration control 3-wire serial digital interface (Schmitt trigger on SCLK) This document provides users with an overview of the AD7790; it is not a notice of performance or intent. Refer to the AD7790 data sheet for performance and more specific information about this product. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved. AD7790 Key Sheet KEY CHARACTERISTICS FUNDAMENTAL SPECIFICATIONS Table 1. Parameter ADC Type Number of Input Channels Resolution Output Data Rate (ODR) Differential Input Voltage Range Power Supply Voltage VDD with Respect to GND Power Supply Current With VDD = 3.6 V, Buffer Off With VDD = 5.25 V, Buffer On Offset Error Offset Error Drift vs. Temperature Full-Scale Error Gain Drift vs. Temperature Integral Nonlinearity (INL) Power Supply Rejection Operating Temperature Range Min Typ 16 9.5 −REFIN/gain Max Σ- Δ ADC One fully differential input channel 16 120 +REFIN/gain 2.5 65 145 ±3 ±10 ±10 ±0.5 ±3.5 −15 90 −40 Unit Bits SPS V 5.25 V 75 160 µA µA µV nV/°C µV ppm/°C ppm of FSR dB °C +15 +105 NOISE Table 2. Output Data Rates and RMS Noise Output Data Rate (SPS) 120 100 33.3 20 16.6 16.7 13.3 9.5 1 f3dB (Hz) 28 24 8 4.7 4 4 3.2 2.3 RMS Noise (µV) 40 25 3.36 1.6 1.5 1.5 1.2 1.1 Rejection 25 dB @ 60 Hz 25 dB @ 50 Hz 80 dB @ 60 Hz 65 dB @ 50 Hz and 60 Hz (default setting) 1 80 dB @ 50 Hz 62 dB @ 50 Hz and 60 Hz Simultaneous 50 Hz and 60 Hz rejection is optimized when the ODR equals 16.6 SPS because notches are placed at both 50 Hz and 60 Hz with this update rate. Rev. 0 | Page 2 of 6 Key Sheet AD7790 OPERATING THE AD7790 DATA INTERFACE The data interface for the AD7790 is • • • • Performed using a 4- or 3-wire SPI Compatible with SPI, QSPI, MICROWIRE, and DSP Allows a user to both write to and read from the AD7790 on the same data bus Indicates when transferred data is available by bringing the DOUT/RDY signal and the RDY bit in the status register low the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The user can read this register additional times, if required. CS DIN DATA REQUEST DATA REQUEST DATA DOUT/RDY DATA 11264-003 AD7790 (SLAVE) SCLK CS1 Figure 3. Continuous Conversion Mode SCLK Continuous Read Mode DSP/FPGA/ MICROCONTROLLER Rather than write to the communications register each time a conversion is complete to access the data, the AD7790 can be configured so that the conversions are automatically placed on the DOUT/RDY line. By writing 001111XX (where XX represent don’t cares) to the communications register, the user need only apply the appropriate number of SCLK cycles to the ADC, and the conversion word is automatically placed on the DOUT/RDY line when a conversion is complete. 1CS IS PERMANENTLY TIED LOW IN THE 3-WIRE INTERFACE. (IF CS IS REQUIRED AS A DECODING SIGNAL, IT CAN BE GENERATED FROM A PORT PIN.) 11264-002 DIN Figure 2. AD7790 Data Interface, 4-Wire SPI Table 3. 4-Wire Serial Interface Pin Functions Pin CS1 SCLK DOUT/RDY DIN Function Selects the ADC (also applicable in systems with multiple devices on the serial bus). Provides a frame synchronization signal.2 Determines when data transfers (either on DIN or DOUT/RDY) occur. Accesses data from the on-chip registers. Indicates when the transferred data is available. Transfers data into the on-chip registers. CS is permanently tied low in the 3-wire interface. (If CS is required as a decoding signal, it can be generated from a port pin.) 2 Useful for DSP interfaces. The first bit (MSB) is effectively clocked out by CS because CS typically occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed. CS DIN DOUT/RDY There are three data modes available: continuous conversion mode, continuous read mode, and single conversion mode. Continuous Conversion Mode (Default) Continuous conversion is the default power-up mode. In this mode, the AD7790 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of DATA SCLK DATA Figure 4. Continuous Read Mode 1 DATA MODES DATA 11264-006 DOUT/RDY In continuous read mode, the serial interface is dedicated to reads of the data register. If any other register needs to be accessed, continuous read mode must be disabled. In addition, every time a conversion is available, the serial interface is reset in this mode. Therefore, it is essential that the conversion be read before the next conversion is available. While in the continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset occurs if 32 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. Rev. 0 | Page 3 of 6 AD7790 Key Sheet Single Conversion Mode CS In single conversion mode, the AD7790 performs a single conversion and is placed in standby mode after the conversion is complete. DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY goes high. The data register can be read several times, if required, even when DOUT/RDY has gone high. DATA REQUEST DIN DATA 11264-004 DOUT/RDY SCLK Figure 5. Single Conversion Mode TYPICAL APPLICATION DIAGRAM POWER SUPPLY 0.1µF 10µF VDD REFIN(+) IN+ AD7790 OUT+ CS AIN(+) DOUT/RDY IN– AIN(–) MICROCONTROLLER SCLK REFIN(–) GND Figure 6. Typical Application Diagram Rev. 0 | Page 4 of 6 11264-005 OUT– Key Sheet AD7790 FREQUENTLY ASKED QUESTIONS What is the optional internal rail-to-rail buffer? The AD7790 has one differential analog input channel that is • • Connected to the on-chip buffer amplifier when the device is operated in buffered mode Connected directly to the modulator when the device is operated in unbuffered mode In buffered mode, the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors, such as strain gauges or resistance temperature detectors (RTDs). What is 50 Hz and 60 Hz rejection? The mains power supply generates interference at 50 Hz or 60 Hz, with the frequency varying from one country to another. The AD7790 has the ability to simultaneously reject 50 Hz and 60 Hz signals at an ODR of 16.6 SPS. What MCLK divide options are available? The AD7790 has a current consumption of 160 µA maximum when operated with the buffer enabled and with a 5 V power supply. The power can be reduced further by setting the CDIV1 and CDIV0 bits in the filter register appropriately. By setting these bits, the internal clock is divided by 2, 4, or 8 before being applied to the modulator and filter, resulting in a reduction of the output data rate and a reduction in the digital current. How do I interface with the part? The part can be configured by using a 4-wire SPI interface; this interface is also used as the data interface. The SPI interface allows the user to read the status of the part and to change the setup. Are there any ESD protection schemes that should be considered for the AD7790? This converter is manufactured on a standard CMOS process; therefore, all standard practices and protection schemes that apply to other CMOS devices also apply to this device. There are ESD protection diodes on all the inputs that protect the device from possible ESD damage due to handling and production. To determine the appropriate ESD precautions, refer to the AD7790 data sheet for information about the absolute maximum ratings. Is an antialiasing filter required? The analog input is sampled at 64 kHz. The digital filter does not provide any rejection at this frequency or at frequencies that are multiples of 64 kHz; an external antialiasing filter is required to provide rejection at these frequencies, with a simple RC filter being sufficient. Typical values for the filter are • • • 1 kΩ resistor in series with each analog input 0.1 µF capacitor between the analog input pins 0.01 µF capacitor from each input pin to ground These typical values can be used only when the buffer is enabled. When the buffer is disabled, smaller RC values are required because larger values can cause gain errors. Can filtering be added to the reference pins? The reference input to the AD7790 is not buffered. Therefore, the filtering must be limited on the reference pins because large RC values can cause gain errors. Suitable capacitor values are • • 2200 pF capacitor between the reference pins 220 pF capacitor from each pin to ground With these capacitor values, there can be some resistance in parallel with the reference pins. However, it must be limited to less than 100 Ω. Rev. 0 | Page 5 of 6 AD7790 Key Sheet LEARN MORE AND START DESIGNING To learn more about the AD7790 and compatible products or to sample and buy the AD7790 device, click on the links provided or contact an Analog Devices, Inc., sales representative. COMPATIBLE DEVICES Table 4. Recommended Compatible Devices 1 Linear Regulators ADP3303 family ADP3330 family 1 Precision References ADR380 family ADR361 family ADC Driver Amplifiers N/A (the AD7790 includes an on-board internal buffer) Circuits from the Lab™ CN-0271, K-Type Thermocouple Measurement System with Integrated Cold Junction Compensation Information about additional companion products are provided on the AD7790 product page. PACKAGE DIAGRAM 3.10 3.00 2.90 10 3.10 3.00 2.90 5.15 4.90 4.65 6 1 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 6° 0° 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 7. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters GETTING STARTED AD7790 DATA SHEET SAMPLE AND BUY THE AD7790 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11264-0-1/13(0) Rev. 0 | Page 6 of 6 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 Evaluation Board AD7791 evaluation board is recommended for AD7790 evaluation