APPLICATION NOTE AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I Atmel AVR XMEGA Introduction This application note lists out the differences and changes between Revision E and Revision I of ATxmega64D3/128D3/192D3/256D3 devices. For complete device details, always refer to the most recent version of the ® ATxmega64D3/128D3/192D3/256D3 datasheet and the Atmel XMEGA D manual. Errata differences are not listed in this document, only in the device datasheet. In addition to the differences described in this document, other typical characteristics could be different. Check the latest datasheets for details. The new configuration options and functions available in Revision I of ATxmega64D3/128D3/192D3/256D3 are a superset of existing functions, and this means that existing code for these revisions will work on the new revision without changing existing configurations or enabling new functions. The new options and functions are still listed in this application note for customers, who wish to consider using new functions, in addition to the migration process. Features • Enhancements and added functions • Memories • System clock and clock options • Reset system • I/O ports • Registers • Changes in electrical characteristics Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 1 Enhancements and Added Functions In this chapter, we summarize the list of enhancements or added features available in Revision I. 1.1 Clock System • • • • • • Alternate pin location for TOSC1 and TOSC2 pins for 32.768kHz crystal connection on devices with shared TOSC and XTAL location A divide-by-two option for the PLL output that enables output frequency down to 10MHz PLL lock failure detection with optionally Non-Maskable Interrupt (NMI), for improved safety and robustness Non-prescaled Real Time Counter clock source options: External clock from TOSC1, 32.768kHz from TOSC, and the 32.768kHz from the 32.768kHz Internal Oscillator Higher drive option for external crystal oscillator to support crystals with higher load The 32MHz Internal Oscillator can be tuned to run at any frequency between 30MHz and 55MHz 1.2 I/O Ports 1.3 Two-wire Interface 1.4 Analog to Digital Converter 1.5 Analog Comparator 1.6 CRC16/CRC32 Generator 1.7 16-bit Timer/Counter 0 1.8 High Resolution Extension • • • • • • • • • • • • • • Alternate pin locations for Timer/Counter 0 Compare Channels, USART0, and SPI Alternate pin locations for the Peripheral Clock and Event output functions The Real Time Counter clock can be output to a port pin Any Event Channel can be output to a port pin The SDA Hold time can be increased and configured in order to be SMBUS compliant Automatic input channel scan VCC/2 voltage reference option 1/2x (divide-by-two) gain stage setting Internal Ground can be used as negative input in differential mode with and without gain Sample time is configurable Analog Comparator 1 can be output on a port pin A constant current source ® A CRC16/CRC32 Generator Module that supports CRC16 (RC-CCITT) and CRC-32 (IEEE 802.3) Split mode that enables two 8-bit Timer/Counters with four PWM channels each Hi-Res+ option to allow PWM resolution to be increased with 8x (3-bit). 1.9 Power Management Possibility to enable sequential start of the components used for analog modules ADC and Analog Comparator in order to reduce start-up current. 2 AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 2 Memories 2.1 NVM Controller For Atmel ATxmega64D3/128D3/192D3/256D3 Revision E devices, the chip erase time is about 40ms. The chip erase time of ATxmega64D3/128D3/192D3/256D3 Revision I is longer. The typical chip erase time of ATxmega64D3/128D3/192D3/256D3 Revision I devices are in Table 2-1. Table 2-1. ATxmega64D3/128D3/192D3/256D3 Revision I Chip Erase Time Product Flash and Boot Code Size Chip Erase Time ATxmega64D3 64KB + 4KB 55ms ATxmega128D3 128KB + 8KB 75ms ATxmega192D3 192KB + 8KB 90ms ATxmega256D3 256KB + 8KB 105ms To ensure that the flash chip erase is finished correctly, no flash access should be done during the chip erase time. In the user code, it is always needed to check the FBUSY bit in the Non-Volatile Memory Status Register to see when the chip erase is finished. CRC32 is automatically used instead of existing CRC module if the new CRC16/CRC32 module is enabled. There are no changes in the commands. 2.2 Fuses and Lock Bits BOD levels are different in ATxmega64D3/128D3/192D3/256D3 Revision I. Refer Section 4.1 Brown-out Detection for detailed information. 3 System Clock and Clock Options 3.1 Clock Failure The PLLDFIF flag, indicating if the PLL looses lock, is no longer automatically cleared, but must be done from software. AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I [APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 3 4 Reset System 4.1 Brown-out Detection The programmable BODLEVEL settings are different in ATxmega64D3/128D3/192D3/256D3 Revision I. See Table 4-1 for details. Refer to the device datasheet regarding tolerance for the brown-out levels. Table 4-1. Brown-out Levels VBOT – Revision E VBOT – Revision I BOD LEVEL Minimum Typical Maximum Minimum Typical Maximum 111 1.62 1.63V 1.7 1.4 1.6V 1.7 110 1.9V 1.8V 101 2.17V 2.0V 100 2.43V 2.2V 011 2.68V 2.4V 010 2.96V 2.6V 001 3.22V 2.8V 000 3.49V 3.0V Until Revision E, the BOD is forced on for all Non-Volatile Memory (NVM) programming. In the new Revision I, the BOD is forced on only during chip erase and when the PDI is enabled. For other NVM programming operations, the POR threshold voltage (VPOT+) is the limit for aborting. 5 I/O Ports The I/O port pins are LV-TTL and LVCOMS compatible for ATxmega64D3/128D3/192D3/256D3 Revision I. The minimum “Input High Voltage” is never higher than 2.0V for VCC > 2.7V. In the Atmel ATxmega64D3/128D3/192D3/256D3 revision E, the minimum “Input High Voltage” is 0.7 VCC, and could be higher than 2.0V for VCC > 2.86V. 5.1 I/O Pin Behavior when Disabling TX in USART When the transmitter is disabled in USART peripheral, it will no longer override the TxDn pin, and the pin direction is set as input automatically by hardware, even if it was configured as output by the user. This behavior as mentioned in the XMEGA D Manual is valid after Revision E. In the older revision the pin direction does not get changed to input automatically. 4 AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 6 Registers 6.1 Added Registers and Bits Table 6-1 lists the registers and bits, which are added in ATxmega64D3/128D3/192D3/256D3 Revision I. Table 6-1. Register Bits and Functionality added in the ATxmega64D3/128D3/192D3/256D3 Revision I Register Name Bit Function SAMPCTRL Bit[5:0] - SAMPVAL[5:0] Sampling time control register The SAMPVAL bits control the ADC sampling time in number of half ADC prescaled clock cycles (depends on ADC_PRESCALER value), thus controlling the ADC input impedance. Sampling time is set according to the formula: Sampling time = (SAMPVAL+1)*(ClkADC/2) 6.2 Removed Registers and Bits Table 6-2 lists the registers and bits, which exist in Atmel ATxmega64D3/128D3/192D3/256D3 Revision E but not in ATxmega64D3/128D3/192D3/256D3 Revision I. Table 6-2. 6.3 Register Bits and Functionality that does not exist in ATxmega64D3/128D3/192D3/256D3 Revision I Register Name Bit Function COMP0 COMP[7:0] Oscillator Compare Register 0 CALH Register not Applicable For the ATxmega64D3/128D3/192D3/256D3 Revision I, CALH is not applicable hence it cannot be written. When read, the CALH register will return zero. This new design ATxmega64D3/128D3/192D3/256D3 ADC requires only one calibration byte (only 8 bit value, not 12 bit value). For coding compatibility, dependent registers like CALH, CALL, ADC CAL0, and ADC CAL1 has been kept same as the older design. AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I [APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 5 6.4 MUXNEG Configuration in ADC Channel MUX Control Register In Revision E of ATxmega64D3/128D3/192D3/256D3 devices, Bit 2 of the MUXNEG configuration in ADC Channel MUX Control registers is reserved. This bit is now available for configuration in Revision I. Below is the configuration available in the older and later revisions: Revision E: Bit 7 +0x01 - Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 6-3. Table 6-4. 6 6 5 4 3 MUXPOS[3:0] 2 1 - 0 MUXNEG[1:0] MUXCTRL ADC MUXNEG Configuration, INPUTMODE[1:0] = 10, Differential without Gain MUXNEG[1:0] Group Configuration Analog Input 00 PIN0 ADC0 pin 01 PIN1 ADC1 pin 10 PIN2 ADC2 pin 11 PIN3 ADC3 pin ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, Differential with Gain MUXNEG[1:0] Group Configuration Analog Input 00 PIN4 ADC4 pin 01 PIN5 ADC5 pin 10 PIN6 ADC6 pin 11 PIN7 ADC7 pin AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 Revision I: Bit 7 +0x01 - Read/Write R R/W R/W R/W R/W R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 6-5. Table 6-6. 6 5 4 3 2 MUXPOS[3:0] 1 0 MUXNEG[2:0] ADC MUXNEG Configuration, INPUTMODE[1:0] = 10, Differential without Gain MUXNEG[2:0] Group Configuration Analog Input 000 PIN0 ADC0 pin 001 PIN1 ADC1 pin 010 PIN2 ADC2 pin 011 PIN3 ADC3 pin 100 - Reserved 101 GND PAD ground 110 - Reserved 111 INTGND Internal ground ADC MUXNEG Configuration, INPUTMODE[1:0] = 11, Differential with Gain MUXNEG[2:0] Group Configuration Analog Input 000 PIN4 ADC4 pin 001 PIN5 ADC5 pin 010 PIN6 ADC6 pin 011 PIN7 ADC7 pin 100 INTGND Initial ground 101 - Reserved 110 - Reserved 111 GND PAD ground AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I [APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 7 7 Changes in Electrical Characteristics 7.1 Reduced Current Consumption in Active and Idle Mode Table 7-1 trough Table 7-4 list the typical and maximum current consumption details in Revision E and Revision I devices. Table 7-1. Current Consumption Details of ATxmega64D3 Revision E Parameter Condition 32kHz, ext. clk. Active power consumption 1MHz, ext. clk. 2MHz, ext. clk. Min. Reset power consumption 8 Typ. Max. 25 50 VCC = 3.0V 71 130 VCC = 1.8V 317 215 VCC = 3.0V 697 475 VCC = 1.8V 613 800 445 600 VCC = 3.0V 1.3 1.8 0.95 1.5 15.7 18 7.8 12 2.8 VCC = 3.0V 6.9 3 VCC = 1.8V 112 46 VCC = 3.0V 215 92 VCC = 1.8V 224 350 93 225 430 650 184 350 32MHz, ext. clk. 6.9 8 2.9 5 T = 25°C 0.1 3 0.07 1 1.75 5 1.3 5 WDT and sampled BOD enabled, T = 25°C 1 6 1.4 2 WDT and sampled BOD enabled, T = 85°C 2.7 10 2.6 6 1MHz, ext. clk. T = 85°C VCC = 3.0V VCC = 1.8V 0.5 1.7 VCC = 3.0V 0.7 1.8 RTC from 1.024kHz low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.5 4 0.5 2 VCC = 3.0V 0.7 4 0.7 2 RTC from low power 32.768kHz TOSC, T = 25°C VCC = 1.8V na na 0.9 3 VCC = 3.0V 1.16 na 1.2 3 VCC = 3.0V 1300 AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 120 mA µA RTC from ULP clock, WDT and sampled BOD enabled, T = 25°C Current through RESET pin subtracted Units µA 3.6 2MHz, ext. clk. Power-save power consumption Min. VCC = 1.8V 32kHz, ext. clk. Power-down power consumption Max. VCC = 1.8V 32MHz, ext. clk. Idle power consumption Typ. Revision I mA µA Table 7-2. Current Consumption Details of ATxmega128D3 Revision E Parameter Condition 32kHz, ext. clk. 1MHz, ext. clk. Active power consumption 2MHz, ext. clk. Min. Max. 25 55 VCC = 3.0V 71 135 VCC = 1.8V 317 237 VCC = 3.0V 697 515 VCC = 1.8V 613 800 425 700 VCC = 3.0V 1.3 1.8 0.9 1.5 15.7 18 8.3 12 VCC = 3.0V 6.9 3.1 VCC = 1.8V 112 47 VCC = 3.0V 215 95 VCC = 1.8V 224 350 94 200 430 650 190 400 32MHz, ext. clk. 6.9 8 3 7 T = 25°C 0.1 3 0.1 1 1.75 5 1.9 4 WDT and sampled BOD enabled, T = 25°C 1 6 1.5 2 WDT and sampled BOD enabled, T = 85°C 2.7 10 3 8 T = 85°C VCC = 3.0V mA µA RTC from ULP clock, WDT and sampled BOD enabled, T = 25°C VCC = 1.8V 0.5 1.3 VCC = 3.0V 0.7 1.4 RTC from 1.024kHz low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.5 4 0.7 2 VCC = 3.0V 0.7 4 0.8 2 RTC from low power 32.768kHz TOSC, T = 25°C VCC = 1.8V na na 0.9 3 VCC = 3.0V 1.16 na 1.1 3 VCC = 3.0V 1300 Current through RESET pin subtracted Units µA 2.8 2MHz, ext. clk. Reset power consumption Typ. 3.6 1MHz, ext. clk. Power-save power consumption Min. VCC = 1.8V 32kHz, ext. clk. Power-down power consumption Max. VCC = 1.8V 32MHz, ext. clk. Idle power consumption Typ. Revision I mA µA 145 AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I [APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 9 Table 7-3. Current Consumption Details of ATxmega192D3 Revision E Parameter Condition 32kHz, ext. clk. Active power consumption 1MHz, ext. clk. 2MHz, ext. clk. Min. Reset power consumption 10 Typ. Max. 25 60 VCC = 3.0V 71 140 VCC = 1.8V 317 245 VCC = 3.0V 697 550 VCC = 1.8V 613 800 440 700 VCC = 3.0V 1.3 1.8 0.9 1.5 15.7 18 9 15 3 VCC = 3.0V 6.9 3.5 VCC = 1.8V 112 55 VCC = 3.0V 215 110 VCC = 1.8V 224 350 105 350 430 650 215 650 32MHz, ext. clk. 6.9 8 3.4 8 T = 25°C 0.1 3 0.1 1 1.75 5 3.5 6 WDT and sampled BOD enabled, T = 25°C 1 6 1.5 2 WDT and sampled BOD enabled, T = 85°C 2.7 10 5.8 10 1MHz, ext. clk. T = 85°C VCC = 3.0V VCC = 1.8V 0.5 1.3 VCC = 3.0V 0.7 1.4 RTC from 1.024kHz low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.5 4 0.7 2 VCC = 3.0V 0.7 4 0.8 2 RTC from low power 32.768kHz TOSC, T = 25°C VCC = 1.8V na na 0.9 3 VCC = 3.0V 1.16 na 1.1 3 VCC = 3.0V 1300 AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 170 mA µA RTC from ULP clock, WDT and sampled BOD enabled, T = 25°C Current through RESET pin subtracted Units µA 3.6 2MHz, ext. clk. Power-save power consumption Min. VCC = 1.8V 32kHz, ext. clk. Power-down power consumption Max. VCC = 1.8V 32MHz, ext. clk. Idle power consumption Typ. Revision I mA µA Table 7-4. Current Consumption Details of ATxmega256D3 Revision E Parameter Condition 32kHz, ext. clk. 1MHz, ext. clk. Active power consumption 2MHz, ext. clk. Min. Max. 25 60 VCC = 3.0V 71 140 VCC = 1.8V 317 245 VCC = 3.0V 697 550 VCC = 1.8V 613 800 440 700 VCC = 3.0V 1.34 1.8 0.9 1.5 15.7 18 9 15 VCC = 3.0V 6.9 3.5 VCC = 1.8V 112 55 VCC = 3.0V 215 110 VCC = 1.8V 224 350 105 350 430 650 215 650 32MHz, ext. clk. 6.9 8 3.4 8 T = 25°C 0.1 3 0.1 1 1.75 5 3.5 6 WDT and sampled BOD enabled, T = 25°C 1 6 1.5 2 WDT and sampled BOD enabled, T = 85°C 2.7 10 5.8 10 T = 85°C VCC = 3.0V mA µA RTC from ULP clock, WDT and sampled BOD enabled, T = 25°C VCC = 1.8V 0.5 1.3 VCC = 3.0V 0.7 1.4 RTC from 1.024kHz low power 32.768kHz TOSC, T = 25°C VCC = 1.8V 0.5 4 0.7 2 VCC = 3.0V 0.7 4 0.8 2 RTC from low power 32.768kHz TOSC, T = 25°C VCC = 1.8V na na 0.9 3 VCC = 3.0V 1.16 na 1.1 3 VCC = 3.0V 1300 Current through RESET pin subtracted Units µA 3 2MHz, ext. clk. Reset power consumption Typ. 3.6 1MHz, ext. clk. Power-save power consumption Min. VCC = 1.8V 32kHz, ext. clk. Power-down power consumption Max. VCC = 1.8V 32MHz, ext. clk. Idle power consumption Typ. Revision I mA µA 170 AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I [APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 11 7.2 Increased ADC Maximum Samples Rate The maximum ADC clock frequency and sample rate is increased, as shown in Table 7-5. Table 7-5. Changes in ADC Parameters of ATxmega64D3/128D3/192D3/256D3 Devices Revision E 7.3 Parameter Min. ADC clock frequency ADC sample rates Typ. Revision I Max. Min. na 1400 na 200 Typ. Max. Units 100 1800 kHz 16 300 kSPS Typ. Max. Units na Reduced Analog Comparator Propagation Delay The Analog Comparator propagation delay is reduced, as shown in Table 7-6 and Table 7-7. Table 7-6. Propagation Delay of Analog Comparator in ATxmega64D3/128D3/192D3/256D3 Revision E Devices Revision E Table 7-7. Parameter Condition Min. Propagation delay VCC = 3.0V, T = 85°C na Propagation delay VCC = 1.6 – 3.6V, T = 25°C 175 ns Propagation Delay of Analog Comparator in ATxmega64D3/128D3/192D3/256D3 Revision I Devices Revision I Note: 7.4 1. Parameter Condition Min. Typ. Propagation delay VCC = 3.0V, T = 85°C 20 Propagation delay VCC = 3.0V, T = 25°C 17 Max. 40 Units (1) ns For ATxmega128D3, the value is 90ns. 32kHz Internal ULP Oscillator Frequency The frequency of the 32kHz internal ULP oscillator is increased to match its nominal frequency with guaranteed accuracy. Refer Table 7-8. Table 7-8. Changes in 32kHz Internal ULP Oscillator Frequency of ATxmega64D3/128D3/192D3/256D3 Devices Revision E Parameter Condition Min. Factory calibrated frequency Factory calibration accuracy Accuracy 12 Typ. Revision I Max. Min. 26 VCC = 3.0V, T = 85°C Typ. Max. 32 kHz na na -12 12 na na -30 30 AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 Units % 8 Revision History Doc Rev. Date 42403A 02/2015 Comments Initial document release. AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I [APPLICATION NOTE] Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 13 Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 │ www.atmel.com © 2015 Atmel Corporation. / Rev.:Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015. 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Atmel-42403A-Migration-from-ATxmega64D3-128D3-192D3-256D3-RevisionE-to-RevisionI-ApplicationNote_AT11009_022015 14 AT11009: Migration from ATxmega64D3/128D3/192D3/256D3 Revision E to Revision I APPLICATION NOTE]