Programming Specification for AT17N Series FPGA Configuration Memories The FPGA Configurator The FPGA Configurator is a serial EEPROM memory that can also be used to load programmable devices. This document describes the features needed to program the Configurator from within its programming mode (i.e., when SER_EN is driven Low). There are many ways to program an AT17N Series Configurator: • Using a third-party programmer • Using Atmel’s Configurator Programming Kit ATDH2200E • Using a custom programming solution For details of other programming options, please refer to the “Introducing Atmel Configurators” application note, available on the Atmel web site (www.atmel.com). AT17N Series FPGA Configuration Memory Application Note Serial Bus Overview The serial bus is a 2-wire bus. One wire (CLOCK) functions as a clock and is provided by the programmer, the second wire (DATA) is a bi-directional signal and is used to provide data and control information. Information is transmitted on the serial bus in messages. Each MESSAGE is preceded by a Start Condition and is ended with a Stop Condition. The message consists of an integer number of bytes, each byte consisting of 8 bits of data, followed by a 9th Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted byte. This is possible because devices may only drive the DATA line Low. The system must provide a small pull-up current for the DATA line. The MESSAGE FORMAT for read and write instructions consists of the bytes shown in “Bit Format” on page 2. While writing, the programmer is responsible for issuing the instruction and data. While reading, the programmer issues the instruction and acknowledges the data from the Configurator as necessary. Again, the Acknowledge Bit is asserted on the DATA line by the receiving device on a byte-by-byte basis. The factory blanks devices to all zeros before shipping. The array cannot otherwise be “initialized” except by explicitly writing a known value to each location using the serial protocol described herein. Rev. 3015A–CNFG–05/03 1 Bit Format Data on the DATA pin may change only during the CLOCK Low time; whereas Start and Stop Conditions are identified as transitions during the CLOCK High time. Write Instruction Message Format START CONDITION DEVICE ADDRESS MS EEPROM ADDRESS BYTE (512K, 4M) (NEXT) EEPROM ADDRESS BYTE LS EEPROM ADDRESS BYTE DATA BYTE 1 DATA BYTE n STOP CONDITION ACK BIT (CONFIGURATOR) Current Address Read (Extended to Sequential Read) Instruction Message Format START CONDITION DEVICE ADDRESS DATA BYTE 1 DATA BYTE n STOP CONDITION ACK BIT ACK BIT (CONFIGURATOR) (PROGRAMMER) Start and Stop Conditions The Start Condition is indicated by a high-to-low transition of the DATA line when the CLOCK line is High. Similarly, the Stop Condition is generated by a low-to-high transition of the DATA line when the CLOCK line is High, see Figure 1. The Start Condition will return the device to the state where it is waiting for a Device Address (its normal quiescent mode). The Stop Condition initiates an internally timed write signal whose maximum duration is tWR (refer to the AC Characteristics tables for actual value). During this time, the Configurator must remain in programming mode (i.e., SER_EN is driven Low). DATA and CLOCK lines are ignored until the cycle is completed. Since the write cycle typically completes in less than tWR seconds, we recommend the use of “polling” as described in page 8. Input levels to all other pins should be held constant until the write cycle has been completed. Acknowledge Bit The Acknowledge (ACK) Bit shown in Figure 1 is provided by the Configurator receiving the byte. The receiving Configurator can accept the byte by asserting a Low value on the DATA line, or it can refuse the byte by asserting (allowing the signal to be externally pulled up to) a High value on the DATA line. All bytes from accepted messages must be terminated by either an Acknowledge Bit or a Stop Condition. Following an ACK Bit, when the DATA line is released during an exchange of control between the Configurator and the Programmer, the DATA line may be pulled High temporarily as shown above due to the open-collector output nature of the line. Control of the line must resume before the next rising edge of the clock. Bit Ordering Protocol The most significant bit is the first bit of a byte transmitted on the DATA line for the Device Address Byte and the EEPROM Address Bytes. It is followed by the lesser significant bits until the eighth bit, the least significant bit, is transmitted. However, for Data Bytes (both writing and reading), the first bit transmitted is the least significant bit. This protocol is shown in "Device Address Byte" and "EEPROM Address". 2 AT17N Series Programming Specification 3015A–CNFG–05/03 AT17N Series Programming Specification Device Address Byte The contents of the Device Address Byte are shown below, along with the order in which the bits are clocked into the device. The CE pin cannot be used for device selection in programming mode (i.e., when SER_EN is drive Low). Figure 1. Start and Stop Conditions CLOCK DATA 8th BIT ACK BIT Byte n t WR START Condition STOP Condition Device Address Byte MSB LSB 1 0 1 0 0 1 1 R/W 1st 2nd 3rd 4th 5th 6th 7th 8th Where:R/W = 1 Read = 0 Write 3 3015A–CNFG–05/03 EEPROM Address The EEPROM Address consists of two bytes on the 256-Kbit parts, and three bytes on the 512-Kbit, 1- and 2- and 4-Mbit parts. Each Address Byte is followed by an Acknowledge Bit (provided by the Configurator). These bytes define the normal address space of the Configurator, as described below. The order in which each byte is clocked into the Configurator is also indicated. Unused bits in an Address Byte must be set to “0”. Exceptions to this are: • when setting the reset polarity; • when reading Device and Manufacturer Codes. 2- and 4-Mbit Page Length 512-Kbit and 1M-bit Page Length This byte is only used on the 512-Kbit, and the 1-, 2- and 4-Mbit parts 256-Kbit Page Length byte order MSB 0 1st LSB 0 0 0 2nd 3rd 4th 0 5th AE18 A E17 AE16 ACK 6th 7th 8th MSB LSB AE15 AE14 AE13 AE12 AE11 AE10 AE9 AE8 1st 2nd 3rd 4th 5th 6th 7th 8th LSB MSB ACK AE7 AE6 AE5 AE4 AE3 AE2 AE1 AE0 1st 2nd 3rd 4th 5th 6th 7th 8th ACK 256-Kbit Address Page 512-Kbit Address Page 1-Mbit Address Space 2-Mbit Address Space 4 -Mbit Address Space 4 AT17N Series Programming Specification 3015A–CNFG–05/03 AT17N Series Programming Specification Programming Summary: Write to Whole Device Notes: START 1 SER_EN ≤ Low CE ≤ Low 3 RESET/OE ≤ Low 3 PAGE_COUNT ≤ 0 1. Pull-up resistor required on DATA line 2. Data byte received/sent LSB to MSB 3. These signals have “don’t care” conditions for the AT17N512/010/002 and AT17N040. 4. The 512-Kbit, and 1-, 2- and 4-Mbit parts require three EEPROM address bytes; all three bytes must be individually ACK’d by the EEPROM. EEPROM Address is Defined as: 256 Send Start Condition BYTE_COUNT ≤ 0 Send Device Address (A6\h) ACK? No ACK? No 0x8x7x6 x5x4x3x2 x1x000 0000 512 0000 0000 x8x7x6x5 x4x3x2x1 x0000 0000 010 0000 000x9 x8x7x6x5 x4x3x2x1 x0000 0000 002 0000 00x9X8 x7x6x5x4 x3x2x1x0 0000 0000 040 000 0x10X9X8 x7x6x5x4 x3x2x1x0 0000 0000 Note: Yes Send MSB of EEPROM Address 4 Yes Send LSB of EEPROM Address 4 No Yes ACK? No Yes No 64 AT17N512/010 128 AT17N002 256 AT17N040 256 T_PAGE AT17N256 BYTE_COUNT = T_BYTE? Send Stop Condition PAGE_COUNT ≤ PAGE_COUNT+1 T_BYTE Per Page AT17N256 ACK? Send Data Byte2 BYTE_COUNT ≤ BYTE_COUNT+1 1. where Xn ... X0 is (PAGE_COUNT)\b where Xn ... X0 is (PAGE_COUNT)\b PAGE_COUNT = T_PAGE? 512 AT17N512 512 AT17N010 1024 AT17N002 1024 AT17N040 2048 No START CONDITION Yes CLK DATA Verify Final Write Cycle Completion Send Start Condition STOP CONDITION Send Device Address (A7\h) ACK? No DATA Yes SER_EN ≤ High CE ≤ High RESET/OE ≤ "X" Low-power (Standby) CLK 1st Data Byte Value Changed Due to Write? No DATA BIT CLK Yes DATA Power-Cycle EEPROM (Latches 1st Byte for FPGA Download Operations) ACK BIT CLK END DATA ACK 5 3015A–CNFG–05/03 Programming Summary: Read from Whole Device Notes: START 1 1. Pull-up resistor required on DATA line 2. Data byte received/sent LSB to MSB 3. These signals have “don’t care” conditions for the AT17N512/010/002 and AT17N040. 4. The 512-Kbit, and 1-, 2- and 4-Mbit parts require three EEPROM address bytes; all three bytes must be individually ACK’d by the EEPROM. EEPROM Address is Defined as: SER_EN ≤ Low CE ≤ Low 3 RESET/OE ≤ Low 3 256 00 00 \h 512/010/002/040 00 00 00 \h TT_BYTE Send Start Condition Random Access Setup AT17N256 Send Device Address (A6\h) ACK? No ACK? No 32768 \d AT17N512 65536 \d AT17N010 131072 \d AT17N002 262144 \d AT17N040 524288 \d Yes START CONDITION Send MSB of EEPROM Address 4 CLK Yes DATA Send LSB of EEPROM Address 4 ACK? No STOP CONDITION CLK Yes DATA Send Start condition BYTE_COUNT ≤ 0 SAMPLE DATA BIT CLK Send Device Address (A7\h) ACK? No DATA Sequential Read from Current Address Yes ACK BIT Read Data Byte 2 BYTE_COUNT ≤ BYTE_COUNT+1 CLK DATA No Send ACK ACK BYTE_COUNT= TT_BYTE? Yes Sent Stop Condition SER_EN ≤ High CE ≤ High RESET/OE ≤ "X" Low-power (Standby) END 6 AT17N Series Programming Specification 3015A–CNFG–05/03 AT17N Series Programming Specification Programming Summary: Write Reset Polarity Notes: START1 SER_EN ≤ Low CE ≤ High3 RESET/OE ≤ Low 3,6 Send Start Condition 1. Pull-up resistor required on DATA line 2. Data byte received/sent LSB to MSB 3. These signals have “don’t care” conditions for the AT17N512/010/002 and AT17N040. 4. The 512-Kbit, and 1-, 2- and 4-Mbit parts require three EEPROM address bytes; all three bytes must be individually ACK’d by the EEPROM. 5. Drive RESET/OE high for active low RESET, active high OE. Drive RESET/OE low for active high RESET, active low OE. 6. The 512-Kbit, and 1-, 2- and 4-Mbit parts require four data bytes of the same value to program the reset polarity; all four bytes must be individually ACK’d by the EEPROM. EEPROM Address is Defined as: AT17N256 Send Device Address 2 (A6\h) ACK? No Yes Send MSB of EEPROM Address 4 ACK? 3F FF \h AT17N512/010 02 00 00 \h AT17N002 400 000 \h AT17N040 400 000 \h No Data Byte is Defined as: Yes Send LSB of EEPROM Address 4 ACK? No 256 FF \h 512/010/002/040 (active low RESET) FF \h 512/010/002/040 (active high RESET) 00 \h Yes Send Data Byte 7 ACK? No START CONDITION CLK Yes DATA Send Stop Condition STOP CONDITION Wait 10 ms CLK DATA Verify Final Write Cycle Completion Send Start Condition DATA BIT Send Device Address (A7\h) ACK? No CLK DATA Yes SER_EN ≤ High CE ≤ high RESET/OE ≤ "X" Low-power (Standby) Is Reset Polarity a New Value? Yes Power Cycle EEPROM (Latches New Polarity for FPGA Download Operations) No ACK BIT CLK DATA ACK END 7 3015A–CNFG–05/03 Data Byte The organization of the Data Byte is shown below. Note that in this case, the Data Byte is clocked into the device LSB first and MSB last. Writing Writing to the normal address space takes place in pages. A page is 64 bytes long in 256-Kbit parts; 128 bytes long in 512-Kbit and 1-Mbit parts, and 256 bytes long in the 2and 4-Mbit parts. The page boundaries are, respectively, addresses where AE6 down to AEOS are all zero, and AE6 down to AE0 are all zero. Writing can start at any address within a page and the number of bytes written must be 64 for the 256-Kbit parts, 128 for the 512-Kbit and 1-Mbit parts, and 256 for the 2- and 4-Mbit parts. The first byte is written at the transmitted address. The address is incremented in the Configurator following the receipt of each Data Byte. Only the lower bits of the address (6, 7 or 8, depending on the page length) are incremented. Thus, after writing to the last byte address within the given page, the address will roll over to the first byte address of the same page. Data Byte LSB MSB D0 D1 D2 D3 D4 D5 D6 D7 1st 2nd 3rd 4th 5th 6th 7th 8th A Write Instruction consists of a Start Condition a Device Address Byte with R/W = 0 An Acknowledge Bit from the Configurator MS Byte of the EEPROM Address (512-Kbit, and 1-, 2- and 4-Mbit parts only) An Acknowledge Bit from the Configurator (Next) Byte of the EEPROM Address An Acknowledge Bit from the Configurator LS Byte of EEPROM Address An Acknowledge Bit from the Configurator One or more Data Bytes (sent to the Configurator) Each followed by an Acknowledge Bit from the Configurator a Stop Condition WRITE POLLING: On receipt of the Stop Condition, the Configurator enters an internally-timed write cycle. While the Configurator is busy with this write cycle, it will not acknowledge any transfers. The programmer can start the next page write by sending the Start Condition followed by the Device Address, in effect polling the Configurator. If this is not acknowledged, then the programmer should abandon the transfer without asserting a Stop Condition. The programmer can then repeatedly initiate a write instruction as above, until an acknowledge is received. When the Acknowledge Bit is received, the write instruction should continue by sending the first EEPROM Address Byte to the Configurator. An alternative to write polling would be to wait a period of tWR before sending the next page of data or exiting the programming mode. All signals must be maintained during the entire write cycle. 8 AT17N Series Programming Specification 3015A–CNFG–05/03 AT17N Series Programming Specification Reading Read instructions are initiated similarly to write instructions, but the R/W bit in the Device Address is set to one. There are three variants of the read instruction: current address read, random read and sequential read. For all reads, it is important to understand that the internal Data Byte address counter maintains the last address accessed during the previous read or write operation, incremented by one. This address remains valid between operations as long as the chip power is maintained and the device remains in 2-wire access mode (i.e., SER_EN is driven Low). If the last operation was a read at address n, then the current address would be n + 1. If the final operation was a write at address n, then the current address would again be n + 1 with one exception. If address n was the last byte address in the page, the incremented address n + 1 would “roll over” to the first byte address on the next page. CURRENT ADDRESS READ: Once the Device Address (with the R/W select bit set to High) is clocked in and acknowledged by the Configurator, the Data Byte at the current address is serially clocked out by the Configurator in response to the clock from the programmer. The programmer generates a Stop Condition to accept the single byte of data and terminate the read instruction. A Current Address Read instruction consists of a Start Condition a Device Address with R/W = 1 An Acknowledge Bit from the Configurator a Data Byte from the Configurator a Stop Condition from the programmer. RANDOM READ: A Random Read is a Current Address Read preceded by an aborted write instruction. The write instruction is only initiated for the purpose of loading the EEPROM Address Bytes. Once the Device Address Byte and the EEPROM Address Bytes are clocked in and acknowledged by the Configurator, the programmer immediately initiates a Current Address Read. A Random Address Read instruction consists of a Start Condition a Device Address with R/W = 0 An Acknowledge Bit from the Configurator MS Byte of the EEPROM Address (512-Kbit, and 1-, 2- and 4-Mbit parts only) An Acknowledge Bit from the Configurator (Next) Byte of the EEPROM Address An Acknowledge Bit from the Configurator LS Byte of EEPROM Address An Acknowledge bit from the Configurator a Start Condition a Device Address with R/W = 1 An Acknowledge Bit from the Configurator a Data Byte from the Configurator a Stop Condition from the programmer. SEQUENTIAL READ: Sequential Reads follow either a Current Address Read or a Random Address Read. After the programmer receives a Data Byte, it may respond with an Acknowledge Bit. As long as the Configurator receives an Acknowledge Bit, it will continue to increment the Data Byte address and serially clock out sequential Data Bytes until the memory address limit is reached. The Sequential Read instruction is terminated when the programmer does not respond with an Acknowledge Bit, but instead generates a Stop Condition following the receipt of a Data Byte. 9 3015A–CNFG–05/03 Programmer Functions The following programmer functions are supported while the Configurator is in programming mode (i.e., when SER_EN is driven Low): 1. Reading the Manufacturer’s Code and the Device Code. 2. Programing the device. 3. Verifying the device. 4. Setting the Reset Polarity option. In the order given above, they are performed in the following manner. The same protocol and operations are used for both 5V and 3.3V devices, as well as for the Altera pinout variants except where stated. Reading Manufacturer’s and Device Codes The AT17N512/010/002 Configurators use a different algorithm than the AT17N256 Configurators, the sequential reading of these bytes are accomplished by performing a Random Read at EEPROM Address 040000H. On AT17N002/040 Configurators, the sequential reading of these bytes are accomplished by performing a Random Read at EEPROM Address 100000H. On AT17N256 Configurators, the sequential read is done at EEPROM Address 0 by performing a Current Address Read with the following additional DC voltages set: RESET/OE = 0V CE = 11.5 ± 0.5V The correct codes are(1): Note: Programming the Device Manufacturers Code - Byte 0 1E All Device Code - Byte 1 77 AT17N256 37 AT17N512 F7 AT17N010 78 AT17N002 74 AT17N040 1. The Manufacturer’s Code and Device Code are read using the byte ordering specified for Data Bytes; i.e., LSB first, MSB last. These procedures are not supported by the supplied ISP reference design schematics for AT17N65/128/256(A) Configurators. After reading the manufacturer identification bytes, a hardware power cycle (power on reset) is required in order to access the actual location of the memory in the programming mode. For the AT17N series devices, toggling the SER_EN pin from Low to High and the Low with respect to the programming clock cycle will automatically exit the manufacturer identification read mode without power cycle. All the bytes in a given page must be written. The page access order is not important but it is suggested that the Configurator be written sequentially from address 0. Writing is accomplished by using the DATA and CLOCK pins. For the AT17N256 Configurators only, two additional programming pins must be set as follows: RESET/OE (OE)= 0V (Write protection disable) CE (nCS) Important Note on AT17N Series Configurators Programming 10 = 0V The first byte of data will not be cached for read back during FPGA Configuration (i.e., when SER_EN is driven High) until the Configurator is power-cycled. This may be critical in cascaded ISP applications where the first byte of the second or subsequent EEPROM is likely to change between updated bitstreams. AT17N Series Programming Specification 3015A–CNFG–05/03 AT17N Series Programming Specification Verifying the Device All bytes in the Configurator should be read and compared to their intended values. Reading is done using the CLOCK and DATA pins. For the AT17N256 Configurator, two additional programming pins must be set as follows: RESET/OE (OE)= 0V (Write protection disable) CE (nCS) RESET Polarity Option = 0V All Configurators in the AT17N Series have the ability to change the polarity of the RESET/OE pin. This is required to allow the devices to properly configure various FPGA families. The default condition is active Low OE and active High RESET. The AT17N256 Configurators use a different algorithm from the AT17N512/010/002 Configurators; the algorithms are described below. AT17N256 Configurator RESET/OE Polarity Programming Setting the polarity option active High OE (active Low RESET): Write Data Byte “FF” to address 3FFFH, with two additional programming pins set to the following: RESET/OE (OE)= VCC +/- 0.25V CE (nCS) = VCC +/- 0.25V Setting the polarity option active Low OE (active High RESET): Write a byte “FF” to address 3FFFH, with two additional programming pins set to the following: RESET/OE (OE)= 0V CE (nCS) = VCC +/- 0.25V Verifying the RESET Polarity: Power up the device with: RESET/OE (OE)= 0V CE = 0V SER_EN = VCC +/- 0.25V CLK (DCLK) = 0V DATA = Input to programmer In this condition, if the DATA pin is tri-stated, then the RESET/OE (OE) fuse is programmed for active High OE (active Low RESET); if the DATA pin reads a “0” or a “1”, the RESET/OE (OE) fuse is active Low OE (active High RESET). AT17N512/010 Configurator RESET/OE (OE) Polarity Programming Setting the polarity option active High OE (active Low RESET): Write four bytes “FF FF FF FF” to addresses 20000H - 20003H. Setting the polarity option active Low OE (active High RESET): Write four bytes “00 00 00 00” to addresses 20000H - 20003H. Verifying the RESET/OE Polarity AT17N512/010 Configurators: Perform a Random Read of four Data Bytes from addresses 20000H - 20003H. If the data is “00 00 00 00” then the fuse is programmed for active Low OE (active High RESET); if the data is “FF FF FF FF” then the fuse is programmed for active High OE (active Low RESET). AT17N002/040 Configurator RESET/OE Polarity Programming Setting the polarity option active High OE (active Low RESET): Write four bytes “FF FF FF FF” to addresses 400000H - 400003H. Setting the polarity option active Low OE (active High RESET): Write four bytes “00 00 00 00” to addresses 400000H - 400003H. Verifying the RESET/OE Polarity AT17N002/040 Configurators: Perform a Random Read of four Data Bytes from addresses 400000H - 400003H. If the data is “00 00 00 00” then the fuse is programmed for active Low OE (active High RESET); if the data is “FF FF FF FF” then the fuse ISP programmed for active High OE (ACTIVE LOW RESET). 11 3015A–CNFG–05/03 Important Notes on AT17N Series Configurators RESET Polarity Programming 1. The pin conditions above must be maintained during the entire write cycle; tWR or until the next Device Address is acknowledged (if using Write polling). Atmel AT40K and AT6K Applications All AT6K FPGAs and AT40K FPGAs can be configured with our AT17N Series Configurators using a simple 3-wire interface that is highly desirable for ISP applications. 2. After the RESET polarity has been modified, the Configurator must be powered down and back up again before attempting to verify functionality or use the newly programmed RESET function. Figure 2. Typical System Setup using the ATDH2200 Programmer 10-pin Ribbon Cable Parallel Cable DB-25M Parallel Port PC 25 FPGA ATDH2200 DB-25F Target System FPGA 10 In-System In-System Programming Programming Connector Connector Header Header AT17N Configurator Figure 3. Typical System Setup using the ATDH2225 Download Cable 10-pin Ribbon Cable Target System FPGA FPGA ATDH2225 10 PC Programming Dongle 12 In-System Programming Connector Header AT17N Configurator AT17N Series Programming Specification 3015A–CNFG–05/03 AT17N Series Programming Specification DC Characteristics in Programming Mode (SER_EN) VCC = 3.3V - 5V ± 10%, TA = -40°C - 85°C(1)(2) Symbol Parameter VCC Supply Voltage ICC Supply Current ILL Min Typ Max Units 3.0 4.13 5.25 V VCC = 3.6 2.0 5.0 mA Input Leakage Current VIN = VCC or VSS 0.10 10 µA ILO Output Leakage Current VOUT = VCC or VSS 0.05 10 µA VIH High-level Input Voltage VCC x 0.7 VCC + 0.5 V VIL Low-level Input Voltage -0.5 0.4 V VOL Output Low-level Voltage 0.4 V Max Units 400 KHz Notes: Test Condition IOL = 2.1 mA 1. Commercial temperature range -40°C - 70°C 2. Industrial temperature range -40°C - 85°C AC Characteristics VCC = 3.3V - 5V ± 10%, TA = -40°C - 85°C(1)(2) Symbol Parameter fCLOCK Clock Frequency, Clock tLOW Clock Pulse Width Low 1.2 µs tHIGH Clock Pulse Width High 1.2 µs tAA Clock Low to Data Out Valid tBUF Time the bus must be free before a new transmission can start 1.2 µs tHD;STA Start Hold Time 0.6 µs tSU;STA Start Setup Time 0.6 µs tHD DAT Data In Hold Time 0.1 µs tSU DAT Data In Setup Time 0.1 µs tR Inputs Rise Time 0.3 µs tF Inputs Fall Time 0.3 µs tSU STO Stop Setup Time tDH Data Out Hold Time tWR Write Cycle Time Notes: Min 0.9 µs 0.6 µs 0 µs 25 ms 1. Commercial temperature range -40°C - 70°C 2. Industrial temperature range -40°C - 85°C 13 3015A–CNFG–05/03 Figure 4. Serial Data Timing Diagram t LOW t HIGH CLOCK t HD.STA tR tF t SU.STO t SU.DAT t SU.STA t HD.DAT DATA(IN) t BUF tAA t DH DATA(OUT) 14 AT17N Series Programming Specification 3015A–CNFG–05/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof are the registered trademark of Atmel. Xilinx ®, Spartan ® and Virtex ® are the registered trademarks of Xilinx Corporation. Altera ® is the registered trademark of Altera Corporation. FLEX ™ is the trademark of Altera Corporation. Other terms and product names may be the trademarks of others. Printed on recycled paper. 3015A–CNFG–05/03 xM