AVR455: ATAVRSB201 User's guide Features • ATmega16HVA smart battery chip evaluation and development kits. - ATAVRSB201-1 for Single Series Li-Ion Cell applications. - ATAVRSB201-2 for 2 Series Li-Ion Cell applications. • High-side N-FETs. • 10 mΩ sense resistor current measurements with the 18-Bit CC-ADC. • Input filters for cell voltages to the 12-bit voltage ADC. • All components on one side. • Four layer PCB with the reference design part implemented on two layers. • Balancing FETs. • Polarity safety FET. • Holes for mounting of pin headers or wires. • ISP connector for programming via SPI, and debugging via debugWIRE interface. 8-bit Microcontrollers Application Note 1 Introduction The ATAVRSB201-1/SB201-2 kits are evaluation and development kits for the new Atmel AVR® smart battery device ATmega16HVA. This device is made for battery packs with 1 series or 2 series lithium ion and lithium polymer cells, and feature autonomous battery protection as well as very accurate voltage, current and temperature monitoring capabilities. The device provides the means to protect the battery pack and surroundings from hazardous conditions and gain the most from the batteries. The kits consist of both hardware and firmware, with hardware documented here and firmware in application note AVR456. The boards have an edge connector for connection to ATAVRSB200 Smart battery Evaluation kit, but can for development purposes also be used alone. Figure 1-1. SB201-1 Kit. Rev. 8131A-AVR-10/08 2 Hardware The SB201-1 and SB201-2 have a common PCB and only differ in which components are mounted and the silk screen. They will be commonly referred to as SB201 in this document unless differences exist. The SB201 consist of three parts, the edge connector, the main area and the connector and support area. The main area contains all the circuitry needed in a battery pack design. Edge Connector Main area Connector and supporting area Figure 2-1. SB201 Block layout. 2.1 Main area The main area contain the ATmega16HVA device, charge and discharge N-FETs, 10mΩ sense resistor, decoupling capacitors, filter capacitors/resistors for the voltage and current ADCs and ESD protection. 2.2 Connector and support area The connector area contains holes for two pin headers with 2x6 and 2x2 pins, to give access to several signals and device pins as shown in Table 2-1 and Table 2-2. Pin headers with 2.54mm spacing or wires can be soldered in here. A connector for incircuit programming is mounted. Lastly the area contains cell balancing and a board ID system, which are described in more details in the next subsections. Table 2-1. Signals that can be found on the 2x6 pin header holes. 2 Name Description PACK+ Battery-pack positive input/output. Also connected to BATT pin. PACK- Battery-pack negative input/output (ground). CELL+ Cell stack positive terminal. CELL- Cell stack negative terminal. VFET VFET pin. VREG Regulator output. Connected to VCC. AVR455 8131A-AVR-10/08 AVR455 Name Description PV1R Cell1 positive input. PV2R Cell2 positive input. PA0 PA0 pin. PA1 PA1 pin. PB0 PB0 pin. PC0 PC0 pin. Used for 1-wire SW-UART. Includes ESD protection. Table 2-2. Signals that can be found on the 2x2 pin header holes. Name Description C1BO Cell1 Balancing On input. C2BO Cell2 Balancing On input. VREF VREF. VGND VREF ground. ISP programming via SPI interface. Table 2-3 shows connections. Alternative pin names are also noted. Table 2-3. ISP connector (J111) signals Name Pin no Description MISO 1 Serial data out. (PB3) VCC 2 Supply voltage SCK 3 Serial clock. (PB1) MOSI 4 Serial data in. (PB2). RESET 5 Reset signal (active low) GND 6 Ground 2.2.1 Polarity safety FET A voltage negative to ground connected on the input (charger with reverse polarity) will pull the source of the discharge FET to negative voltage and with the ground potential on the gate the FET will likely be turned on. Since the diode of the Charge FET will conduct a discharge current, a large current will in this case flow out of the battery cell(s) with the ATmega16HVA unable to stop it. A FET (Q2) on the pack input which pulls the source of the discharge FET to the negative input voltage is included in the design to avoid this situation. This is an optional part in a design but included in the main area. 2.2.2 Board ID system A board identification system is included to allow the SB200 to recognize which board is inserted. The wiring and thus response of this is different between SB201-1 and SB201-2. The board ID system is not relevant for stand-alone usage of the SB201 or designs with the ATmega16HVA. 3 8131A-AVR-10/08 2.2.3 Single cell mode capacitors The capacitors connected to CF1P/N and CF2P/N allow step up operation of the regulator. It is used for powering the device from 1.8V to approximately 3.6V input voltage and would normally not be needed in 2-cell applications as the input voltage should then not go that low, but it is included to allow the same PCB layout to be used for both SB201-1 and SB201-2. Please see the voltage regulator section in the data sheet for details of regulator operation. In a regular design one would only include the capacitors for a 1-cell design. 2.2.4 Cell balancing The SB201-2 contains cell-balancing FETs, while this circuitry is un-mounted on SB201-1. Cell balancing is controlled by PB2 and PB3 on SB201-2, and if PB2/PB3 are desired used for other tasks the 0Ω resistors R21/R22 connecting them to the cell balancing should be removed. 2.3 Edge connector The edge connector provides a quick and secure connection to the demonstration board SB200. 3 Connecting batteries to SB201 The SB201-1 is made for 1 series Cell battery pack, while the SB201-2 is made for 2 series cells battery packs. The connections are described in the following subsections. WARNING: Li-Ion batteries must be handled with care as they may pose a safety hazard if treated incorrectly. It is important that the development of Li-Ion battery applications are done by people that are skilled and knowledgeable of correct use and handling of such batteries. 3.1 2-cell application SB201-2 For applications with 2 series cells, connect cells as shown in Figure 3-1: Positive terminal of upper cell to CELL+, negative terminal of upper cell and positive of lower cell to PV1R, and finally negative terminal of lower cell to CELL-. Load or charge the batteries trough PACK+ and PACK-. To start the part and thus possibly open the FETs, a charge condition must be initiated by a charger. 4 AVR455 8131A-AVR-10/08 AVR455 Figure 3-1. Connection of 2-cells in series packs to SB201-2. 3.2 1-cell application SB201-1 The SB201-1 for 1-cell in series applications, connect the cell as shown in Figure 3-2: Positive terminal of cell to CELL+ and negative terminal to CELL-. Load or charge the battery through PACK+ and PACK-. To start the part and thus possibly open the FETs, a charge condition must be initiated by a charger. Figure 3-2. Connection of 1-cells packs to SB201-1. CELL+ CELL- 4 Programming The board can be programmed with STK®500, STK600, AVRISPmkI/mkII, JTAGICE mkII and AVR Dragon™ via the ISP socket. See the ATmega16HVA datasheet and AVR Studio® help for connections. 5 Debugging ATmega16HVA features on-chip debugging via debugWIRE interface, with either JTAGICEmkII or AVR Dragon. To enable debugging the capacitor (C10) on the reset line needs to be removed, as this stabilization of the Reset pin prevents communication through debugWIRE. Please notice that debugWIRE must be enabled via the ISP interface if not enabled, and disabled after debugging to enable ISP again. This is described in AVR Studio help. Leaving the ATmega16HVA with DWEN-fuse on will increase current consumption. 5 8131A-AVR-10/08 6 Powering up the SB201 Please see the ATmega16HVA datasheet for how to wake the device from Power Off mode, and thus enable programming and/or operation. The SB200 provides this functionality automatically and manually. 7 Considerations when using SB201 in SB200 WARNING: Connecting SB201-1 in a SB200 with Cell2 mounted will result in the destruction of tracks as PV2R and PV1R is shorted through a 0 Ω resistor (R9) on SB201-1. Make sure you use correct board with correct number of cells. The resistor (R24) connecting the PV2R and CELL+ should be removed on SB201 to facilitate correct current measurements through the jumper position, as otherwise some of the current may flow through the PV2R connection. 8 Specifications Max continuous current: +/-3A. Max input voltage: 9V. Table 8-1. Power consumption. Frequency [MHz] Active mode [mA] Idle mode [mA] Power save [μA] 1 1.00 0.38 30 Application current consumption is dependant on the firmware, and if communications are active as the ATmega16HVA has no hardware UART. AVR455 showed a typical current consumption of 160uA for SB201-1 in a 1-cell application. 9 Schematics The schematics for SB201-1 and SB201-2 are provided in the .zip-file that can be downloaded from Atmel AVR Application notes. A small version of the common schematic is provided here. 6 AVR455 8131A-AVR-10/08 AVR455 Figure 9-1. Schematics for SB201. 1 2 _ _ Y = (I0)•(I2) + (I1)•(I2) 3 4 5 R24 0R J4 PV1R PV2R 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 J5 MEC1_60PAD_PCB VCC U2 NC7SZ57P6X PACK+ PACK+ ESD PGND C11 C12 100n 100n 100n 3 2 7 6 2-Input AND 3 2 1 5 ODG 1 8 4 VFET PMWD15UN OCG J8 VFET VFET CELL- Si1022R OC Mount for 2 cell application 2-Input NAND with inverted A Input R5 1k 2 BATT GND R18 WSL0805R0100FEA PGND PGND PV1R PV1R R19 C3 C5 VREG C5 100n NI 100R PGND C1BO MOSI Net Tie A7 A6 C8 OD BATT RESET PB0 PB0 J11 RESET PA1 PA1 PA0 J13 PA0 C1 C2 VREF VREFGND J14 R15 VREF TC_COM TCOM 10k VREFGND C J15 C4 1u VREFGND VGND ISP circuit GND GND PGND PB2 E7 E3 E4 100R MISO MOSI SCK J16 C9 220n GND - PGND connection close to RSENSE VREG CELL- B3 VREG VCC R13 10k PGND dW/RESET/PA2 (ADC1/SGND/T1)PA1 (ADC0/SGND/T0)PA0 C8 220n PGNDGND CELL1_BAL_ON C1BO J12 R22 0R 1 5 PI 100R CF1P CF1N CF2P CF2N MISO MOSI SCK VREG VREG J17 PGND C7 100n 2.2uF/10V CELL- GND GND J18 MISO SCK RESET D3 BAS40L C6 Block Reset 5V from Master to VREG 1 3 5 TSM-103-01-T-DH-TR 1 6 Q4A NDC7001C 4 B4 C4 B1 B2 A1 A8 B7 E1 E2 E8 2 Q4B NDC7001C 3 R14 470R R17 PB3 R7 10k PGND NV 470R D7 D6 E5 E6 2 MISO C3 100n (MISO/INT2)PB3 (MOSI/INT1)PB2 (SCK)PB1 (SS/CKOUT)/PB0 R10 PC0 B6 (ICP0/INT0)PC0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 R21 0R R16 PV2 PV1 NV PI NI B ATmega16HVA-36CK1 A5 B5 B8 C6 C7 D3 D4 D5 D8 6 5 1 R12 10k A2 A3 A4 D1 D2 PV1 470R C2BO CELL2_BAL_ON C2BO J10 Q3A NDC7001C 4 R8 470R C2 Mount for 2 cell application 100n R11 DNC1 DNC2 DNC3 DNC4 DNC5 DNC6 2 Q3B NDC7001C 3 C R9 0R PV2R R3 10k VFET Mount for 1 cell application PV2R 470R OC Mount for 2 cell application CF1P CF1N CF2P CF2N Cell-balancing U3 PV2 PC0 J9 D2 BZB984-C5V6 GND_ID R2 USART1W R6 1k PGND OD R4 1k R1 10k 3 Mount for 1 cell application D1 BAS40L 1 Q1 J7 1 PACK- 2 RESET PB0 SCK MOSI MISO USART1W C2BO C1BO J6 2 GND Polarity safety MOSFET CELL- ID_Y1 4 GND_ID R25 0R 100n A ESD Q2 0R C14 Charge & Discharge MOSFETs Y R26 C13 PGND RESET 60 58 PB0 56 SCK MOSI 54 MISO 52 50 USART1W 48 46 44 42 40 38 36 34 32 30 28 26 24 2 5 ID_A ID_B GND_ID I0 I1 I2 CELL+ 19 17 15 13 11 9 7 5 3 1 VCC_ID ID_Y2 ID_Y1 ID_B ID_A 2-Input AND B 8 CELL+ 20 18 16 14 12 10 8 6 4 2 GND_ID ID_Y2 4 GND Y A 3 1 6 7 J3 PCB Edge-connector to SB200 TC_COM PA0 PA1 VCC I0 I1 I2 PV2R Remove when using SB200 GND_ID U1 NC7SZ57P6X VREG 5 C1 100n 3 1 6 6 J1 J2 PV1R VCC_ID VREG 2 4 6 MOSI PGND R20 10k RESET C10 10n PCB1 ATMEL Norway GND PCB2 D Vestre Rosten 79 Remove C10 to use debugWire LOGO1 LOGO2 AVR 3MM NORWAY 17.04.2008 10:13:28 PAGE: 1 A08-0482 SB201.SchDoc A08-0483 2 3 4 5 6 7 8 7 8131A-AVR-10/08 of 1 Assembly Variant: Revision: D Document number: A08-482/A08-483 Variant name is not interpreted until output TITLE: SB201 monitoring and protection circuit for 1/2-cell Li-ion ATMEL AVR_LOGO_OVERLAY_3MM ATMEL_LOGO_OVERLAY 1 D 7075 TILLER Date: 10 Component Placement Component placement for SB201-1 and SB201-2 are provided in the .zip-file that can be downloaded from Atmel AVR Application notes. A small version of SB201-1 is shown here. Figure 10-1. Assembly drawing. 11 Bill of Materials (BOM) The BOM is provided in the .zip file that can be downloaded from Atmel AVR Application notes. The difference between SB201-1 and SB201-2 is that the SB201-2 provides cell balancing circuitry. Otherwise the SB201-1 has a 0 Ω resistor connecting PV2 and PV1, and the board identification has a different resistor mounting.b 8 AVR455 8131A-AVR-10/08 AVR455 12 EVALUATION BOARD/KIT IMPORTANT NOTICE This evaluation board/kit is intended for use for FURTHER ENGINEERING, DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY. It is not a finished product and may not (yet) comply with some or any technical or legal requirements that are applicable to finished products, including, without limitation, directives regarding electromagnetic compatibility, recycling (WEEE), FCC, CE or UL (except as may be otherwise noted on the board/kit). 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