AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE AN N1200.2 23 Reccomm mendedSX X1272 2Settingssfor LoRaWA ANNetwo orkOp perattion Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 1 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE nt TableofConten 1 Inttroduction............................................................................................................................3 2 Up plinkTran nsmission ns........................................................................................................3 2.1 LoRa Mode e .................................................................................................................................. 3 2.2 GFSK Mode ................................................................................................................................. 4 3 Do ownlinkR ReceptionSlotsFolllowingan nUplink....................................................5 3.1 LORA Mod de ................................................................................................................................. 6 3.1.1 Registter Settings ................................................................................................................. 6 3.1.2 RX Window Precisse Timing ................................................................................................. 7 3.2 GFSK Mode ............................................................................................................................... 12 3.2.1 Registter Settings ............................................................................................................... 12 3.2.2 RX Window Precisse Timing in GFSK Mode ...................................................................... 14 4 RaandomNu umberGen nerationfforCrypto ography..................... . ...........................15 Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 2 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE 1 Inttroductio on This app plication note e presents th he recomme ended setup of the SX1272 radio transceiver opeerating in a LoRaW WAN networkk. 2 Up plinkTra ansmissio ons 2.1 Lo oRaMode e Uplink trransmissionss can use thee following Lo oRa settings: 1. LoRa modulaation with 12 25 kHz bandw width, SF7 to o SF12. 2. LoRa modullation with 250 kHz baandwidth, SF7 only. Co orrespondingg to the higgh speed c channel The follo owing radio ssettings shou uld be used: SX1272 Reegister (address) Registerr bit field (bit #)) Values No ote RegOpMode (0x01) LongRan ngeMode[7] Mode[2::0] PaRamp[3:0] Bw[7:6] CodingRate[5:3] ImplicitH HeaderModeOn n[2] RxPayloaadCrcOn[1] LowDataaRateOptimize[[0] ‘1’ ‘011’ ‘1000’ ‘00’ or ‘0 01’ ‘001’ ‘0’ ‘1’ ‘0’ or ‘1’ RegModem mConfig2 (0x1EE) Spreadin ngFactor[7:4] ‘0111’ to o ‘1100’ RegSyncW Word (0x39) LoRa syn nc word 0x34 RegInvertIIQ (0x33) RegInvertIIQ2 (0x3B) IQ inverssion bits IQ inverttion bits 0x27 0x1d LoR Ra mode enableed Tx mode 50 us PA Ramp‐up p time ‘00 0’ for 125kHz modulation Band dwidth ‘01 1’ for 250kHz modulation Band dwidth 4/5 5 error coding rrate Pacckets have up‐ffront header CRC C enable ‘0’ when Spreadin ng Factor is <= 1 10 ‘1’ when Spreadin ng Factor is >= 1 11 witth 125kHz band dwidth : ‘01 111’ (SF7) = 6kkbit/s ‘11 100’ (SF12) = 30 00 bit/s (on nly SF7 is supported s witth 250kHz ban ndwidth) Sett sync word for LoRaWAN netw works (deefault is 0x12 fo or other networrks) Thiis is the defaultt value, no inversion Thiis is the defaultt value, no inversion RegPaRam mp (0x0A) RegModem mConfig1 (0x1D D) All registters not expllicitly mentio oned can stayy with their default valuee. Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 3 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE 2.2 G GFSKMode e The LoRaaWAN speciffication defin nes a high sp peed uplink cchannel usin ng 50kbit/s G GFSK modulation. The followingg radio settin ngs should b be used (all se ettings omittted should b be left to their default value) General and Transmitter settingss Modulation = FSK Fdev = +/‐25 5kHz (modullation index = 1) Bit rate setting = 50kbit//s Gaussian filt G er ON Filter settingg : BT=0.5 Output Powe O er setting: haardware dep pendent PA selection: hardware d dependent SX1272 Reegister (address) Registerr bit field (bit #)) Values No ote RegOpMode (0x01) LongRan ngeMode[7] ModulattionType[6:5] ModulattionShaping[4:3 3] Mode[2::0] BitRate[1 15:8] BitRate[7 7:0] Fdev[13::8] Fdev[7:0 0] ‘0’ ‘00’ ‘10’ ‘011’ 0x02 0x80 0x01 0x99 FSK K/OOK mode en nable FSK K Modulation sccheme Gaussian filter BT = 0.5 Tx mode BitRate set to 50kkbps RegBitrateeMsb (0x02) RegBitrateeLsb (0x03) RegFdevM Msb (0x04) RegFdevLssb (0x05) Freequency deviatiion set to +/‐25 5kHz Frame and Packet Haandler settin ngs Figure 1:: Packet Handle er Format Packet Mode e : this modee inserts a PH HY header to o support varriable payloaad length Preamble Le ength = 5 byttes S Sync Word= 3 bytes : 0xxC194C1 V Variable Len gth frame fo ormat DC‐free dataa encoding = Whitening C CrcOn=1, Crc cAutoclearOn=1 Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 4 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE SX1272 Reegister (address) Registerr bit field (bit #)) Values No ote RegPream mbleMsb (0x25) RegPream mbleLsb (0x26) RegSyncCo onfig (0x27) PreambleSize[15:8] PreambleSize[7:0] AutoRestartRxMode[7:6] PreamblePolarity[5] SyncOn[4] FifoFillCo ondition[3] SyncSizee[2:0] PacketFo ormat[7] DcFree[6 6:5] CrcOn[4]] CrcAutoC ClearOff[3] AddressFFiltering[2:1] CrcWhiteeningType[0] DataMod de[6] SyncValu ue[63:56] SyncValu ue[55:48] SyncValu ue[47:40] 0x00 0x05 ‘00’ ‘0’ ‘1’ ‘0’ ‘002’ ‘1’ ‘10’ ‘1’ ‘0’ ‘00’ ‘0’ ‘1’ 0xC1 0x94 0xC1 5 B Byte of preamblle for each packket RegPackettConfig1 (0x30) RegPackettConfig2 (0x31) RegSyncVaalue1 (0x28) RegSyncVaalue2 (0x29) RegSyncVaalue2 (0x2A) AuttoRestart OFF Pre eamble 0xAA Syn nc Address enable Fill FIFO when Syn nc Address is deetected 3 B Bytes of Sync W Word Varriable length paackets Wh hitening encoding enable Enaable CRC calculation Cle ear FIFO when C CRC check fails No address filterin ng CCITT CRC and Wh hitening implem mentation Paccket Mode Syn nc Address is 0xxC194C1 3 Do ownlinkR ReceptionSlotsFollowing ganUplin nk A LoRaW WAN node op pens two recception slots for potentiaal downlink ccommunicatiions after each uplink transmisssions. The delay d between the end of a transmission (signaaled by the TxDone T IRQ)) and the beginnin ng of the reception slot iss constant an nd defined eextremely precisely to minimize the rreception current o overhead on n the end‐po oint side. Mo ost of the tim me this recep ption slot will not be useed by the gatewayys, id no fram me will be reeceived. Therrefore, to minimize the ccurrent conssumption thee radio is program mmed to liste en to the ch hannel for th he minimum m time required to detect with certaainty the presencee or absencee of a pream mble. In the absence of aa preamble, the radio go oes back to stand‐by mode. Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 5 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE 3.1 LO ORAMod de 3.1.1 RegisterSe R ettings In LoRa m mode this is achieved sim mply by usingg the Receivee Single mod de, with “IQ inversion” SX1272 Reegister (address) Regisster bit field (bit #) Values Note RegOpMode (0x01) LongRangeMode[7] Mode[2:0] LnaG Gain[7:5] LnaB Boost[1:0] Bw[7 7:6] Codin ngRate[5:3] ImpliicitHeaderModeOn[2] RxPayloadCrcOn[1] LowD DataRateOptim mize[0] ‘1’ ‘110 0’ ‘001 1’ ‘11’’ ‘00’’ or ‘01’ ‘001 1’ ‘0’ ‘1’ ‘0’ o or ‘1’ RegSymbTTimeoutLsb (0x1 1F) SpreaadingFactor[7:4 4] AgcA AutoOn[2] Symb bTimeout[1:0] Symb bTimeout[7:0] ‘011 11’ to ‘1100’ ‘1’ ‘00’’ 0x0 05 or 0x08 RegMaxPaayloadLength (0 0x23) Paylo oadMaxLength[[7:0] 0x4 40 RegSyncW Word (0x39) LoRa sync word 0x3 34 RegInvertIIQ (0x33) RegInvertIIQ2 (0x3B) IQ inversion bits IQ invertion bits 0x6 67 0x1 19 LoRa mode enable Receive Single mode LNA gain set tto the maximum m value LNA Boost en nable ‘00’ for 125kH Hz modulation Bandwidth ‘01’ for 250kH Hz modulation Bandwidth 4/5 error cod ding rate Packet have u up‐front header CRC enable ‘0’ when Spre eading Factor iss <= 10 ‘1’ when Spre eading Factor iss >= 11 with 125kHz bandwidth: ‘0111’ (SF7) == 6kbit/s ‘1100’ (SF12) = 300 bit/s (only SF7 is su upported with 2 250kHz bw) LNA gain set by internal AGC C loop 0x05 when Sp preading Factorr is >= 10 0x08 when Sp preading Factorr is <= 9 Length of the receiver window in symbols. If no preamble is detected during this time , the receivver goes back to stand‐by Sets the maaximum possib ble downlink payload size to 64 bytes. Packets with payload greaater than this threshold t will not be de emodulated, receiver r will immediately go back to “sstand‐by” low power mode Set sync word d for LoRaWAN N networks (default is 0x1 12 for other neetworks) Optimised for inverted IQ Optimised for inverted IQ RegLna (0xx0C) RegModem mConfig1 (0x1D D) RegModem mConfig2 (0x1EE) Note: seettings relatted to IQ in nversion mu ust be reverrted back to o their defaault value fo or uplink transmisssion. Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 6 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE 3.1.2 RXWindow R wPreciseTiming This parragraph explains the op ptimal RX sttart‐up time and RX slo ot duration for f the giveen timing precision n reachable by the end‐d device. The dow wnlink pream mble transmitted by thee gateways contains c 8 symbols. s The e receiver reequires 5 symbols to detect the t preamblle and synch hronize. Theerefore there must be a 5 symbolss overlap between n the receivee window and d the transm mitted pream mble. The gateeway always initiates thee transmissio on of the preeamble 1 secc +/‐ 20uSecc after the en nd of the uplink. TTherefore the beginning of the downlink preamble can be cconsidered aas a perfectly precise referencce for the resst of this calcculation. Notation n: BW Signal modulation b bandwidth in H Hz SF LORA spreading fact s tor : 7 to 12 Tsyymb Duratio on of a LORA symbol = sec RXwind dow Length h of the receivve window RXofffset Offsett in sec betw ween the optiimal receiver turn‐on timee and the actual start of the gaateway transm mission RXeerror Maxim mum timing errror of the recceiver. The reeceiver will turn‐on in a [‐RXerrror : +Rxerrorr] sec interval around RXofffset T_RX_eearly Earliesst time at whiich the receivver can start aand synchroniize on the downliink preamble T_RX__late Latest time at whicch the receiveer can start and a synchronize on the downliink preamble Those vaariables are iillustrated in the followin ng diagram: Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 7 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE Downlink staart: T = end_up plink + 1 second (+/‐ 20uSec) Desired RX startt D (without timing e error) Actual RX start RXwind dow actual RX window RX Xerror (positive) RX Xoffset (n negative) Tsymb Downlinkk preamble 8 symbols Time Figure 2: TTypical Rx Wind dow Timing The follo owing diagraam illustrates the positio oning of the earliest and d latest possiible receive windows to achievve 5 overlapping symbols with the do ownlink preaamble: Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 8 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE Downlink start: T = Rxx + 1 second (+/‐ 20uSSec) T_RX X_late T_RX_earrly Lateest possible RX X window start Earliestt possible RX window w start Latesst RX windo ow Earliest RX window Downliink preamble 8 symb bols Figure 3: Worst Case Rx Win ndow Timings From thiis diagram th he following equation can be deduceed: 3 x Tsymb T_RX_late = T T_RX_early = T = 5 x Tsymb –– RXwindow w Addition nnaly the diffference betw ween T_RX_llate and T_R RX_early corrresponds to the maximum timing error ran nge of the re eceiver thereefore: T_RX_late – T T_RX_early = 2 x RXerror To allow w this maximum timing eerror range tthe receiver should be p programmed to ideally tu urn‐on at the mid‐‐point betweeen T_RX_latte and T_RX__early , thereefore: RXoffset = (TT_RX_late + TT_RX_early)//2 So assum ming the RX Xerror param meter is set (RXerror is a direct co onsequence of a given design, d it dependss on the oscillator precision, temperaature drift, … …) We can d deduce: RXwindow == 2 x Tsymb ++ 2 x RXerrorr RXoffset = 4 x Tsymb – R Rxwindow/2 Because the minimu um RXwindo ow must be at least 5 syymbols longg, the system m always tolerates at least an RXerror of at least 1.5 x Tsymb Numericcal applicatio on: Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 9 of 16 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE The senssor can achie eve a +/‐ 1.5 5mSec timingg drift after aa 1sec sleep period and is using SF7//125kHz At SF7/1 125kHz Tsymb = 1mSec So we seet RXerror = 1.5mSec We dedu uce RXwindo ow = 2 x Tsymb + 2 x RXeerror = 2 x 128 8 / 125e3 + 3 3e‐3 = 5mSecc The RXw window is expressed in syymbol unit in the SX127 72 transceiveer, at SF7 a ssymbol is 1m mSec long thereforre the RWwin ndow corresponds to 5 ssymbols. The senssor will progrrammed to sstart with RX Xoffset = = 4 x Tsymb – – RXwindow//2 = = 4e‐3 – 2.5e ‐3 = 1.5e3. Withoutt timing erro or, the receeiver should d turn on exactly e 1.5mSec after th he beginning of the downlink preamble. The senssor can achie eve a +/‐ 20m mSec timingg drift after aa 1sec sleep period and iis using SF7//125kHz RXwindo ow = 2 x Tsyymb + 2x RX Xerror = 42m mSec , this is larger thaan 5 symbolls , therefore we set RXwindo ow to the immediatemy ggreater or eq qual length w which is an in nteger multiple of Tsymb b RXwindow == 42 x Tsymb = 42mSec Then: RXoffset = 4 x Tsymb – R RXwindow/2 = ‐17mSec The receeiver should be programm med to start 17mSec beffore the startt of the downlink preamble The sam me sensor but now using SF10/125kH Hz instead off SF7 At SF10//125kHz Tsym mb = 8.2mSeec RXwindo ow = 2 x Tsyymb + 2x RX Xerror = 56.4 4mSec , this is larger than 5 symbols , thereforre we set RXwindo ow to the immediately grreater or equ ual length wh hich is an intteger multiple of Tsymb RXwindow == 7 x Tsymb == 57.4mSec Then: RXoffset = 4 x Tsymb – R RXwindow/2 = 4.1mSec The receeiver should be programm med to start 4.1mSec aftter the start of the downlink preamble Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 10 of 1 P 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE The follo owing tables give a few n numerical exaamples for vvarious SF / B BW/ timing eerror sets: Rxerrror +/‐ 1.5 5 mSec BW 125 5 kHz SF 7 8 9 10 11 12 Tsymb RXoffset (mSec) 1.0 2.0 4.1 8.2 16.4 32.8 (mSec) 1.5 3.1 6.1 12.3 24.6 49.2 RX wind dow Symb 5.0 5.0 5.0 5.0 5.0 5.0 mSec 5.1 10.2 20.5 41.0 81.9 163.8 Rxerrror +/‐ 20 0 mSec BW 250 0 kHz SF 7 8 9 10 11 12 Tsymb RXoffset (mSec) 0.5 1.0 2.0 4.1 8.2 16.4 (mSec) ‐18.7 ‐17.4 ‐14.3 ‐8.2 4.1 24.6 RX wind dow Symb 81.0 42.0 22.0 12.0 7.0 5.0 mSec 41.5 43.0 45.1 49.2 57.3 81.9 Rxerrror +/‐ 20 0 mSec BW 250 0 kHz SF 7 8 9 10 11 12 Tsymb RXoffset (mSec) 0.5 1.0 2.0 4.1 8.2 16.4 (mSec) ‐18.7 ‐17.4 ‐14.3 ‐8.2 4.1 24.6 RX wind dow Symb 81.0 42.0 22.0 12.0 7.0 5.0 mSec 41.5 43.0 45.1 49.2 57.3 81.9 Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 11 of 1 P 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE 3.2 G GFSKMode e 3.2.1 RegisterSe R ettings Receiverr‐specific setttings RxBw=50kHzz // single sid de Carson BW W=50kHz AfcBw=83.3k A kHz // assum ming +/‐30pp pm of LO misalignment att 869.525 MHz AgcAuto=On A n Preamble De etection On, over 2 Bytess, Number off samples in error = 10 AfcAutoOn A rOn AfcAutoClea A RxTrigger=Prreamble LnaBoost=On SX1272 Reegister (address) Register bit field (bit #)) Values No ote RegLna (0xx0C) LnaGain[[7:5] LnaBoostt[1:0] RestartRxOnCollision[7]] RestartRxWithoutPllLocck[6] RestartRxWithPllLock[5 5] AfcAutoO On[4] AgcAutoOn[3] RxTrigger[2:0] RxBwMaant[4:3] RxBwExp p[2:0] RxBwMaantAfc[4:3] RxBwExp pAfc[2:0] PreambleDetectorOn[7 7] PreambleDetectorSize[6:5] PreambleDetectorTol[4 4:0] AutoResttartRxMode[7:6] PreamblePolarity[5] SyncOn[4 4] FifoFillCo ondition[3] SyncSize[2:0] PacketFo ormat[7] DcFree[6 6:5] CrcOn[4]] CrcAutoC ClearOff[3] AddressFFiltering[2:1] CrcWhiteeningType[0] ‘001’ ‘11’ ’0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘110’ ‘01’ ‘011’ ‘10’ ‘010’ ‘1’ ‘01’ ‘01010’ ‘00’ ‘0’ ‘1’ ‘0’ ‘002’ ‘1’ ‘10’ ‘1’ ‘1’ ‘00’ ‘0’ LN NA gain set to th he highest gain LN NA Boost enablee No o restart on collision Co orrects frequency offset Au utomatic gain control Trigs on preamble only Re eceiver Bandwid dth =50kHz SSB B DataMod de[6] SyncValu ue[63:56] SyncValu ue[55:48] SyncValu ue[47:40] ‘1’ 0xC1 0x94 0xC1 RegRxConfig (0x0D) RegRxBw ((0x12) RegAfcBw (0x13) RegPream mbleDetect (0x1F) RegSyncCo onfig (0x27) RegPackettConfig1 (0x30) RegPackettConfig2 (0x31) RegSyncVaalue1 (0x28) RegSyncVaalue2 (0x29) RegSyncVaalue2 (0x2A) Re eceiver Bandwid dth =83.3kHz SSB for AFC Prreamble detecto or enable Prreamble detection over 2 bytees 10 0 chip errors tollerated over deetection Au utoRestart OFF Prreamble 0xAA Syync Address enaable Filll FIFO when Syync Address is d detected 3 B Bytes of Sync W Word Vaariable length p packets W Whitening encod ding enable En nable CRC calcu ulation PaayloadReady IRQ will always be geenerated at thee end of the frame, f CRC must be checked through dedicated flag No o address filteriing CC CITT CRC and W Whitening impleementation Paacket Mode Syync Address is 0 0xC194C1 Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 12 of 1 P 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE Expected d performance: @ BER=0 0.1% = ‐109d dBm (confirm med with PER R on a short p packet) Operatio on Flowchartt for Receiverr The follo owing flowch hart shows h how the receeiver should be operated d for each reeception slott in GFSK mode. Figure 4: FSSK Rx Operation Flowchart Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 13 of 1 P 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE DownlinkPresent tim meout : timerr started wh hen the devicce is set to R Rx mode. Sizzed to only lleave the receiver open for a short amount of time w when the downlink comm mand is exp pected. It is m meant to nc Word + maargin, so sho ould be set to o 1.3ms. capture 5 bytes of Prreamble + 3 Bytes of Syn The “Syn ncAddress” interupt i can be mapped d to the DIO O2 line of the e SX1272 orr can alternaatively be polled th hrough the SSPI interface. The “PayyloadReady”” interrupt can be mapped to the DIIO0 line of the SX1272 o or polled through the SPI interrface. 3.2.2 RXWindow R wPreciseTiminginGF FSKMode We notee FSKbitrate tthe bit rate o of the GFSK m modulation iin bit per secc The GFSK frame preeamble is 8 b bytes long (5 5 bytes preamble + 3 bytes sync word), thereforre the RX window and the begginning of thee TX preamb ble must overrlap on 8*8/FSKbitrate seec The LoRaaWAN v3 only supports aa single GFSK K bit rate = 5 50kbits/sec Thereforre the overlaap must be equal or greater than 1.3m mSec So using the same no otation than in the LORA A section we have: 0 T_RX_late = T T_RX_early = T = 1.3mSec – RXwindow Similarlyy we can ded duce that for 50kbit/sec G GFSK the min nimal RXwind dow is: RXwindow == 1.3mSec + 2 2 x RXerror and RXoffset = – Rxwindow/2 2 Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 14 of 1 P 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE 4 Ra andomNu umberGe enerationforCry yptograph hy The LoR RaWAN MA AC softwaree layer requires the generation g of truly random numbers for cryptogrraphy purposses. This can be achieved d using the naturally rand dom noise off the radio channel. The reco ommended w way to generrate a random m binary num mber is the ffollowing: Radio receiver settin ngs: SX1272 Reegister (address) Regisster bit field (biit #) Values Note RegOpMode (0x01) LongR RangeMode[7] Modee[2:0] Bw[7:6] Codin ngRate[5:3] ImplicitHeaderModeeOn[2] RxPayyloadCrcOn[1] LowD DataRateOptimize[0] SpreaadingFactor[7:4 4] AgcA AutoOn[2] Symb bTimeout[1:0] ‘1’ ‘101 1’ ‘00’’ ‘001 1’ ‘0’ ‘1’ ‘0’ ‘011 11’ ‘1’ ‘00’’ LoRa mode en nable Receive Continuous mode ‘00’ for 125kH Hz modulation B Bandwidth 4/5 error coding rate Packet have u up‐front headerr CRC enable ‘0’ when Spre eading Factor is <= 10 ‘0111’ (SF7) == 6kbit/s RegModem mConfig1 (0x1D D) RegModem mConfig2 (0x1EE) To generate an N bit random number, perfform N read d operation of o the registter RegRssiW Wideband (addresss 0x2c) and use the LSB B of the fetcched value. The T value frrom RegRssiW Wideband iss derived from a w wideband (4M MHz) signal sstrength at the receiver iinput and the e LSB of this value constaantly and randomlly changes. The RegRssiValue re egister (at ad ddress 0x1b)) should nott be used fo or random number geneeration. It has been n experimentally measurred that if a constant CW W input poweer is applied at the receiver input inside th he current reeceiver channel the LSB o of the RegRsssiValue regiister may bee constant orr strongly biased. Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 15 of 1 P 6 www.semttech.com AN1 1200.23 3 SX1272 Se ettings ffor LoR RaWAN N WIRELES SS, SENSING & TIMING APPLICATIO ON NOTE © Semtech 2015 All rights rreserved. Repro oduction in who ole or in part iss prohibited witthout the prior written consen nt of the copyriight owner. The inform mation presenteed in this docum ment does not form part of an ny quotation orr contract, is beelieved to be acccurate and reliable an nd may be chan nged without n notice. No liability will be acceepted by the publisher for any consequencee of its use. Publication thereof doess not convey no or imply any liccense under paatent or other iindustrial or intellectual property rights. Semtech aassumes no ressponsibility or liability whatso oever for any faailure or unexp pected operatio on resulting fro om misuse, neglect im mproper installaation, repair or improper hand dling or unusuaal physical or electrical stress including, but not limited to, exposu ure to parameteers beyond the specified maximum ratings orr operation outtside the specified range. SEMTECH PRODUCTS AR RE NOT DESIGN NED, INTENDED D, AUTHORIZED D OR WARRAN NTED TO BE SU UITABLE FOR USE IN LIFE‐ SUPPORT APPLICATIONS,, DEVICES OR SSYSTEMS OR OTTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRO ODUCTS IN SUCH APP PLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELYY AT THE CUSTOMER’S OWN RISK. Should a a customer purchase o or use Semtech h products for any such unautthorized appliccation, the custtomer shall indemnify and hold Semtech and its offficers, employees, subsidiariess, affiliates, and d distributors harmless againsst all claims, cossts damages an nd attorney fees which h could arise. Contact Information Semttech Corporration Wirele ess Sensing and Timingg Products D Division 20 00 Flynn Ro oad, Camariillo, CA 93012 Phon ne: (805) 49 98‐2111 Faxx: (805) 498‐3804 E‐m mail: suppo ort_rf_na@ @semtech.co om In nternet: htttp://www.ssemtech.co om Revision 2 – June 2015 ©2015 SSemtech Corrporation Page 16 of 1 P 6 www.semttech.com