24AA025E48 DATA SHEET (03/18/2015) DOWNLOAD

24AA02E48/24AA025E48/
24AA02E64/24AA025E64
2K I2C™ Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity
Device Selection Table
VCC
Range
Max. Clock
Frequency
Temp. Ranges
Cascadable
Page Size
Node
Address
1.7-5.5V
400 kHz(1)
I, E
No
8-Byte
EUI-48™
24AA025E48
1.7-5.5V
400 kHz
(1)
I, E
Yes
16-Byte
EUI-48™
24AA02E64
1.7-5.5V
400 kHz(1)
I, E
No
8-Byte
EUI-64™
1.7-5.5V
(1)
I, E
Yes
16-Byte
EUI-64™
Part Number
24AA02E48
24AA025E64
Note 1:
400 kHz
100 kHz for VCC <2.5V
Features
Description
• Pre-programmed Globally Unique, 48-bit or 64-bit
Node Address
• Compatible with EUI-48™ and EUI-64™
• Single Supply with Operation Down to 1.7V
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current: 1 µA, max (I-temp)
5 µA, max (E-temp)
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• Page Write Buffer:
- 8-byte page (24AA02E48/24AA02E64)
- 16-byte page (24AA025E48/24AA025E64)
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 Years
• Factory Programming Available
• Available Packages:
- 8-lead SOIC and 5-lead SOT-23
(24AA02E48/24AA02E64)
- 8-lead SOIC and 6-lead SOT-23
(24AA025E48/24AA025E64)
• RoHS Compliant
• Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
The
Microchip
Technology
Inc.
24AA02E48/
24AA025E48/24AA02E64/24AA025E64
(24AA02XEXX*) is a 2 Kbit Electrically Erasable PROM.
The device is organized as two blocks of 128 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.7V, with maximum standby
currents of only 1 µA for I-Temp and 5 µA for E-Temp, as
well as a maximum active current of 1 mA. The
24AA02XEXX also has a page write capability for up to
eight bytes of data (16 bytes on the 24AA025E48/
24AA025E64). The 24AA02XEXX is available in the
standard 8-pin SOIC, 5-lead SOT-23, and 6-lead SOT-23
packages.
Packages (24AA02E48/24AA02E64)
SOT-23
SCL
1
Vss
2
SDA
3
SOIC
NC
5
4
Vcc
NC
1
8
VCC
NC
2
7
NC
NC
3
6
SCL
VSS
4
5
SDA
Packages (24AA025E48/24AA025E64)
SOT-23
SOIC
SCL
1
6
VCC
VSS
2
5
A0
SDA
3
4
A1
A0
1
8
VCC
A1
2
7
NC
A2
3
6
SCL
VSS
4
5
SDA
*24AA02XEXX is used in this document as a generic
part number for the 24AA02E48/24AA025E48/
24AA02E64/24AA025E64 devices.
 2008-2014 Microchip Technology Inc.
DS20002124F-page 1
24AA02E48/24AA025E48/24AA02E64/24AA025E64
Block Diagram
A0(1) A1(1) A2(1)
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
SDA SCL
VCC
VSS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
Note 1: Pins A0, A1 and A2 are not available on
the 24AA02E48/24AA02E64.
DS20002124F-page 2
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins  4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Industrial (I):
Automotive (E):
TA = -40°C to +85°C, VCC = +1.7V to +5.5V
TA = -40°C to +125°C, VCC = +1.7V to +5.5V
Min.
Typ.
Max.
Units
—
—
—
Conditions
—
—
SCL, SDA, A0, A1, and
A2 pins
—
D1
VIH
High-level Input Voltage
0.7 VCC
—
—
V
—
D2
VIL
Low-level Input Voltage
—
—
0.3 VCC
V
—
D3
VHYS
Hysteresis of Schmitt
Trigger inputs
0.05 VCC
—
—
V
(Note)
D4
VOL
Low-level Output Voltage
—
—
0.40
V
IOL = 3.0 mA, VCC = 2.5V
D5
ILI
Input Leakage Current
—
—
±1
µA
VIN = VSS or VCC
D6
ILO
Output Leakage Current
—
—
±1
µA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin Capacitance
(all inputs/outputs)
—
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D8
ICC write Operating Current
—
0.1
3
mA
VCC = 5.5V, SCL =
400 kHz
D9
ICC read
—
0.05
1
mA
—
D10
ICCS
—
0.01
1
µA
Industrial (I)
SDA = SCL = VCC
—
0.01
5
µA
Automotive (E)
SDA = SCL = VCC
Note:
Standby Current
This parameter is periodically sampled and not 100% tested.
 2008-2014 Microchip Technology Inc.
DS20002124F-page 3
24AA02E48/24AA025E48/24AA02E64/24AA025E64
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
No.
Sym.
Characteristic
Industrial (I):
Automotive (E):
TA = -40°C to +85°C, VCC = +1.7V to +5.5V
TA = -40°C to +125°C, VCC = +1.7V to +5.5V
Min.
Typ.
Max.
Units
Conditions
1
FCLK
Clock frequency
—
—
—
—
400
100
kHz
2.5V  VCC  5.5V
1.7V  VCC  2.5V
2
THIGH
Clock high time
600
4000
—
—
—
—
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
3
TLOW
Clock low time
1300
4700
—
—
—
—
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
4
TR
SDA and SCL rise time
(Note 1)
—
—
—
—
300
1000
ns
2.5V  VCC  5.5V (Note 1)
1.7V  VCC  2.5V (Note 1)
5
TF
SDA and SCL fall time
—
—
—
300
ns
(Note 1)
6
THD:STA
Start condition hold time
600
4000
—
—
—
—
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
7
TSU:STA
Start condition setup
time
600
4700
—
—
—
—
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
8
THD:DAT
Data input hold time
0
—
—
—
ns
(Note 2)
9
TSU:DAT
Data input setup time
100
250
—
—
—
—
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
10
TSU:STO
Stop condition setup
time
600
4000
—
—
—
—
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
11
TAA
Output valid from clock
(Note 2)
—
—
—
—
900
3500
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
12
TBUF
Bus free time: Time the
bus must be free before
a new transmission can
start
1300
4700
—
—
—
—
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
13
TOF
Output fall time from VIH
minimum to VIL
maximum
—
—
—
—
250
250
ns
2.5V  VCC  5.5V
1.7V  VCC  2.5V
14
TSP
Input filter spike
suppression
(SDA and SCL pins)
—
—
50
ns
(Notes 1 and 3)
15
TWC
Write cycle time (byte or
page)
—
—
5
ms
—
16
—
Endurance
1M
—
—
Note 1:
2:
3:
4:
cycles 25°C (Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
DS20002124F-page 4
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
FIGURE 1-1:
BUS TIMING DATA
5
4
2
3
SCL
7
SDA
IN
8
10
9
6
14
12
11
SDA
OUT
FIGURE 1-2:
BUS TIMING START/STOP
D3
SCL
6
7
10
SDA
Start
 2008-2014 Microchip Technology Inc.
Stop
DS20002124F-page 5
24AA02E48/24AA025E48/24AA02E64/24AA025E64
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
SOIC
5-Pin SOT-23
6-Pin SOT-23
A0
1
—
5
Chip Address Input(1)
A1
2
—
4
Chip Address Input(1)
A2
3
—
—
Chip Address Input(1)
VSS
4
2
2
Ground
Description
SDA
5
3
3
Serial Address/Data I/O
SCL
6
1
1
Serial Clock
NC
7
5
—
Not Connected
VCC
8
4
6
+1.7V to 5.5V Power Supply
Note 1:
2.1
PIN FUNCTION TABLE
Chip address inputs A0, A1 and A2 are not connected on the 24AA02E48/24AA02E64.
Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. Since it is an opendrain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.2
Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
2.3
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 pins are not used by the
24AA02E48/24AA02E64. They may be left floating or
tied to either VSS or VCC.
For the 24AA025E48/24AA025E64, the levels on the
A0, A1 and A2 inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true. For the 6-lead SOT-23
package, pin A2 is not connected and its corresponding
bit in the slave address should always be set to ‘0’.
Up to eight 24AA025E48/24AA025E64 devices (four
for the SOT-23 package) may be connected to the
same bus by using different Chip Select bit combinations. These inputs must be connected to either VSS or
VCC.
DS20002124F-page 6
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
3.0
FUNCTIONAL DESCRIPTION
The 24AA02XEXX supports a bidirectional, 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, while a
device receiving data is defined as a receiver. The bus
has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access
and generates the Start and Stop conditions, while the
24AA02XEXX works as slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 4-1:
(A)
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
4.4
The 24AA02XEXX does not generate any
Acknowledge bits
if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable-low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24AA02XEXX) will leave the
data line high to enable the master to generate the Stop
condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
 2008-2014 Microchip Technology Inc.
Data
Allowed
to Change
Stop
Condition
DS20002124F-page 7
24AA02E48/24AA025E48/24AA02E64/24AA025E64
5.0
DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a four-bit control code. For the
24AA02XEXX, this is set as ‘1010’ binary for read and
write operations. For the 24AA02E48/24AA02E64 the
next three bits of the control byte are “don’t cares”.
For the 24AA025E48/24AA025E64, the next three bits
of the control byte are the Chip Select bits (A2, A1, A0).
The Chip Select bits allow the use of up to eight
24AA025E48/24AA025E64 devices on the same bus
and are used to select which device is accessed. The
Chip Select bits in the control byte must correspond to
the logic levels on the corresponding A2, A1 and A0
pins for the device to respond. These bits are in effect
the three Most Significant bits of the word address.
For the 6-pin SOT-23 package, the A2 address pin is
not available. During device addressing, the A2 Chip
Select bit should be set to ‘0’.
The last bit of the control byte defines the operation to
be performed. When set to ‘1’, a read operation is
selected. When set to ‘0’, a write operation is selected.
Following the Start condition, the 24AA02XEXX monitors the SDA bus, checking the device type identifier
being transmitted and, upon a ‘1010’ code, the slave
device outputs an Acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the
24AA02XEXX will select a read or write operation.
Operation
Control
Code
Chip Select
R/W
Read
1010
Chip Address
1
Write
1010
Chip Address
0
FIGURE 5-2:
CONTROL BYTE
ALLOCATION
Read/Write Bit
Chip
Select
Bits
Control Code
S
1
0
1
0
A2* A1* A0* R/W ACK
Slave Address
Acknowledge Bit
Start Bit
Note:
5.1
* Bits A0, A1 and A2 are “don’t cares” for
the 24AA02E48/24AA02E64.
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24AA025E48/24AA025E64
devices on the same bus. In this case, software can
use A0 of the control byte as address bit A8, A1 as
address bit A9 and A2 as address bit A10. It is not possible to sequentially read across device boundaries.
For the SOT-23 package, up to four 24AA025E48/
24AA025E64 devices can be added for up to 8K bits of
address space. In this case, software can us A0 of the
control byte as address bit A8, and A1 as address bit
A9. It is not possible to sequentially read across device
boundaries.
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
0
1
Control
Code
Note:
DS20002124F-page 8
0 A2* A1* A0* R/W
Address Low Byte
A
7
•
•
•
•
•
•
A
0
Chip
Select
bits
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
6.0
WRITE OPERATION
6.1
Byte Write
24AA025E64) of the word address remain constant. If
the master should transmit more than eight words (16
for the 24AA025E48/24AA025E64) prior to generating
the Stop condition, the address counter will roll over and
the previously received data will be overwritten. As with
the byte write operation, once the Stop condition is
received an internal write cycle will begin (Figure 6-2).
Following the Start condition from the master, the
device code (4 bits), the chip address (3 bits) and the
R/W bit which is a logic-low, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow once it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be
written into the Address Pointer of the 24AA02XEXX.
After receiving another Acknowledge signal from the
24AA02XEXX, the master device will transmit the data
word to be written into the addressed memory location.
The 24AA02XEXX acknowledges again and the
master generates a Stop condition. This initiates the
internal write cycle and, during this time, the
24AA02XEXX will not generate Acknowledge signals
(Figure 6-1).
6.2
Note:
Page Write
The write-control byte, word address and the first data
byte are transmitted to the 24AA02XEXX in the same
way as in a byte write. However, instead of generating
a Stop condition, the master transmits up to eight data
bytes to the 24AA02XEXX, which are temporarily
stored in the on-chip page buffer and will be written into
memory once the master has transmitted a Stop condition. Upon receipt of each word, the three lower-order
Address Pointer bits (four for the 24AA025E48/
24AA025E64) are internally incremented by ‘1’. The
higher-order five bits (four for the 24AA025E48/
FIGURE 6-1:
Bus Activity
Master
SDA Line
S
Control
Byte
1
0
1
The remaining half of the array (00h-7Fh) can be
written to and read from normally.
Word
Address
Chip
Select
Bits
S
T
O
P
Data
P
A
C
K
A
C
K
A
C
K
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
FIGURE 6-2:
PAGE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1 0 1 0 A2 A1 A0 0
Note:
The upper half of the array (80h-FFh) is permanently
write-protected. Write operations to this address range
are inhibited. Read operations are not affected.
0 A2* A1*A0* 0
Bus Activity
Bus Activity
Write Protection
BYTE WRITE
S
T
A
R
T
Note:
6.3
Page write operations are limited to writing bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Control
Byte
Word
Address (n)
Data (n)
S
T
O
P
Data (n + 7)
Data (n + 1)
* * *
P
A
C
K
A
C
K
Chip
Select
Bits
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
 2008-2014 Microchip Technology Inc.
A
C
K
A
C
K
A
C
K
DS20002124F-page 9
24AA02E48/24AA025E48/24AA02E64/24AA025E64
7.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally-timed write cycle and ACK polling
can then be initiated immediately. This involves the
master sending a Start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next read or write
command. See Figure 7-1 for a flow diagram of this
operation.
FIGURE 7-1:
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
DS20002124F-page 10
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
8.0
READ OPERATION
8.3
Sequential Read
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a
random read, except that once the 24AA02XEXX
transmits the first data byte, the master issues an
acknowledge as opposed to a Stop condition in a random read. This directs the 24AA02XEXX to transmit the
next sequentially-addressed 8-bit word (Figure 8-3).
8.1
To provide sequential reads, the 24AA02XEXX
contains an internal Address Pointer that is
incremented by one upon completion of each operation. This Address Pointer allows the entire memory
contents to be serially read during one operation.
Current Address Read
The 24AA02XEXX contains an address counter that
maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous
access (either a read or write operation) was to address
n, the next current address read operation would
access data from address n + 1. Upon receipt of the
slave address with R/W bit set to ‘1’, the 24AA02XEXX
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition, and the 24AA02XEXX
discontinues transmission (Figure 8-1).
8.2
8.4
Noise Protection
The 24AA02XEXX employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24AA02XEXX as part of a write
operation. Once the word address is sent, the master
generates a Start condition following the acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a ‘1’.
The 24AA02XEXX will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, but does generate a Stop
condition, and the 24AA02XEXX will discontinue
transmission (Figure 8-2).
FIGURE 8-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S 1
Bus Activity
Note:
Control
Byte
0
1
S
T
O
P
Data (n)
0 A2* A1*A0* 1
Chip
Select
Bits
P
A
C
K
N
o
A
C
K
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
 2008-2014 Microchip Technology Inc.
DS20002124F-page 11
24AA02E48/24AA025E48/24AA02E64/24AA025E64
FIGURE 8-2:
RANDOM READ
Bus Activity
Master
S
T
A
R
T
S
T
A
R
T
Word
Address (n)
Control
Byte
* * *
Chip
Select
Bits
Bus Activity
Note:
FIGURE 8-3:
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Data (n)
* **
S 1 0 1 0 A2A1A0 0
SDA Line
Control
Byte
S 1 0 1 0 A2A1A0 1
A
C
K
A
C
K
Chip
Select
Bits
P
A
C
K
N
o
A
C
K
* Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48/24AA02E64.
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + x)
P
1
A
C
K
A
C
K
A
C
K
A
C
K
N
o
A
C
K
DS20002124F-page 12
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
9.0
PRE-PROGRAMMED EUI-48™
OR EUI-64™ NODE ADDRESS
The 24AA02XEXX is programmed at the factory with a
globally unique node address stored in the upper half
of the array and permanently write-protected. The
remaining 1,024 bits are available for application use.
FIGURE 9-1:
MEMORY ORGANIZATION
9.1.1
EUI-64™ SUPPORT USING THE
24AAXXXE48
The pre-programmed EUI-48 node address of the
24AAXXXE48 can easily be encapsulated at the application level to form a globally unique, 64-bit node
address for systems utilizing the EUI-64 standard. This
is done by adding 0xFFFE between the OUI and the
Extension Identifier, as shown below.
Note:
00h
Standard
EEPROM
80h
Write-Protected
Node Address Block
As an alternative, the 24AAXXXE64
features an EUI-64 node address that can
be used in EUI-64 applications directly
without the need for encapsulation,
thereby simplifying system software. See
Section 9.2 “EUI-64™ Node Address
(24AAXXXE64)” for details.
FFh
9.1
EUI-48™ Node Address
(24AAXXXE48)
The 6-byte EUI-48™ node address value of the
24AAXXXE48 is stored in array locations 0xFA through
0xFF, as shown in Figure 9-2. The first three bytes are
the Organizationally Unique Identifier (OUI) assigned
to Microchip by the IEEE Registration Authority. The
remaining three bytes are the Extension Identifier, and
are generated by Microchip to ensure a globally
unique, 48-bit value.
Note:
Currently,
Microchip’s
OUIs
are
0x0004A3, 0x001EC0 and 0xD88039,
though this will change as addresses are
exhausted.
FIGURE 9-2:
Description
EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (24AAXXXE48)
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
FAh
04h
A3h
24-bit Extension
Identifier
12h
34h
56h
FFh
Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56
Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56
 2008-2014 Microchip Technology Inc.
DS20002124F-page 13
24AA02E48/24AA025E48/24AA02E64/24AA025E64
EUI-64™ Node Address
(24AAXXXE64)
9.2
The remaining five bytes are the Extension Identifier,
and are generated by Microchip to ensure a globally
unique, 64-bit value.
The 8-byte EUI-64™ node address value of the
24AAXXXE64 is stored in array locations 0xF8 through
0xFF, as shown in Figure 9-3. The first three bytes are
the Organizationally Unique Identifier (OUI) assigned
to Microchip by the IEEE Registration Authority.
Note:
Note:
Currently,
Microchip’s
OUIs
are
0x0004A3, 0x001EC0 and 0xD88039,
though this will change as addresses are
exhausted.
FIGURE 9-3:
Description
In conformance with IEEE guidelines,
Microchip will not use the values 0xFFFE
and 0xFFFF for the first two bytes of the
EUI-64 Extension Identifier. These two
values are specifically reserved to allow
applications to encapsulate EUI-48
addresses into EUI-64 addresses.
EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (24AAXXXE64)
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
F8h
04h
A3h
40-bit Extension
Identifier
12h
34h
56h
78h
90h
FFh
Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90
DS20002124F-page 14
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
8-Lead SOIC (3.90 mm)
Example:
24A2E48I
SN e3 1438
13F
XXXXXXXT
XXXXYYWW
NNN
5-Lead SOT-23 (1-Line Marking)
Example:
XXNN
2K3F
6-Lead SOT-23 (1-Line Marking)
Example:
XXNN
HS3F
5-Lead SOT-23 (2-Line Marking)
Example:
XXXXY
WWNNN
AAAB3
271L7
6-Lead SOT-23 (2-Line Marking)
Example:
XXXXY
WWNNN
AAAC3
271L7
1st Line Marking Code
Part Number
SOT-23
SOIC
I Temp.
E Temp.
I Temp.
E Temp.
24AA02E48
2KNN(1, 2)
AABLY(3)
24A2E48I
24A2E48E
24AA025E48
HSNN(1, 2)
AABMY(3)
4A25E48I
4A25E48E
24AA02E64
AAABY(3)
AABNY(3)
24A2E64I
24A2E64E
24AA025E64
AAACY(3)
AABPY(3)
4A25E64I
4A25E64E
Note 1: NN = Alphanumeric traceability code
2: These parts use the 1-line SOT-23 marking format
3: These parts use the 2-line SOT-23 marking format
 2008-2014 Microchip Technology Inc.
DS20002124F-page 15
24AA02E48/24AA025E48/24AA02E64/24AA025E64
Legend: XX...X
T
Y
YY
WW
NNN
e3
Note:
Note:
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
For very small packages with no room for the JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
DS20002124F-page 16
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2008-2014 Microchip Technology Inc.
DS20002124F-page 17
24AA02E48/24AA025E48/24AA02E64/24AA025E64
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002124F-page 18
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
!"#$%
&
!
"#$%&"'""
($)
%
*++&&&!
!+$
 2008-2014 Microchip Technology Inc.
DS20002124F-page 19
24AA02E48/24AA025E48/24AA02E64/24AA025E64
'
(("()%
&
!
"#$%&"'""
($)
%
*++&&&!
!+$
b
N
E
E1
3
2
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e
e1
D
A2
A
c
φ
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L
L1
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!"
@!"
A#!H
)("
@@66
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AE
G
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;
@%(
;<=
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3
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%%($$""
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))
3
K
3;
E>L%
6
K
1
%%($L%
63
31
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3
E>@
K
13
3<=
3;
@
@
3
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7%3!!"%
!"
%
683;
<=* <"!"
7>#"
&&
#
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& =3<
DS20002124F-page 20
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2008-2014 Microchip Technology Inc.
DS20002124F-page 21
24AA02E48/24AA025E48/24AA02E64/24AA025E64
*
(("()%
&
!
"#$%&"'""
($)
%
*++&&&!
!+$
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
A
A2
c
φ
L
A1
L1
?"
!"
@!"
A#!H
)("
@@66
A
A
AE
G
N
(
;<=
E#"%@%(
3
3<=
E>J
K
%%($$""
K
3;
31
%
))
3
K
3;
E>L%
6
K
1
%%($L%
63
31
K
3
E>@
K
13
@
@
3
K
N
@3
1;
K
O
K
1O
@%$""
K
N
@%L%
H
K
;3
&
3 !"
"%63%
#%!
%)"
#"
"
%)"
#"
""
7%3!!"%
!"
%
683;
<=* <"!"
7>#"
&&
#
"
& =<
DS20002124F-page 22
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2008-2014 Microchip Technology Inc.
DS20002124F-page 23
24AA02E48/24AA025E48/24AA02E64/24AA025E64
APPENDIX A:
REVISION HISTORY
Revision A (12/08)
Original release of this document.
Revision B (01/09)
Removed preliminary status.
Revision C (03/10)
Added new sections 2.0 through 9.0.
Revision D (05/10)
Added 24AA025E48 part number and 6-lead SOT-23
package.
Revision E (04/13)
Added 24AA02E64 and 24AA025E64 part numbers.
Revision F (10/14)
Added E-temp option to part numbers.
DS20002124F-page 24
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
 2008-2014 Microchip Technology Inc.
DS20002124F-page 25
24AA02E48/24AA025E48/24AA02E64/24AA025E64
NOTES:
DS20002124F-page 26
 2008-2014 Microchip Technology Inc.
24AA02E48/24AA025E48/24AA02E64/24AA025E64
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
X
/XX
Temperature Package
Range
24AA02E48
=
24AA02E48T =
24AA025E48 =
24AA025E48T =
24AA02E64
=
24AA02E64T =
24AA025E64 =
24AA025E64T =
1.7V, 2 Kbit I2C™ Serial EEPROM
with EUI-48™ Node Identity
1.7V, 2 Kbit I2C Serial EEPROM
with EUI-48™ Node Identity (Tape
and Reel)
1.7V, 2 Kbit I2C Serial EEPROM with
EUI-48™ Node Identity and Address
Pins
1.7V, 2 Kbit I2C Serial EEPROM with
EUI-48™ Node Identity and Address
Pins (Tape and Reel)
1.7V, 2 Kbit I2C™ Serial EEPROM
with EUI-64™ Node Identity
1.7V, 2 Kbit I2C Serial EEPROM
with EUI-64™ Node Identity (Tape
and Reel)
1.7V, 2 Kbit I2C Serial EEPROM with
EUI-64™ Node Identity and Address
Pins
1.7V, 2 Kbit I2C Serial EEPROM with
EUI-64™ Node Identity and Address
Pins (Tape and Reel)
Temperature I
Range:
E
=
=
-40°C to +85°C
-40°C to +125°C
Package:
=
=
Plastic SOIC (3.90 mm body), 8-lead
SOT-23 (Tape and Reel only)
SN
OT
Examples:
a)
b)
c)
24AA02E48-I/SN: 2 Kbit, 8-byte
Serial EEPROM with EUI-48
identity, Industrial Temperature,
SOIC package
24AA02E48T-I/OT: 2 Kbit, 8-byte
Serial EEPROM with EUI-48
identity, Industrial Temperature,
SOT-23 package, tape and reel
24AA025E48-I/SN: 2 Kbit, 16-byte
Serial EEPROM with EUI-48
identity, Industrial Temperature,
page,
node
1.7V,
page,
node
1.7V,
page,
node
1.7V,
Cascadable, SOIC package
d)
24AA02E64-I/SN: 2 Kbit, 8-byte page,
Serial EEPROM with EUI-64 node
identity, Industrial Temperature, 1.7V,
SOIC package
e)
24AA02E64T-I/OT: 2 Kbit, 8-byte
Serial EEPROM with EUI-64
identity, Industrial Temperature,
SOT-23 package, tape and reel
24AA025E64-I/SN: 2 Kbit, 16-byte
Serial EEPROM with EUI-64
identity, Industrial Temperature,
f)
page,
node
1.7V,
page,
node
1.7V,
Cascadable, SOIC package
g)
24AA025E48T-E/SN: 2 Kbit, 16-byte page,
Serial EEPROM with EUI-48 node
identity, Automotive Temperature, 1.7V,
Cascadable, SOIC package, tape and reel
h)
24AA02E48-E/SN: 2 Kbit, 8-byte page,
Serial EEPROM with EUI-48 node
identity, Automotive Temperature, 1.7V,
SOIC package
i)
24AA025E48T-E/OT: 2 Kbit, 16-byte page,
Serial EEPROM with EUI-48 node
identity, Automotive Temperature, 1.7V,
Cascadable, SOT-23 package, tape and
reel
 2008-2013 Microchip Technology Inc.
DS20002124F-page27
24AA02E48/24AA025E48/24AA02E64/24AA025E64
NOTES:
DS20002124F-page 28
 2008-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2008-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-736-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2008-2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20002124F-page 29
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
DS20002124F-page 30
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Germany - Pforzheim
Tel: 49-7231-424750
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Italy - Venice
Tel: 39-049-7625286
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Poland - Warsaw
Tel: 48-22-3325737
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
 2008-2014 Microchip Technology Inc.
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