25AA02E64 DATA SHEET (02/03/2015) DOWNLOAD

25AA02E48/25AA02E64
2K SPI Bus Serial EEPROMs with EUI-48™ or EUI-64™ Node Identity
Device Selection Table
Part Number
VCC Range
Page Size
Temp. Ranges
Packages
Node Address
25AA02E48
1.8-5.5V
16 Bytes
I
SN, OT
EUI-48™
25AA02E64
1.8-5.5V
16 Bytes
I
SN, OT
EUI-64™
Features
Description
• Pre-Programmed Globally Unique, 48-Bit or
64-Bit Node Address
• Compatible with EUI-48™ and EUI-64™
• 10 MHz Maximum Clock Frequency
• Low-Power CMOS Technology:
- Maximum Write Current: 5 mA at 5.5V
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 1 A at 2.5V
• 256 x 8-Bit Organization
• Write Page mode (up to 16 bytes)
• Sequential Read
• Self-Timed Erase and Write Cycles
(5 ms maximum)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-in Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: >200 years
- ESD protection: >4000V
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
The
Microchip
Technology
Inc.
25AA02E48/25AA02E64 (25AA02EXX*) is a 2 Kbit
Serial Electrically Erasable Programmable Read-Only
Memory (EEPROM). The memory is accessed via a
simple Serial Peripheral Interface (SPI) compatible
serial bus. The bus signals required are a clock input
(SCK) plus separate data in (SI) and data out (SO)
lines. Access to the device is controlled through a Chip
Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
The 25AA02EXX is available in the standard 8-lead
SOIC and 6-lead SOT-23 packages.
Pin Function Table
Name
Function
CS
Chip Select Input
SO
Serial Data Output
WP
Write-Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
• Pb-Free and RoHS Compliant
HOLD
Hold Input
Package Types (not to scale)
VCC
Supply Voltage
SOT-23
SOIC
(OT)
(SN)
1
6
VSS
2
5
CS
SI
3
4
SO
SCK
VDD
CS
SO
1
2
8
7
VCC
HOLD
WP
3
6
SCK
VSS
4
5
SI
*25AA02EXX is used in this document as a generic part number for the 25AA02E48/25AA02E64 devices.
 2008-2015 Microchip Technology Inc.
DS20002123E-page 1
25AA02E48/25AA02E64
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature .................................................................................................................................-65°C to 150°C
Ambient temperature under bias .................................................................................................................-40°C to 85°C
ESD protection on all pins ..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Industrial (I):
TA = -40°C to +85°C
Min.
Max.
Units
VCC = 1.8V to 5.5V
Test Conditions
D001
VIH1
High-level Input Voltage
0.7 VCC
VCC +1
V
D002
VIL1
Low-level Input Voltage
-0.3
0.3 VCC
V
VCC2.7V (Note 1)
D003
VIL2
Low-level Input Voltage
-0.3
0.2 VCC
V
VCC < 2.7V (Note 1)
D004
VOL
Low-level Output Voltage
—
0.4
V
IOL = 2.1 mA
D005
VOL
Low-level Output Voltage
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
D006
VOH
High-level Output Voltage
VCC -0.5
—
V
IOH = -400 A
D007
ILI
Input Leakage Current
—
±1
A
CS = VCC, VIN = VSS or VCC
D008
ILO
Output Leakage Current
—
±1
A
CS = VCC, VOUT = VSS or VCC
D009
CINT
Internal Capacitance
(all inputs and outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note 1)
—
5
mA
VCC = 5.5V; FCLK = 10.0 MHz,
SO = Open
—
2.5
mA
VCC = 2.5V; FCLK = 5.0 MHz,
SO = Open
—
5
mA
VCC = 5.5V
—
3
mA
VCC = 2.5V
—
1
A
CS = VCC = 2.5V, Inputs tied to
VCC or VSS, TA = +85°C
D010
D011
D012
ICCREAD Operating Current
ICCWRITE Operating Current
ICCS
Standby Current
Note 1: This parameter is periodically sampled and not 100% tested.
DS20002123E-page 2
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
Symbol
No.
1
FCLK
2
TCSS
3
TCSH
Characteristic
Clock Frequency
CS Setup Time
CS Hold Time
Industrial (I):
TA = -40°C to +85°C
VCC = 1.8V to 5.5V
Min.
Max.
Units
Test Conditions
—
10
MHz
4.5V VCC  5.5V
—
5
MHz
2.5V VCC  4.5V
—
3
MHz
1.8V VCC  2.5V
50
—
ns
4.5V VCC  5.5V
100
—
ns
2.5V VCC  4.5V
150
—
ns
1.8V VCC  2.5V
100
—
ns
4.5V VCC  5.5V
200
—
ns
2.5V VCC  4.5V
250
—
ns
1.8V VCC  2.5V
4
TCSD
CS Disable Time
50
—
ns
—
5
Tsu
Data Setup Time
10
—
ns
4.5V VCC  5.5V
20
—
ns
2.5V VCC  4.5V
30
—
ns
1.8V VCC  2.5V
20
—
ns
4.5V VCC  5.5V
40
—
ns
2.5V VCC  4.5V
50
—
ns
1.8V VCC  2.5V
6
THD
Data Hold Time
7
TR
CLK Rise Time
—
100
ns
(Note 1)
8
TF
CLK Fall Time
—
100
ns
(Note 1)
9
THI
Clock High Time
50
—
ns
4.5V VCC  5.5V
100
—
ns
2.5V VCC  4.5V
150
—
ns
1.8V VCC  2.5V
50
—
ns
4.5V VCC  5.5V
100
—
ns
2.5V VCC  4.5V
150
—
ns
1.8V VCC  2.5V
10
TLO
Clock Low Time
11
TCLD
Clock Delay Time
50
—
ns
—
12
TCLE
Clock Enable Time
50
—
ns
—
13
TV
Output Valid from Clock
Low
—
50
ns
4.5V VCC  5.5V
—
100
ns
2.5V VCC  4.5V
—
160
ns
1.8V VCC  2.5V
0
—
ns
(Note 1)
14
THO
Output Hold Time
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
 2008-2015 Microchip Technology Inc.
DS20002123E-page 3
25AA02E48/25AA02E64
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
AC CHARACTERISTICS
Param.
Symbol
No.
15
TDIS
16
THS
17
THH
18
THZ
19
THV
20
TWC
21
—
Industrial (I):
Characteristic
TA = -40°C to +85°C
VCC = 1.8V to 5.5V
Min.
Max.
Units
—
40
ns
4.5V VCC  5.5V (Note 1)
—
80
ns
2.5V VCC  4.5V (Note 1)
—
160
ns
1.8V VCC  2.5V (Note 1)
20
—
ns
4.5V VCC  5.5V
40
—
ns
2.5V VCC  4.5V
80
—
ns
1.8V VCC  2.5V
20
—
ns
4.5V VCC  5.5V
40
—
ns
2.5V VCC  4.5V
80
—
ns
1.8V VCC  2.5V
30
—
ns
4.5V VCC  5.5V (Note 1)
60
—
ns
2.5V VCC  4.5V (Note 1)
160
—
ns
1.8V VCC  2.5V (Note 1)
30
—
ns
4.5V VCC  5.5V
60
—
ns
2.5V VCC  4.5V
160
—
ns
1.8V VCC  2.5V
Internal Write Cycle Time
(byte or page)
—
5
ms
(Note 3)
Endurance
1M
—
Output Disable Time
HOLD Setup Time
HOLD Hold Time
HOLD Low to Output
High-Z
HOLD High to Output
Valid
Test Conditions
E/W 25°C, VCC = 5.5V (Note 2)
Cycles
Note 1: This parameter is periodically sampled and not 100% tested.
2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform
VLO = 0.2V
—
VHI = VCC - 0.2V
(Note 1)
VHI = 4.0V
(Note 2)
CL = 100 pF
—
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1: For VCC  4.0V
2: For VCC  4.0V
DS20002123E-page 4
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
FIGURE 1-1:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
n
19
High-Impedance
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
7
Mode 1,1
12
11
8
3
SCK Mode 0,0
5
SI
6
MSB in
LSB in
High-Impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
14
SO
MSB out
SI
 2008-2015 Microchip Technology Inc.
15
ISB out
Don’t Care
DS20002123E-page 5
25AA02E48/25AA02E64
2.0
FUNCTIONAL DESCRIPTION
2.1
Principles of Operation
The 25AA02EXX is a 256-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
software to match the SPI protocol.
The 25AA02EXX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25AA02EXX in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
2.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25AA02EXX
followed by an 8-bit address. See Figure 2-1 for more
details.
After the correct READ instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. Data stored in the memory
at the next address can be read sequentially by
continuing to provide clock pulses to the slave. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. When the highest address is reached
(FFh), the address counter rolls over to address 00h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin
(Figure 2-1).
2.3
Write Sequence
After setting the write enable latch, the user may
proceed by driving CS low, issuing a WRITE instruction,
followed by the remainder of the address, and then the
data to be written. Up to 16 bytes of data can be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. Additionally, a page address begins with
XXXX 0000 and ends with XXXX 1111. If the internal
address counter reaches XXXX 1111 and clock signals
continue to be applied to the chip, the address counter
will roll back to the first address of the page and
over-write any data that previously existed in those
locations.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is, therefore, necessary for
the application software to prevent page
write operations that would attempt to
cross a page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 2-2 and Figure 2-3 for more
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the write
is in progress, the STATUS register may be read to
check the status of the WIP, WEL, BP1 and BP0 bits
(Figure 2-6). Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the write cycle is completed, the write enable latch is
reset.
Prior to any attempt to write data to the 25AA02EXX,
the write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25AA02EXX. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
driven high, data will not be written to the array since
the write enable latch was not properly set.
DS20002123E-page 6
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
BLOCK DIAGRAM
STATUS
Register
HV Generator
Memory
Control
Logic
I/O Control
Logic
EEPROM
Array
X
Dec
Page Latches
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
TABLE 2-1:
INSTRUCTION SET
Instruction Name
Instruction Format
Description
READ
0000 x011
Read data from memory array beginning at selected address
WRITE
0000 x010
Write data to memory array beginning at selected address
WRDI
0000 x100
Reset the write enable latch (disable write operations)
WREN
0000 x110
Set the write enable latch (enable write operations)
RDSR
0000 x101
Read STATUS register
WRSR
0000 x001
Write STATUS register
x = don’t care
FIGURE 2-1:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High-Impedance
SO
 2008-2015 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS20002123E-page 7
25AA02E48/25AA02E64
FIGURE 2-2:
BYTE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Twc
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
Data Byte
0 A7 A6 A5 A4 A3 A2 A1 A0
1
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 2-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
0
0
0
0 1
Data Byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
6
DS20002123E-page 8
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n (16 max)
1
0
7
6
5
4
3
2
1
0
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
2.4
Write Enable (WREN) and Write
Disable (WRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
•
The 25AA02EXX contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 2-4:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
WP pin is brought low
WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
0
1
1
0
High-Impedance
SO
FIGURE 2-5:
WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
High-Impedance
SO
 2008-2015 Microchip Technology Inc.
DS20002123E-page 9
25AA02E48/25AA02E64
2.5
Read Status Register Instruction
(RDSR)
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 2-4 and Figure 2-5.
The Read Status Register instruction (RDSR) provides
access to the STATUS register. See Figure 2-6 for the
RDSR timing sequence. The STATUS register may be
read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 2-2:
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction, which
is shown in Figure 2-7. These bits are nonvolatile and
are described in more detail in Table 2-3.
STATUS REGISTER
7
6 5 4
3
2
1
–
– – – W/R W/R
R
X
X X X BP1 BP0 WEL
W/R = writable/readable. R = read-only.
0
R
WIP
The Write-In-Process (WIP) bit indicates whether the
25AA02EXX is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
FIGURE 2-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
1
0
1
Data from STATUS register
High-Impedance
SO
DS20002123E-page 10
7
6
5
4
3
2
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
2.6
TABLE 2-3:
Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows
the user to write to the nonvolatile bits in the STATUS
register, as shown in Table 2-2. See Figure 2-7 for the
WRSR timing sequence. Four levels of protection for
the array are selectable by writing to the appropriate
bits in the STATUS register. The user has the ability to
write-protect none, one, two, or all four of the
segments of the array as shown in Table 2-3.
FIGURE 2-7:
ARRAY PROTECTION
BP1
BP0
Array Addresses
Write-Protected
0
0
none
0
1
upper 1/4
(C0h-FFh)
1
0
upper 1/2
(80h-FFh)
1
1
all
(00h-FFh)
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
 2008-2015 Microchip Technology Inc.
DS20002123E-page 11
25AA02E48/25AA02E64
2.7
Data Protection
2.8
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
TABLE 2-4:
Power-On State
The 25AA02EXX powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
WRITE-PROTECT FUNCTIONALITY MATRIX
WP
(pin 3)
0 (low)
1 (high)
1 (high)
x = don’t care
DS20002123E-page 12
WEL
(SR bit 1)
Protected Blocks
Unprotected Blocks
STATUS Register
x
0
1
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Protected
Writable
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
3.0
PRE-PROGRAMMED EUI-48™
OR EUI-64™ NODE ADDRESS
The 25AA02EXX is programmed at the factory with a
globally unique node address stored in the upper 1/4 of
the array and write-protected through the STATUS
register. The remaining 1,536 bits are available for
application use.
FIGURE 3-1:
EUI-48™ Node Address
(25AA02E48)
3.2
The 6-byte EUI-48™ node address value of the
25AA02E48 is stored in array locations 0xFA through
0xFF, as shown in Figure 3-2. The first three bytes are
the Organizationally Unique Identifier (OUI) assigned
to Microchip by the IEEE Registration Authority. The
remaining three bytes are the Extension Identifier, and
are generated by Microchip to ensure a globally
unique, 48-bit value.
MEMORY ORGANIZATION
00h
Note:
Standard
EEPROM
Write-Protected
Node Address Block
3.1
C0h
3.2.1
FFh
6
X
—
5
X
—
4
X
—
3
BP1
0
2
BP0
1
1
WEL
—
Note:
0
WIP
—
This protects the upper 1/4 of the array (0xC0 to 0xFF)
from write operations. This array block can be utilized
for writing by clearing the BP bits with a Write Status
Register (WRSR) instruction. Note that if this is
performed, care must be taken to prevent overwriting
the node address value.
FIGURE 3-2:
EUI-64™ SUPPORT USING THE
25AA02E48
The pre-programmed EUI-48 node address of the
25AA02E48 can easily be encapsulated at the
application level to form a globally unique, 64-bit node
address for systems utilizing the EUI-64 standard. This
is done by adding 0xFFFE between the OUI and the
Extension Identifier, as shown below.
Factory-Programmed Write
Protection
In order to help guard against accidental corruption of
the node address, the BP1 and BP0 bits of the STATUS
register are programmed at the factory to ‘0’ and ‘1’,
respectively, as shown in the following table:
7
X
—
Currently,
Microchip’s
OUIs
are
0x0004A3, 0x001EC0 and 0xD88039,
though this will change as addresses are
exhausted.
As an alternative, the 25AA02E64
features an EUI-64 node address that can
be used in EUI-64 applications directly
without the need for encapsulation,
thereby simplifying system software. See
Section 3.3 “EUI-64™ Node Address
(25AA02E64)” for details.
EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (25AA02E48)
Description
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
FAh
04h
A3h
24-bit Extension
Identifier
12h
34h
56h
FFh
Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56
Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56
 2008-2015 Microchip Technology Inc.
DS20002123E-page 13
25AA02E48/25AA02E64
3.3
EUI-64™ Node Address
(25AA02E64)
The 8-byte EUI-64™ node address value of the
25AA02E64 is stored in array locations 0xF8 through
0xFF, as shown in Figure 3-3. The first three bytes are
the Organizationally Unique Identifier (OUI) assigned
to Microchip by the IEEE Registration Authority. The
remaining five bytes are the Extension Identifier, and
are generated by Microchip to ensure a globally
unique, 64-bit value.
FIGURE 3-3:
Description
Note:
Currently,
Microchip’s
OUIs
are
0x0004A3, 0x001EC0 and 0xD88039,
though this will change as addresses are
exhausted.
Note:
In conformance with IEEE guidelines,
Microchip will not use the values 0xFFFE
and 0xFFFF for the first two bytes of the
EUI-64 Extension Identifier. These two
values are specifically reserved to allow
applications to encapsulate EUI-48
addresses into EUI-64 addresses.
EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (25AA02E64)
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
F8h
04h
A3h
40-bit Extension
Identifier
12h
34h
56h
78h
90h
FFh
Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90
DS20002123E-page 14
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
4.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 4-1.
TABLE 4-1:
4.1
PIN FUNCTION TABLE
Name
SOIC
SOT-23
Function
CS
1
5
Chip Select Input
SO
2
4
Serial Data Output
WP
3
—
Write-Protect Pin
VSS
4
2
Ground
SI
5
3
Serial Data Input
SCK
6
1
Serial Clock Input
HOLD
7
—
Hold Input
VCC
8
6
Supply Voltage
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After
power-up, a low level on CS is required prior to any
sequence being initiated.
4.2
Serial Output (SO)
The SO pin is used to transfer data out of the
25AA02EXX. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
4.3
Write-Protect (WP)
The WP pin is a hardware write-protect input pin.
When it is low, all writes to the array or STATUS
register are disabled, but any other operations
function normally. When WP is high, all functions,
including nonvolatile writes, operate normally. At any
time when WP is low, the write enable Reset latch will
be reset and programming will be inhibited. However,
if a write cycle is already in progress, WP going low
will not change or disable the write cycle. See Table
2-4 for the Write-Protect Functionality Matrix.
4.4
4.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25AA02EXX. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
4.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25AA02EXX while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK
high-to-low transition. The 25AA02EXX must remain
selected during this sequence. The SI, SCK and SO
pins are in a high-impedance state during the time the
device is paused and transitions on these pins will be
ignored. To resume serial communication, HOLD must
be brought high while the SCK pin is low, otherwise
serial communication will not resume. Lowering the
HOLD line at any time will tri-state the SO line.
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
 2008-2015 Microchip Technology Inc.
DS20002123E-page 15
25AA02E48/25AA02E64
5.0
PACKAGING INFORMATION
5.1
Package Marking Information*
Example:
8-Lead SOIC
25A2E48I
SN e3 1503
1L7
XXXXXXXT
XXXXYYWW
NNN
6-Lead SOT-23 (25AA02E48)
Example:
XXNN
20L7
6-Lead SOT-23 (25AA02E64)
Example:
XXXXY
WWNNN
AAAA3
271L7
1st Line Marking Code
Part Number
SOIC
SOT-23
25AA02E48
25A2E48I
20NN
25AA02E64
25A2E64I
AAAAY
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free** JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code,
and traceability code.
** Please visit www.microchip.com/Pbfree for the latest information on Pb-free
conversion.
Note:
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it
will be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20002123E-page 16
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2008-2015 Microchip Technology Inc.
DS20002123E-page 17
25AA02E48/25AA02E64
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002123E-page 18
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
!"#$%
&
!
"#$%&"'""
($)
%
*++&&&!
!+$
 2008-2015 Microchip Technology Inc.
DS20002123E-page 19
25AA02E48/25AA02E64
'
(("()%
&
!
"#$%&"'""
($)
%
*++&&&!
!+$
b
4
N
E
E1
PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
A
A2
c
φ
L
A1
L1
>"
!"
?!"
@#!G
)("
??66
@
@
@A
E
H
(
;<
A#"%?%(
3
3;<
A=J
K
%%($$""
L
K
3
31
%
))
3
K
3
A=N%
6
K
1
%%($N%
63
31
K
3L
A=?
K
13
?
?
3
K
H
?3
1
K
L
O
K
1O
?%$""
L
K
H
?%N%
G
K
3
&
3 !"
"%63%
#%!
%)"
#"
"
%)"
#"
""
7%3!!"%
!"
%
683
;<* ;"!"
7=#"
&&
#
"
& <L;
DS20002123E-page 20
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2008-2015 Microchip Technology Inc.
DS20002123E-page 21
25AA02E48/25AA02E64
APPENDIX A:
REVISION HISTORY
Revision A (12/08)
• Original release of this document.
Revision B (04/10)
•
•
•
•
Removed Preliminary status.
Revised Section 2.0.
Add sentence to Section 3.0.
Add SOT-23 Land Pattern.
Revision C (12/2012)
• Revised Table 1-2, Parameter 21.
Revision D (4/2013)
• Added 25AA02E64 part number.
Revision E (02/2015)
• Updated Section 3.0.
• Updated Product Identification System.
DS20002123E-page 22
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
 2008-2015 Microchip Technology Inc.
DS20002123E-page 23
25AA02E48/25AA02E64
NOTES:
DS20002123E-page 24
 2008-2015 Microchip Technology Inc.
25AA02E48/25AA02E64
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
[X](1)
X
/XX
Device
Tape and Reel
Option
Temperature
Range
Package
Examples:
a)
b)
Device:
25AA02E48 =
2k-Bit, 1.8V, 16-Byte Page, SPI Serial EEPROM
with EUI-48™ Node Identity
c)
25AA02E64 =
2k-Bit, 1.8V, 16-Byte Page, SPI Serial EEPROM
with EUI-64™ Node Identity
d)
Tape and Reel
Option:
Blank
T
=
=
Blank = Standard packaging (tube or tray)
T=Tape and Reel(1)
e)
Temperature
Range:
I
=
-40C to+85C
f)
Package:
SN
OT
=
=
Plastic SOIC (3.90 mm body), 8-lead
SOT-23, 6-lead (Tape and Reel only)
25AA02E48-I/SN = 2k-bit, 16-byte page, 1.8V
Serial EEPROM with EUI-48 node identity,
Industrial temp., SOIC package
25AA02E48T-I/SN = 2k-bit, 16-byte page, 1.8V
Serial EEPROM with EUI-48 node identity,
Industrial temp., Tape & Reel, SOIC package
25AA02E48T-I/OT = 2k-bit, 16-byte page, 1.8V
Serial EEPROM with EUI-48 node identity,
Industrial temp., Tape & Reel, SOT-23 package
25AA02E64-I/SN = 2k-bit, 16-byte page, 1.8V
Serial EEPROM with EUI-64 node identity,
Industrial temp., SOIC package
25AA02E64T-I/SN = 2k-bit, 16-byte page, 1.8V
Serial EEPROM with EUI-64 node identity,
Industrial temp., Tape & Reel, SOIC package
25AA02E64T-I/OT = 2k-bit, 16-byte page, 1.8V
Serial EEPROM with EUI-64 node identity,
Industrial temp., Tape & Reel, SOT-23 package
Note 1: Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
 2008-2015 Microchip Technology Inc.
DS20002123E-page 25
25AA02E48/25AA02E64
NOTES:
DS20002123E-page 26
 2008-2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2008-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-026-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2008-2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20002123E-page 27
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Austin, TX
Tel: 512-257-3370
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Dongguan
Tel: 86-769-8702-9880
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Venice
Tel: 39-049-7625286
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
01/27/15
DS20002123E-page 28
 2008-2015 Microchip Technology Inc.
Similar pages