Precision, Low Cost, High Speed BiFET Dual Op Amp AD712 CONNECTION DIAGRAM Enhanced replacement for LF412 and TL082 AC performance Settles to ±0.01% in 1.0 μs 16 V/μs minimum slew rate (AD712J) 3 MHz minimum unity-gain bandwidth (AD712J) DC performance 200 V/mV minimum open-loop gain (AD712K) Surface mount available in tape and reel in accordance with the EIA-481A standard MIL-STD-883B parts available Single version available: AD711 Quad version: AD713 Available in PDIP, SOIC_N, and CERDIP packages AMPLIFIER NO. 1 AMPLIFIER NO. 2 OUTPUT 1 8 V+ INVERTING INPUT OUTPUT 2 7 NONINVERTING INPUT 3 INVERTING 6 INPUT V– 4 AD712 5 NONINVERTING INPUT 00823-001 FEATURES Figure 1. 8-Lead PDIP (N-Suffix), SOIC_N (R-Suffix), and CERDIP (Q-Suffix) GENERAL DESCRIPTION The AD712 is a high speed, precision, monolithic operational amplifier offering high performance at very modest prices. Its very low offset voltage and offset voltage drift are the results of advanced laser wafer trimming technology. These performance benefits allow the user to easily upgrade existing designs that use older precision BiFETs and, in many cases, bipolar op amps. The superior ac and dc performance of this op amp makes it suitable for active filter applications. With a slew rate of 16 V/μs and a settling time of 1 μs to ±0.01%, the AD712 is ideal as a buffer for 12-bit digital-to-analog converters (DACs) and analogto-digital converters (ADCs) and as a high speed integrator. The settling time is unmatched by any similar IC amplifier. The combination of excellent noise performance and low input current also make the AD712 useful for photo diode preamps. Common-mode rejection of 88 dB and open-loop gain of 400 V/mV ensure 12-bit performance even in high speed unity-gain buffer circuits. The AD712 is pinned out in a standard op amp configuration and is available in seven performance grades. The AD712J and AD712K are rated over the commercial temperature range of 0°C to 70°C. The AD712A is rated over the industrial temperature range of −40°C to +85°C. The AD712S is rated over the military temperature range of −55°C to +125°C and is available processed to MIL-STD-883B, Rev. C. Extended reliability PLUS screening is available, specified over the commercial and industrial temperature ranges. PLUS screening includes 168-hour burn-in, in addition to other environmental and physical tests. The AD712 is available in 8-lead PDIP, SOIC_N, and CERDIP packages. PRODUCT HIGHLIGHTS 1. The AD712 offers excellent overall performance at very competitive prices. 2. The Analog Devices, Inc., advanced processing technology and 100% testing guarantee a low input offset voltage (3 mV maximum, J grade). Input offset voltage is specified in the warmed-up condition. 3. Together with precision dc performance, the AD712 offers excellent dynamic response. It settles to ±0.01% in 1 μs and has a minimum slew rate of 16 V/μs. Thus, this device is ideal for applications such as DAC and ADC buffers that require a combination of superior ac and dc performance. Rev. H Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©1986–2010 Analog Devices, Inc. All rights reserved. AD712 TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 14 Connection Diagram ....................................................................... 1 Guarding ...................................................................................... 14 General Description ......................................................................... 1 DAC Converter Applications .................................................... 14 Product Highlights ........................................................................... 1 Noise Characteristics ................................................................. 15 Revision History ............................................................................... 2 Driving the Analog Input of an ADC ...................................... 15 Specifications..................................................................................... 3 Driving a Large Capacitive Load .............................................. 16 Absolute Maximum Ratings............................................................ 5 Filters ................................................................................................ 17 ESD Caution .................................................................................. 5 Active Filter Applications .......................................................... 17 Typical Performance Characteristics ............................................. 6 Second-Order Low-Pass Filter.................................................. 17 Settling Time ................................................................................... 11 9-Pole Chebychev Filter............................................................. 18 Optimizing Settling Time .......................................................... 11 Outline Dimensions ....................................................................... 19 Op Amp Settling Time—A Mathematical Model .................. 12 Ordering Guide .......................................................................... 20 REVISION HISTORY Changes to Figure 43...................................................................... 15 7/10—Rev. G to Rev. H Changes to Product Title ................................................................. 1 Added Input Voltage Noise Parameter, Input Current Noise Parameter, and Open-Loop Gain Parameter, Table 1 .................. 4 Moved Figure 29 and Figure 30 .................................................... 11 Moved Figure 34 ............................................................................. 12 Moved Figure 44 and Figure 45 .................................................... 15 Changes to Ordering Guide .......................................................... 20 8/06—Rev. F to Rev. G Edits to Figure 1 ................................................................................ 1 Change to 9-Pole Chebychev Filter Section ................................ 18 6/06—Rev. E to Rev. F 7/02—Rev. D to Rev. E Edits to Features.................................................................................1 9/01—Rev. C to Rev. D Edits to Features.................................................................................1 Edits to General Description ...........................................................1 Edits to Connection Diagram ..........................................................1 Edits to Ordering Guide ...................................................................3 Deleted Metalization Photograph ...................................................3 Edits to Absolute Maximum Ratings .............................................3 Edits to Figure 7 .................................................................................9 Edits to Outline Dimensions......................................................... 15 Updated Format .................................................................. Universal Deleted B, C, and T Models............................................... Universal Changes to General Description .................................................... 1 Changes to Product Highlights....................................................... 1 Changes to Specifications Section .................................................. 3 Rev. H | Page 2 of 20 AD712 SPECIFICATIONS VS = ±15 V @ TA = 25°C, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum specifications are guaranteed, although only those shown in boldface are tested on all production units. Table 1. Parameter INPUT OFFSET VOLTAGE 1 Initial Offset TMIN to TMAX vs. Temperature vs. Supply TMIN to TMAX Long-Term Offset Stability INPUT BIAS CURRENT 2 VCM = 0 V VCM = 0 V @ TMAX VCM = ±10 V INPUT OFFSET CURRENT VCM = 0 V VCM = 0 V @ TMAX MATCHING CHARACTERISTICS Input Offset Voltage TMIN to TMAX Input Offset Voltage Drift Input Bias Current Crosstalk @ f = 1 kHz @ f = 100 kHz FREQUENCY RESPONSE Small Signal Bandwidth Full Power Response Slew Rate Settling Time to 0.01% Total Harmonic Distortion INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential 3 Common-Mode Voltage 4 TMIN to TMAX Common-Mode Rejection Ratio VCM = ±10 V TMIN to TMAX VCM = ±11 V TMIN to TMAX Min AD712J/AD712A/AD712S Typ Max 0.3 76 76/76/76 Min 0.2 3/1/1 4/2/2 20/20/20 7 95 AD712K Typ 80 80 15 7 100 mV mV μV/°C dB dB μV/month 75 1.7/4.8/77 100 20 0.5 75 1.7 100 pA nA pA 10 0.3/0.7/11 25 0.6/1.6/26 5 0.1 25 0.6 pA nA 1.0 2.0 10 25 mV mV μV/°C pA 4.0 200 20 1.0 0.0003 3.4 18 1.2 120 90 dB dB 4.0 200 20 1.0 0.0003 MHz kHz V/μs μs % 1.2 3×1012||5.5 3×1012||5.5 3×1012||5.5 3×1012||5.5 Ω||pF Ω||pF ±20 +14.5, −11.5 ±20 +14.5, −11.5 V V V −VS + 4 76 76/76/76 70 70/70/70 1.0 2.0 10 25 0.6/1.6/26 120 90 16 Unit 15 3/1/1 4/2/2 20/20/20 25 3.0 Max +VS − 2 88 84 84 80 −VS + 4 80 80 76 74 Rev. H | Page 3 of 20 +VS − 2 88 84 84 80 dB dB dB dB AD712 Parameter INPUT VOLTAGE NOISE f = 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz INPUT CURRENT NOISE f = 1 kHz OPEN-LOOP GAIN VOUT = −10 V to +10 V TMIN to TMAX OUTPUT CHARACTERISTICS Voltage Current POWER SUPPLY Rated Performance Operating Range Quiescent Current Min AD712J/AD712A/AD712S Typ Max Min AD712K Typ Max Unit 2 45 22 18 16 2 45 22 18 16 μV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz 0.01 0.01 pA/√Hz 150 100/100/100 400 200 100 400 V/mV V/mV +13, −12.5 ±12/±12/±12 +13.9, −13.3 +13.8, −13.1 +25 +13, −12.5 ±12 +13.9, −13.3 +13.8, −13.1 +25 V V mA ±15 ±4.5 +5.0 ±15 ±18 +6.8 1 ±4.5 +5.0 ±18 +6.0 V V mA Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C. Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C. 3 Defined as voltage between inputs, such that neither exceeds ±10 V from ground. 4 Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal. 2 Rev. H | Page 4 of 20 AD712 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Internal Power Dissipation1 Input Voltage2 Output Short-Circuit Duration Differential Input Voltage Storage Temperature Range Q-Suffix N-Suffix and R-Suffix Operating Temperature Range AD712J/K AD712A AD712S Lead Temperature Range (Soldering 60 sec) 1 2 Thermal characteristics: 8-lead PDIP package: 8-lead CERDIP package: 8-lead SOIC package: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating ±18 V ±18 V Indefinite +VS and −VS −65°C to +150°C −65°C to +125°C ESD CAUTION 0°C to 70°C −40°C to +85°C −55°C to +125°C 300°C θJA = 165°C/W θJC = 22°C/W; θJA = 110°C/W θJA = 100°C/W For supply voltages less than ±18 V, the absolute maximum voltage is equal to the supply voltage. Rev. H | Page 5 of 20 AD712 TYPICAL PERFORMANCE CHARACTERISTICS 15 10 RL = 2kΩ 25°C 5 0 5 10 SUPPLY VOLTAGE ± V 15 20 4 3 2 0 Figure 2. Input Voltage Swing vs. Supply Voltage 15 20 INPUT BIAS CURRENT (VCM = 0) (Amps) 106 15 +VOUT –VOUT 10 RL = 2kΩ 25°C 5 0 0 5 10 SUPPLY VOLTAGE ± V 15 20 107 108 109 1010 1011 1012 –60 00823-003 –40 –20 0 20 40 60 80 TEMPERATURE (°C) 100 120 140 Figure 6. Input Bias Current vs. Temperature Figure 3. Output Voltage Swing vs. Supply Voltage 100 30 OUTPUT IMPEDANCE (Ω) 25 20 ±15V SUPPLIES 15 10 10 1.0 0.1 5 100 1k LOAD RESISTANCE (Ω) 10k 0.01 1k 00823-004 0 10 10k 100k FREQUENCY (Hz) 1M Figure 7. Output Impedance vs. Frequency Figure 4. Output Voltage Swing vs. Load Resistance Rev. H | Page 6 of 20 10M 00823-007 OUTPUT VOLTAGE SWING (V) 10 SUPPLY VOLTAGE ± V Figure 5. Quiescent Current vs. Supply Voltage 20 OUTPUT VOLTAGE SWING (V p-p) 5 00823-006 0 5 00823-005 QUIESCENT CURRENT (mA) 6 00823-002 INPUT VOLTAGE SWING (V) 20 OPEN-LOOP GAIN (dB) VS = 15V 25°C 50 100 80 80 60 60 40 40 GAIN PHASE 2kΩ 100pF LOAD 20 25 20 0 0 –5 0 5 COMMON MODE VOLTAGE (V) 10 –20 00823-008 0 –10 100 1k 10k 100k 1M –20 10M FREQUENCY (Hz) Figure 11. Open-Loop Gain and Phase Margin vs. Frequency Figure 8. Input Bias Current vs. Common-Mode Voltage 125 26 24 120 OPEN-LOOP GAIN (dB) + OUTPUT CURRENT 22 20 18 – OUTPUT CURRENT 16 115 RL = 2kΩ 25°C 110 105 14 100 12 10 –60 –40 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE (°C) 120 140 95 00823-009 SHORT-CIRCUIT CURRENT LIMIT (mA) 10 0 5 10 SUPPLY VOLTAGE ± V 15 20 00823-012 INPUT BIAS CURRENT (pA) MAX J GRADE LIMIT 75 100 00823-011 100 PHASE MARGIN (Degrees) AD712 Figure 12. Open-Loop Gain vs. Supply Voltage Figure 9. Short-Circuit Current Limit vs. Temperature 110 5.0 POWER SUPPLY REJECTION (dB) 4.5 4.0 3.5 + SUPPLY 80 60 – SUPPLY 40 20 3.0 –60 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 140 0 10 100 1k 10k 100k SUPPLY MODULATION FREQUENCY (Hz) Figure 10. Unity-Gain Bandwidth vs. Temperature Figure 13. Power Supply Rejection vs. Frequency Rev. H | Page 7 of 20 1M 00823-013 VS = ±15V SUPPLIES WITH 1V p-p SINEWAVE 25°C 00823-010 UNITY-GAIN BANDWIDTH (MHz) 100 AD712 100 –70 VS = ±15V VCM = 1V p-p 25°C 80 –80 3V rms RL = 2kΩ CL = 100pF 60 THD (dB) CMR (dB) –90 40 –100 –110 20 100 1k 10k 100k 1M FREQUENCY (Hz) –130 100 30 100k 1k RL = 2kΩ 25°C VS = ±15V 25 INPUT NOISE VOLTAGE (nV/√Hz) 20 15 10 5 1M FREQUENCY (Hz) 10M 10 1 00823-015 0 100k 100 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 18. Input Noise Voltage Spectral Density Figure 15. Large Signal Frequency Response 10 25 8 6 20 2 1% 0.1% SLEW RATE (V/µs) 4 0.01% 0 –2 ERROR 1% 0.1% 0.01% –4 –6 15 10 5 –8 0.6 0.8 0.7 SETTLING TIME (µs) 0.9 1.0 0 00823-016 –10 0.5 0 100 200 300 400 500 600 700 INPUT ERROR SIGNAL (mV) (AT SUMMING JUNCTION) Figure 19. Slew Rate vs. Input Error Signal Figure 16. Output Swing and Error vs. Settling Time Rev. H | Page 8 of 20 800 900 00823-019 OUTPUT VOLTAGE SWING (V p-p) 10k FREQUENCY (Hz) Figure 17. Total Harmonic Distortion vs. Frequency Figure 14. Common-Mode Rejection vs. Frequency OUTPUT SWING FROM 0V TO ±VOLTS 1k 00823-018 10 00823-014 0 00823-017 –120 AD712 25 +VS – 8 VOUT 1/2 20 AD712 + VIN 4 SQUARE WAVE INPUT –40 0 –20 20 40 60 80 TEMPERATURE (°C) 100 120 140 RL 2kΩ CL 100pF –VS 00823-020 15 –60 0.1µF 00823-023 SLEW RATE (V/µs) 0.1µF Figure 23. Unity-Gain Follower Figure 20. Slew Rate vs. Temperature +VS 0.1µF 100 8 + 90 1/2 100pF 2kΩ 0.1µF 00823-021 AD712 – 4 INPUT OUTPUT –VS 10 5V Figure 21. THD Test Circuit Figure 24. Unity-Gain Follower Pulse Response (Large Signal) VOUT 20V p-p 3 – 6 AD712 + 5 8 1/2 1 AD712 + 5kΩ VIN CROSSTALK = 20 log VOUT 10V IN 7 5kΩ 1/2 4 –VS 10 0% 50mV Figure 22. Crosstalk Test Circuit 100ns 00823-025 – 90 2.2kΩ 00823-022 2 100 20kΩ +VS 1µs 00823-024 0% Figure 25. Unity-Gain Follower Pulse Response (Small Signal) Rev. H | Page 9 of 20 AD712 5kΩ +VS 0.1µF 100 90 5kΩ – 8 VOUT 1/2 SQUARE WAVE INPUT 4 0.1µF RL 2kΩ CL 100pF 00823-026 AD712 + –VS 10 0% 50mV Figure 28. Unity-Gain Inverter Pulse Response (Small Signal) Figure 26. Unity-Gain Inverter 100 90 10 1µs 00823-027 0% 5V 200ns 00823-028 VIN Figure 27. Unity-Gain Inverter Pulse Response (Large Signal) Rev. H | Page 10 of 20 AD712 SETTLING TIME OPTIMIZING SETTLING TIME Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%) requires that 375 μV or less appears at the summing junction. This means that the error between the input and output (that voltage which appears at the AD712 summing junction) must be less than 375 μV. As shown in Figure 29, the total settling time for the AD712/AD565A combination is 1.2 microseconds. Most bipolar high speed DACs have current outputs; therefore, for most applications, an external op amp is required for a currentto-voltage conversion. The settling time of the converter/op amp combination depends on the settling time of the DAC and output amplifier. A good approximation is (tS DAC)2 + (t S AMP )2 1mV The settling time of an op amp DAC buffer varies with the noise gain of the circuit, the DAC output capacitance, and the amount of external compensation capacitance across the DAC output scaling resistor. 5V 100 90 SUMMING JUNCTION Settling time for a bipolar DAC is typically 100 ns to 500 ns. Previously, conventional op amps have required much longer settling times than have typical state-of-the-art DACs; therefore, the amplifier settling time has been the major limitation to a high speed, voltage output, digital-to-analog function. The introduction of the AD71x family of op amps with their 1 μs (to ±0.01% of final value) settling time permits the full high speed capabilities of most modern DACs to be realized. 0V OUTPUT 10 –10V 500ns Figure 29. Settling Characteristics for AD712 with AD565A, Full-Scale Negative Transition In addition to a significant improvement in settling time, the low offset voltage, low offset voltage drift, and high open-loop gain of the AD71x family assure 12-bit accuracy over the full operating temperature range. 1mV 5V 100 90 SUMMING JUNCTION The excellent high speed performance of the AD712 is shown in the oscilloscope photos in Figure 29 and Figure 30. Measurements were taken using a low input capacitance amplifier connected directly to the summing junction of the AD712, and both figures show a worst-case situation: full-scale input transition. The 4 kΩ [10 kΩ||8 kΩ = 4.4 kΩ] output impedance of the DAC, together with a 10 kΩ feedback resistor, produce an op amp noise gain of 3.25. The current output from the DAC produces a 10 V step at the op amp output (0 to −10 V shown in Figure 29, and −10 V to 0 V shown in Figure 30). 0V OUTPUT 10 0% –10V 500ns Figure 30. Settling Characteristics for AD712 with AD565A, Full-Scale Positive Transition 0.1µF BIPOLAR OFFSET ADJUST R2 GAIN 100Ω ADJUST REF OUT VCC BIPOLAR OFF 20V SPAN + 10V 5kΩ AD565A – REF IN R1 100Ω 19.95kΩ 9.95kΩ 10V SPAN 0.5mA 5kΩ IREF DAC REF GND 20kΩ IOUT = 4 × IREF × CODE IO 10pF DAC OUT 8kΩ +15V 0.1µF – 8 1/2 MSB LSB 0.1µF –15V 00823-029 POWER GND OUTPUT –10V TO +10V AD712 + 4 –VEE 0.1µF 00823-030 0% Figure 31. ±10 V Voltage Output Bipolar DAC Rev. H | Page 11 of 20 00823-031 t S Total = AD712 OP AMP SETTLING TIME—A MATHEMATICAL MODEL The design of the AD712 gives careful attention to optimizing individual circuit components; in addition, a careful trade-off was made: the gain bandwidth product (4 MHz) and slew rate (20 V/μs) were chosen to be high enough to provide very fast settling time but not too high to cause a significant reduction in phase margin (and therefore, stability). Thus designed, the AD712 settles to ±0.01%, with a 10 V output step, in under 1 μs, while retaining the ability to drive a 250 pF load capacitance when operating as a unity-gain follower. When RO and IO are replaced with their Thevenin VIN and RIN equivalents, the general-purpose inverting amplifier shown in Figure 33 is created. Note that when using this general model, Capacitance CX is either the input capacitance of the op amp, if a simple inverting op amp is being simulated, or the combined capacitance of the DAC output and the op amp input if the DAC buffer is being modeled. + 1/2 AD712 – RIN VO −R = I IN R(C X ) 2 ⎛ G N s + ⎜⎜ + RC f ωO ⎝ ωO (1) ⎞ ⎟ s +1 ⎟ ⎠ Where CL R VIN CX Figure 33. Simplified Model of the AD712 Used as an Inverter In either case, Capacitance CX causes the system to go from a one-pole to a two-pole response; this additional pole increases settling time by introducing peaking or ringing in the op amp output. Because the value of CX can be estimated with reasonable accuracy, Equation 2 can be used to choose a small capacitor (CF) to cancel the input pole and optimize amplifier response. Figure 34 is a graphical solution of Equation 2 for the AD712 with R = 4 kΩ. ωO = unity-gain frequency of the op amp. 2π 60 GN = noise gain of circuit ⎛⎜1 + R ⎞⎟ . ⎟ ⎜ ⎝ RL 00823-033 If an op amp is modeled as an ideal integrator with a unity-gain crossover frequency of ωO/2π, then Equation 1 accurately describes the small signal behavior of the circuit of Figure 32, consisting of an op amp connected as an I-to-V converter at the output of a bipolar or CMOS DAC. This equation would completely describe the output of the system if not for the finite slew rate and other nonlinear effects of the op amp. VOUT CF 50 RO ⎠ GN = 4.0 40 CX This equation can then be solved for Cf RC X ωO + (1 − GN ) 2 − GN CX = +2 RωO RωO 30 GN = 3.0 (2) GN = 2.0 20 GN = 1.5 + 1/2 AD712 – VOUT CF RL CL IO RO CX 00823-032 R Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer Rev. H | Page 12 of 20 10 GN = 1.0 0 0 10 20 30 CF 40 50 Figure 34. Value of Capacitor CF vs. Value of CX 60 00823-034 In these equations, Capacitance CX is the total capacitance appearing at the inverting terminal of the op amp. When modeling a DAC buffer application, the Norton equivalent circuit shown in Figure 32 can be used directly; Capacitance CX is the total capacitance of the output of the DAC plus the input capacitance of the op amp (because the two are in parallel). AD712 The photos of Figure 35 and Figure 36 show the dynamic response of the AD712 in the settling test circuit of Figure 37. 5V 100 90 5V 100 90 10 5mV 10 500ns 0% Figure 36. Settling Characteristics 0 V to −10 V Step Upper Trace: Output of AD712 Under Test (5 V/Div) Lower Trace: Amplified Error Voltage (0.01%/Div) 00823-035 5mV 500ns Figure 35. Settling Characteristics 0 V to +10 V Step Upper Trace: Output of AD712 Under Test (5 V/Div) Lower Trace: Amplified Error Voltage (0.01%/Div) The input of the settling time fixture is driven by a flat top pulse generator. The error signal output from the false summing node of A1 is clamped, amplified by A2, and then clamped again. The error signal is thus clamped twice: once to prevent overloading Amplifier A2 and then a second time to avoid overloading the oscilloscope preamp. The Tektronix oscilloscope preamp type 7A26 was carefully chosen because it does not overload with these input levels. Amplifier A2 needs to be a very high speed FET-input op amp; it provides a gain of 10, amplifying the error signal output of A1. 5pF HP2835 + 1/2 AD712 – 205Ω VERROR × 5 TEKTRONIX 7A26 OSCILLOSCOPE PREAMP INPUT SECTION 1MΩ 20pF HP2835 0.47µF 0.47µF 4.99kΩ 4.99kΩ 200Ω DATA DYNAMICS 5109 5 TO 18pF –15V +15V 10kΩ 10kΩ 1.1kΩ VIN 10kΩ 0.2 TO 0.6pF – 1/2 VOUT AD712 + 0.1µF 5kΩ 10pF 0.1µF 00823-037 (OR EQUIVALENT FLAT TOP PULSE GENERATION) 00823-036 0% –15V +15V Figure 37. Settling Time Test Circuit Rev. H | Page 13 of 20 AD712 APPLICATIONS INFORMATION GUARDING Figure 39 and Figure 40 show the AD712 and AD7545 (12-bit CMOS DAC) configured for unipolar binary (2-quadrant multiplication) or bipolar (4-quadrant multiplication) operation. Capacitor C1 provides phase compensation to reduce overshoot and ringing. The low input bias current (15 pA) and low noise characteristics of the AD712 BiFET op amp make it suitable for electrometer applications such as photo diode preamplifiers and picoampere current-to-voltage converters. The use of a guarding technique, such as that shown in Figure 38, in printed circuit board (PCB) layout and construction is critical to minimize leakage currents. The guard ring is connected to a low impedance potential at the same level as the inputs. High impedance signal lines should not be extended for any unnecessary length on the PCB. VDD R2A* +15V C1A 33pF GAIN ADJUST VIN R1A* RFB VDD – OUT1 VREF 1/2 AD7545 +AD712 AGND PDIP (N), CERDIP (Q), AND SOIC (R) PACKAGES. 0.1µF VOUTA DGND ANALOG COMMON *REFER TO TABLE 3 4 5 DB11 TO DB0 6 R2B* VDD 7 1 C1B 33pF 00823-038 8 GAIN ADJUST Figure 38. Board Layout for Guarding Inputs VIN R1B* DAC CONVERTER APPLICATIONS RFB VDD – OUT1 VREF 1/2 AD7545 +AD712 AGND DGND The AD712 is an excellent output amplifier for CMOS DACs. It can be used to perform both 2-quadrant and 4-quadrant operations. The output impedance of a DAC using an inverted R-2R ladder approaches R for codes containing many 1s, and 3R for codes containing a single 1. For codes containing all 0s, the output impedance is infinite. 0.1µF ANALOG COMMON *REFER TO TABLE 3 –15V DB11 TO DB0 Figure 39. Unipolar Binary Operation R1 and R2 calibrate the zero offset and gain error of the DAC. Specific values for these resistors depend upon the grade of AD7545 and are listed in Table 3. For example, the output resistance of the AD7545 modulates between 11 kΩ and 33 kΩ. Therefore, with an 11 kΩ DAC internal feedback resistance, the noise gain varies from 2 to 4/3. This changing noise gain modulates the effect of the input offset voltage of the amplifier, resulting in nonlinear DAC amplifier performance. Table 3. Recommended Trim Resistor Values vs. Grades of the AD7545 for VDD = 5 V Trim Resistor R1 R2 JN/AQ 500 Ω 150 Ω KN/BQ 200 Ω 68 Ω LN 100 Ω 33 Ω The AD712K with guaranteed 700 μV offset voltage minimizes this effect to achieve 12-bit performance. R2* GAIN ADJUST VDD RFB OUT1 VREF AD7545 VIN R1* AGND DB11 TO DB0 R4 20kΩ 1% +15V C1 33pF 0.1µF R5 20kΩ 1% – – 1/2 +AD712 DGND R3 10kΩ 1% 1/2 AD712 + 0.1µF 12 DATA INPUT *FOR VALUES OF R1 AND R2 SEE TABLE 3 VOUT –15V ANALOG COMMON Figure 40. Bipolar Operation Rev. H | Page 14 of 20 00823-040 VDD VOUTB 00823-039 3 2 GLN 20 Ω 6.8 Ω AD712 Figure 41 and Figure 42 show the settling time characteristics of the AD712 when used as a DAC output buffer for the AD7545. 12/8 STS CS HIGH BITS AO R/C AD574A MIDDLE CE BITS REF IN GAIN ADJUST 1mV 100 90 +15V 0.1µF R2 100Ω R1 100Ω LOW BITS REF OUT BIP OFF +5V OFFSET ADJUST – 10VIN 1/2 5V 500ns 0.1µF 00823-041 0% –15V AC DC 00823-043 10 20VIN AD712 + ±10V ANALOG INPUT +15V ANALOG COM –15V Figure 43. AD712 as an ADC Unity-Gain Buffer Figure 41. Positive Settling Characteristics for AD712 with AD7545 A few hundred microamps reflected from the change in converter loading can introduce errors in instantaneous input voltage. If the analog-to-digital conversion speed is not excessive and the bandwidth of the amplifier is sufficient, the amplifier output returns to the nominal value before the converter makes its comparison. However, many amplifiers have relatively narrow bandwidth yielding slow recovery from output transients. The AD712 is ideally suited to drive high speed ADCs because it offers both wide bandwidth and high open-loop gain. 1mV 100 90 10 0% 500ns PD711 BUFF 1mV 00823-042 5V 100 Figure 42. Negative Settling Characteristics for AD712 with AD7545 90 NOISE CHARACTERISTICS The random nature of noise, particularly in the flicker noise region, makes it difficult to specify in practical terms. At the same time, designers of precision instrumentation require certain guaranteed maximum noise levels to realize the full accuracy of their equipment. All grades of the AD712 are sample tested on an AQL basis to a limit of 6 μV p-p, 0.1 Hz to 10 Hz. 10 500mV 200ns –10V ADC IN 00823-044 0% Figure 44. ADC Input Unity Gain Buffer Recovery Times, −10 V ADC IN An op amp driving the analog input of an ADC, such as that shown in Figure 43, must be capable of maintaining a constant output voltage under dynamically changing load conditions. In successive approximation converters, the input current is compared to a series of switched trial currents. The comparison point is diode clamped, but can deviate several hundred millivolts resulting in high frequency modulation of analog-to-digital input current. The output impedance of a feedback amplifier is made artificially low by the loop gain. At high frequencies, where the loop gain is low, the amplifier output impedance can approach its open-loop value. Most IC amplifiers exhibit a minimum open-loop output impedance of 25 Ω due to current-limiting resistors. PD711 BUFF 1mV 100 90 10 0% 500mV –5V ADC IN 200ns 00823-045 DRIVING THE ANALOG INPUT OF AN ADC Figure 45. ADC Input Unity Gain Buffer Recovery Times, −5 V ADC IN Rev. H | Page 15 of 20 AD712 DRIVING A LARGE CAPACITIVE LOAD The circuit in Figure 46 uses a 100 Ω isolation resistor that enables the amplifier to drive capacitive loads exceeding 1500 pF; the resistor effectively isolates the high frequency feedback from the load and stabilizes the circuit. Low frequency feedback is returned to the amplifier summing junction via the low-pass filter formed by the 100 Ω series resistor and the Load Capacitance CL. Figure 47 shows a typical transient response for this connection. 5V 1µs 100 90 10 4.99kΩ 0% 00823-047 30pF +VIN 0.1µF + – 100Ω 1/2 INPUT TYPICAL CAPACITANCE LIMIT FOR VARIOUS LOAD RESISTORS R1 C1 UP TO 2kΩ 10kΩ 20Ω 1500pF 1500pF 1000pF Figure 47. Transient Response RL = 2 kΩ, CL = 500 pF – +AD712 C1 OUTPUT R1 0.1µF – + –VIN 00823-046 4.99kΩ Figure 46. Circuit for Driving a Large Capacitive Load Rev. H | Page 16 of 20 AD712 FILTERS C1 560pF ACTIVE FILTER APPLICATIONS In active filter applications using op amps, the dc accuracy of the amplifier is critical to optimal filter performance. The amplifier offset voltage and bias current contribute to output error. Offset voltage is passed by the filter and can be amplified to produce excessive output offset. For low frequency applications requiring large value input resistors, bias currents flowing through these resistors also generate an offset voltage. +15V R1 20kΩ VIN R2 20kΩ 0.1µF + 1/2 AD712 – C2 280pF VOUT 00823-048 0.1µF –15V In addition, at higher frequencies, the op amp dynamics must be carefully considered. Here, slew rate, bandwidth, and openloop gain play a major role in op amp selection. The slew rate must be fast as well as symmetrical to minimize distortion. The amplifier bandwidth in conjunction with the filter gain dictates the frequency response of the filter. The use of a high performance amplifier such as the AD712 minimizes both dc and ac errors in all active filter applications. SECOND-ORDER LOW-PASS FILTER Figure 48 depicts the AD712 configured as a second-order, Butterworth low-pass filter. With the values as shown, the corner frequency is 20 kHz; however, the wide bandwidth of the AD712 permits a corner frequency as high as several hundred kilohertz. Equations for component selection are as follows: Figure 48. Second-Order Low-Pass Filter An important property of filters is their out-of-band rejection. The simple 20 kHz low-pass filter shown in Figure 48, can be used to condition a signal contaminated with clock pulses or sampling glitches that have considerable energy content at high frequencies. The low output impedance and high bandwidth of the AD712 minimize high frequency feedthrough as shown in Figure 49. The upper trace is that of another low cost BiFET op amp showing 17 dB more feedthrough at 5 MHz. REF 20.0 dBm 10dB/DIV RANGE 15.0dBm OFFSET .0 Hz 0dB R1 = R2 = A user selected value (10 kΩ to 100 kΩ, typical) C2 = TYPICAL BIFET 1.414 (2π) f cutoff (R1) ( ) AD712 0.707 (2π) f cutoff (R1) ( ) CENTER 5 000 000.0Hz RBW 30kHz VBW 30kHz SPAN 10 000 000.0Hz ST .8 SEC Figure 49. High Frequency Feedthrough Rev. H | Page 17 of 20 00823-049 C1 (in farads) = AD712 +15V 0.1µF + 0.001µF A1 2800Ω 6190Ω 6490Ω 6190Ω 2800Ω 5.9276E –15 5.9276E –15 4.9395E –15 + AD711 – 4.9395E –15 0.1µF A B + + C + D A2 VOUT AD711 – + 0.1µF –15V * 100kΩ * * * 0.001µF 124kΩ 4.99kΩ –15V 4.99kΩ *SEE TEXT 00823-050 VIN +15V 0.1µF Figure 50. 9-Pole Chebychev Filter 9-POLE CHEBYCHEV FILTER REF 5.0dBm 10dB/DIV RANGE –5.0dBm START.0Hz RBW 300Hz VBW 30Hz MARKER 96 800.0Hz –90dBm As shown in Figure 50, the filter is comprised of four FDNRs (A, B, C, D) having values of 4.9395 × 10−15 and 5.9276 × 10–15 farad-seconds. Each FDNR active network provides a two-pole response for eight poles. The ninth pole consists of a 0.001 μF capacitor and a 124 kΩ resistor at Pin 3 of Amplifier A2. Figure 51 depicts the circuits for each FDNR with the proper selection of R. To achieve optimal performance, the 0.001 μF capacitors must be selected for 1% or better matching and all resistors should have 1% or better tolerance. +15V 0.1µF + 0.001µF R – + 1/2 AD712 – 0.1µF 1/2 AD712 + 0.001µF –15V 1.0kΩ 24.9kΩ FOR 4.9395E –15 29.4kΩ FOR 5.9276E –15 4.99kΩ 00823-051 R: Figure 51. FDNR for 9-Pole Chebychev Filter Rev. H | Page 18 of 20 STOP 200 000.0Hz ST 69.6 SEC 00823-052 Figure 50 and Figure 51 show the AD712 and its dual counterpart, the AD711, as a 9-pole Chebychev filter using active frequency dependent negative resistors (FDNRs). With a cutoff frequency of 50 kHz and better than 90 dB rejection, it can be used as an antialiasing filter for a 12-bit data acquisition system with 100 kHz throughput. Figure 52. High Frequency Response for 9-Pole Chebychev Filter AD712 OUTLINE DIMENSIONS 0.400 (10.16) 0.365 (9.27) 0.355 (9.02) 8 5 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 4 0.100 (2.54) BSC 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 53. 8-Lead Plastic Dual In-Line Package [PDIP] (N-8) Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 8 0.055 (1.40) MAX 5 0.310 (7.87) 0.220 (5.59) 1 4 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) SEATING PLANE 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) Rev. H | Page 19 of 20 070606-A 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) AD712 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 55. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1 AD712AQ AD712JNZ AD712JR AD712JR-REEL AD712JR-REEL7 AD712JRZ AD712JRZ-REEL AD712JRZ-REEL7 AD712KNZ AD712KRZ AD712KRZ-REEL AD712KRZ-REEL7 AD712SQ/883B 1 Temperature Range −40°C to +85°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C −55°C to +125°C Package Description 8-Lead CERDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead CERDIP Z = RoHS Compliant Part. ©1986–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00823-0-7/10(H) Rev. H | Page 20 of 20 Package Option Q-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 N-8 R-8 R-8 R-8 Q-8