dm00155929

STM32F446xC/xE
Errata sheet
STM32F446xC/xE device limitations
Silicon identification
This errata sheet applies to the revision A of STM32F446xx microcontroller families.
The STM32F446xx devices feature an ARM® 32-bit Cortex®-M4 core with FPU, for which
an errata notice is also available (see Section 1 for details).
The full list of part numbers is shown in Table 2. The products are identifiable as shown in
Table 1:
•
by the revision code marked below the order code on the device package
•
by the last three digits of the Internal order code printed on the box label
Table 1. Device identification(1)
Order code
Revision code marked on device(2)
STM32F446xx
“A”
1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the RM0390
STM32F446xx reference manual for details on how to find the revision code).
2. Refer to the device datasheets for details on how to identify the revision code and the date code on the
different packages.
Table 2. Device summary
Reference
STM32F446xx
March 2015
Part number
STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE,
STM32F446VC, STM32F446VE, STM32F446ZC, STM32F446ZE.
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Contents
STM32F446xC/xE
Contents
1
2
ARM 32-bit Cortex-M4 with FPU limitations . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Cortex-M4 interrupted loads to stack pointer can cause
erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
VDIV or VSQRT instructions might not complete correctly
when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM32F446xx silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
Debugging Sleep/Stop mode with WFE/WFI entry . . . . . . . . . . . . . . . . . 9
2.1.2
Wakeup sequence from Standby mode when using more than
one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3
Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 10
2.1.4
MPU attribute to RTC and IWDG registers could be managed
incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.5
Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 10
2.1.6
Internal noise impacting the ADC accuracy . . . . . . . . . . . . . . . . . . . . . . 10
IWDG peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1
2.3
2.4
2.5
I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3.1
SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2
Start cannot be generated after a misplaced Stop . . . . . . . . . . . . . . . . . 12
2.3.3
Mismatch on the “Setup time for a repeated Start condition” timing
parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.4
Data valid time (tVD;DAT) violated without the OVR flag being set . . . . . 12
2.3.5
Both SDA and SCL maximum rise time (tr) violated when VDD_I2C bus
higher than ((VDD+0.3) / 0.7) V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.6
Wrong data sampling when data set-up time (tSU;DAT) is smaller than
one FMPI2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I2S peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.1
In I2S slave mode, with Bit ASTRTEN=1, WS level must be set by the
external masterwhen enabling the I2S . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2
In I2S slave PCM short pulse mode when WS hold time is not
respected, it results in data corruption . . . . . . . . . . . . . . . . . . . . . . . . . . 14
USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1
2/23
RVU and PVU flags are not reset in STOP mode . . . . . . . . . . . . . . . . . 11
Idle frame is not detected if receiver clock speed is deviated . . . . . . . . 15
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2.5.2
In full duplex mode, the Parity Error (PE) flag can be cleared by
writing to the data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.3
Parity Error (PE) flag is not set when receiving in Mute mode
using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.4
Break frame is transmitted regardless of nCTS input line status . . . . . . 15
2.5.5
nRTS signal abnormally driven low after a protocol violation . . . . . . . . 16
2.5.6
Start bit detected too soon when sampling for NACK signal
from the smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.7
Break request can prevent the Transmission Complete flag (TC)
from being set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.5.8
Guard time is not respected when data are sent on TXE events . . . . . . 17
2.5.9
nRTS is active while RE or UE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
bxCAN limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.1
2.7
FSMC peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7.1
2.8
2.9
2.11
2.8.1
Wrong CCRCFAIL status after a response without CRC is received . . . 18
2.8.2
No underrun detection with wrong data transmission . . . . . . . . . . . . . . 18
ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 19
DAC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.10.1
DMA underrun flag management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.10.2
DMA request not automatically cleared by DMAEN=0 . . . . . . . . . . . . . 20
QuadSPI limitation: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.11.1
3
Dummy read cycles inserted when reading synchronous memories . . . 18
SDIO peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.9.1
2.10
bxCAN time triggered communication mode not supported . . . . . . . . . 17
Extra data written in the FIFO at the end of a read transfer . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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List of tables
STM32F446xC/xE
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
4/23
Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Cortex-M4 core limitations and impact on microcontroller behavior . . . . . . . . . . . . . . . . . . . 5
Summary of silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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ARM 32-bit Cortex-M4 with FPU limitations
ARM 32-bit Cortex-M4 with FPU limitations
An errata notice of the STM32F446xx core is available from http://infocenter.arm.com.
All the described limitations are minor and related to the revision r0p1-v1 of the Cortex-M4
core. Table 3 summarizes these limitations and their implications on the behavior of
STM32F446xx devices.
Table 3. Cortex-M4 core limitations and impact on microcontroller behavior
1.1
ARM ID
ARM
category
752770
Cat B
Interrupted loads to SP can cause erroneous
behavior
Minor
776924
Cat B
VDIV or VSQRT instructions might not complete
correctly when very short ISRs are used
Minor
ARM summary of errata
Impact on STM32F446xx
Cortex-M4 interrupted loads to stack pointer can cause
erroneous behavior
Description
An interrupt occurring during the data-phase of a single word load to the stack pointer
(SP/R13) can cause an erroneous behavior of the device. In addition, returning from the
interrupt results in the load instruction being executed an additional time.
For all the instructions performing an update of the base register, the base register is
erroneously updated on each execution, resulting in the stack pointer being loaded from an
incorrect memory location.
The instructions affected by this limitation are the following:
•
LDR SP, [Rn],#imm
•
LDR SP, [Rn,#imm]!
•
LDR SP, [Rn,#imm]
•
LDR SP, [Rn]
•
LDR SP, [Rn,Rm]
Workaround
As of today, no compiler generates these particular instructions. This limitation can only
occur with hand-written assembly code.
Both limitations can be solved by replacing the direct load to the stack pointer by an
intermediate load to a general-purpose register followed by a move to the stack pointer.
Example:
Replace LDR SP, [R0] by
LDR R2,[R0]
MOV SP,R2
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ARM 32-bit Cortex-M4 with FPU limitations
1.2
STM32F446xC/xE
VDIV or VSQRT instructions might not complete correctly
when very short ISRs are used
Description
On Cortex-M4 with FPU core, 14 cycles are required to execute a VDIV or VSQRT
instruction.
This limitation is present when the following conditions are met:
•
A VDIV or VSQRT is executed
•
The destination register for VDIV or VSQRT is one of s0 - s15
•
An interrupt occurs and is taken
•
The ISR being executed does not contain a floating point instruction
•
14 cycles after the VDIV or VSQRT is executed, an interrupt return is executed
In this case, if there are only one or two instructions inside the interrupt service routine, then
the VDIV or VQSRT instruction does not complete correctly and the register bank and
FPSCR are not updated, meaning that these registers hold incorrect out-of-date data.
Workaround
Two workarounds are applicable:
6/23
•
Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the
FPCCR at address 0xE000EF34).
•
Ensure that every ISR contains more than 2 instructions in addition to the exception
return instruction.
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STM32F446xx silicon limitations
STM32F446xx silicon limitations
Table 4 gives quick references to all documented limitations.
Legend for Table 4: A = workaround available; N = no workaround available; P = partial
workaround available, ‘-’ and grayed = fixed.
Table 4. Summary of silicon limitations
Links to silicon limitations
Section 2.1.1: Debugging Sleep/Stop mode with WFE/WFI entry
A
Section 2.1.2: Wakeup sequence from Standby mode when using
more than one wakeup source
A
Section 2.1.3: Full JTAG configuration without NJTRST pin cannot
Section 2.1:
be used
System limitations
Section 2.1.4: MPU attribute to RTC and IWDG registers could be
managed incorrectly
Section 2.2:
IWDG peripheral
limitation
Section 2.3: I2C
peripheral
limitations
Section 2.4: I2S
peripheral
limitation
Revision A
A
A
Section 2.1.5: Delay after an RCC peripheral clock enabling
A
Section 2.1.6: Internal noise impacting the ADC accuracy
A
Section 2.2.1: RVU and PVU flags are not reset in STOP mode
A
Section 2.3.1: SMBus standard not fully supported
A
Section 2.3.2: Start cannot be generated after a misplaced Stop
A
Section 2.3.3: Mismatch on the “Setup time for a repeated Start
condition” timing parameter
A
Section 2.3.4: Data valid time (tVD;DAT) violated without the OVR
flag being set
A
Section 2.3.5: Both SDA and SCL maximum rise time (tr) violated
when VDD_I2C bus higher than ((VDD+0.3) / 0.7) V
A
Section 2.3.6: Wrong data sampling when data set-up time
(tSU;DAT) is smaller than one FMPI2CCLK period
A
Section 2.4.1: In I2S slave mode, with Bit ASTRTEN=1, WS level
must be set by the external masterwhen enabling the I2S
A
Section 2.4.2: In I2S slave PCM short pulse mode when WS hold
time is not respected, it results in data corruption
A
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STM32F446xx silicon limitations
STM32F446xC/xE
Table 4. Summary of silicon limitations (continued)
Links to silicon limitations
Section 2.5.1: Idle frame is not detected if receiver clock speed is
deviated
N
Section 2.5.2: In full duplex mode, the Parity Error (PE) flag can be
cleared by writing to the data register
A
Section 2.5.3: Parity Error (PE) flag is not set when receiving in
Mute mode using address mark detection
N
Section 2.5.4: Break frame is transmitted regardless of nCTS input
line status
N
Section 2.5:
USART peripheral Section 2.5.5: nRTS signal abnormally driven low after a protocol
limitations
violation
A
Section 2.5.6: Start bit detected too soon when sampling for NACK
signal from the smartcard
A
Section 2.5.7: Break request can prevent the Transmission
Complete flag (TC) from being set
A
Section 2.5.8: Guard time is not respected when data are sent on
TXE events
A
Section 2.5.9: nRTS is active while RE or UE = 0
A
Section 2.6:
bxCAN limitation
Section 2.6.1: bxCAN time triggered communication mode not
supported
A
Section 2.7:
FSMC peripheral
limitation
Section 2.7.1: Dummy read cycles inserted when reading
synchronous memories
N
Section 2.8: SDIO Section 2.8.1: Wrong CCRCFAIL status after a response without
CRC is received
peripheral
limitations
Section 2.8.2: No underrun detection with wrong data transmission
Section 2.9: ADC
peripheral
limitations
Section 2.10:
DAC peripheral
limitations
Section 2.11:
QuadSPI
limitation:
8/23
Revision A
A
A
Section 2.9.1: ADC sequencer modification during conversion
A
Section 2.10.1: DMA underrun flag management
A
Section 2.10.2: DMA request not automatically cleared by
DMAEN=0
A
Section 2.11.1: Extra data written in the FIFO at the end of a read
transfer
A
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STM32F446xx silicon limitations
2.1
System limitations
2.1.1
Debugging Sleep/Stop mode with WFE/WFI entry
Description
When the Sleep debug or Stop debug mode is enabled (DBG_SLEEP bit or DBG_STOP bit
are set in the DBGMCU_CR register), this allows software debugging during Sleep or Stop
mode. After wakeup some unreachable instructions could be executed if the following
condition are met:
•
If the application software disables the Prefetch queue
•
The number of wait state configured on Flash interface is higher than 0
•
And Linker place WFE or WFI instructions on 4-bytes aligned addresses
(0x080xx_xxx4)
Workaround
2.1.2
•
Add three NOPs after WFI/WFE instruction
•
Keep one AHB master active during sleep (example keep DMA1 or DMA2 RCC clock
enable bit set)
•
Execute WFI/WFE instruction from routines inside the SRAM
Wakeup sequence from Standby mode when using more than
one wakeup source
Description
The various wakeup sources are logically OR-ed in front of the rising-edge detector which
generates the wakeup flag (WUF). The WUF needs to be cleared prior to Standby mode
entry, otherwise the MCU wakes up immediately.
If one of the configured wakeup sources is kept high during the clearing of the WUF (by
setting the CWUF bit), it may mask further wakeup events on the input of the edge detector.
As a consequence, the MCU might not be able to wake up from Standby mode.
Workaround
To avoid this problem, the following sequence should be applied before entering
Standby mode:
Note:
•
Disable all used wakeup sources,
•
Clear all related wakeup flags,
•
Re-enable all used wakeup sources,
•
Enter Standby mode
Be aware that, when applying this workaround, if one of the wakeup sources is still kept
high, the MCU enters Standby mode but then it wakes up immediately generating a power
reset.
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STM32F446xx silicon limitations
2.1.3
STM32F446xC/xE
Full JTAG configuration without NJTRST pin cannot be used
Description
When using the JTAG debug port in debug mode, the connection with the debugger is lost if
the NJTRST pin (PB4) is used as a GPIO. Only the 4-wire JTAG port configuration is
impacted.
Workaround
Use the SWD debug port instead of the full 4-wire JTAG port.
2.1.4
MPU attribute to RTC and IWDG registers could be managed
incorrectly
Description
If the MPU is used and the non bufferable attribute is set to the RTC or IWDG memory map
region, the CPU access to the RTC or IWDG registers could be treated as bufferable,
provided that there is no APB prescaler configured (AHB/APB prescaler is equal to 1).
Workaround
If the non bufferable attribute is required for these registers, the software could perform a
read after the write to guaranty the completion of the write access.
2.1.5
Delay after an RCC peripheral clock enabling
Description
A delay between an RCC peripheral clock enable and the effective peripheral enabling
should be taken into account in order to manage the peripheral read/write to registers.
This delay depends on the peripheral’s mapping:
•
If the peripheral is mapped on AHB: the delay should be equal to 2 AHB cycles.
•
If the peripheral is mapped on APB: the delay should be equal to 1 + (AHB/APB
prescaler) cycles.
Workarounds
2.1.6
1.
Use the DSB instruction to stall the Cortex-M4 CPU pipeline until the instruction is
completed.
2.
Insert “n” NOPs between the RCC enable bit write and the peripheral register writes
(n = 2 for AHB peripherals, n = 1 + AHB/APB prescaler in case of APB peripherals).
Internal noise impacting the ADC accuracy
Description
An internal noise generated on VDD supplies and propagated internally may impact the ADC
accuracy.
This noise is always active whatever the power mode of the MCU (RUN or Sleep).
10/23
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STM32F446xx silicon limitations
Workarounds
To adapt the accuracy level to the application requirements, set one of the following options:
•
Option1
Set the ADCDC1 bit in the PWR_CR register.
•
Option2
Set the corresponding ADCxDC2 bit in the SYSCFG_PMC register.
Only one option can be set at a time.
For more details on option 1 and option2 mechanisms, refer to AN4073.
2.2
IWDG peripheral limitation
2.2.1
RVU and PVU flags are not reset in STOP mode
Description
The RVU and PVU flags of the IWDG_SR register are set by hardware after a write access
to the IWDG_RLR and the IWDG_PR registers, respectively. If the Stop mode is entered
immediately after the write access, the RVU and PVU flags are not reset by hardware.
Before performing a second write operation to the IWDG_RLR or the IWDG_PR register,
the application software must wait for the RVU or PVU flag to be reset. However, since the
RVU/PVU bit is not reset after exiting the Stop mode, the software goes into an infinite loop
and the independent watchdog (IWDG) generates a reset after the programmed timeout
period.
Workaround
Wait until the RVU or PVU flag of the IWDG_SR register is reset before entering the Stop
mode.
2.3
I2C peripheral limitations
2.3.1
SMBus standard not fully supported
Description
The I2C peripheral is not fully compliant with the SMBus v2.0 standard since It does not
support the capability to NACK an invalid byte/command.
Workarounds
A higher-level mechanism should be used to verify that a write operation is being performed
correctly at the target device, such as:
1.
Using the SMBAL pin if supported by the host
2.
the alert response address (ARA) protocol
3.
the Host notify protocol
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STM32F446xx silicon limitations
2.3.2
STM32F446xC/xE
Start cannot be generated after a misplaced Stop
Description
If a master generates a misplaced Stop on the bus (bus error), the peripheral cannot
generate a Start anymore.
Workaround
In the I²C standard, it is allowed to send a Stop only at the end of the full byte (8 bits +
acknowledge), so this scenario is not allowed. Other derived protocols like CBUS allow it,
but they are not supported by the I²C peripheral.
A software workaround consists in asserting the software reset using the SWRST bit in the
I2C_CR1 control register.
2.3.3
Mismatch on the “Setup time for a repeated Start condition” timing
parameter
Description
In case of a repeated Start, the “Setup time for a repeated Start condition” (named Tsu;sta in
the I²C specification) can be slightly violated when the I²C operates in Master Standard
mode at a frequency between 88 kHz and 100 kHz.
The limitation can occur only in the following configuration:
•
in Master mode
•
in Standard mode at a frequency between 88 kHz and 100 kHz (no limitation in Fastmode)
•
SCL rise time:
–
If the slave does not stretch the clock and the SCL rise time is more than 300 ns (if
the SCL rise time is less than 300 ns, the limitation cannot occur)
–
If the slave stretches the clock
The setup time can be violated independently of the APB peripheral frequency.
Workaround
Reduce the frequency down to 88 kHz or use the I²C Fast-mode, if supported by the slave.
2.3.4
Data valid time (tVD;DAT) violated without the OVR flag being set
Description
The data valid time (tVD;DAT, tVD;ACK) described by the I²C standard can be violated (as well
as the maximum data hold time of the current data (tHD;DAT)) under the conditions described
below. This violation cannot be detected because the OVR flag is not set (no transmit buffer
underrun is detected).
This limitation can occur only under the following conditions:
12/23
•
in Slave transmit mode
•
with clock stretching disabled (NOSTRETCH=1)
•
if the software is late to write the DR data register, but not late enough to set the OVR
flag (the data register is written before)
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STM32F446xx silicon limitations
Workaround
If the master device allows it, use the clock stretching mechanism by programming the bit
NOSTRETCH=0 in the I2C_CR1 register.
If the master device does not allow it, ensure that the software is fast enough when polling
the TXE or ADDR flag to immediately write to the DR data register. For instance, use an
interrupt on the TXE or ADDR flag and boost its priority to the higher level.
2.3.5
Both SDA and SCL maximum rise time (tr) violated when VDD_I2C bus
higher than ((VDD+0.3) / 0.7) V
Description
When an external legacy I2C bus voltage (VDD_I2C) is set to 5 V while the MCU is powered
from VDD, the internal 5-Volt tolerant circuitry is activated as soon the input voltage (VIN)
reaches the VDD + diode threshold level. An additional internal large capacitance then
prevents the external pull-up resistor (RP) from rising the SDA and SCL signals within the
maximum timing (tr) which is 300 ns in fast mode and 1000 ns in Standard mode.
The rise time (tr) is measured from VIL and VIH with levels set at 0.3VDD_I2C and
0.7VDD_I2C.
Workaround
The external VDD_I2C bus voltage should be limited to a maximum value of
((VDD+0.3) / 0.7) V. As a result, when the MCU is powered from VDD=3.3 V, VDD_I2C
should not exceed 5.14 V to be compliant with I2C specifications.
2.3.6
Wrong data sampling when data set-up time (tSU;DAT) is smaller than
one FMPI2CCLK period
Description
The I2C bus specification and user manual specifies a minimum data set-up time (tSU;DAT)
at:
•
250ns in Standard-mode,
•
100 ns in Fast-mode,
•
50 ns in Fast-mode Plus.
The I2C SDA line is not correctly sampled when tSU;DAT is smaller than one FMPI2CCLK
(FMPI2C clock) period: the previous SDA value is sampled instead of the current one. This
can result in a wrong slave address reception, a wrong received data byte, or a wrong
received acknowledge bit.
Workaround
Increase the I2CCLK frequency to get I2CCLK period smaller than the transmitter minimum
data set-up time. Or, if it is possible, increase the transmitter minimum data set-up time
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STM32F446xx silicon limitations
STM32F446xC/xE
2.4
I2S peripheral limitation
2.4.1
In I2S slave mode, with Bit ASTRTEN=1, WS level must be set by the
external masterwhen enabling the I2S
Description
In slave mode, and when Bit ASTRTEN=1: I2S Asynchronous Start is enabled, the WS
signal level is used only to start the communication. If the I2S (in slave mode) is enabled
while the master is already sending the clock and the WS signal level is low (for I2S
protocol) or is high (for the LSB or MSB-justified mode), the slave starts communicating data
immediately. In this case, the master and slave will be desynchronized throughout the whole
communication.
Workaround
The I2S peripheral must be enabled when the external master sets the WS line at:
2.4.2
•
High level when the I2S protocol is selected.
•
Low level when the LSB or MSB-justified mode is selected.
In I2S slave PCM short pulse mode when WS hold time is not
respected, it results in data corruption
Description
If I2S peripheral is configured in
•
Slave mode (I2SCFG = '00' or '01')
•
I2S PCM standard selected (I2SSTD = '11')
•
I2S Asynchronous Start is disabled (ASTRTEN = '0')
and the WS signal does not respect hold time versus SCK. In these conditions the data
transmitted and received by the slave are corrupted, because the master and slave will be
de-synchronized throughout the whole communication.
Workaround
Two work around are possible :
14/23
•
The THOLD (NSS_WS vs SCK rising edge) time must be respected by the I2S Master.
•
Enable I2S Asynchronous Start (ASTRTEN bit is equal to '1') when using I2S PCM
standard.
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2.5
USART peripheral limitations
2.5.1
Idle frame is not detected if receiver clock speed is deviated
Description
If the USART receives an idle frame followed by a character, and the clock of the transmitter
device is faster than the USART receiver clock, the USART receive signal falls too early
when receiving the character start bit, with the result that the idle frame is not detected
(IDLE flag is not set).
Workaround
None.
2.5.2
In full duplex mode, the Parity Error (PE) flag can be cleared by
writing to the data register
Description
In full duplex mode, when the Parity Error flag is set by the receiver at the end of a
reception, it may be cleared while transmitting by reading the USART_SR register to check
the TXE or TC flags and writing data to the data register.
Consequently, the software receiver can read the PE flag as '0' even if a parity error
occurred.
Workaround
The Parity Error flag should be checked after the end of reception and before transmission.
2.5.3
Parity Error (PE) flag is not set when receiving in Mute mode
using address mark detection
Description
The USART receiver is in Mute mode and is configured to exit the Mute mode using the
address mark detection. When the USART receiver recognizes a valid address with a parity
error, it exits the Mute mode without setting the Parity Error flag.
Workaround
None.
2.5.4
Break frame is transmitted regardless of nCTS input line status
Description
When CTS hardware flow control is enabled (CTSE = 1) and the Send Break bit (SBK) is
set, the transmitter sends a break frame at the end of the current transmission regardless of
nCTS input line status.
Consequently, if an external receiver device is not ready to accept a frame, the transmitted
break frame is lost.
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Workaround
None.
2.5.5
nRTS signal abnormally driven low after a protocol violation
Description
When RTS hardware flow control is enabled, the nRTS signal goes high when data is
received. If this data was not read and new data is sent to the USART (protocol violation),
the nRTS signal goes back to low level at the end of this new data.
Consequently, the sender gets the wrong information that the USART is ready to receive
further data.
On USART side, an overrun is detected, which indicates that data has been lost.
Workaround
Workarounds are required only if the other USART device violates the communication
protocol, which is not the case in most applications.
Two workarounds can be used:
2.5.6
•
After data reception and before reading the data in the data register, the software takes
over the control of the nRTS signal as a GPIO and holds it high as long as needed. If
the USART device is not ready, the software holds the nRTS pin high, and releases it
when the device is ready to receive new data.
•
The time required by the software to read the received data must always be lower than
the duration of the second data reception. For example, this can be ensured by treating
all the receptions by DMA mode.
Start bit detected too soon when sampling for NACK signal
from the smartcard
Description
In the ISO7816, when a character parity error is incorrect, the Smartcard receiver shall
transmit a NACK error signal at (10.5 +/- 0.2) etu after the character START bit falling edge.
In this case, the USART transmitter should be able to detect correctly the NACK signal by
sampling at (11.0 +/-0.2) etu after the character START bit falling edge.
The USART peripheral used in Smartcard mode doesn't respect the (11 +/-0.2) etu timing,
and when the NACK falling edge arrives at 10.68 etu or later, the USART might misinterpret
this transition as a START bit even if the NACK is correctly detected.
Workaround
None
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2.5.7
STM32F446xx silicon limitations
Break request can prevent the Transmission Complete flag (TC)
from being set
Description
After the end of transmission of a data (D1), the Transmission Complete (TC) flag will not be
set if the following conditions are met:
•
CTS hardware flow control is enabled.
•
D1 is being transmitted.
•
A break transfer is requested before the end of D1 transfer.
•
nCTS is de-asserted before the end of D1 data transfer.
Workaround
If the application needs to detect the end of a data transfer, the break request should be
issued after checking that the TC flag is set.
2.5.8
Guard time is not respected when data are sent on TXE events
Description
In smartcard mode, when sending a data on TXE event, the programmed guard time is not
respected i.e. the data written in the data register is transferred on the bus without waiting
the completion of the guardtime duration corresponding to the previous transmitted data.
Workaround
Write the data after TC is set because in smartcard mode, the TC flag is set at the end of the
guard time duration.
2.5.9
nRTS is active while RE or UE = 0
Description
The nRTS line is driven low as soon as RTSE bit is set even if the USART is disabled (UE =
0) or if the receiver is disabled (RE=0) i.e. not ready to receive data.
Workaround
Configure the I/O used for nRTS as an alternate function after setting the UE and RE bits.
2.6
bxCAN limitation
2.6.1
bxCAN time triggered communication mode not supported
Description
The time triggered communication mode described in the reference manual is not
supported. As a result timestamp values are not available. TTCM bit must be kept cleared in
the CAN_MCR register (time triggered communication mode disabled).
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Workaround
None
2.7
FSMC peripheral limitation
2.7.1
Dummy read cycles inserted when reading synchronous memories
Description
When performing a burst read access to a synchronous memory, two dummy read accesses
are performed at the end of the burst cycle whatever the type of AHB burst access.
However, the extra data values which are read are not used by the FSMC and there is no
functional failure.
Workaround
None.
2.8
SDIO peripheral limitations
2.8.1
Wrong CCRCFAIL status after a response without CRC is received
Description
The CRC is calculated even if the response to a command does not contain any CRC field.
As a consequence, after the SDIO command IO_SEND_OP_COND (CMD5) is sent, the
CCRCFAIL bit of the SDIO_STA register is set.
Workaround
The CCRCFAIL bit in the SDIO_STA register shall be ignored by the software. CCRCFAIL
must be cleared by setting CCRCFAILC bit of the SDIO_ICR register after reception of the
response to the CMD5 command.
2.8.2
No underrun detection with wrong data transmission
Description
In case there is an ongoing data transfer from the SDIO host to the SD card and the
hardware flow control is disabled (bit 14 of the SDIO_CLKCR is not set), if an underrun
condition occurs, the controller may transmit a corrupted data block (with wrong data word)
without detecting the underrun condition when the clock frequencies have the following
relationship:
[3 x period(PCLK2) + 3 x period(SDIOCLK)] >= (32 / (BusWidth)) x period(SDIO_CK)
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Workaround
Avoid the above-mentioned clock frequency relationship, by:
•
Incrementing the APB frequency
•
or decreasing the transfer bandwidth
•
or reducing SDIO_CK frequency
2.9
ADC peripheral limitations
2.9.1
ADC sequencer modification during conversion
Description
If an ADC conversion is started by software (writing the SWSTART bit), and if the
ADC_SQRx or ADC_JSQRx registers are modified during the conversion, the current
conversion is reset and the ADC does not restart a new conversion sequence automatically.
If an ADC conversion is started by hardware trigger, this limitation does not apply. The ADC
restarts a new conversion sequence automatically.
Workaround
When an ADC conversion sequence is started by software, a new conversion sequence can
be restarted only by setting the SWSTART bit in the ADC_CR2 register.
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2.10
DAC peripheral limitations
2.10.1
DMA underrun flag management
Description
If the DMA is not fast enough to input the next digital data to the DAC, as a consequence,
the same digital data is converted twice. In these conditions, the DMAUDR flag is set, which
usually leads to disable the DMA data transfers. This is not the case: the DMA is not
disabled by DMAUDR=1, and it keeps servicing the DAC.
Workaround
To disable the DAC DMA stream, reset the EN bit (corresponding to the DAC DMA stream)
in the DMA_SxCR register.
2.10.2
DMA request not automatically cleared by DMAEN=0
Description
if the application wants to stop the current DMA-to-DAC transfer, the DMA request is not
automatically cleared by DMAEN=0, or by DACEN=0.
If the application stops the DAC operation while the DMA request is high, the DMA request
will be pending while the DAC is reinitialized and restarted; with the risk that a spurious
unwanted DMA request is serviced as soon as the DAC is re-enabled.
Workaround
To stop the current DMA-to-DAC transfer and restart, the following sequence should be
applied:
1.
Check if DMAUDR is set.
2.
Clear the DAC/DMAEN bit.
3.
Clear the EN bit of the DAC DMA/Stream
4.
Reconfigure by software the DAC, DMA, triggers etc.
5.
Restart the application.
2.11
QuadSPI limitation:
2.11.1
Extra data written in the FIFO at the end of a read transfer
Description
When all the conditions listed below are gathered:
•
QUADSPI is used in indirect mode
•
QUADSPI clock is AHB/2 (PRESCALER = 0x01 in the QUADSPI_CR)
•
QUADSPI is in quad mode (DMO
–
•
QUADSPI is in DDR mode (DDR
–
20/23
DE = 0b11 in the QUADSPI_CCR)
M = 0b1 in the QUADSPI_CCR)
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An extra data is incorrectly written in the FIFO when a data is read at the same time that the
FIFO gets full at the end of a read transfer.
Workaround
One of the two workarounds listed below can be done:
•
Read out the extra data until the BUSY flag goes low and discard it.
•
Request an abort after reading out all the correct received data from FIFO in order to
flush FIFO and have the busy low. Abort will keep the last register configuration (set the
ABORT bit in the QUADSPI_CR).
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Revision history
3
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Revision history
Table 5. Document revision history
22/23
Date
Revision
16-Mar-2015
1
Changes
Initial release.
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