dm00095523

STM32F401xB/C
Errata sheet
STM32F401xB and STM32F401xC device limitations
Silicon identification
This errata sheet applies to the STMicroelectronics STM32F401xB/C microcontroller.
The STM32F401xB/C devices feature an ARM® 32-bit Cortex®-M4 core with FPU, for which
an errata notice is also available (see Section 1 for details).
The full list of part numbers is shown in Table 2. The products are identifiable as shown in
Table 1:
•
by the revision code marked below the order code on the device package
•
by the last three digits of the Internal order code printed on the box label
Table 1. Device identification(1)
Order code
Revision code marked on device(2)
STM32F401xB, STM32F401xC
“A”, “Z”
1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the RM0368
STM32F401xx reference manual for details on how to find the revision code).
2. Refer to datasheet for the device marking.
Table 2. Device summary
Reference
March 2015
Part number
STM32F401xB
STM32F401VB, STM32F401RB, STM32F401CB
STM32F401xC
STM32F401VC, STM32F401RC, STM32F401CC
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1
Contents
STM32F401xB/C
Contents
1
2
ARM 32-bit Cortex-M4 with FPU limitations . . . . . . . . . . . . . . . . . . . . . . 5
1.1
Cortex-M4 interrupted loads to stack pointer can cause
erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2
VDIV or VSQRT instructions might not complete correctly
when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
STM32F401xB/C silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . . 9
2.1.2
Debugging Stop mode with WFE entry . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3
Wakeup sequence from Standby mode when using more than
one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.4
Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 10
2.1.5
MPU attribute to RTC and IWDG registers could be managed
incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.6
Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 10
2.1.7
PB5 I/O VIN limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.8
PA0 I/O VIN limitation in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.9
PH1 cannot be used as a GPIO in HSE bypass mode . . . . . . . . . . . . . 11
IWDG peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2.1
2.3
2.4
2.5
RTC_Tamper limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.1
Spurious tamper detection when disabling the tamper channel . . . . . . . 12
2.3.2
Detection of a tamper event occuring before enabling the tamper
detection is not supported in edge detection mode . . . . . . . . . . . . . . . . 12
I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.1
SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4.2
Start cannot be generated after a misplaced Stop . . . . . . . . . . . . . . . . . 13
2.4.3
Mismatch on the “Setup time for a repeated Start condition” timing
parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.4
Data valid time (tVD;DAT) violated without the OVR flag being set . . . . . 14
2.4.5
Both SDA and SCL maximum rise time (tr) violated when VDD_I2C
bus higher than ((VDD+0.3) / 0.7) V . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
I2S peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.1
2/23
RVU and PVU flags are not reset in STOP mode . . . . . . . . . . . . . . . . . 11
In I2S slave mode, WS level must be set by the external master
when enabling the I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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2.6
2.7
2.8
2.9
Contents
USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6.1
Idle frame is not detected if receiver clock speed is deviated . . . . . . . . 15
2.6.2
In full duplex mode, the Parity Error (PE) flag can be cleared by
writing to the data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6.3
Parity Error (PE) flag is not set when receiving in Mute mode
using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6.4
Break frame is transmitted regardless of nCTS input line status . . . . . . 16
2.6.5
nRTS signal abnormally driven low after a protocol violation . . . . . . . . 16
2.6.6
Start bit detected too soon when sampling for NACK signal
from the smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.7
Break request can prevent the Transmission Complete flag (TC)
from being set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.8
Guard time is not respected when data are sent on TXE events . . . . . . 17
2.6.9
nRTS is active while RE or UE = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
OTG_FS peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7.1
Data in RxFIFO is overwritten when all channels are disabled
simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7.2
OTG host blocks the receive channel when receiving IN packets and no
TxFIFO is configured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7.3
Host channel-halted interrupt not generated when the channel is
disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7.4
Error in software-read OTG_FS_DCFG register values . . . . . . . . . . . . 19
SDIO peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8.1
SDIO HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8.2
Wrong CCRCFAIL status after a response without CRC is received . . . 19
2.8.3
Data corruption in SDIO clock dephasing (NEGEDGE) mode . . . . . . . . 19
2.8.4
CE-ATA multiple write command and card busy signal management . . 20
2.8.5
No underrun detection with wrong data transmission . . . . . . . . . . . . . . 20
ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.9.1
3
ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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List of tables
STM32F401xB/C
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
4/23
Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Cortex-M4 core limitations and impact on microcontroller behavior . . . . . . . . . . . . . . . . . . . 5
Summary of silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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ARM 32-bit Cortex-M4 with FPU limitations
ARM 32-bit Cortex-M4 with FPU limitations
An errata notice of the STM32F401xB/C core is available from http://infocenter.arm.com.
All the described limitations are minor and related to the revision r0p1-v1 of the Cortex-M4
core. Table 3 summarizes these limitations and their implications on the behavior of
STM32F401xB/C devices.
Table 3. Cortex-M4 core limitations and impact on microcontroller behavior
1.1
ARM ID
ARM
category
752770
Cat B
Interrupted loads to SP can cause erroneous
behavior
Minor
776924
Cat B
VDIV or VSQRT instructions might not complete
correctly when very short ISRs are used
Minor
ARM summary of errata
Impact on
STM32F401xB/C
Cortex-M4 interrupted loads to stack pointer can cause
erroneous behavior
Description
An interrupt occurring during the data-phase of a single word load to the stack pointer
(SP/R13) can cause an erroneous behavior of the device. In addition, returning from the
interrupt results in the load instruction being executed an additional time.
For all the instructions performing an update of the base register, the base register is
erroneously updated on each execution, resulting in the stack pointer being loaded from an
incorrect memory location.
The instructions affected by this limitation are the following:
•
LDR SP, [Rn],#imm
•
LDR SP, [Rn,#imm]!
•
LDR SP, [Rn,#imm]
•
LDR SP, [Rn]
•
LDR SP, [Rn,Rm]
Workaround
As of today, no compiler generates these particular instructions. This limitation can only
occur with hand-written assembly code.
Both limitations can be solved by replacing the direct load to the stack pointer by an
intermediate load to a general-purpose register followed by a move to the stack pointer.
Example:
Replace LDR SP, [R0] by
LDR R2,[R0]
MOV SP,R2
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1.2
STM32F401xB/C
VDIV or VSQRT instructions might not complete correctly
when very short ISRs are used
Description
On Cortex-M4 with FPU core, 14 cycles are required to execute a VDIV or VSQRT
instruction.
This limitation is present when the following conditions are met:
•
A VDIV or VSQRT is executed
•
The destination register for VDIV or VSQRT is one of s0 - s15
•
An interrupt occurs and is taken
•
The ISR being executed does not contain a floating point instruction
•
14 cycles after the VDIV or VSQRT is executed, an interrupt return is executed
In this case, if there are only one or two instructions inside the interrupt service routine, then
the VDIV or VQSRT instruction does not complete correctly and the register bank and
FPSCR are not updated, meaning that these registers hold incorrect out-of-date data.
Workaround
Two workarounds are applicable:
6/23
•
Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the
FPCCR at address 0xE000EF34).
•
Ensure that every ISR contains more than 2 instructions in addition to the exception
return instruction.
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STM32F401xB/C silicon limitations
STM32F401xB/C silicon limitations
Table 4 gives quick references to all documented limitations.
Legend for Table 4: A = workaround available; N = no workaround available; P = partial
workaround available, ‘-’ and grayed = fixed.
Table 4. Summary of silicon limitations
Links to silicon limitations
Section 2.1: System
limitations
Section 2.2: IWDG
peripheral limitation
Section 2.3:
RTC_Tamper
limitations
Section 2.1.1: Debugging Stop mode and system tick timer
A
Section 2.1.2: Debugging Stop mode with WFE entry
A
Section 2.1.3: Wakeup sequence from Standby mode when using more
than one wakeup source
A
Section 2.1.4: Full JTAG configuration without NJTRST pin cannot be
used
A
Section 2.1.5: MPU attribute to RTC and IWDG registers could be
managed incorrectly
A
Section 2.1.6: Delay after an RCC peripheral clock enabling
A
Section 2.1.7: PB5 I/O VIN limitation
A
Section 2.1.8: PA0 I/O VIN limitation in Standby mode
A
Section 2.1.9: PH1 cannot be used as a GPIO in HSE bypass mode
N
Section 2.2.1: RVU and PVU flags are not reset in STOP mode
A
Section 2.3.1: Spurious tamper detection when disabling the tamper
channel
A
Section 2.3.2: Detection of a tamper event occuring before enabling
the tamper detection is not supported in edge detection mode
A
Section 2.4.1: SMBus standard not fully supported
A
Section 2.4.2: Start cannot be generated after a misplaced Stop
A
Section 2.4.3: Mismatch on the “Setup time for a repeated Start
Section 2.4: I2C
condition” timing parameter
peripheral limitations
Section 2.4.4: Data valid time (tVD;DAT) violated without the OVR flag
being set
Section 2.5: I2S
peripheral limitation
Revision A and Z
A
A
Section 2.4.5: Both SDA and SCL maximum rise time (tr) violated when
VDD_I2C bus higher than ((VDD+0.3) / 0.7) V
A
Section 2.5.1: In I2S slave mode, WS level must be set by the external
master when enabling the I2S
A
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Table 4. Summary of silicon limitations (continued)
Links to silicon limitations
Section 2.6.1: Idle frame is not detected if receiver clock speed is
deviated
N
Section 2.6.2: In full duplex mode, the Parity Error (PE) flag can be
cleared by writing to the data register
A
Section 2.6.3: Parity Error (PE) flag is not set when receiving in Mute
mode using address mark detection
N
Section 2.6.4: Break frame is transmitted regardless of nCTS input line
status
N
Section 2.6: USART
Section 2.6.5: nRTS signal abnormally driven low after a protocol
peripheral limitations
violation
Section 2.7:
OTG_FS peripheral
limitations
Revision A and Z
A
Section 2.6.6: Start bit detected too soon when sampling for NACK
signal from the smartcard
A
Section 2.6.7: Break request can prevent the Transmission Complete
flag (TC) from being set
A
Section 2.6.8: Guard time is not respected when data are sent on TXE
events
A
Section 2.6.9: nRTS is active while RE or UE = 0
A
Section 2.7.1: Data in RxFIFO is overwritten when all channels are
disabled simultaneously
A
Section 2.7.2: OTG host blocks the receive channel when receiving IN
packets and no TxFIFO is configured
A
Section 2.7.3: Host channel-halted interrupt not generated when the
channel is disabled
A
Section 2.7.4: Error in software-read OTG_FS_DCFG register values
A
Section 2.8.1: SDIO HW flow control
N
Section 2.8.2: Wrong CCRCFAIL status after a response without CRC
is received
A
Section 2.8: SDIO
Section 2.8.3: Data corruption in SDIO clock dephasing (NEGEDGE)
peripheral limitations mode
N
Section 2.8.4: CE-ATA multiple write command and card busy signal
management
A
Section 2.8.5: No underrun detection with wrong data transmission
A
Section 2.9: ADC
Section 2.9.1: ADC sequencer modification during conversion
peripheral limitations
8/23
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STM32F401xB/C
STM32F401xB/C silicon limitations
2.1
System limitations
2.1.1
Debugging Stop mode and system tick timer
Description
If the system tick timer interrupt is enabled during the Stop mode debug (DBG_STOP bit set
in the DBGMCU_CR register), it will wake up the system from Stop mode.
Workaround
To debug the Stop mode, disable the system tick timer interrupt.
2.1.2
Debugging Stop mode with WFE entry
Description
When the Stop debug mode is enabled (DBG_STOP bit set in the DBGMCU_CR register),
this allows software debugging during Stop mode.
However, if the application software uses the WFE instruction to enter Stop mode, after
wakeup some instructions could be missed if the WFE is followed by sequential instructions.
This affects only Stop debug mode with WFE entry.
Workaround
To debug Stop mode with WFE entry, the WFE instruction must be inside a dedicated
function with 1 instruction (NOP) between the execution of the WFE and the Bx LR.
Example:
__asm void _WFE(void) {
WFE
NOP
BX lr }
2.1.3
Wakeup sequence from Standby mode when using more than
one wakeup source
Description
The various wakeup sources are logically OR-ed in front of the rising-edge detector which
generates the wakeup flag (WUF). The WUF needs to be cleared prior to Standby mode
entry, otherwise the MCU wakes up immediately.
If one of the configured wakeup sources is kept high during the clearing of the WUF (by
setting the CWUF bit), it may mask further wakeup events on the input of the edge detector.
As a consequence, the MCU might not be able to wake up from Standby mode.
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Workaround
To avoid this problem, the following sequence should be applied before entering
Standby mode:
•
Disable all used wakeup sources,
•
Clear all related wakeup flags,
•
Re-enable all used wakeup sources,
•
Enter Standby mode
Note:
Be aware that, when applying this workaround, if one of the wakeup sources is still kept
high, the MCU enters Standby mode but then it wakes up immediately generating a power
reset.
2.1.4
Full JTAG configuration without NJTRST pin cannot be used
Description
When using the JTAG debug port in debug mode, the connection with the debugger is lost if
the NJTRST pin (PB4) is used as a GPIO. Only the 4-wire JTAG port configuration is
impacted.
Workaround
Use the SWD debug port instead of the full 4-wire JTAG port.
2.1.5
MPU attribute to RTC and IWDG registers could be managed
incorrectly
Description
If the MPU is used and the non bufferable attribute is set to the RTC or IWDG memory map
region, the CPU access to the RTC or IWDG registers could be treated as bufferable,
provided that there is no APB prescaler configured (AHB/APB prescaler is equal to 1).
Workaround
If the non bufferable attribute is required for these registers, the software could perform a
read after the write to guaranty the completion of the write access.
2.1.6
Delay after an RCC peripheral clock enabling
Description
A delay between an RCC peripheral clock enable and the effective peripheral enabling
should be taken into account in order to manage the peripheral read/write to registers.
This delay depends on the peripheral’s mapping:
10/23
•
If the peripheral is mapped on AHB: the delay should be equal to 2 AHB cycles.
•
If the peripheral is mapped on APB: the delay should be equal to 1 + (AHB/APB
prescaler) cycles.
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Workarounds
2.1.7
1.
Use the DSB instruction to stall the Cortex-M4 CPU pipeline until the instruction is
completed.
2.
Insert “n” NOPs between the RCC enable bit write and the peripheral register writes
(n = 2 for AHB peripherals, n = 1 + AHB/APB prescaler in case of APB peripherals).
PB5 I/O VIN limitation
Description
If the input voltage (VIN) applied to PB5 exceeds VDD supply voltage, an I/O leakage
current, which can impact the product lifetime, is observed.
Workaround
There is no functional limitation on PB5 pad if VIN does not exceed VDD.
2.1.8
PA0 I/O VIN limitation in Standby mode
Description
In Standby mode, if the input voltage (VIN) applied to PA0 exceeds VDD supply voltage, an
I/O leakage current, which can impact the product lifetime, is observed.
Workaround
There is no functional limitation on PA0 pad if VIN does not exceed VDD.
If the device does not operate in Standby mode, PA0 is 5 V tolerant (FT) thus allowing an
input voltage higher than VDD (according to the datasheet specifications).
2.1.9
PH1 cannot be used as a GPIO in HSE bypass mode
Description
When an external clock is used and the HSE is bypassed, PH1 cannot be used as GPIO.
Work around
None.
2.2
IWDG peripheral limitation
2.2.1
RVU and PVU flags are not reset in STOP mode
Description
The RVU and PVU flags of the IWDG_SR register are set by hardware after a write access
to the IWDG_RLR and the IWDG_PR registers, respectively. If the Stop mode is entered
immediately after the write access, the RVU and PVU flags are not reset by hardware.
Before performing a second write operation to the IWDG_RLR or the IWDG_PR register,
the application software must wait for the RVU or PVU flag to be reset. However, since the
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RVU/PVU bit is not reset after exiting the Stop mode, the software goes into an infinite loop
and the independent watchdog (IWDG) generates a reset after the programmed timeout
period.
Workaround
Wait until the RVU or PVU flag of the IWDG_SR register is reset before entering the Stop
mode.
2.3
RTC_Tamper limitations
2.3.1
Spurious tamper detection when disabling the tamper channel
Description
If the tamper detection is configured for detection on falling edge event (TAMPFLT=00 and
TAMPxTRG=1) and if the tamper event detection is disabled when the tamper pin is at high
level, a false tamper event is detected.
Workaround
None
2.3.2
Detection of a tamper event occuring before enabling the tamper
detection is not supported in edge detection mode
Description
When the tamper detection is enabled in edge detection mode (TAMPFLT=00):
•
When TAMPxTRG=0 (rising edge detection): if the tamper input is already high before
enabling the tamper detection, the tamper event may or may not be detected when
enabling the tamper detection. The probability to detect it increases with the APB
frequency.
•
When TAMPxTRG=1 (falling edge detection): if the tamper input is already low before
enabling the tamper detection, the tamper event is not detected when enabling the
tamper detection.
Workaround
The I/O state should be checked by software in the GPIO registers, just after enabling the
tamper detection and before writing sensitive values in the backup registers, in order to
ensure that no active edge occurred before enabling the tamper event detection.
2.4
I2C peripheral limitations
2.4.1
SMBus standard not fully supported
Description
The I2C peripheral is not fully compliant with the SMBus v2.0 standard since It does not
support the capability to NACK an invalid byte/command.
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Workarounds
A higher-level mechanism should be used to verify that a write operation is being performed
correctly at the target device, such as:
2.4.2
1.
Using the SMBAL pin if supported by the host
2.
the alert response address (ARA) protocol
3.
the Host notify protocol
Start cannot be generated after a misplaced Stop
Description
If a master generates a misplaced Stop on the bus (bus error), the peripheral cannot
generate a Start anymore.
Workaround
In the I²C standard, it is allowed to send a Stop only at the end of the full byte (8 bits +
acknowledge), so this scenario is not allowed. Other derived protocols like CBUS allow it,
but they are not supported by the I²C peripheral.
A software workaround consists in asserting the software reset using the SWRST bit in the
I2C_CR1 control register.
2.4.3
Mismatch on the “Setup time for a repeated Start condition” timing
parameter
Description
In case of a repeated Start, the “Setup time for a repeated Start condition” (named Tsu;sta in
the I²C specification) can be slightly violated when the I²C operates in Master Standard
mode at a frequency between 88 kHz and 100 kHz.
The limitation can occur only in the following configuration:
•
in Master mode
•
in Standard mode at a frequency between 88 kHz and 100 kHz (no limitation in Fastmode)
•
SCL rise time:
–
If the slave does not stretch the clock and the SCL rise time is more than 300 ns (if
the SCL rise time is less than 300 ns, the limitation cannot occur)
–
If the slave stretches the clock
The setup time can be violated independently of the APB peripheral frequency.
Workaround
Reduce the frequency down to 88 kHz or use the I²C Fast-mode, if supported by the slave.
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2.4.4
STM32F401xB/C
Data valid time (tVD;DAT) violated without the OVR flag being set
Description
The data valid time (tVD;DAT, tVD;ACK) described by the I²C standard can be violated (as well
as the maximum data hold time of the current data (tHD;DAT)) under the conditions described
below. This violation cannot be detected because the OVR flag is not set (no transmit buffer
underrun is detected).
This limitation can occur only under the following conditions:
•
in Slave transmit mode
•
with clock stretching disabled (NOSTRETCH=1)
•
if the software is late to write the DR data register, but not late enough to set the OVR
flag (the data register is written before)
Workaround
If the master device allows it, use the clock stretching mechanism by programming the bit
NOSTRETCH=0 in the I2C_CR1 register.
If the master device does not allow it, ensure that the software is fast enough when polling
the TXE or ADDR flag to immediately write to the DR data register. For instance, use an
interrupt on the TXE or ADDR flag and boost its priority to the higher level.
2.4.5
Both SDA and SCL maximum rise time (tr) violated when VDD_I2C
bus higher than ((VDD+0.3) / 0.7) V
Description
When an external legacy I2C bus voltage (VDD_I2C) is set to 5 V while the MCU is powered
from VDD, the internal 5-Volt tolerant circuitry is activated as soon the input voltage (VIN)
reaches the VDD + diode threshold level. An additional internal large capacitance then
prevents the external pull-up resistor (RP) from rising the SDA and SCL signals within the
maximum timing (tr) which is 300 ns in fast mode and 1000 ns in Standard mode.
The rise time (tr) is measured from VIL and VIH with levels set at 0.3VDD_I2C and
0.7VDD_I2C.
Workaround
The external VDD_I2C bus voltage should be limited to a maximum value of
((VDD+0.3) / 0.7) V. As a result, when the MCU is powered from VDD=3.3 V, VDD_I2C
should not exceed 5.14 V to be compliant with I2C specifications.
2.5
I2S peripheral limitation
2.5.1
In I2S slave mode, WS level must be set by the external master
when enabling the I2S
Description
In slave mode, the WS signal level is used only to start the communication. If the I2S (in
slave mode) is enabled while the master is already sending the clock and the WS signal
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level is low (for I2S protocol) or is high (for the LSB or MSB-justified mode), the slave starts
communicating data immediately. In this case, the master and slave will be desynchronized
throughout the whole communication.
Workaround
The I2S peripheral must be enabled when the external master sets the WS line at:
•
High level when the I2S protocol is selected.
•
Low level when the LSB or MSB-justified mode is selected.
2.6
USART peripheral limitations
2.6.1
Idle frame is not detected if receiver clock speed is deviated
Description
If the USART receives an idle frame followed by a character, and the clock of the transmitter
device is faster than the USART receiver clock, the USART receive signal falls too early
when receiving the character start bit, with the result that the idle frame is not detected
(IDLE flag is not set).
Workaround
None.
2.6.2
In full duplex mode, the Parity Error (PE) flag can be cleared by
writing to the data register
Description
In full duplex mode, when the Parity Error flag is set by the receiver at the end of a
reception, it may be cleared while transmitting by reading the USART_SR register to check
the TXE or TC flags and writing data to the data register.
Consequently, the software receiver can read the PE flag as '0' even if a parity error
occurred.
Workaround
The Parity Error flag should be checked after the end of reception and before transmission.
2.6.3
Parity Error (PE) flag is not set when receiving in Mute mode
using address mark detection
Description
The USART receiver is in Mute mode and is configured to exit the Mute mode using the
address mark detection. When the USART receiver recognizes a valid address with a parity
error, it exits the Mute mode without setting the Parity Error flag.
Workaround
None.
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2.6.4
STM32F401xB/C
Break frame is transmitted regardless of nCTS input line status
Description
When CTS hardware flow control is enabled (CTSE = 1) and the Send Break bit (SBK) is
set, the transmitter sends a break frame at the end of the current transmission regardless of
nCTS input line status.
Consequently, if an external receiver device is not ready to accept a frame, the transmitted
break frame is lost.
Workaround
None.
2.6.5
nRTS signal abnormally driven low after a protocol violation
Description
When RTS hardware flow control is enabled, the nRTS signal goes high when data is
received. If this data was not read and new data is sent to the USART (protocol violation),
the nRTS signal goes back to low level at the end of this new data.
Consequently, the sender gets the wrong information that the USART is ready to receive
further data.
On USART side, an overrun is detected, which indicates that data has been lost.
Workaround
Workarounds are required only if the other USART device violates the communication
protocol, which is not the case in most applications.
Two workarounds can be used:
2.6.6
•
After data reception and before reading the data in the data register, the software takes
over the control of the nRTS signal as a GPIO and holds it high as long as needed. If
the USART device is not ready, the software holds the nRTS pin high, and releases it
when the device is ready to receive new data.
•
The time required by the software to read the received data must always be lower than
the duration of the second data reception. For example, this can be ensured by treating
all the receptions by DMA mode.
Start bit detected too soon when sampling for NACK signal
from the smartcard
Description
According to ISO/IEC 7816-3 standard, when a character parity error is detected, the
receiver shall transmit a NACK error signal 10.5 ± 0.2 ETUs after the character START bit
falling edge. In this case, the transmitter should be able to detect correctly the NACK signal
until 11 ± 0.2 ETUs after the character START bit falling edge.
In Smartcard mode, the USART peripheral monitors the NACK signal during the receiver
time frame (10.5 ± 0.2 ETUs), while it should wait for it during the transmitter one (11 ± 0.2
ETUs). In real cases, this would not be a problem as the card itself needs to respect a 10.7
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ETU period when sending the NACK signal. However this may be an issue to undertake a
certification.
Workaround
None
2.6.7
Break request can prevent the Transmission Complete flag (TC)
from being set
Description
After the end of transmission of a data (D1), the Transmission Complete (TC) flag will not be
set if the following conditions are met:
•
CTS hardware flow control is enabled.
•
D1 is being transmitted.
•
A break transfer is requested before the end of D1 transfer.
•
nCTS is de-asserted before the end of D1 data transfer.
Workaround
If the application needs to detect the end of a data transfer, the break request should be
issued after checking that the TC flag is set.
2.6.8
Guard time is not respected when data are sent on TXE events
Description
In smartcard mode, when sending a data on TXE event, the programmed guard time is not
respected i.e. the data written in the data register is transferred on the bus without waiting
the completion of the guardtime duration corresponding to the previous transmitted data.
Workaround
Write the data after TC is set because in smartcard mode, the TC flag is set at the end of the
guard time duration.
2.6.9
nRTS is active while RE or UE = 0
Description
The nRTS line is driven low as soon as RTSE bit is set even if the USART is disabled (UE =
0) or if the receiver is disabled (RE=0) i.e. not ready to receive data.
Workaround
Configure the I/O used for nRTS as an alternate function after setting the UE and RE bits.
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2.7
OTG_FS peripheral limitations
2.7.1
Data in RxFIFO is overwritten when all channels are disabled
simultaneously
Description
If the available RxFIFO is just large enough to host 1 packet + its data status, and is
currently occupied by the last received data + its status and, at the same time, the
application requests that more IN channels be disabled, the OTG_FS peripheral does not
first check for available space before inserting the disabled status of the IN channels. It just
inserts them by overwriting the existing data payload.
Workaround
Use one of the following recommendations:
2.7.2
1.
Configure the RxFIFO to host a minimum of 2 × MPSIZ + 2 × data status entries.
2.
The application has to check the RXFLVL bit (RxFIFO non-empty) in the
OTG_FS_GINTSTS register before disabling each IN channel. If this bit is not set, then
the application can disable an IN channel at a time. Each time the application disables
an IN channel, however, it first has to check that the RXFLVL bit = 0 condition is true.
OTG host blocks the receive channel when receiving IN packets and no
TxFIFO is configured
Description
When receiving data, the OTG_FS core erroneously checks for available TxFIFO space
when it should only check for RxFIFO space. If the OTG_FS core cannot see any space
allocated for data transmission, it blocks the reception channel and no data is received.
Workaround
Set at least one TxFIFO equal to the maximum packet size. In this way, the host application,
which intends to supports only IN traffic, also has to allocate some space for the TxFIFO.
Since a USB host is expected to support any kind of connected endpoint, it is good practice
to always configure enough TxFIFO space for OUT endpoints.
2.7.3
Host channel-halted interrupt not generated when the channel is
disabled
Description
When the application enables, then immediately disables the host channel before the
OTG_FS host has had time to begin the transfer sequence, the OTG_FS core, as a host,
does not generate a channel-halted interrupt. The OTG_FS core continues to operate
normally.
Workaround
Do not disable the host channel immediately after enabling it.
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STM32F401xB/C silicon limitations
Error in software-read OTG_FS_DCFG register values
Description
When the application writes to the DAD and PFIVL bitfields in the OTG_FS_DCFG register,
and then reads the newly written bitfield values, the read values may not be correct.
The values written by the application, however, are correctly retained by the core, and the
normal operation of the device is not affected.
Workaround
Do not read from the OTG_FS_DCFG register’s DAD and PFIVL bitfields just after
programming them.
2.8
SDIO peripheral limitations
2.8.1
SDIO HW flow control
Description
When enabling the HW flow control by setting bit 14 of the SDIO_CLKCR register to ‘1’,
glitches can occur on the SDIOCLK output clock resulting in wrong data to be written into
the SD/MMC card or into the SDIO device. As a consequence, a CRC error will be reported
to the SD/SDIO MMC host interface (DCRCFAIL bit set to ‘1’ in SDIO_STA register).
Workaround
None.
Note:
Do not use the HW flow control. Overrun errors (Rx mode) and FIFO underrun (Tx mode)
should be managed by the application software.
2.8.2
Wrong CCRCFAIL status after a response without CRC is received
Description
The CRC is calculated even if the response to a command does not contain any CRC field.
As a consequence, after the SDIO command IO_SEND_OP_COND (CMD5) is sent, the
CCRCFAIL bit of the SDIO_STA register is set.
Workaround
The CCRCFAIL bit in the SDIO_STA register shall be ignored by the software. CCRCFAIL
must be cleared by setting CCRCFAILC bit of the SDIO_ICR register after reception of the
response to the CMD5 command.
2.8.3
Data corruption in SDIO clock dephasing (NEGEDGE) mode
Description
When NEGEDGE bit is set to ‘1’, it may lead to invalid data and command response read.
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Workaround
None. A configuration with the NEGEDGE bit equal to ‘1’ should not be used.
2.8.4
CE-ATA multiple write command and card busy signal management
Description
The CE-ATA card may inform the host that it is busy by driving the SDIO_D0 line low, two
cycles after the transfer of a write command (RW_MULTIPLE_REGISTER or
RW_MULTIPLE_BLOCK). When the card is in a busy state, the host must not send any
data until the BUSY signal is de-asserted (SDIO_D0 released by the card).
This condition is not respected if the data state machine leaves the IDLE state (Write
operation programmed and started, DTEN = 1, DTDIR = 0 in SDIO_DCTRL register and
TXFIFOE = 0 in SDIO_STA register).
As a consequence, the write transfer fails and the data lines are corrupted.
Workaround
After sending the write command (RW_MULTIPLE_REGISTER or
RW_MULTIPLE_BLOCK), the application must check that the card is not busy by polling the
BSY bit of the ATA status register using the FAST_IO (CMD39) command before enabling
the data state machine.
2.8.5
No underrun detection with wrong data transmission
Description
In case there is an ongoing data transfer from the SDIO host to the SD card and the
hardware flow control is disabled (bit 14 of the SDIO_CLKCR is not set), if an underrun
condition occurs, the controller may transmit a corrupted data block (with wrong data word)
without detecting the underrun condition when the clock frequencies have the following
relationship:
[3 x period(PCLK2) + 3 x period(SDIOCLK)] >= (32 / (BusWidth)) x period(SDIO_CK)
Workaround
Avoid the above-mentioned clock frequency relationship, by:
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Incrementing the APB frequency
•
or decreasing the transfer bandwidth
•
or reducing SDIO_CK frequency
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2.9
ADC peripheral limitations
2.9.1
ADC sequencer modification during conversion
Description
If an ADC conversion is started by software (writing the SWSTART bit), and if the
ADC_SQRx or ADC_JSQRx registers are modified during the conversion, the current
conversion is reset and the ADC does not restart a new conversion sequence automatically.
If an ADC conversion is started by hardware trigger, this limitation does not apply. The ADC
restarts a new conversion sequence automatically.
Workaround
When an ADC conversion sequence is started by software, a new conversion sequence can
be restarted only by setting the SWSTART bit in the ADC_CR2 register.
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Revision history
3
STM32F401xB/C
Revision history
Table 5. Document revision history
Date
Revision
20-Sep-2013
1
Initial release.
19-Dec-2013
2
Added STM32F401xD and STM32F401xE part numbers.
Changed STM32F401xx reference manual name to RM0368.
3
Added:
– rev “Z” on Table 1: Device identification and in Table 4: Summary
of silicon limitations
– Section 1.2: VDIV or VSQRT instructions might not complete
correctly when very short ISRs are used.
– Section 2.1.7: PB5 I/O VIN limitation
– Section 2.1.8: PA0 I/O VIN limitation in Standby mode
– Section 2.1.9: PH1 cannot be used as a GPIO in HSE bypass
mode
– Section 2.3: RTC_Tamper limitations
– From Section 2.6.6 to Section 2.6.9
Removed reference in all document to Root Part Numbers
STM32F401D/E
Updated:
– Section Table 4.: Summary of silicon limitations
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