24AA16H/24LC16BH 16K I2C™ Serial EEPROM with Half-Array Write-Protect Device Selection Table Description: Part Number VCC Range Max. Clock Frequency Temp. Ranges 24AA16H 1.7-5.5 400 kHz(1) I 2.5-5.5 400 kHz I, E 24LC16BH Note 1: 100 kHz for VCC <2.5V Features: • Single Supply with Operation Down to 1.7V for 24AA16H Devices, 2.5V for 24LC16BH Devices • Low-Power CMOS Technology: - Read current 1 mA, max. - Standby current 1 μA, max. • 2-Wire Serial Interface, I2C™ Compatible • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to eliminate Ground Bounce • 100 kHz and 400 kHz Clock Compatibility • Page Write Time 3 ms, typical • Self-Timed Erase/Write Cycle • 16-Byte Page Write Buffer • Hardware Write-Protect for Half-Array (400h-7FFh) • ESD Protection >4,000V • More than 1 Million Erase/Write Cycles • Data Retention >200 years • Factory Programming available • Packages include 8-lead PDIP, SOIC, TSSOP, TDFN, MSOP and 5-lead SOT-23 • Pb-Free and RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C The Microchip Technology Inc. 24AA16H/24LC16BH (24XX16H*) is an 16 Kbit Electrically Erasable PROM. The device is organized as eight blocks of 256 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 1 mA, respectively. The 24XX16H also has a page write capability for up to 16 bytes of data. The 24XX16H is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP, 2x3 TDFN and MSOP packages, and is also available in the 5-lead SOT-23 package. All packages are Pb-free and RoHS compliant. Block Diagram HV Generator WP I/O Control Logic Memory Control Logic XDEC Page Latches I/O SCL YDEC SDA Sense Amp. R/W Control VCC VSS Package Types SOIC, TSSOP PDIP, MSOP A0 1 8 VCC A0 1 8 VCC A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL VSS 4 5 SDA VSS 4 5 SDA SOT-23-5 SCL 1 TDFN 5 WP A0 1 A1 2 *24XX16H is used in this document as a generic part number for the 24AA16H/24LC16BH devices. © 2008 Microchip Technology Inc. EEPROM Array Vss 2 SDA 3 Note: A2 3 VSS 4 4 8 VCC 7 WP 6 SCL 5 SDA Vcc Pins A0, A1 and A2 are not used by the 24XX08. (No internal connections). DS22118A-page 1 24AA16H/24LC16BH 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. Symbol No. Characteristic VCC = +1.7V to +5.5V Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Min. Typ. Max. Units Conditions D1 VIH WP, SCL and SDA pins — — — — — D2 — High-level input voltage 0.7 VCC — — V — D3 VIL Low-level input voltage D4 VHYS Hysteresis of Schmitt Trigger inputs D5 VOL D6 — — 0.3 VCC V — 0.05 VCC — — V (Note) Low-level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V ILI Input leakage current — — ±1 μA VIN = VSS or VCC D7 ILO Output leakage current — — ±1 μA VOUT = VSS or VCC D8 CIN, COUT Pin capacitance (all inputs/outputs) — — 10 pF VCC = 5.0V (Note) TA = 25°C, FCLK = 1 MHz D9 ICC write Operating current — 0.1 3 mA VCC = 5.5V, SCL = 400 kHz D10 ICC read D11 ICCS Note: Standby current — 0.05 1 mA — — — 0.01 — 1 5 μA μA Industrial Automotive SDA = SCL = VCC WP = VSS This parameter is periodically sampled and not 100% tested. DS22118A-page 2 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH TABLE 1-2: AC CHARACTERISTICS Industrial (I): Automotive (E): AC CHARACTERISTICS Param. Symbol No. Characteristic TA = -40°C to +85°C, VCC = +1.7V to +5.5V TA = -40°C to +125°C, VCC = +2.5V to +5.5V Min. Max. Units Conditions 1 FCLK Clock Frequency — — 400 100 kHz kHz 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 2 THIGH Clock High Time 600 4000 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 3 TLOW Clock Low Time 1300 4700 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 4 TR SDA and SCL Rise Time (Note 1) — — 300 1000 ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 5 TF SDA and SCL Fall Time — 300 ns (Note 1) 6 THD:STA Start Condition Hold Time 600 4000 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 7 TSU:STA Start Condition Setup Time 600 4700 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 8 THD:DAT Data Input Hold Time 0 — ns (Note 2) 9 TSU:DAT Data Input Setup Time 100 250 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 10 TSU:STO Stop Condition Setup Time 600 4000 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 11 TSU:WP WP Setup Time 600 4000 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 12 THD:WP WP Hold Time 1300 4700 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 13 TAA Output Valid from Clock (Note 2) — — 900 3500 ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 1300 4700 — — ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 15 TOF Output Fall Time from VIH Minimum to VIL Maximum — — 250 250 ns ns 2.5V ≤ VCC ≤ 5.5V 1.7V ≤ VCC < 2.5V (24AA16H) 16 TSP Input Filter Spike Suppression (SDA and SCL pins) — 50 ns (Notes 1 and 3) 17 TWC Write Cycle Time (byte or page) — 5 ms — 18 — Endurance 1M — Note 1: 2: 3: 4: cycles 25°C, (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained on Microchip’s web site at www.microchip.com. © 2008 Microchip Technology Inc. DS22118A-page 3 24AA16H/24LC16BH FIGURE 1-1: BUS TIMING DATA 5 SCL SDA IN 7 3 4 D4 2 8 10 9 6 16 14 13 SDA OUT WP DS22118A-page 4 (protected) (unprotected) 11 12 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH 2.0 FUNCTIONAL DESCRIPTION The 24XX16H supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX16H works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 3.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 3-1: (A) Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first-in firstout (FIFO) fashion. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: Bus Not Busy (A) Both data and clock lines remain high. 3.2 3.4 The 24XX16H does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX16H) will leave the data line high to enable the master to generate the Stop condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA © 2008 Microchip Technology Inc. Data Allowed to Change Stop Condition DS22118A-page 5 24AA16H/24LC16BH 3.6 FIGURE 3-2: Device Addressing A control byte is the first byte received following the Start condition from the master device (Figure 3-2). The control byte consists of a four-bit control code. For the 24XX16H, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the block-select bits (B2, B1, B0). They are used by the master device to select which of the eight 256 wordblocks of memory are to be accessed. These bits are in effect the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to ‘1’ a read operation is selected. When set to ‘0’ a write operation is selected. Following the Start condition, the 24XX16H monitors the SDA bus, checking the device type identifier being transmitted and, upon receiving a ‘1010’ code, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX16H will select a read or write operation. Operation Control Code Block Select R/W Read 1010 Block Address 1 1010 Block Address 0 Write DS22118A-page 6 CONTROL BYTE ALLOCATION Read/Write Bit Control Code S 1 0 1 0 Block Select Bits B2 B1 B0 R/W ACK Slave Address Start Bit Acknowledge Bit © 2008 Microchip Technology Inc. 24AA16H/24LC16BH 4.0 WRITE OPERATION 4.1 Byte Write 4.2 The write control byte, word address and the first data byte are transmitted to the 24XX16H in the same way as in a byte write. However, instead of generating a Stop condition, the master transmits up to 16 data bytes to the 24XX16H, which are temporarily stored in the onchip page buffer and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the four lower-order Address Pointer bits are internally incremented by ‘1’. The higher-order 7 bits of the word address remain constant. If the master should transmit more than 16 words prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 4-2). Following the Start condition from the master, the device code (4 bits), the block address (3 bits) and the R/W bit, which is a logic-low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow once it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24XX16H. After receiving another Acknowledge signal from the 24XX16H, the master device will transmit the data word to be written into the addressed memory location. The 24XX16H acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and, during this time, the 24XX16H will not generate Acknowledge signals (Figure 4-1). FIGURE 4-1: Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page-size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. BYTE WRITE Bus Activity Master S T A R T SDA Line S 1 0 1 0 B2 B1 B0 0 Control Byte Bus Activity FIGURE 4-2: Page Write Word Address Block Select Bits S T O P Data P A C K A C K A C K PAGE WRITE Bus Activity Master S T A R T SDA Line S 1 0 1 0 B2B1B00 Word Address (n) Control Byte Bus Activity © 2008 Microchip Technology Inc. Block Select Bits Data (n + 1) Data (n) S T O P Data (n + 15) P A C K A C K A C K A C K A C K DS22118A-page 7 24AA16H/24LC16BH 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 5-1 for a flow diagram of this operation. FIGURE 5-1: 6.0 WRITE PROTECTION The WP pin allows the user to write-protect half of the array (400h-7FFh) when the pin is tied to VCC. If the pin is tied to VSS the write protection is disabled. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation DS22118A-page 8 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH 7.0 READ OPERATION 7.3 Sequential Read Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. Sequential reads are initiated in the same way as a random read, except that once the 24XX16H transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24XX16H to transmit the next sequentiallyaddressed 8-bit word (Figure 7-3). 7.1 To provide sequential reads, the 24XX16H contains an internal Address Pointer that is incremented by one upon completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. Current Address Read The 24XX16H contains an address counter that maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to ‘1’, the 24XX16H issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24XX16H discontinues transmission (Figure 7-1). 7.2 7.4 Noise Protection The 24XX16H employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5V at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24XX16H as part of a write operation. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX16H will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24XX16H will discontinue transmission (Figure 7-2). FIGURE 7-1: CURRENT ADDRESS READ Bus Activity Master S T A R T SDA Line S 1 0 1 0 B2 B1 B0 1 Bus Activity © 2008 Microchip Technology Inc. Control Byte Block Select Bits S T O P Data (n) P A C K N o A C K DS22118A-page 9 24AA16H/24LC16BH FIGURE 7-2: Bus Activity Master SDA Line RANDOM READ S T Control A Byte R T S 1 0 1 0 B2B1B0 0 FIGURE 7-3: Bus Activity Master SDA Line Bus Activity DS22118A-page 10 Control Byte S T O P P Data (n) S 1 0 1 0B2B1B01 A C K A Block C Select K Bits Bus Activity S T A R T Word Address (n) A Block C Select K Bits N o A C K SEQUENTIAL READ Control Byte Data (n) Data (n + 1) Data (n + 2) S T O P Data (n + X) P 1 A C K A C K A C K A C K N o A C K © 2008 Microchip Technology Inc. 24AA16H/24LC16BH 8.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 8-1. TABLE 8-1: PIN FUNCTION TABLE Name PDIP SOIC TSSOP TDFN MSOP SOT-23 A0 1 1 1 1 1 — Not Connected A1 2 2 2 2 2 — Not Connected 8.1 A2 3 3 3 3 3 — Not Connected VSS 4 4 4 4 4 2 Ground SDA 5 5 5 5 5 3 Serial Address/Data I/O SCL 6 6 6 6 6 1 Serial Clock WP 7 7 7 7 7 5 Write-Protect Input VCC 8 8 8 8 8 4 +1.7V to 5.5V Power Supply Serial Address/Data Input/Output (SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an opendrain terminal, the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating Start and Stop conditions. 8.2 Description Serial Clock (SCL) 8.3 Write-Protect (WP) The WP pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory 000h-7FFh). If tied to VCC, write operations are inhibited, half of the memory will be write-protected (400h-7FFh). Read operations are not affected. 8.4 A0, A1, A2 The A0, A1 and A2 pins are not used by the 24XX16H. They may be left floating or tied to either VSS or VCC. The SCL input is used to synchronize the data transfer to and from the device. © 2008 Microchip Technology Inc. DS22118A-page 11 24AA16H/24LC16BH 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXX T/XXYYWW NNN 8-Lead TSSOP 24LC16BH I/P e3 13F 0827 Example: 24L16BHI SN e3 0827 13F Example: XXXX 4L6H TYWW I827 NNN 13F 8-Lead MSOP Example: XXXXXT YWWNNN 4L16HI 82713F 5-Lead SOT-23 Example: XXNN 8-Lead 2x3 TDFN XXX YWW NN DS22118A-page 12 Example: 5QNN Example: AG4 827 13 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH 1st Line Marking MSOP Part No. SOT-23 TDFN TSSOP I-Temp E-Temp I-Temp E-Temp I-Temp E-Temp 24AA16H 4A6H 4A16HI — BWNN — AG1 — 24LC16BH 4L6H 4L16HI 4L16HE 5QNN 5RNN AG4 AS5 Legend: XX...X T Y YY WW NNN e3 Note: Note: Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. © 2008 Microchip Technology Inc. DS22118A-page 13 24AA16H/24LC16BH 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 9'&! 7"') %! 7,8. 7 7 7: ; < & & & = = ##44!! - 1!& & = = "#& "#>#& . - - ##4>#& . < : 9& -< -? & & 9 - 9#4!! < ) ? ) < 1 = = 69#>#& 9 *9#>#& : *+ 1, - !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#/!# '! #& .0 1,21!'! &$& "! **& "&& ! * ,<1 DS22118A-page 14 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH ! ""#$%& !' 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 6&! '! 9'&! 7"') %! β 99.. 7 7 7: ; < & : 8& = 1, = ##44!! = = &# %%+ = : >#& . ##4>#& . -1, : 9& 1, ?1, ,'%@ & A = 3 &9& 9 = 3 && 9 .3 3 & I B = <B 9#4!! = 9#>#& ) - = #%& D B = B #%&1 && ' E B = B !"#$%&"' ()"&'"!&) &#*&&&# +%&,&!& - '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,1 © 2008 Microchip Technology Inc. DS22118A-page 15 24AA16H/24LC16BH ! ""#$%& !' 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 DS22118A-page 16 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH () )"* ! (+%+( ! 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; < & : 8& = ?1, = ##44!! < &# %% = : >#& . ##4>#& . - ?1, ##49& - - 3 &9& 9 ? 3 && 9 .3 3 & I B = <B 9#4!! = 9#>#& ) = - !"#$%&"' ()"&'"!&) &#*&&&# '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,<?1 © 2008 Microchip Technology Inc. DS22118A-page 17 24AA16H/24LC16BH ," ! *-, , ! 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 D N E E1 NOTE 1 1 2 e b A2 A c φ L L1 A1 6&! '! 9'&! 7"') %! 99.. 7 7 7: ; < & : 8& = ?1, = ##44!! < &# %% = : >#& . ##4>#& . -1, : 9& -1, 3 &9& 9 3 && 9 1, ? < .3 3 & B = <B 9#4!! < = - 9#>#& ) = !"#$%&"' ()"&'"!&) &#*&&&# '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# - '! #& .0 1,2 1!'! &$& "! **& "&& ! .32 %'! ("!"*& "&& (% % '& " !! * ,1 DS22118A-page 18 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH . ! (""!( !(/ 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 b N E E1 3 2 1 e e1 D A2 A c φ A1 L L1 6&! '! 9'&! 7"') %! 99.. 7 7: ; 7 9#& 1, :"&!#9#& : 8& = ##44!! < = - &# %% = : >#& . = - ##4>#& . - = < : 9& = - 1, 3 &9& 9 = ? 3 && 9 - = < 3 & B = -B 9#4!! < = ? 9#>#& ) = '! !#.# &"#' #%! &"! ! #%! &"! !! &$#''!# '! #& .0 1,2 1!'! &$& "! **& "&& ! * ,1 © 2008 Microchip Technology Inc. DS22118A-page 19 24AA16H/24LC16BH 0 $*-,/11%2.(0 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 DS22118A-page 20 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH 0 $*-,/11%2.(0 3 &' !&"&4#*!(!!& 4%& &#& &&255***' '54 © 2008 Microchip Technology Inc. DS22118A-page 21 24AA16H/24LC16BH APPENDIX A: REVISION HISTORY Revision A (11/2008) Original release. DS22118A-page 22 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2008 Microchip Technology Inc. DS22118A-page 23 24AA16H/24LC16BH READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y Device: 24AA16H/24LC16BH N Literature Number: DS22118A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS22118A-page 24 © 2008 Microchip Technology Inc. 24AA16H/24LC16BH PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device: X Note 1: Examples: Temperature Package Range I2C 24AA16H = 1.7V, 16 Kbit Serial EEPROM 24AA16HT = 1.7V, 16 Kbit I2C Serial EEPROM (Tape and Reel) 24LC16BH = 2.5V, 16 Kbit I2C Serial EEPROM 24LC16BHT= 2.5V, 16 Kbit I2C Serial EEPROM (Tape and Reel) Temperature I Range: E Package: /XX = = P SN ST MNY(1) = = = = MS OT = = -40°C to +85°C -40°C to +125°C a) 24AA16H-I/P: Industrial Temperature,1.7V, PDIP package b) 24AA16H-I/SN: Industrial Temperature,1.7V, SOIC package c) 24AA16HT-I/OT: Industrial Temperature, 1.7V, SOT-23 package, Tape and Reel d) 24LC16BH-I/P: Industrial Temperature, 2.5V, PDIP package e) 24LC16BH-E/SN: Automotive Temp.,2.5V SOIC package f) 24LC16BHT-I/OT: Industrial Temperature, 2.5V, SOT-23 package, Tape and Reel Plastic DIP (300 mil body), 8-lead Plastic SOIC (3.90 mm body), 8-lead Plastic TSSOP (4.4 mm), 8-lead Plastic Dual Flat (TDFN), No lead package, 2x3 mm body, 8-lead Plastic Micro Small Outline (MSOP), 8-lead SOT-23, 5-lead (Tape and Reel only) “Y” indicates a Nickel Palladium Gold (NiPdAu) finish. © 2008 Microchip Technology Inc. DS22118A-page 25 24AA16H/24LC16BH NOTES: DS22118A-page 26 © 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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