Data Sheet

Powerline Modules
Low Power Embedded HomePlug® AV Modules
FEATURES
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Based on Qualcomm Atheros
AR6400/AR1400 chipset
Supports HomePlug® AV Standard with
data rates of 200Mbps
Temperature rated for industrial
applications
MII (Host & PHY) interface
Supports1024/256/64/16/8-QAM, QPSK,
BPSK, and ROBO modulation schemes
128-bit AES Link Encryption with key
management for secure power line
communications
Windowed OFDM with noise mitigation
based on patented line synchronization
techniques improves data integrity in
noisy conditions
Dynamic channel adaptation and channel
estimation maximizes throughput in
harsh channel conditions
Advanced turbo code forward error
correction
ToS, CoS and IP port number packet
classifiers
Supports IGMP managed multicast
sessions
Green standard (ROHS) compliant
GPIO second function as general data
lines
Horizontal mounting configuration using
standard 1.27mm pin header
Integrates all components necessary to
add HomePlug AV functionality to any
embedded system at low cost
APPLICATIONS
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Over-the-Top Video
Retail Adapters
Telco / IPTV
Smart Grid
Ethernet-over-Powerline (PLC) and Multi-Dwelling
Unit (MDU) applications
Part Number
Mount
Temp Range
0804-5000-17
Vertical
0 - 70°C
0804-5000-18
Horizontal
0 - 70°C
0804-5000-24
Horizontal
-40 - +85°C
Including Heatsink
In Partnership with
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
CORPORATE
ASIA
EUROPE
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel 201-432-0463
Fax 201-432-9542
www.belfuse.com
Bel Fuse Ltd.
8F / 8 Luk Hop Street
San Po Kong
Kowloon, Hong Kong
Tel 852-2328-5515
Fax 852-2352-3706
www.belfuse.com
Bel Integrated Modules
28 Turkey Court, Turkey Mill
Ashford Road
Maidstone, Kent ME14 5PP U.K.
Tel 44-1622-757395
Fax 44-1622-663252
www.belfuse.com
1
Powerline Modules
Low Power Embedded HomePlug® AV Modules
MODULE BLOCK DIAGRAM
GPIO
LEDs AND
CONFIG
MII
(MDI)
DAC
M
A
C
BPF
TX
PLC
COUPLER
P
H
Y
BPF
ADC
AR1400
RX
ZERO CROSS
DETECTOR
AR6400
RESET
FLASH
SYS CLK
3.3V
DC
CXO
PLL
RAM
DC-DC
1V 11.2V
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
2
Powerline Modules
Low Power Embedded HomePlug® AV Modules
PRESENTATION
The Bel Single In-line Package (SIP) module is a HomePlug AV, open- standard-based
MAC/PHY/AFE Powerline Communications (PLC) transceiver. The module is available in both
industrial and commercial temperature-rated variants.
The module enables the development of HD-grade communication bridges, to and from the
Powerline. It also serves as a translator between the digital and analogue worlds. On the digital
side, host interfaces include: Ethernet MII Host or PHY. The data received and transmitted is
translated by the AR6400 to and from a complex analogue signal which is modulated on multiple
carriers and transmitted over the AC wiring.
MODULE INTERFACE
Pin I/O Table
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1.
2.
Pin Name
VDD
VSS
VDD
VSS
VDD
TX+
TXVSS
RX+
RXRESET/
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
ZC_IN
MDIO
Pin Number
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Pin Name
MDC
(0)
Reserved
(2)
Reserved
VSS
MRX_D0
MRX_D1
MRX_D2
MRX_D3
COL
MRX_CLK
VSS
MRX_ERR
MRX_DV
MTX_D0
MTX_D1
MTX_D2
MTX_D3
CRS
MTX_CLK
MTX_EN
VSS
PHY_RST/
VSS
PHY_CLK
VSS
Pin 27: Internally connected and reserved for future use. Do not connect externally.
Pin 28: Internally connected and reserved for future use. Required connection to Ground.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
3
Powerline Modules
Low Power Embedded HomePlug® AV Modules
SYSTEM BLOCK DIAGRAM
Reset
Power
MII (MAC or
PHY mode)
Coupling
Interface
Mains
MAINS
COUPLER
PHY DEVICE
POWERLINE
MODULE
OR
MDI
MAC
CONTROLLER
PHY utility
ZERO
CROSS
DETECTOR
GPIO
The block diagram presents the powerline module in a typical environment. Eight different types of
interfaces are shown. These interfaces are described in detail below.
Media Independent Interface (MII)
The MII interface is configured as either an Ethernet Medium Access Controller (MAC) or a
Physical Medium Dependent (PMD or PHY) controller. Medium Independent Interface (MII) is an
industry standard, multi-vendor interface between the MAC and PHY sub-layers. It provides a
simple connection between Ethernet PHY controllers and IEEE802.3 Ethernet MACs from a variety
of sources.
MII consists of separate 4-bit data paths for transmit and receive data along with carrier sense and
collision detection. Further details of the MII are available from the IEEE 802.3u Standard.
Configuration straps described in Section 3 set the MII operation to a MAC or PHY controller. The
MAC and PHY configurations support 10 Mbps or 100 Mbps in half-duplex or full-duplex modes
and flow control for half-duplex and full-duplex connections. The Ethernet MAC module implements
standard Ethernet MAC functionality. The Ethernet MAC is connected to an external Ethernet PHY
function. The MAC configuration provides bridging between Ethernet and the powerline. The PHY
configuration emulates Ethernet PHY functionality and provides HomePlug AV connectivity to
devices designed to communicate over an Ethernet network.
The MII (Ethernet) interface has separate transmit and receive packet buffering. When operating
as a MAC the MII transmit FIFO is 2 KB and the receive FIFO is 8 KB. When operating as a PHY
controller, the MII transmit FIFO is 8 KB and the receive FIFO is 2 KB.
MII MAC
The MII MAC configuration operates as an IEEE 802.3 10/100-Mbps Ethernet MAC connected to
an external 10/100-Mbps Ethernet PHY.
When the Power line module boots it attempts to configure the MII MAC interface, it will first scan
all external MII PHY’s starting from PHY #0 and will select the first PHY that responds with valid
register contents.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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Powerline Modules
Low Power Embedded HomePlug® AV Modules
The PHY’s Link Status register will be read, and if the link is up, auto-negotiation will be performed.
If the PHY’s status indicates that auto-negotiation is not supported, auto-negotiation will not be
performed.
Based upon the results of the PHY’s status registers, or auto-negotiation results, the PHY will be
configured in an operational mode (i.e. no loopback, no collision test, not in isolate, etc.). The MII
MAC within the Power line module will be configured for the same speed and duplex. External
devices do not have direct access to any MII MAC registers in the AR6400.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
5
Powerline Modules
Low Power Embedded HomePlug® AV Modules
MII PHY
The MII PHY emulation hardware connects to an external 10/100-Mbps Ethernet MAC. The default
PHY functionality is configured through standard management data interface communications (MDI
interface) and may be overridden by the AR6400 MAC firmware access to the PHY emulation
registers. The interface supports the standard control and status register.
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Link speed at 10 Mbps or 100 Mbps
Full-duplex or half-duplex operation
Management data interface base address
Isolate to disconnect the PHY from the MII port
In MII PHY mode, auto-negotiation is not supported. GPIO Strapping on the Power line module will
determine the desired configuration, these straps will be reflected in the default settings in the MII
PHY Emulation registers.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
6
Powerline Modules
Low Power Embedded HomePlug® AV Modules
MII Signals
I/O
Pin
Pin Name MAC PHY
Number
Mode Mode
30
31
32
33
MRX_D0
MRX_D1
MRX_D2
MRX_D3
I
O
34
COL
I
O
35
MRX_CLK
I
O
37
MRX_ERR
I
O
38
MRX_DV
39
MTX_D0
40
MTX_D1
41
MTX_D2
42
MTX_D3
43
CRS
I
O
I
Description
MII Receive Data. The PHY controller drives MRX_D[3:0] and the
MAC core receives MRX_D[3:0]. MRX_D[3:0] transitions
synchronously with respect to MRX_CLK. For each MRX_CLK period
in which MRX_DV is asserted, MRX_D[3:0] is valid. MRX_D0 is the
least-significant bit. The PHY controller tri-states MRX_D[3:0] in isolate
mode.
MII Collision Detected. The PHY controller asserts COL when it
detects a collision on the medium. COL remains asserted while the
collision condition persists. COL signal transitions are not synchronous
to either the MTX_CLK or the MRX_CLK. The MAC core ignores the
COL signal when operating in the full-duplex mode. The PHY
controller tristates COL in isolate mode.
MII Receive Clock. MRX_CLK is a continuous clock that provides the
timing reference for the transfer of the MRX_DV and MRX_D[3:0]
signals from the PHY controller to the MAC core. The PHY controller
sources MRX_CLK. MRX_CLK frequency is equal to 25% of the data
rate of the received signal on the Ethernet cable. The PHY controller
tri-states MRX_CLK in isolate mode.
MII Receive Error. The PHY controller asserts MRX_ERR high for
one or more MRX_ CLK periods to indicate to the MAC core that an
error (a coding error or any error that the PHY is capable of detecting
that is otherwise undetectable by the MAC) was detected somewhere
in the current frame. MRX_ERR transitions synchronously with respect
to MRX_CLK. While MRX_DV is de-asserted, MRX_ERR has no
effect on the MAC core. The PHY controller tri-states MRX_ERR in
isolate mode.
O
MII Receive Data Valid. The PHY controller asserts MRX_DV to
indicate to the MAC core that it is presenting the recovered and
decoded data bits on MRX_D[3:0] and that the data on MRX_D[3:0] is
synchronous to MRX_CLK. MRX_DV transitions synchronously with
respect to MRX_CLK. MRX_DV remains asserted continuously from
the first recovered nibble of the frame through the final recovered
nibble, and is de-asserted prior to the first MRX_CLK that follows the
final nibble. The PHY controller tri-states MRX_DV in isolate mode.
I
MII Transmit Data. The MAC core drives MTX_D[3:0] and the PHY
controller receives MTX_D[3:0]. MTX_D[3:0] transitions synchronously
with respect to MTX_CLK. For each MTX_CLK period in which
MTX_EN is asserted, MTX_D[3:0] is valid. MTX_D0 is the least
significant bit. The PHY controller ignores MTX_D[3:0] in isolate mode.
O
MII Carrier Sense. The PHY controller asserts CRS when either
transmit or receive medium is non-idle. The PHY de-asserts CRS
when both transmit and receive medium are idle. The PHY must
ensure that CRS remains asserted throughout the duration of a
collision condition. The transitions on the CRS signal are not
synchronous to either the MTX_CLK or the MRX_CLK. The PHY
controller tri-states CRS in isolate mode.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
7
Powerline Modules
Low Power Embedded HomePlug® AV Modules
44
45
MTX_CLK
MTX_EN
I
O
O
MII Transmit Clock. MTX_CLK is a continuous clock that provides a
timing reference for the transfer of the MTX_EN and MTX_D[3:0]
signals from the MAC core to the PHY controller. The PHY controller
sources MTX_CLK. The operating frequency of MTX_CLK is 25 MHz
when operating at 100 Mbps and 2.5 MHz when operating at 10 Mbps.
The PHY controller tri-states MTX_CLK in isolate mode.
I
MII Transmit Enable. A high assertion on MTX_EN indicates that the
MAC core is presenting nibbles to the PHY controller for transmission.
The AR6400 MAC core asserts MTX_EN with the first nibble of the
preamble and keeps MTX_EN asserted while all nibbles to be
transmitted are presented to the MII. MTX_EN is de-asserted prior to
the first MTX_CLK following the final nibble of the frame. MTX_EN
transitions synchronously with respect to MTX_CLK. The PHY
controller ignores MTX_EN in isolate mode.
Special care must be taken during PCB layout of the MII bus. Keep MII signal traces as short as possible and preferably on inner PCB
layers.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
8
Powerline Modules
Low Power Embedded HomePlug® AV Modules
MII Management Data Interface (MDI)
Pin
Number
I/O
Pin Name
MAC
Mode
Description
PHY
Mode
25
MDIO
I/O
I/O
26
MDC
O
I
MII Management Data In/Out. This is the data input signal
from the PHY controller. The PHY drives the Read Data
synchronously with respect to the MDC clock during the read
cycles. This is also the data output signal from the MAC core
that drives the control information during the Read/Write cycles
to the PHY controller. The MAC core drives the MDO signal
synchronously with respect to the MDC. An external pull-up
resistor is needed on this pin.
MII Management Data Clock. The MAC core sources MDC as
the timing reference for transfer of information on the MDIO
signal. MDC signal has no maximum high or low times. MDC
minimum high and low times are 160 ns each, and the
minimum period for MDC is 400 ns.
The MII interface has a two-wires bi-directional serial Management Data Interface (MDI). This
interface provides access to the status and control registers in the Ethernet PHY logic. The MII
and MDI pins are shared between the MAC and PHY interfaces.
General Purpose Input/Output (GPIO) Pins Interface
General Purpose I/O pins are software programmable inputs or outputs, which can also be used as
an external interrupt source. As indicated in the table below, some of these GPIO signals also have
additional functionality as configuration straps. See section 3 for configuration options.
Pin Number
Pin Name
Configuration Strap
Function
I/O*
Internal Pull Up/Down
12
GPIO0
N/A
S.C.
Up
13
GPIO1
N/A
S.C.
Up
14
GPIO2
N/A
S.C.
Up
15
GPIO3
ISODEF
S.C.
Up
16
GPIO4
SPEED
S.C.
Up
17
GPIO5
MD_A3
S.C.
Up
18
GPIO6
CFG_SEL
S.C.
Down
19
GPIO7
MD_A4
S.C.
Down
20
GPIO8
MP_SEL
S.C.
Up
21
GPIO9
N/A
S.C.
Down
22
GPIO10
BM_SEL
S.C.
Down
23
GPIO11
N/A
S.C.
Down
* S. C. = software configurable.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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Powerline Modules
Low Power Embedded HomePlug® AV Modules
In addition to their configuration strap function, the GPIOs can perform some software
configurable functions after reset. The default configuration provided by Bel Fuse is as shown in
the chart that follows.
GPIO
I/O
GPIO0
O
GPIO1
I
GPIO2
I
GPIO[3..7]
O
1.
2.
GPIO8
O
GPIO9
O
GPIO10
O
GPIO11
O
Default function after reset
Not Used (HiZ)
Typically connected to a push-button. This GPIO is used to add a new device
to, or remove an old device from, a HomePlug AC logical network. Contact Bel
Fuse for further information.
Typically connected to a push-button. The factory default PIB can be restored
by applying a low-level digital voltage on GPIO2 for greater than 0.5 seconds
and less than 3.0 seconds.
Not Used (HiZ)
To be connected to an LED. The LED gives indications about Power line Link &
activity:
On: Powerline link detected.
(1)
Flash: TX or RX powerline activity .
Off: Powerline link not detected.
To be connected to an LED. The LED gives indications about Ethernet Link &
activity:
On: Ethernet link detected.
Flash: Transmit or receive activity.
Off: No link detected.
To be connected to an LED. The LED gives indications about Power line mode:
On: HomePlug 1.0 traffic detected
Flash: N/A
Off: Silence
To be connected to an LED. The LED gives indication about Power:
On: Power ready
(2)
Flash: Load firmware
Off: Power not ready
The Power line Link LED indicator turns On when powerline link is detected. If the AR6400 module is serving as a STATION (STA), the LED
indicator will flash to indicate transmit or receive powerline activity. If the INT6400 module is serving as a CCO (central coordinator), the LED
indicator will light steadily ON, even in the presence of powerline activity.
If module flash memory is corrupted/blank or a host processor does not provide FW, the module ROM based code will blink the POWER LED
On and Off at a frequency of one cycle per second.
PHY Utility Interface
Pin
Number
Pin Name
I/O
Description
47
PHY_RST/
O
PHY device Reset (active low). Connect to an external Ethernet
PHY. This reset output is a stretched version of the RESET/
input.
O
25MHz Clock Out. This output is a dedicated clock output that
can be used to drive the clock input on an external Ethernet
PHY. This clock output is only available when the AR6400 is
configured in MAC mode, and not in PHY mode of operation.
Note that if this output is used, it is strongly advised that the
corresponding PHY_RST/ signal also be connected to the
external Ethernet PHY.
49
PHY_CLK
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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Powerline Modules
Low Power Embedded HomePlug® AV Modules
Coupling Interface
Pin Number
Pin Name
I/O
Description
6
TX+
O
Differential TX Line Driver output, connects to coupling
transformer
7
TX-
O
Differential TX Line Driver output, connects to coupling
transformer
9
RX+
I
Differential RX Line Filter input, connects to coupling
transformer
10
RX-
I
Differential RX Line Filter input, connects to coupling
transformer
Special care must be taken during PCB layout of the coupling interface signals.
Route differential pairs close together and away from all other signals. Route each differential
pair on the same PCB layer. Keep both traces of each differential pair as identical to each other
as possible.
Wide copper is needed here to support current density of up to 30MHz. These high frequencies
result in higher resistance due to skin effect. The wide traces also accommodate high transient
currents caused by voltage spikes. Trace widths between the Module and the coupling
transformer must be no less than 0.020” (0.5 mm) and should be no greater than 0.030” (0.75
mm).
Use of the Bel Fuse 0557-7700-36, 0557-7700-40, 0557-7700-41 or 0557-7700-42 powerline
couplers is recommended. Details can be found in their associated datasheets.
Reset Interface
Pin
Number
11
Pin Name
I/O
RESET/
I
Description
Resets all IC logic when low. Maintain this signal active for 100 ms after
the VDD rail is stable.
Zero-Crossing Interface
Pin
Number
24
Pin
Name
ZC_IN
I/O
Description
I
Zero Cross Detector Input. The zero cross detector provides a logic level
signal with safety isolation that corresponds to the polarity of the AC power
line waveform. This information synchronizes the channel adaptation of the
AR6400 to the line cycle periodic noise present on the power line.
Power Interface
Pin Number
Pin Name
I/O
Description
1, 3, 5
VDD
I
+3.3V with respect to VSS
2, 4, 8, 29, 36, 46, 48, 50
VSS
I
Ground
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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Powerline Modules
Low Power Embedded HomePlug® AV Modules
CONFIGURATION OPTIONS
The AR6400 MII and boot options are selected by the initial condition of GPIO pins. If a GPIO pin
is not used and its internal strapping resistor sets the booting option correctly, then the pin may
be left unconnected. If a GPIO pin is not used but the internal strapping resistor sets the booting
option incorrectly, then the pin must be pulled high or low to the correct booting option by an
external resistor. This resistor can be 10 k-Ohms down to a few hundred Ohms. 3.3 k-Ohms is
typical. Many GPIO pins are driven by firmware for LED output immediately after boot up so
connecting these GPIO directly to ground or VDD is not permitted.
Pin Number
Pin Name
Strap
Function
Internal Pull
Up/Down
Default Function
15
GPIO3
ISODEF
Up
PHY MODE: Hi-Z MII interface
16
GPIO4
SPEED
Up
PHY MODE: 100Mbps
17
GPIO5
MD_A3
Up
PHY MODE: PHY Address
0x0100
18
GPIO6
CFG_SEL
Down
BOOT: SDRAM parameters
from Host
19
GPIO7
MD_A4
Down
PHY MODE: PHY address
0x0100
20
GPIO8
MP_SEL
Up
22
GPIO10
BM_SEL
Down
49
PHY_CLK
DUPLEX
Up
HOST: MAC mode
BOOT: Firmware From Host
PHY MODE: Full Duplex
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
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Powerline Modules
Low Power Embedded HomePlug® AV Modules
MII Options
The MP_SEL strap is used to specify whether the AR6400 chip is configured for MII MAC mode, or
in MII PHY mode (i.e. reverse-MII mode). The encoding of this signal is shown in the following
table:
MP_SEL
Mode
0
1
MII in PHY mode
MII in MAC mode
In MII PHY mode, there are 5 additional configuration straps that are unique to this mode of
operation.
SPEED
MII Speed
DUPLEX
MII Duplex
0
1
10Mbps
100Mbps
0
1
Half Duplex
Full Duplex
ISODEF
Isolation
MD_A[3,4]
MII Management address
0
1
Normal Operation
Isolated
00
01
10
11
0x00
0x08
0x10
0x18
Boot Options
BM_SEL
CFG_SEL
Meaning
0
0
Load SDRAM configuration and boot code from external host
0
1
Load SDRAM configuration applet from Flash, and then load boot code
from external host
1
0
Not supported
1
1
Load SDRAM configuration and boot code from Flash
The BM_SEL strap is used to determine the source of the boot code for the embedded ARM
processor. Similarly, the CFG_SEL strap is used to determine the source of the SDRAM
configuration applet. The encodings for these two signals are shown in the following table.
DESIGN NOTES





Leave below lines unconnected if they are not unused:
 Pin 47: PHY_RST#
 Pin 49: PHY_CLK
 Pin 27: Reserved
Connect Pin 28 (Reserved) signal to the Ground.
Zero-cross Detection circuit is not required for DC line connection, but to work correctly the
PLC Module requires a pull-up resistor (10k) on ZC_IN line
Do not force other logic levels than default during the module boot on reserved GPIO
Strapping’s, GPIO: 0-2 and 3.
When the Power line module is in PHY mode, RX_ER signal should not be connected to
the MII Bus. This line is NOT tri-stated. Use a 10K Ohm pull down resistor only.
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
13
Powerline Modules
Low Power Embedded HomePlug® AV Modules
FIRMWARE
The powerline module is supplied pre-programmed with the most recent firmware version and
default Parameter Information Block (PIB) for North America from Qualcomm Atheros. The PIB
contains the parameters used to configure the operation of the AR6400 chipset including:





Network Management Key (NMK),
MAC address
Device Access Key (DAK),
GPIO function after reset.
Tone bins suitable for North American use (Alternatives available)
This factory default PIB can be superseded by a customized User PIB using the Avitar PCbased application. A non disclosure agreement is required with Qualcomm Atheros to
access this tool.
ELECTRICAL CHARACTERISTICS
Symbol
VDD
Parameter
Test Conditions
Supply voltage (1)
VIL
Low-level input voltage
VIH
High-level input voltage
VOL
Low-level output voltage
VOH
High-level output voltage
Max
Units
3.0
3.6
V
0.8
V
2.0
IOL = 4 mA, 12 mA
(2)
IOH = -4 mA, -12
mA (3)
IIL
Low-level input current
VI = Gnd
IIH
High-level input current
VI = 3.3 V
IOZ
High-impedance output
current
Operating temperature
range
Gnd < VI < 3.3 V
Top
Min
V
0.4
V
2.4
V
-1
μA
1
μA
-1
+1
μA
-40
+85
°C
1. A typical supply current, assuming a nominal operation of 50% transmit and 50% receive duty cycle, is 580 mA.
2. IOL=12 mA for all GPIOs. IOL = 4 mA for all other digital interfaces.
3. IOH = -12 mA for all GPIOs. IOH = -4 mA for all other digital interfaces
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
14
Powerline Modules
Low Power Embedded HomePlug® AV Modules
MECHANICAL
0804-5000-17
Vertical Mount
0804-5000-18
Horizontal Mount
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
Bel Fuse Inc. 206 Van Vorst Street, Jersey City, NJ 07302 • Tel 201-432-0463 • Fax 201-432-9542 • www.belfuse.com
15
Powerline Modules
Low Power Embedded HomePlug® AV Modules
0804-5000-24
Horizontal Mount - Industrial Temperature with Heatsink
©2013 Bel Fuse Inc. Specifications subject to change without notice. 03.09.2013
CORPORATE
ASIA
EUROPE
Bel Fuse Inc.
206 Van Vorst Street
Jersey City, NJ 07302
Tel 201-432-0463
Fax 201-432-9542
www.belfuse.com
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8F / 8 Luk Hop Street
San Po Kong
Kowloon, Hong Kong
Tel 852-2328-5515
Fax 852-2352-3706
www.belfuse.com
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Ashford Road
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Tel 44-1622-757395
Fax 44-1622-663252
www.belfuse.com
16
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