R7780

R7780
Burst Triple Mode PWM Controller with Integrated HV
Start-up Device for Zero Power Monitor Application
General Description
The R7780 is a high-performance current mode PWM
controller with integrated HV start-up device inside. During
start-up, a current source through integrated HV device to
charge VDD capacitor for quick start-up while it dissipates
no loss in normal operation.
The R7780 provides the users a superior AC/DC power
application of higher efficiency, few external component
counts, and low cost solution. It features frequency jitter,
Under Voltage LockOut (UVLO), Leading Edge Blanking
(LEB), internal slope compensation in the tiny SOP-7
package. It offers complete protection coverage with Over
Temperature Protection (OTP), Over Load Protection (OLP)
and Over Voltage Protection (OVP).
Moreover, it also provides a special interface for zero power
application when the converter is in sleeping mode. EN/
DIS pin receives ON/OFF signal from secondary scalar
controller. During turning off, the controller will be shutdown
completely with pretty low power consumption.
Ordering Information
R7780
Features
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Applications
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Package Type
S : SOP-7
Integrated HV Start-up Device
Enable/Disable Function
UVLO: 9V/16.5V
Current Mode Control
Built-in 65kHz Operation Frequency
Built-in Jittering Frequency
Internal PWM Leading Edge Blanking
Internal Slope Compensation
Compensated Burst Triple Mode PWM
Cycle-by-Cycle Current Limit
Internal Auto Recovery OVP
Internal Auto Recovery OLP
Internal Auto Recovery OTP
CS Pin Open Protection
Secondary Rectifier Short Protection
Soft Driving for Reducing EMI Noise
High Noise Immunity
RoHS Compliant and Halogen Free
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Switching AC/DC Adaptor
TV and Monitor Application
Low Standby Power Home Appliance
Lead Plating System
G : Green (Halogen Free and Pb Free)
Pin Configurations
Note :
Richtek products are :
`
RoHS compliant and compatible with the current require-
(TOP VIEW)
ments of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
R7780GS : Product Number
R7780
GSYMDNN
R7780-01
8
EN/DIS
HV
COMP
2
7
CS
3
6
VDD
GND
4
5
GATE
SOP-7
YMDNN : Date Code
September 2011
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1
R7780
Typical Application Circuit
VO+
AC Mains
(90V to 265V)
#
VOR7780
1
EN/DIS
HV
VDD
8
6
#
LDO
OPTO1
2
COMP
GATE
4
OPTO2
GND
CS
5
#
3
OPTO1
GPIO
Scalar
# See Application Information
OPTO2
Functional Pin Description
Pin No.
Pin Name
Pin Description
1
EN/DIS
2
COMP
3
CS
Current Sensing.
4
GND
Ground.
5
GATE
Gate Drive Output to Drive the External MOSFET.
6
VDD
Power Supply Pin.
7
NC
No Internal Connection.
8
HV
700V High Voltage Device for Start-up.
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2
Enable/Disable Function.
Voltage Feedback. By connecting an opto-coupler to close control loop and
achieve the regulation.
R7780-01
September 2011
R7780
Function Block Diagram
HV
8
EN/DIS 1
6 VDD
OVP
Secondary Rectifier Short Protection
& CS Open Protection
2.6V Shutdown
+
Logic
+
-
OTP
UVLO
+
-
Brownout
Sensing
Bias &
Bandgap
COMP Open
Sensing
Oscillator
SS
Constant
Power
Dmax
Soft
Driver
S
COMP 2
Slope
Ramp
CS 3
R7780-01
September 2011
9/16.5V
Counter
OLP
LEB
28V
POR
X3
+
PWM
Comparator
5 GATE
Q
R
COMP
Burst Triple
Mode& TP
Compensation
VBURH
VBURL
VDD
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3
R7780
Absolute Maximum Ratings
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(Note 1)
HV Pin ------------------------------------------------------------------------------------------------------------------- −0.3V to 700V
Supply Input Voltage, VDD ------------------------------------------------------------------------------------------- −0.3V to 30V
GATE Pin ---------------------------------------------------------------------------------------------------------------- −0.3V to 20V
EN/DIS, COMP, CS Pin --------------------------------------------------------------------------------------------- −0.3V to 6.5V
Power Dissipation, PD @ TA = 85°C
SOP-7 -------------------------------------------------------------------------------------------------------------------- 0.625W
Package Thermal Resistance (Note 2)
SOP-7, θJA -------------------------------------------------------------------------------------------------------------- 160°C/W
Junction Temperature ------------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260°C
Storage Temperature Range ---------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
Human Body Mode (Except HV pin) ------------------------------------------------------------------------------ 6kV
Machine Mode ---------------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
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(Note 4)
Supply Input Voltage, VDD ------------------------------------------------------------------------------------------- 12V to 25V
Junction Temperature Range ---------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range ---------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VDD = 15V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VDD < VTH_ON , HV = 500V
1
--
--
mA
VDD = VTH_OFF, HV = 500V
--
--
25
μA
HV Section
HV Start-up Current
IJEFT_ST
Off State Leakage Current
VDD Section
On Threshold Voltage
VTH_ON
15.5
16.5
17.5
V
Off Threshold Voltage
VTH_OFF
8
9
10
V
VDD Zener Clamp Voltage
VZ
30
--
--
V
Operating Current
IDD_OP
VDD = 15V, 65kHz
COMP pin , GATE pin open
--
550
1000
μA
VDD Holdup Mode End Point
VDD_HIGH
VCOMP < 1.6V
--
10.5
--
V
VDD Holdup Mode Entry Point
VDD_LOW
VCOMP < 1.6V
--
10
--
V
VDD Over Voltage Protection Level
VOVP
27
28
29
V
To be continued
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4
R7780-01
September 2011
R7780
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Oscillator Section
Normal PWM Frequency
f OSC
60
65
70
kHz
Maximum Duty Cycle
DMAX
70
75
80
%
PWM Frequency Jitter Range
Δf
--
±7
--
%
PWM Frequency Jitter Period
TJIT
For 65kHz
--
4
--
ms
Frequency Variation Versus VDD
f DV
VDD = 12V to 25V
--
--
2
%
Frequency Variation Versus
Temperature
f DT
TA = −30°C to 105°C (Note 5)
--
--
5
%
5.5
5.75
6
V
5.25
--
--
V
--
56
--
ms
--
272
400
μA
0.67
0.7
0.73
V
COMP Input Section
Open-Loop Voltage
VCOMP_OP COMP pin open
COMP Open 56ms Protection
VCOMP_56
COMP Open-Loop Protection Delay
t OLP
Time
Short Circuit COMP Current
I ZERO
VCOMP = 0V
Current-Sense Section
Initial Current Limit Offset
VCSTH
Leading Edge Blanking Time
t LEB
(Note 6)
150
250
350
ns
Internal Propagation Delay Time
t PD
(Note 6)
--
100
--
ns
Minimum On Time
t ON (MIN)
250
350
450
ns
GATE Section
Gate Output Clamping Voltage
VCLAMP
VDD = 25V
--
14
--
V
Rising Time
tR
VDD = 15V, CL = 1nF
--
125
--
ns
Falling Time
tF
VDD = 15V, CL = 1nF
--
45
--
ns
0.8
1.05
1.3
V
--
--
30
μA
EN/DIS Interface Section
EN Threshold Voltage
VEN
EN/DIS Pin Max Clamping Current
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Note 6. Leading edge blanking time and internal propagation delay time are guaranteed by design.
R7780-01
September 2011
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5
R7780
Typical Operating Characteristics
Start-up Current (IDD_ST) vs. Temperature
HV Start-up Current (IJFET_ST) vs. Temperature
4.0
50
40
I JFET_ST (mA)
I DD_ST (µA)
3.0
30
20
2.0
1.0
10
0
0.0
0
40
80
120
-40
0
40
80
120
Temperature (°C)
Temperature (°C)
On Threshold Voltage (VTH_ON) vs. Temperature
Off Threshold Voltage (VTH_OFF) vs. Temperature
18.0
10.0
17.6
9.6
VTH_OFF (V)
VTH_ON (V)
-40
17.2
16.8
9.2
8.8
8.4
16.4
8.0
16.0
-40
0
40
80
120
-40
40
80
120
Temperature (°C)
Temperature (°C)
Normal PWM Frequency (fOSC) vs. VDD
Normal PWM Frequency (fOSC) vs. Temperature
68
68
66
66
f OSC (kHz)
f OSC (kHz)
0
64
62
60
64
62
60
58
58
-40
0
40
Temperature (°C)
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6
80
120
10
15
20
25
VDD (V)
R7780-01
September 2011
R7780
Gate Output Clamping Voltage (VCLAMP) vs. VDD
20
20
18
16
VCLAMP (V)
VCLAMP (V)
Gate Output Clamping Voltage (VCLAMP) vs. Temperature
16
14
12
8
4
12
0
10
-40
0
40
80
10
120
15
Temperature (°C)
Operating Current (IDD_OP) vs. VDD
Operating Current (IDD_OP) vs. Temperature
1000
COMP Pin Open,
GATE Pin Open
VDD = 15V,
COMP Pin Open,
GATE Pin Open
800
I DD_OP (µA)
I DD_OP (µA)
25
VDD (V)
1000
800
20
600
400
600
400
200
200
0
0
-40
0
40
80
10
120
15
20
25
VDD (V)
Temperature (°C)
Open-Loop Voltage (VCOMP_OP) vs. Temperature
Short Circuit COMP Current (IZERO) vs. Temperature
0.5
6.3
0.4
I ZERO (mA)
VCOMP_OP (V)
6.0
5.7
5.4
0.2
0.1
0.0
5.1
-40
0
40
Temperature (°C)
R7780-01
0.3
September 2011
80
120
-40
0
40
80
120
Temperature (°C)
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7
R7780
VDD Over Voltage Protection Level (VOVP) vs.
Temperature
Initial Current Limit Offset (VCSTH) vs. Temperature
31
0.72
30
VOVP (V)
VCSTH (V)
0.71
0.70
29
28
0.69
27
0.68
26
-40
0
40
80
-40
120
0
40
80
120
Temperature (°C)
Temperature (°C)
Enable Threshold Voltage (VEN_TH) vs. Temperature
Maximum Duty Cycle (DCYMAX) vs. Temperature
80
2.4
78
DCYMAX (%)
VEN_TH (V)
1.8
1.2
76
74
0.6
72
0
70
-40
0
40
Temperature (°C)
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8
80
120
-40
0
40
80
120
Temperature (°C)
R7780-01
September 2011
R7780
Application Information
efficiency calculation. This mode can reduce the
switching loss. When the output load gets light, the
feedback signal drops and touches VBURL. Clock signal
will be blanked and system ceases switching. After VOUT
drops and feedback signal goes back to VBURH, the
system will restart switching again. The burst mode
entry points of high and low line are compensated to
reduce audio noise at high line and get better efficiency
at low line. This kind of operation, is shown in the timing
diagram of Figure 1.
The R7780 is specially designed for advanced monitor
application. The proprietary ON/OFF control pin completely
shuts down the controller after receiving downstream
scalar signal from secondary side. (It achieves almost
zero power under sleeping mode.)
HV Start-up Device
An in-house design 700V start-up device is integrated in
the controller to further minimized loss and enhance
performance. The HV start-up device will be turned on
during start-up and be pulled low during normal operation.
It guarantees fast start-up time and no power loss in this
path after start-up.
#
A 10kΩ resistor is recommended to be connected in
series with HV pin.
Burst Triple Mode
The R7780 applies Burst Triple Mode for light load
operation, because it's reliable, simple and no patent
infringement issues. Refer to Figure 1 for details.
`
PWM Mode
For most of load, the circuit will run at traditional PWM
current mode.
#
It's highly recommended to add a resistor in parallel
with the photo-coupler. To provide sufficient bias current
to make TL-431 regulate properly, 1.2kΩ resistor is
suggested.
`
Burst Mode
During light load, switching loss will dominate the power
Normal
Operation
Light
Load
`
VDD Holdup Mode
Under light load or load transient moment, feedback
signal will drop and touch VBURL. Then PWM signal will
be blanked and system ceases to switch. VDD could
drop down to turn off threshold voltage. To avoid this,
when V DD drops to a setting threshold, 10V, the
hysteresis comparator will bypass PWM and burst mode
loop and force switching at a very low level to supply
energy to VDD pin. VDD holdup mode is also improved
to hold up VDD by less switching cycles. It's not likely
for VDD to touch UVLO turn off threshold during any light
load condition. This will also makes bias winding design
and transient design easier.
Furthermore, VDD holdup mode is only designed to
prevent VDD from touching turn off threshold voltage under
light load or load transient moment. Relative to burst
mode, switching loss will increase on the system at
VDD holdup mode, so it is highly recommended that
the system should avoid operating at this mode during
light load or no load condition, normally.
No Load
(VDD Holdup Mode)
Load
VDD
VDD_HIGH
VDD_LOW
VCOMP
VBURH
VBURL
VGATE
Figure 1. Burst Triple Mode
R7780-01
September 2011
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9
R7780
Oscillator
To guarantee precise frequency, it is trimmed to 5%
tolerance. It also generates slope compensation saw-tooth,
75% maximum duty cycle pulse and overload protection
slope. It typically operates at built-in 65kHz center
frequency and features frequency jittering function. Its
jittering depth is 7% with about 4ms envelope frequency
at 65kHz.
Gate Driver
A totem pole gate driver is fine tuned to meet both EMI
and efficiency requirement in low power application. An
internal pull low circuit is activated after pretty low VDD to
prevent external MOSFET from accidental turning-on
during UVLO.
#
Typical application circuits are suggested adding at least
10Ω GATE pin resistor to alleviate ringing spike of gate
drive loop.
The deglitch delay time of the disable function is about
20μs. The internal bias current of EN/DIS is 2μA. For low
power consumption, it's a high impedance pin. Therefore,
proper layout is necessary for noise immunity. If capacitor
is unavoidable, capacitor value should be carefully
calculated and not to influence system operation.
Protection
The R7780 provides fruitful protection functions that intend
to protect system from being damaged. All the protection
functions can be listed as below.
`
This is a basic but very useful function and it can be
implemented easily in current mode controller.
`
`
When the voltage of EN/DIS pin exceeds 1.2V or EN/DIS
pin is floating, the system will be start-up. When the
voltage of EN/DIS pin falls below 0.8V, the system will be
shut down. For low standby power application, it's
important to make current in this path as small as possible.
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10
Over Voltage Protection
Output voltage can be roughly sensed by VDD pin. If
the sensed voltage reaches 28V threshold, system will
be shut down after 20μs deglitch delay. This will last
until fault is removed.
`
Over Temperature Protection
Internal 110/140°C hysteresis comparator will provide
Over Temperature Protection (OTP) for controller itself.
It's not suggested to use the function as precise OTP.
OTP will not shut down system. It stops the system
from switching until the temperature is under 110°C.
Meanwhile , if VDD touches VDD turn off threshold voltage,
system will hiccup.
EN/DIS Pin
The R7780 features an enable/disable circuit. If the voltage
on EN/DIS pin is greater than enable threshold voltage or
EN/DIS pin is floating, the controller is enabled and
switching will occur. If the voltage on the EN/DIS pin falls
below enable threshold voltage, the controller will be shut
down and consume almost zero power.
Over Load Protection
Long time cycle-by-cycle current limit will lead to system
thermal stress. To further protect system, system will
be shut down after about 56ms. After shutdown, system
will resume and behave as hiccup. Through our
proprietary prolong turn off period as hiccup, the power
loss and thermal during OLP will be averaged to an
acceptable level over the ON/OFF cycle of the IC. This
will last until fault is removed.
Tight Current Limit Tolerance
Generally, the saw current limit is applied to low cost
flyback controller because of simple design. However, saw
current limit is hard to test in mass production. Therefore,
it's generally "guarantee by design". The variation of
process and package will make its tolerance wider. It will
leads to 20% to 30% variation when doing OLP test at
certain line voltage. This will cause yield loss in power
supply mass production. Through well foundry control,
design and test/trim mode in final test, the R7780 current
limit tolerance is tight enough to make design and mass
production easier.
Cycle-by-Cycle Current Limit
`
Feedback Open and Opto short
This will trigger OVP or 56ms delay protection. It
depends on which one occurs first.
R7780-01
September 2011
R7780
`
CS Pin Open Protection
When CS pin is opened, the system will be shut down
and into auto recovery after couples of cycle. It could
pass CS pin open test easier.
`
AC Mains
(90V to 265V)
#
HV
Secondary Rectifier Short Protection
As shown in Figure 2. The current spike during
secondary rectifier short test is extremely high because
of saturated main transformer. Meanwhile, the
transformer acts like a leakage inductance. During high
line, the current in power FET is sometimes too high to
wait for a 56ms OLP delay time. To offer better and
easier protection design, the R7780 shuts down the
controller after couples of cycles before fuse is blown
up.
Secondary Rectifier Short
VDD
VDD
GATE
CS
September 2011
#
3
Figure 3. R-C Filter on CS Pin
Layout Considerations
A proper PCB layout can abate unknown noise interference
and EMI issue in the switching power supply. Please refer
to the guidelines when you want to design PCB layout for
switching power supply:
`
The current path(1) from bulk capacitor, transformer,
MOSFET, Rcs return to bulk capacitor is a huge high
frequency current loop. The path(2) from gate pin,
MOSFET, Rcs return to bulk capacitor is also a huge
high frequency current loop. They must be as short as
possible to decrease noise coupling and kept a space
to other low voltage traces, such as IC control circuit
paths, especially. Besides, the path(3) between
MOSFET ground(b) and IC ground(d) is recommend to
be as short as possible, too.
`
The path(4) from RCD snubber circuit to MOSFET is a
high switching loop. Keep it as small as possible.
`
The path(5) from bulk capacitor to HV pin is a high
voltage loop. It is highly recommended that EN/DIS
control paths will be kept as far as possible from path
(1), path(2), path(3) and path(4).
Figure 2. Secondary Rectifier Short Protection
R7780-01
5
R-C Filter
VCS
Negative voltage (< -0.3V) on each pin will cause substrate
injection. It leads to controller damage or circuit false
trigger. Generally, it happens at CS pin due to negative
spike because of improper layout or inductive current
sense resistor. Therefore, it is highly recommended to
add a R-C filter to avoid CS pin damage, as shown in
Figure 3. Proper layout and careful circuit design should
be done to guarantee yield rate in mass production.
6
R7780
VCOMP
Negative Voltage Spike on Each Pin
8
` It is good for reducing noise, output ripple and EMI issue
to separate ground traces of bulk capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control circuit
(d). Finally, connect them together on bulk capacitor
ground(a). The areas of these ground traces should be
kept large.
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11
R7780
` Placing bypass capacitor for abating noise on IC is
highly
recommended. The bypass capacitor should be placed
as close to controller as possible.
` To minimize reflected trace inductance and EMI minimize
the area of the loop connecting the secondary winding,
the output diode, and the output filter capacitor. In
addition, apply sufficient copper area at the anode and
cathode terminal of the diode for heatsinking. Apply a
larger area at the quiet cathode terminal. A large anode
area can increase high-frequency radiated EMI.
CBULK
AC Mains
(90V to 265V)
(a)
(5)
1
2
R7780
EN/DIS
HV
VDD
(4)
CBULK Ground (a)
8
6
Trace
Trace
Trace
COMP
GATE
4
GND
CS
5
(c)
3
IC
Ground (d)
Auxiliary
Ground (c)
MOSFET
Ground (b)
(1)
(2)
(d)
(3)
(b)
Figure 4. PCB Layout Guide
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R7780-01
September 2011
R7780
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
7-Lead SOP Plastic Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,
specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed
by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
R7780-01
September 2011
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