AD6653: IF Diversity Receiver Data Sheet (Rev. 0) PDF

IF Diversity Receiver
AD6653
FEATURES
APPLICATIONS
SNR = 70.8 dBc (71.8 dBFS) in a 32.7 MHz BW at
70 MHz @ 150 MSPS
SFDR = 83 dBc to 70 MHz @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
Integrated dual-channel ADC
Sample rates up to 150 MSPS
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Integrated wideband digital downconverter (DDC)
32-bit, complex, numerically controlled oscillator (NCO)
Decimating half-band filter and FIR filter
Supports real and complex output modes
Fast attack/threshold detect bits
Composite signal monitor
Energy-saving power-down modes
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA,
CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
Integrated dual, 12-bit, 125 MSPS/150 MSPS ADC.
Integrated wideband decimation filter and 32-bit
complex NCO.
Fast overrange detect and signal monitor with serial output.
Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
Flexible output modes, including independent CMOS,
interleaved CMOS, IQ mode CMOS, and interleaved LVDS.
SYNC input allows synchronization of multiple devices.
3-bit SPI port for register programming and register readback.
FUNCTIONAL BLOCK DIAGRAM
FD[0:3]A
DVDD
DRVDD
AD6653
CMOS/LVDS
OUTPUT BUFFER
I
VIN+A
SHA
ADC
VIN–A
Q
LP/HP
DECIMATING
HB FILTER +
FIR
VREF
SENSE
CML
RBIAS
SIGNAL
MONITOR
32-BIT
TUNING
NCO
fADC /8
NCO
REF
SELECT
CLK–
DCO
GENERATION
Q
VIN–B
SHA
ADC
VIN+B
I
AGND
MULTI-CHIP
SYNC
FD BITS/THRESHOLD
DETECT
SYNC
FD[0:3]B
LP/HP
DECIMATING
HB FILTER +
FIR
SIGNAL MONITOR
DATA
PROGRAMMING DATA
SIGNAL MONITOR
INTERFACE
SPI
SMI
SMI
SMI
SDFS SCLK/ SDO/
PDWN OEB
SDIO/ SCLK/ CSB
DCS DFS
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 10 FOR LVDS PIN NAMES.
D0A
CLK+
DIVIDE 1
TO 8
DUTY
CYCLE
STABILIZER
D11A
DCOA
DCOB
D11B
D0B
DRGND
06708-001
FD BITS/THRESHOLD
DETECT
CMOS
OUTPUT BUFFER
AVDD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD6653
TABLE OF CONTENTS
Features .............................................................................................. 1
Synchronization.......................................................................... 34
Applications....................................................................................... 1
Combined Filter Performance.................................................. 34
Product Highlights ........................................................................... 1
Final NCO ................................................................................... 34
Functional Block Diagram .............................................................. 1
ADC Overrange and Gain Control.............................................. 35
Revision History ............................................................................... 3
Fast Detect Overview................................................................. 35
General Description ......................................................................... 4
ADC Fast Magnitude ................................................................. 35
Specifications..................................................................................... 5
ADC Overrange (OR)................................................................ 36
ADC DC Specifications ............................................................... 5
Gain Switching............................................................................ 36
ADC AC Specifications ............................................................... 6
Signal Monitor ................................................................................ 38
Digital Specifications ................................................................... 7
Peak Detector Mode................................................................... 38
Switching Specifications .............................................................. 9
RMS/MS Magnitude Mode....................................................... 38
Timing Specifications ................................................................ 10
Threshold Crossing Mode......................................................... 39
Absolute Maximum Ratings.......................................................... 13
Additional Control Bits ............................................................. 39
Thermal Characteristics ............................................................ 13
DC Correction ............................................................................ 39
ESD Caution................................................................................ 13
Signal Monitor SPORT Output ................................................ 40
Pin Configurations and Function Descriptions ......................... 14
Channel/Chip Synchronization.................................................... 41
Equivalent Circuits ......................................................................... 18
Serial Port Interface (SPI).............................................................. 42
Typical Performance Characteristics ........................................... 19
Configuration Using the SPI..................................................... 42
Theory of Operation ...................................................................... 24
Hardware Interface..................................................................... 42
ADC Architecture ...................................................................... 24
Configuration Without the SPI ................................................ 43
Analog Input Considerations.................................................... 24
SPI Accessible Features.............................................................. 43
Voltage Reference ....................................................................... 26
Memory Map .................................................................................. 44
Clock Input Considerations ...................................................... 27
Reading the Memory Map Register Table............................... 44
Power Dissipation and Standby Mode..................................... 29
Memory Map Register Table..................................................... 45
Digital Outputs ........................................................................... 30
Memory Map Register Description ......................................... 49
Digital Downconverter .................................................................. 31
Applications Information .............................................................. 53
Downconverter Modes .............................................................. 31
Design Guidelines ...................................................................... 53
Numerically Controlled Oscillator (NCO) ............................. 31
Evaluation Board ............................................................................ 55
Half-Band Decimating Filter and FIR Filter........................... 31
Power Supplies ............................................................................ 55
fADC/8 Fixed-Frequency NCO ................................................... 31
Input Signals................................................................................ 55
Numerically Controlled Oscillator (NCO) ................................. 32
Output Signals ............................................................................ 55
Frequency Translation ............................................................... 32
Default Operation and Jumper Selection Settings................. 56
NCO Synchronization ............................................................... 32
Alternative Clock Configurations............................................ 56
Phase Offset................................................................................. 32
Alternative Analog Input Drive Configuration...................... 57
NCO Amplitude and Phase Dither .......................................... 32
Schematics................................................................................... 58
Decimating Half-Band Filter and FIR Filter ............................... 33
Evaluation Board Layouts ......................................................... 68
Half-Band Filter Coefficients.................................................... 33
Bill of Materials........................................................................... 76
Half-Band Filter Features .......................................................... 33
Outline Dimensions ....................................................................... 78
Fixed-Coefficient FIR Filter ...................................................... 33
Ordering Guide .......................................................................... 78
Rev. 0 | Page 2 of 80
AD6653
REVISION HISTORY
11/07—Revision 0: Initial Version
Rev. 0 | Page 3 of 80
AD6653
GENERAL DESCRIPTION
The AD6653 is a mixed-signal intermediate frequency (IF) receiver
consisting of dual, 12-bit, 125 MSPS/150 MSPS ADCs and a wideband digital downconverter (DDC). The AD6653 is designed to
support communications applications where low cost, small size,
and versatility are desired.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
ADC data outputs are internally connected directly to the
digital downconverter (DDC) of the receiver, simplifying layout
and reducing interconnection parasitics. The digital receiver has
two channels and provides processing flexibility. Each receive
channel has four cascaded signal processing stages: a 32-bit
frequency translator (numerically controlled oscillator (NCO)),
a decimating half-band filter, a fixed FIR filter, and an fADC/8
fixed-frequency NCO.
In addition to the receiver, DDC, the AD6653 has several functions
that simplify the automatic gain control (AGC) function in the
system receiver. The fast detect feature allows fast overrange
detection by outputting four bits of input level information with
short latency.
In addition, the programmable threshold detector allows
monitoring of the incoming signal power using the four fast
detect bits of the ADC with low latency. If the input signal level
exceeds the programmable threshold, the coarse upper threshold
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition.
The second AGC-related function is the signal monitor. This block
allows the user to monitor the composite magnitude of the
incoming signal, which aids in setting the gain to optimize the
dynamic range of the overall system.
After digital processing, data can be routed directly to the two
external 12-bit output ports. These outputs can be set from 1.8 V
to 3.3 V CMOS or as 1.8 V LVDS. The CMOS data can also be
output in an interleaved configuration at a double data rate,
using only Port A.
The AD6653 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of the main
channel and the diversity channel. This IF sampling architecture
greatly reduces component cost and complexity compared with
traditional analog techniques or less integrated digital methods.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-bit
SPI-compatible serial interface.
The AD6653 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
Rev. 0 | Page 4 of 80
AD6653
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance 1
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS Mode)
DRVDD (LVDS Mode)
Supply Current
IAVDD 2,3
IDVDD2, 3
IDRVDD2 (3.3 V CMOS)
IDRVDD2 (1.8 V CMOS)
IDRVDD2 (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input2 (DRVDD = 1.8 V)
Sine Wave Input2 (DRVDD = 3.3 V)
Standby Power 4
Power-Down Power
Temperature
Full
Full
Full
Full
Min
12
AD6653BCPZ-125
Typ
Max
Min
12
AD6653BCPZ-150
Typ
Max
Guaranteed
±0.3
−2.7
±0.6
−0.7
25°C
25°C
±0.3
±0.1
±0.6
±0.7
Full
Full
±19
±38
Full
Full
±5
7
25°C
0.21
0.21
LSB rms
Full
Full
Full
2
8
6
2
8
6
V p-p
pF
kΩ
Full
Full
Full
−3.9
1.7
1.7
1.7
1.8
3.3
1.8
Full
Full
Full
Full
Full
390
270
20
12
57
Full
Full
Full
Full
Full
770
1215
1275
77
2.5
1
−5.2
Guaranteed
±0.2
±0.6
−3.2
−0.9
Unit
Bits
±0.2
±0.2
±0.7
±0.7
±17
±49
±18
1.9
3.6
1.9
689
800
8
±5
7
1.7
1.7
1.7
1.8
3.3
1.8
440
320
24
15
57
870
1395
1450
77
2.5
% FSR
% FSR
% FSR
% FSR
ppm/°C
ppm/°C
±18
1.9
3.6
1.9
785
905
8
mV
mV
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 11 for the equivalent analog input structure.
Measured with a 9.7 MHz, full-scale sine wave input, NCO enabled with a frequency of 13 MHz, FIR filter enabled and the fS/8 output mix enabled with approximately
5 pF loading on each output bit.
3
The maximum limit applies to the combination of IAVDD and IDVDD currents.
4
Standby power is measured with a dc input and with the CLK pin inactive (set to AVDD or AGND).
2
Rev. 0 | Page 5 of 80
AD6653
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, NCO enabled, half-band filter enabled, FIR filter enabled, unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR 2
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 29.12 MHz, 32.12 MHz (−7 dBFS)
fIN = 169.12 MHz, 172.12 MHz (−7 dBFS)
CROSSTALK 3
ANALOG INPUT BANDWIDTH
1
2
3
Temperature
25°C
25°C
Full
25°C
25°C
Min
Min
71.0
70.8
AD6653BCPZ-150
Typ
Max
70.9
70.8
69.8
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
AD6653BCPZ-125
Typ
Max
dB
dB
dB
dB
dB
69.4
70.6
70.2
70.6
70.0
−85
−84
−84
−83
−74
−73
−83
−81
−82
−77
85
84
84
83
74
82
77
−92
−90
−90
−87
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
73
83
81
Unit
25°C
25°C
Full
25°C
25°C
−88
−84
−83
−78
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
85
81
95
650
85
81
95
650
dBc
dBc
dB
MHz
−82
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
See the Applications Information section for more information about the worst other specifications for the AD6653.
Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
Rev. 0 | Page 6 of 80
−80
AD6653
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS
(CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DCS, SMI SDFS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
AD6653BCPZ-150
Typ Max
Unit
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD − 0.3
AVDD + 1.6
1.1 V
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
4
8
10
12
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDD − 0.3
AVDD + 1.6
1.1 V
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
4
8
10
12
V
V p-p
V
V
V
V
μA
μA
pF
kΩ
CMOS
1.2
CMOS
1.2
Temp
Min
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD6653BCPZ-125
Typ Max
AVDD − 0.3
1.2
0
−10
−10
8
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
4
10
Min
AVDD + 1.6
3.6
0.8
+10
+10
AVDD − 0.3
1.2
0
−10
−10
12
8
3.6
0.6
+10
132
1.22
0
−10
40
26
2
1.22
0
−92
−10
26
2
12
1.22
0
−10
38
26
5
V
V
V
V
μA
μA
pF
kΩ
3.6
0.6
+10
132
V
V
μA
μA
kΩ
pF
3.6
0.6
−135
+10
V
V
μA
μA
kΩ
pF
3.6
0.6
+10
128
V
V
μA
μA
kΩ
pF
26
2
3.6
0.6
+10
128
Rev. 0 | Page 7 of 80
4
10
26
2
3.6
0.6
−135
+10
26
5
AVDD + 1.6
3.6
0.8
+10
+10
AD6653
Parameter
LOGIC INPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD),
ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD),
Reduced Swing Mode
Output Offset Voltage (VOS),
Reduced Swing Mode
1
2
Temp
Min
AD6653BCPZ-125
Typ Max
Min
AD6653BCPZ-150
Typ Max
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
3.6
0.6
−134
+10
1.22
0
−90
−10
3.6
0.6
−134
+10
Full
Full
3.29
3.25
26
5
3.29
3.25
Full
Full
Full
Full
26
5
0.2
0.05
1.79
1.75
Full
Full
V
V
μA
μA
kΩ
pF
V
V
0.2
0.05
1.79
1.75
Unit
V
V
V
V
0.2
0.05
0.2
0.05
V
V
Full
250
350
450
250
350
450
mV
Full
Full
1.15
150
1.25
200
1.35
280
1.15
150
1.25
200
1.35
280
V
mV
Full
1.15
1.25
1.35
1.15
1.25
1.35
V
Pull up.
Pull down.
Rev. 0 | Page 8 of 80
AD6653
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCLKH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode, DCS Enabled
Divide-by-3 Through Divide-by-8 Modes,
DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Noninterleaved Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Noninterleaved Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Interleaved and IQ Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Interleaved and IQ Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD) 2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Pipeline Delay (Latency) NCO, FIR, fS/8 Mix Disabled
Pipeline Delay (Latency) NCO Enabled; FIR and fS/8
Mix Disabled (Complex Output Mode)
Pipeline Delay (Latency) NCO, FIR Filter, and fS/8 Mix
Enabled
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
Temperature
AD6653BCPZ-125
Min
Typ
Max
Full
AD6653BCPZ-150
Min
Typ
Max
625
Full
Full
Full
20
10
8
Full
Full
Full
Full
2.4
3.6
1.6
0.8
Full
Full
Full
Full
Unit
625
MHz
150
150
MSPS
MSPS
ns
125
125
20
10
6.66
4
4
5.6
4.4
2.0
3.0
1.6
0.8
3.33
3.33
4.66
3.66
ns
ns
ns
ns
1.6
4.0
3.9
5.4
9.5
6.5
6.2
7.3
1.6
4.0
3.9
5.4
8.16
5.16
6.2
7.3
ns
ns
ns
ns
Full
Full
Full
Full
1.9
4.4
4.1
5.8
9.7
6.3
6.4
7.7
1.9
4.4
4.1
5.8
8.36
4.96
6.4
7.7
ns
ns
ns
ns
Full
Full
Full
Full
1.6
3.4
3.9
4.8
4.9
3.1
6.2
6.7
1.6
3.4
3.9
4.8
4.23
2.43
6.2
6.7
ns
ns
ns
ns
Full
Full
Full
Full
1.9
3.8
4.1
5.2
5.1
2.9
6.4
7.1
1.9
3.8
4.1
5.2
4.43
2.23
6.4
7.1
ns
ns
ns
ns
Full
Full
Full
Full
2.5
3.7
4.8
5.3
38
38
7.0
7.3
2.5
3.7
4.8
5.3
38
38
7.0
7.3
ns
ns
Cycles
Cycles
Full
109
109
Cycles
Full
Full
Full
Full
1.0
0.1
350
44
1.0
0.1
350
44
ns
ps rms
μs
Cycles
1
Conversion rate is the clock rate after the divider.
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load.
3
Wake-up time is dependent on the value of the decoupling capacitors.
2
Rev. 0 | Page 9 of 80
AD6653
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
SPORT TIMING REQUIREMENTS
tCSSCLK
tSSLKSDO
tSSCLKSDFS
Conditions
Min
SYNC to the rising edge of CLK setup time
SYNC to the rising edge of CLK hold time
Typ
Max
Unit
0.24
0.4
ns
ns
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
3.2
−0.4
−0.4
4.5
0
0
6.2
+0.4
+0.4
ns
ns
ns
Timing Diagrams
CLK+
tDCO
tPD
CHANNEL A/B
DATA BITS
DECIMATED
CMOS DATA
DECIMATED
FD DATA
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
DATA BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
DATA BITS
CHANNEL A/B
FD BITS
06708-109
tS
DECIMATED
DCOA/DCOB
tH
Figure 2. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
CLK+
tPD
tDCO
DECIMATED
CMOS DATA
CHANNEL A/B
DATA BITS
CHANNEL A/B
DATA BITS
CHANNEL A/B
DATA BITS
DECIMATED
FD DATA
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
CHANNEL A/B
FD BITS
DECIMATED
DCOA/DCOB
tH
06708-002
tS
Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
Rev. 0 | Page 10 of 80
AD6653
CLK+
tPD
tDCO
DECIMATED
INTERLEAVED
CMOS DATA
CHANNEL A:
DATA
CHANNEL B:
DATA
CHANNEL A:
DATA
CHANNEL B:
DATA
CHANNEL A:
DATA
CHANNEL B:
DATA
DECIMATED
INTERLEAVED
FD DATA
CHANNEL A:
FD BITS
CHANNEL B:
FD BITS
CHANNEL A:
FD BITS
CHANNEL B:
FD BITS
CHANNEL A:
FD BITS
CHANNEL B:
FD BITS
06708-003
tS
DECIMATED
DCO
tH
Figure 4. Decimated Interleaved CMOS Mode Data and Fast Detect Output Timing
CLK+
tPD
tDCO
DECIMATED
CMOS IQ
OUTPUT DATA
CHANNEL A/B:
Q DATA
CHANNEL A/B:
I DATA
CHANNEL A/B:
Q DATA
CHANNEL A/B:
I DATA
CHANNEL A/B:
Q DATA
CHANNEL A/B:
I DATA
CMOS FD
DATA
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
CHANNEL A/B:
FD BITS
06708-004
tS
DECIMATED
DCOA/DCOB
tH
Figure 5. Decimated IQ Mode CMOS Data and Fast Detect Output Timing
CLK–
CLK+
tPD
LVDS
DATA
CHANNEL A:
DATA
CHANNEL B:
DATA
CHANNEL A:
DATA
CHANNEL B:
DATA
CHANNEL A:
DATA
LVDS
FAST DET
CHANNEL A:
FD
CHANNEL B:
FD
CHANNEL A:
FD
CHANNEL B:
FD
CHANNEL A:
FD
tDCO
06708-005
DCO–
DCO+
Figure 6. Decimated Interleaved LVDS Mode Data and Fast Detect Output Timing
CLK+
tHSYNC
06708-006
tSSYNC
SYNC
Figure 7. SYNC Timing Inputs
Rev. 0 | Page 11 of 80
AD6653
CLK+
CLK–
tCSSCLK
SMI SCLK
tSSCLKSDFS
tSSCLKSDFS
SMI SDO
DATA
Figure 8. Signal Monitor SPORT Output Timing
Rev. 0 | Page 12 of 80
DATA
06708-007
SMI SDFS
AD6653
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
ELECTRICAL
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB to DRGND
SMI SCLK/PDWN to DRGND
SMI SDFS to DRGND
D0A/D0B through D11A/D11B
to DRGND
FD0A/FD0B through FD3A/FD3B
to DRGND
DCOA/DCOB to DRGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
Table 7. Thermal Resistance
Package
Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-3)
Airflow
Velocity
(m/s)
0
1.0
2.0
θJA1, 2
18.8
16.5
15.8
θJC1, 3
0.6
θJB1, 4
6.0
Unit
°C/W
°C/W
°C/W
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown, airflow increases heat dissipation, which
reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
ESD CAUTION
−40°C to +85°C
150°C
−65°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 13 of 80
AD6653
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
D3B
D2B
D1B
D0B (LSB)
DNC
DNC
DVDD
FD3B
FD2B
FD1B
FD0B
SYNC
CSB
CLK–
CLK+
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DRVDD
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B (MSB)
DCOB
DCOA
DNC
DNC
D0A (LSB)
D1A
D2A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD6653
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
06708-008
D3A
D4A
D5A
DRGND
DRVDD
D6A
D7A
DVDD
D8A
D9A
D10A
D11A (MSB)
FD0A
FD1A
FD2A
FD3A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DNC = DO NOT CONNECT
Figure 9. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46
AVDD
0
AGND
12, 13, 58, 59
DNC
ADC Analog
37
VIN+A
38
VIN−A
44
VIN+B
43
VIN−B
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK−
ADC Fast Detect Outputs
29
FD0A
30
FD1A
31
FD2A
32
FD3A
53
FD0B
54
FD1B
55
FD2B
56
FD3B
Type
Description
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Do Not Connect.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Output
Output
Output
Output
Output
Output
Channel A Fast Detect Indicator. See Table 17 for details.
Channel A Fast Detect Indicator. See Table 17 for details.
Channel A Fast Detect Indicator. See Table 17 for details.
Channel A Fast Detect Indicator. See Table 17 for details.
Channel B Fast Detect Indicator. See Table 17 for details.
Channel B Fast Detect Indicator. See Table 17 for details.
Channel B Fast Detect Indicator. See Table 17 for details.
Channel B Fast Detect Indicator. See Table 17 for details.
Rev. 0 | Page 14 of 80
AD6653
Pin No.
Mnemonic
Digital Inputs
52
SYNC
Digital Outputs
14
D0A (LSB)
15
D1A
16
D2A
17
D3A
18
D4A
19
D5A
22
D6A
23
D7A
25
D8A
26
D9A
27
D10A
28
D11A (MSB)
60
D0B (LSB)
61
D1B
62
D2B
63
D3B
2
D4B
3
D5B
4
D6B
5
D7B
6
D8B
7
D9B
8
D10B
9
D11B (MSB)
11
DCOA
10
DCOB
SPI Control
48
SCLK/DFS
47
SDIO/DCS
51
CSB
Signal Monitor Port
33
SMI SDO/OEB
35
SMI SDFS
34
SMI SCLK/PDWN
Type
Description
Input
Digital Synchronization Pin. Slave mode only.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel A Data Clock Output.
Channel B Data Clock Output.
Input
Input/Output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select. Active low.
Input/Output
Output
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
Rev. 0 | Page 15 of 80
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
DNC
DNC
FD3+
FD3–
FD2+
FD2–
DVDD
FD1+
FD1–
FD0+
FD0–
SYNC
CSB
CLK–
CLK+
AD6653
DRVDD
DNC
DNC
D0– (LSB)
D0+ (LSB)
D1–
D1+
D2–
D2+
DCO–
DCO+
D3–
D3+
D4–
D4+
D5–
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD6653
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
06708-009
D5+
D6–
D6+
DRGND
DRVDD
D7–
D7+
DVDD
D8–
D8+
D9–
D9+
D10–
D10+
D11– (MSB)
D11+ (MSB)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DNC = DO NOT CONNECT
Figure 10. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46
AVDD
0
AGND
2, 3, 62, 63
DNC
ADC Analog
37
VIN+A
38
VIN−A
44
VIN+B
43
VIN−B
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK−
ADC Fast Detect Outputs
54
FD0+
53
FD0−
Type
Description
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Do Not Connect.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 17
for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 17
for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 17
for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 17 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 17
for details.
56
55
FD1+
FD1−
Output
Output
59
58
FD2+
FD2−
Output
Output
61
60
FD3+
FD3−
Output
Output
Rev. 0 | Page 16 of 80
AD6653
Pin No.
Mnemonic
Digital Inputs
52
SYNC
Digital Outputs
5
D0+ (LSB)
4
D0− (LSB)
7
D1+
6
D1−
9
D2+
8
D2−
13
D3+
12
D3−
15
D4+
14
D4−
17
D5+
16
D5−
19
D6+
18
D6−
23
D7+
22
D7−
26
D8+
25
D8−
28
D9+
27
D9−
30
D10+
29
D10−
32
D11+ (MSB)
31
D11− (MSB)
11
DCO+
10
DCO−
SPI Control
48
SCLK/DFS
47
SDIO/DCS
51
CSB
Signal Monitor Port
33
SMI SDO/OEB
35
34
SMI SDFS
SMI SCLK/PDWN
Type
Description
Input
Digital Synchronization Pin. Slave mode only.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4 —True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
Input
Input/Output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data Input/Output/Duty Cycle Stabilizer in External Pin Mode.
SPI Chip Select. Active low.
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External
Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input (Active High) in External
Pin Mode.
Output
Input/Output
Rev. 0 | Page 17 of 80
AD6653
EQUIVALENT CIRCUITS
1kΩ
SCLK/DFS
VIN
06708-014
06708-010
26kΩ
Figure 11. Equivalent Analog Input Circuit
Figure 15. Equivalent SCLK/DFS Input Circuit
AVDD
1.2V
10kΩ
CLK–
06708-011
06708-015
10kΩ
CLK+
1kΩ
SENSE
Figure 12. Equivalent Clock lnput Circuit
Figure 16. Equivalent SENSE Circuit
DRVDD
AVDD
26kΩ
1kΩ
06708-012
06708-016
CSB
DRGND
Figure 17. Equivalent CSB Input Circuit
Figure 13. Equivalent Digital Output Circuit
AVDD
DRVDD
DRVDD
VREF
26kΩ
6kΩ
1kΩ
06708-017
06708-013
SDIO/DCS
Figure 18. Equivalent VREF Circuit
Figure 14. Equivalent SDIO/DCS Circuit or SMI SDFS Circuit
Rev. 0 | Page 18 of 80
AD6653
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential
input, VIN = −1.0 dBFS, 64k sample, TA = 25°C, NCO enabled, FIR filter enabled, unless otherwise noted. In the FFT plots that follow,
the location of the second and third harmonics is noted when they fall in the pass band of the filter.
0
–20
–40
SECOND HARMONIC
–60
THIRD HARMONIC
–80
–100
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–100
–120
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
Figure 19. AD6653-150 Single-Tone FFT with fIN = 2.4 MHz, fNCO = 18.75 MHz
0
–140
06708-018
–140
0
0
–80
–100
15
20
25
30
35
150MSPS
220.1MHz @ –1dBFS
SNR = 70.0dBc (71.0dBFS)
SFDR = 80.9dBc
fNCO = 205MHz
–20
–60
10
Figure 22. AD6653-150 Single-Tone FFT with fIN = 140.1 MHz, fNCO = 126 MHz
AMPLITUDE (dBFS)
–40
5
FREQUENCY (MHz)
150MSPS
30.3MHz @ –1dBFS
SNR = 71.0dBc (72.0dBFS)
SFDR = 92.3dBc
fNCO = 24MHz
–20
–60
THIRD HARMONIC
–80
–100
–120
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
Figure 20. AD6653-150 Single-Tone FFT with fIN = 30.3 MHz, fNCO = 24 MHz
0
–140
06708-019
–140
0
0
THIRD HARMONIC
–80
–100
20
25
30
35
150MSPS
332.1MHz @ –1dBFS
SNR = 69.4dBc (70.4dBFS)
SFDR = 91.2dBc
fNCO = 321.5MHz
–20
–60
15
Figure 23. AD6653-150 Single-Tone FFT with fIN = 220.1 MHz, fNCO = 205 MHz
AMPLITUDE (dBFS)
–40
10
FREQUENCY (MHz)
150MSPS
70.1MHz @ –1dBFS
SNR = 70.8dBc (71.8dBFS)
SFDR = 82.9dBc
fNCO = 56MHz
–20
5
06708-022
–120
–40
–60
–80
–100
–120
–140
0
5
10
15
20
25
FREQUENCY (MHz)
30
35
06708-020
–120
–40
Figure 21. AD6653-150 Single-Tone FFT with fIN = 70.1 MHz, fNCO = 56 MHz
Rev. 0 | Page 19 of 80
–140
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
Figure 24. AD6653-150 Single-Tone FFT with fIN = 332.1 MHz,
fNCO = 321.5 MHz
06708-023
AMPLITUDE (dBFS)
–40
06708-021
–120
AMPLITUDE (dBFS)
150MSPS
140.1MHz @ –1dBFS
SNR = 70.6dBc (71.6dBFS)
SFDR = 82.9dBc
fNCO = 126MHz
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
150MSPS
2.4MHz @ –1dBFS
SNR = 70.9dBc (71.9dBFS)
SFDR = 83.2dBc
fNCO = 18.75MHz
AD6653
0
–40
SECOND HARMONIC
–60
THIRD HARMONIC
–80
–100
–60
THIRD HARMONIC
–80
–100
–120
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
Figure 25. AD6653-150 Single-Tone FFT with fIN = 445.1 MHz, fNCO = 429 MHz
0
–140
06708-024
–140
0
–60
15
0
THIRD HARMONIC
–100
20
25
30
125MSPS
140.1MHz @ –1dBFS
SNR = 70.6dBc (71.6dBFS)
SFDR = 86.1dBc
fNCO = 142MHz
–20
SECOND HARMONIC
–80
10
Figure 28. AD6653-125 Single-Tone FFT with fIN = 70.3 MHz, fNCO = 78 MHz
AMPLITUDE (dBFS)
–40
5
FREQUENCY (MHz)
125MSPS
2.4MHz @ –1dBFS
SNR = 71.0dBc (72.0dBFS)
SFDR = 84.6dBc
fNCO = 15.75MHz
–20
–60
THIRD HARMONIC
–80
–100
–120
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 26. AD6653-125 Single-Tone FFT with fIN = 2.4 MHz, fNCO = 15.75 MHz
0
–140
06708-025
–140
0
15
0
THIRD
HARMONIC
–80
–100
25
30
125MSPS
220.1MHz @ –1dBFS
SNR = 70.2dBc (71.2dBFS)
SFDR = 87.9dBc
fNCO = 231MHz
–20
–60
20
Figure 29. AD6653-125 Single-Tone FFT with fIN = 140.1 MHz, fNCO = 142 MHz
AMPLITUDE (dBFS)
–40
10
FREQUENCY (MHz)
125MSPS
30.3MHz @ –1dBFS
SNR = 70.9dBc (71.9dBFS)
SFDR = 90.7dBc
fNCO = 21MHz
–20
5
06708-028
–120
–40
–120
–40
–60
–80
–100
–120
0
5
10
15
20
FREQUENCY (MHz)
25
30
–140
06708-026
–140
Figure 27. AD6653-125 Single-Tone FFT with fIN = 30.3 MHz, fNCO = 21 MHz
0
5
10
15
20
FREQUENCY (MHz)
25
30
06708-029
AMPLITUDE (dBFS)
–40
06708-027
–120
AMPLITUDE (dBFS)
125MSPS
70.3MHz @ –1dBFS
SNR = 70.9dBc (71.9dBFS)
SFDR = 85.9dBc
fNCO = 78MHz
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
150MSPS
445.1MHz @ –1dBFS
SNR = 69.1dBc (70.1dBFS)
SFDR = 73.7dBc
fNCO = 429MHz
Figure 30. AD6653-125 Single-Tone FFT with fIN = 220.1 MHz, fNCO = 231 MHz
Rev. 0 | Page 20 of 80
AD6653
95
120
90
SFDR (dBFS)
SFDR = +85°C
85
80
SNR (dBFS)
40
80
SFDR = –40°C
75
70
20
SNR = +25°C
SNR = +85°C
SNR = –40°C
65
SNR (dBc)
–80
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
60
06708-030
0
–90
Figure 31. AD6653-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 2.4 MHz, fNCO = 18.75 MHz
0
150
200
250
300
350
400
450
Figure 34. AD6653-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with DRVDD = 3.3 V
–1.5
0.5
–2.0
0.4
GAIN ERROR (%FSR)
SFDR (dBFS)
100
SNR/SFDR (dBc AND dBFS)
100
INPUT FREQUENCY (MHz)
120
80
60
50
06708-033
85dB
REFERENCE LINE
SFDR (dBc)
SFDR = +25°C
SNR (dBFS)
40
85dB
REFERENCE LINE
SFDR (dBc)
OFFSET
–2.5
0.3
–3.0
0.2
GAIN
–3.5
20
OFFSET ERROR (%FSR)
60
SNR/SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
100
0.1
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
–4.0
–40
0
20
40
60
80
TEMPERATURE (°C)
Figure 32. AD6653-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 98.12 MHz, fNCO = 100.49 MHz
Figure 35. AD6653-150 Gain and Offset vs. Temperature
95
0
90
–20
85
SFDR/IMD3 (dBc AND dBFS)
SFDR = +85°C
SFDR = +25°C
80
SFDR = –40°C
75
70
SNR = +25°C
SNR = +85°C
SNR = –40°C
60
0
50
100
150
200
250
IMD3 (dBc)
–60
–80
SFDR (dBFS)
IMD3 (dBFS)
–100
300
INPUT FREQUENCY (MHz)
350
400
450
–120
–90
06708-032
65
SFDR (dBc)
–40
Figure 33. AD6653-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with DRVDD = 1.8 V
–78
–66
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
06708-035
SNR/SFDR (dBc)
0
–20
06708-034
–80
06708-031
SNR (dBc)
0
–90
Figure 36. AD6653-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 29.12 MHz, fIN2 = 32.12 MHz, fS = 150 MSPS, fNCO = 22 MHz
Rev. 0 | Page 21 of 80
AD6653
0
0
SFDR (dBc)
AMPLITUDE (dBFS)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
IMD3 (dBFS)
–100
–40
–60
–80
–100
–120
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
–140
0
10
20
25
0
–20
AMPLITUDE (dBFS)
–60
–80
–100
35
NPR = 61.9dBc
NOTCH @ 18.5MHz
NOTCH WIDTH = 3MHz
–20
–40
30
Figure 40. AD6653-150 Two-Tone FFT with fIN1 = 169.12 MHz,
fIN2 = 172.12 MHz, fS = 150 MSPS, fNCO = 177 MHz
0
–40
–60
–80
06708-037
0
5
10
15
20
25
–120
30
0
7.5
FREQUENCY (MHz)
Figure 38. AD6653-125, Two 64k WCDMA Carriers with fIN = 170 MHz,
fS = 122.88 MHz, fNCO = 168.96 MHz
0
80
75
SNR
–100
70
–120
65
15
20
25
FREQUENCY (MHz)
30
35
60
06708-038
–140
10
SFDR
85
–80
5
37.5
90
–60
0
30.0
95
SNR/SFDR (dBc)
–40
22.5
Figure 41. AD6653-150 Noise Power Ratio (NPR)
150MSPS
29.12MHz @ –7dBFS
32.12MHz @ –7dBFS
SFDR = 91.1dBc (98.1dBFS)
fNCO = 22MHz
–20
15.0
FREQUENCY (MHz)
06708-040
–100
–120
AMPLITUDE (dBFS)
15
FREQUENCY (MHz)
Figure 37. AD6653-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 169.12 MHz, fIN2 = 172.12 MHz, fS = 150 MSPS, fNCO = 177 MHz
–140
5
06708-039
–78
06708-036
–120
–90
Figure 39. AD6653-150 Two-Tone FFT with fIN1 = 29.12 MHz, fIN2 = 32.12 MHz,
fS = 150 MSPS, fNCO = 22 MHz
0
25
50
75
100
SAMPLE RATE (MSPS)
125
150
06708-041
SFDR/IMD3 (dBc AND dBFS)
–20
AMPLITUDE (dBFS)
150MSPS
169.12MHz @ –7dBFS
172.12MHz @ –7dBFS
SFDR = 83.6dBc (90.6dBFS)
fNCO = 177MHz
–20
Figure 42. AD6653-150 Single-Tone SNR/SFDR vs. Sample Rate (fS) with
fIN = 2.3 MHz
Rev. 0 | Page 22 of 80
AD6653
12
90
0.21 LSB rms
85
SFDR
8
SNR/SFDR (dBc)
6
4
75
SNR
70
2
N–3
N–2
N–1
N
N+1
N+2
N+3
OUTPUT CODE
65
0.2
06708-042
0
Figure 43. AD6653 Grounded Input Histogram
85
SFDR DCS ON
80
SFDR DCS OFF
75
SNR DCS ON
70
30
40
50
60
DUTY CYCLE (%)
70
80
06708-043
SNR DCS OFF
65
20
0.4
0.6
0.8
1.0
1.2
1.4
INPUT COMMON-MODE VOLTAGE (V)
1.6
Figure 45. AD6653-150 SNR/SFDR vs. Input Common Mode (VCM) with
fIN = 30.3 MHz, fNCO = 45 MHz
90
SNR/SFDR (dBc)
80
06708-044
NUMBER OF HITS (1M)
10
Figure 44. AD6653-150 SNR/SFDR vs. Duty Cycle with fIN = 30.3 MHz,
fNCO = 45 MHz
Rev. 0 | Page 23 of 80
AD6653
THEORY OF OPERATION
The AD6653 has two analog input channels, two decimating
channels, and two digital output channels. The intermediate
frequency (IF) input signal passes through several stages before
appearing at the output port(s) as a filtered, decimated digital
signal.
The dual ADC design can be used for diversity reception of signals,
where the ADCs operate identically on the same carrier but from
two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency
segment from dc to 150 MHz, using appropriate low-pass or
band-pass filtering at the ADC inputs with little loss in ADC
performance. Operation to 450 MHz analog input is permitted
but occurs at the expense of increased ADC noise and distortion.
In nondiversity applications, the AD6653 can be used as a
baseband receiver, where one ADC is used for I input data,
and the other is used for Q input data.
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices. The
NCO phase can be set to produce a known offset relative to
another channel or device.
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 46). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the inputs
to provide dynamic charging currents. This passive network
creates a low-pass filter at the ADC input; therefore, the precise
values are dependent on the application.
In IF undersampling applications, any shunt capacitors should
be reduced. In combination with the driving source impedance,
the shunt capacitors limit input bandwidth. Refer to Application
Note AN-742, Frequency Domain Response of SwitchedCapacitor ADCs; Application Note AN-827, A Resonant Approach
to Interfacing Amplifiers to Switched-Capacitor ADCs; and the
Analog Dialogue article, “Transformer-Coupled Front-End for
Wideband A/D Converters,” for more information on this subject
(see www.analog.com). In general, the precise values are
dependent on the application.
S
Programming and control of the AD6653 are accomplished
using a 3-bit SPI-compatible serial interface.
CH
S
ADC ARCHITECTURE
CS
VIN+
CPIN, PAR
AD6653 architecture consists of a front-end sample-and-hold
amplifier (SHA), followed by a pipelined switched-capacitor ADC.
The quantized outputs from each stage are combined into a final
12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample and the remaining stages to operate on the preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6653 is a differential switchedcapacitor SHA that has been designed for optimum
performance while processing a differential input signal.
S
H
CS
VIN–
S
06708-048
CH
CPIN, PAR
Figure 46. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the
ADC core. The output common mode of the reference buffer is
set to VCMREF (approximately 1.6 V).
Input Common Mode
The analog inputs of the AD6653 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.55 × AVDD is
recommended for optimum performance, but the device functions
over a wider range with reasonable performance (see Figure 45).
An on-board common-mode voltage reference is included in the
design and is available from the CML pin. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the CML pin voltage (typically 0.55 × AVDD).
Rev. 0 | Page 24 of 80
AD6653
Differential Input Configurations
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
Optimum performance is achieved while driving the AD6653 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and ADA4938-2 differential drivers provide
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set with
the CML pin of the AD6653 (see Figure 47), and the driver can
be configured in a Sallen-Key filter topology to provide band
limiting of the input signal.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD6653. For applications where
SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 49).
An alternative to using a transformer coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential
driver, as shown in Figure 50. See the AD8352 data sheet for
more information. In addition, if the application requires an
amplifier with variable gain, the AD8375 or AD8376 digital
variable gain amplifiers (DVGAs) provide good performance
driving the AD6653.
499Ω
R
49.9Ω
VIN+
AVDD
499Ω
523Ω
AD6653
C
AD8138
R
CML
VIN–
499Ω
Figure 47. Differential Input Configuration Using the AD8138
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and source impedance and
may need to be reduced or removed. Table 10 displays
recommended values to set the RC network. However, these
values are dependent on the input signal and should be used
only as a starting guide.
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 48. To bias the
analog input, the CML voltage can be connected to the center
tap of the secondary winding of the transformer.
R
49.9Ω
VIN+
C
Table 10. Example RC Network
AD6653
R
R Series
(Ω Each)
33
33
15
15
CML
Frequency Range (MHz)
0 to 70
70 to 200
200 to 300
>300
06708-050
VIN–
0.1µF
Figure 48. Differential Transformer-Coupled Configuration
0.1µF
0.1µF
R
VIN+
2V p-p
25Ω
PA
S
S
P
25Ω
0.1µF
AD6653
C
0.1µF
R
CML
VIN–
06708-051
2V p-p
Figure 49. Differential Double Balun Input Configuration
VCC
0.1µF
ANALOG INPUT
0Ω
16
8, 13
1
11
0.1µF
0.1µF
2
CD
RD
RG
3
AD8352
10
4
5
ANALOG INPUT
0.1µF
0Ω
R
VIN+
200Ω
0.1µF
200Ω
C
R
AD6653
VIN–
CML
14
0.1µF
0.1µF
Figure 50. Differential Input Configuration Using the AD8352
Rev. 0 | Page 25 of 80
06708-052
0.1µF
06708-049
1V p-p
C Differential (pF)
15
5
5
Open
AD6653
Single-Ended Input Configuration
VIN+A/VIN+B
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 51 shows
a typical single-ended input configuration.
VIN–A/VIN–B
ADC
CORE
VREF
1.0µF
AVDD
1kΩ
R
49.9Ω
0.1µF
1kΩ
0.1µF
0.5V
1kΩ
AVDD
10µF
SENSE
VIN+
AD6653
C
R
AD6653
VIN–
1kΩ
06708-053
2V p-p
SELECT
LOGIC
06708-054
10µF
0.1µF
Figure 51. Single-Ended Input Configuration
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD6653.
The input range can be adjusted by varying the reference voltage
applied to the AD6653, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the sections that follow. The Reference
Decoupling section describes the best practices PCB layout of
the reference.
Figure 52. Internal Reference Configuration
If a resistor divider is connected externally to the chip, as shown
in Figure 53, the switch again sets to the SENSE pin. This puts
the reference amplifier in a noninverting mode with the VREF
output defined as follows:
R2 ⎞
VREF = 0.5 × ⎛⎜1 +
⎟
⎝ R1 ⎠
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VIN+A/VIN+B
VIN–A/VIN–B
Internal Reference Connection
ADC
CORE
VREF
1.0µF
0.1µF
R2
SENSE
R1
SELECT
LOGIC
0.5V
AD6653
06708-055
A comparator within the AD6653 detects the potential at the
SENSE pin and configures the reference into four possible modes,
which are summarized in Table 11. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 52), setting VREF to 1.0 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V
reference output.
Figure 53. Programmable Reference Configuration
Table 11. Reference Configuration Summary
Selected Mode
External Reference
SENSE Voltage
AVDD
Resulting VREF (V)
N/A
Resulting Differential Span (V p-p)
2 × external reference
Internal Fixed Reference
VREF
0.5
1.0
Programmable Reference
0.2 V to VREF
R2 ⎞ (see Figure 53)
⎛
0 .5 × ⎜ 1 +
⎟
R1 ⎠
⎝
2 × VREF
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
Rev. 0 | Page 26 of 80
AD6653
If the internal reference of the AD6653 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 54 depicts
how the internal reference voltage is affected by loading.
0
For optimum performance, the AD6653 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 56) and require no external bias.
AVDD
–0.25
VREF = 1.0V
1.2V
–0.50
CLK+
CLK–
–0.75
2pF
2pF
06708-058
REFERENCE VOLTAGE ERROR (%)
VREF = 0.5V
CLOCK INPUT CONSIDERATIONS
–1.00
0
0.5
1.0
2.0
1.5
LOAD CURRENT (mA)
06708-056
Figure 56. Equivalent Clock Input Circuit
–1.25
Figure 54. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 55 shows the typical drift characteristics of the
internal reference in both 1.0 V and 0.5 V modes.
2.5
1.5
1.0
0.5
The AD6653 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, the clock source jitter is of the
most concern, as described in the Jitter Considerations section.
Figure 57 and Figure 58 show two preferred methods for clocking
the AD6653 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal, using an RF transformer. The back-to-back Schottky diodes
across the transformer secondary limit clock excursions into the
AD6653 to approximately 0.8 V p-p differential. This helps prevent
the large voltage swings of the clock from feeding through to other
portions of the AD6653 while preserving the fast rise and fall
times of the signal, which are critical to low jitter performance.
0
Mini-Circuits®
ADT1–1WT, 1:1Z
0.1µF
XFMR
–0.5
0.1µF
–1.0
CLOCK
INPUT
CLK+
ADC
AD6653
100Ω
50Ω
–1.5
0.1µF
CLK–
–2.0
–20
0
20
40
TEMPERATURE (°C)
60
80
06708-057
–2.5
–40
SCHOTTKY
DIODES:
HSMS2822
0.1µF
06708-059
REFERENCE VOLTAGE ERROR (mV)
2.0
Clock Input Options
Figure 57. Transformer-Coupled Differential Clock (Up to 200 MHz)
Figure 55. Typical VREF Drift
1nF
CLOCK
INPUT
Rev. 0 | Page 27 of 80
0.1µF
CLK+
50Ω
ADC
AD6653
0.1µF
1nF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 58. Balun-Coupled Differential Clock (Up to 625 MHz)
06708-157
When the SENSE pin is tied to AVDD, the internal reference
is disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 18). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
AD6653
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 59. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent
jitter performance.
0.1µF
CLOCK
INPUT
CLK+
50kΩ
100Ω
PECL DRIVER
0.1µF
240Ω
50kΩ
ADC
AD6653
CLK–
06708-060
CLOCK
INPUT
0.1µF
240Ω
Figure 59. Differential PECL Sample Clock (Up to 625 MHz)
0.1µF
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics.
0.1µF
CLK+
AD951x
0.1µF
50kΩ
100Ω
LVDS DRIVER
0.1µF
ADC
AD6653
CLK–
06708-061
CLOCK
INPUT
50kΩ
Figure 60. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
the CLK+ pin should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 61). CLK+ can be
driven directly from a CMOS gate. Although the CLK+ input
circuit supply is AVDD (1.8 V), this input is designed to withstand
input voltages of up to 3.6 V, making the selection of the drive logic
voltage very flexible.
VCC
0.1µF
CLOCK
INPUT
1kΩ
OPTIONAL
0.1µF
100Ω
AD951x
CMOS DRIVER
50Ω
CLK+
ADC
AD6653
1kΩ
06708-062
39kΩ
The AD6653 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
performance of the AD6653. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 44.
Jitter on the rising edge of the input clock is still of paramount
concern and is not easily reduced by the internal stabilization
circuit. The duty cycle control loop does not function for clock
rates less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered when the clock rate
can change dynamically. A wait time of 1.5 μs to 5 μs is required
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time period
that the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
CLK–
0.1µF
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 60. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
CLOCK
INPUT
The AD6653 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD6653 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state.
0.1µF
AD951x
Input Clock Divider
Figure 61. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated by
[
SNR = −20 log 2πf IN × t J
VCC
0.1µF
1kΩ
AD951x
OPTIONAL 0.1µF
100Ω
CMOS DRIVER
50Ω
1kΩ
0.1µF
CLK+
ADC
AD6653
CLK–
06708-063
CLOCK
INPUT
]
In the equation, the rms aperture jitter represents the root mean
square of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 63.
Figure 62. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
Rev. 0 | Page 28 of 80
AD6653
75
0.6
1.50
TOTAL POWER
0.05ps
70
1.25
0.5
TOTAL POWER (W)
0.20ps
0.50ps
1.00ps
1.50ps
45
10
100
IDVDD
0.50
0.2
0.25
2.00ps
2.50ps
3.00ps
1
0.3
0.1
IDRVDD
1000
INPUT FREQUENCY (MHz)
0
0
25
50
100
75
125
0
150
06708-065
50
0.75
SAMPLE RATE (MSPS)
Figure 63. SNR vs. Input Frequency and Jitter
Figure 64. AD6653-150 Power and Current vs. Sample Rate
Refer to Application Note AN-501 and Application Note AN-756
for more information about jitter performance as it relates to
ADCs (see www.analog.com).
0.6
1.50
1.25
0.5
TOTAL POWER
TOTAL POWER (W)
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD6653.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
1.00
0.4
IAVDD
0.75
0.3
0.50
0.2
IDVDD
0.25
0.1
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 64 and Figure 65, the power dissipated by
the AD6653 is proportional to its sample rate. In CMOS output
mode, the digital power dissipation is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated by
IDRVDD = VDRVDD × fCLK × N
where N is the number of output bits (26, in the case of the
AD6653, assuming the FD bits are inactive).
This maximum current occurs when every output bit switches on
every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is established
by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog
input signal. Reducing the capacitive load presented to the output
drivers can minimize digital power consumption. The data in
Figure 64 and Figure 65 was taken using the same operating
conditions as those used for the Typical Performance
Characteristics, with a 5 pF load on each output driver.
0
SUPPLY CURRENT (A)
55
0.4
IDRVDD
0
25
50
75
100
0
125
SAMPLE RATE (MSPS)
06708-066
60
IAVDD
1.00
06708-064
SNR (dBc)
65
SUPPLY CURRENT (A)
MEASURED
Figure 65. AD6653-125 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD6653 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW.
During power-down, the output drivers are placed in a high
impedance state. Asserting the PDWN pin low returns the
AD6653 to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage level. PDWN can be
driven with 1.8 V logic, even when DRVDD is at 3.3 V.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, the wake-up time is related to
the time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
Rev. 0 | Page 29 of 80
AD6653
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and Application Note AN-877, Interfacing
to High Speed ADCs via SPI at www.analog.com for additional
details.
DIGITAL OUTPUTS
The AD6653 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families by matching DRVDD to the
digital supply of the interfaced logic. Alternatively, the AD6653
outputs can be configured for either ANSI LVDS or reduced
drive LVDS using a 1.8 V DRVDD supply.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance. Applications
requiring the ADC to drive large capacitive loads or large fanouts
may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12). As detailed in Application
Note AN-877, Interfacing to High Speed ADCs via SPI, the data
format can be selected for offset binary, twos complement, or
gray code when using the SPI control.
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
AGND (default)
AVDD
SCLK/DFS
Offset binary
Twos complement
If the SMI SDO/OEB pin is low, the output data drivers are enabled.
If the SMI SDO/OEB pin is high, the output data drivers are placed
in a high impedance state.
This OEB function is not intended for rapid access to the data
bus. Note that OEB is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data and fast detect outputs of
each channel can be independently three-stated by using the
output enable bar bit, Bit 4 in Register 0x14.
Interleaved CMOS Mode
Setting Bit 5 in Register 0x14 enables interleaved CMOS output
mode. In this mode, output data is routed through Port A with
the ADC Channel A output data present on the rising edge of
DCO and the ADC Channel B output data present on the
falling edge of DCO.
Timing
The AD6653 provides latched data with a pipeline delay that is
dependent on which of the digital back end features are enabled.
Data outputs are available one propagation delay (tPD) after the
rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD6653.
These transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD6653 is 10 MSPS. At
clock rates below 10 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
SDIO/DCS
DCS disabled
DCS enabled
The AD6653 also provides data clock output (DCO) intended for
capturing the data in an external register. Figure 2 through Figure 6
show a graphical timing description of the AD6653 output modes.
Digital Output Enable Function (OEB)
The AD6653 has a flexible, three-state ability for the digital output
pins. The three-state modeis enabled using the SMI SDO/OEB
pin or through the SPI interface.
Table 13. Output Data Format
Input (V)
VIN+ – VIN−
VIN+ – VIN−
VIN+ – VIN−
VIN+ – VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
1111 1111 1111
Rev. 0 | Page 30 of 80
Twos Complement Mode
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
OR
1
0
0
0
1
AD6653
DIGITAL DOWNCONVERTER
The AD6653 includes a digital processing section that provides
filtering and reduces the output data rate. This digital processing
section includes a numerically controlled oscillator (NCO),
a half-band decimating filter, an FIR filter, and a second coarse
NCO (fADC/8 fixed value) for output frequency translation. Each
of these processing blocks (except the decimating half-band
filter) has control lines that allow it to be independently enabled
and disabled to provide the desired processing function. The
digital downconverter can be configured to output either real data
or complex output data. These blocks can be configured in five
recommended combinations to implement different signal
processing functions.
DOWNCONVERTER MODES
a maximum usable bandwidth of 16.5 MHz when using the filter
in real mode (NCO bypassed) or a maximum usable bandwidth
of 33.0 MHz when using the filter in the complex mode (NCO
enabled).
The optional fixed-coefficient FIR filter provides additional
filtering capability to sharpen the half-band roll-off to enhance
the alias protection. It removes the negative frequency images
to avoid aliasing negative frequencies for real outputs.
fADC/8 FIXED-FREQUENCY NCO
A fixed fADC/8 NCO is provided to translate the filtered, decimated
signal from dc to fADC/8 to allow a real output. Figure 66 to
Figure 69 show an example of a 20 MHz input as it is processed
by the blocks of the AD6653.
Table 14. Downconverter Modes
Output Type
Real
Real
Complex
Complex
Real
–50
–24
–14
–4 0 4
14
24
50
Figure 66. Example AD6653 Real 20 MHz Bandwidth Input Signal Centered at
14 MHz (fADC = 100 MHz)
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
Frequency translation is accomplished with an NCO. Each of
the two processing channels shares a common NCO. Amplitude
and phase dither can be enabled on chip to improve the noise and
spurious performance of the NCO. A phase offset word is available
to create a known phase relationship between multiple AD6653s.
Because the decimation filter prevents usage of half the Nyquist
spectrum, a means is needed to translate the sampled input
spectrum into the usable range of the decimation filter. To
achieve this, a 32-bit, fine tuning, complex NCO is provided.
This NCO/mixer allows the input spectrum to be tuned to dc,
where it can be effectively filtered by the subsequent filter
blocks to prevent aliasing.
–50
–38
–28
–18 –10
0
10
50
06708-068
NCO/Filter
Half-band filter only
Half-band filter and FIR filter
NCO and half-band filter
NCO, half-band filter, and FIR filter
NCO, half-band filter, FIR filter, and
fADC/8 NCO
Figure 67. Example AD6653 20 MHz Bandwidth Input Signal Tuned to
DC Using the NCO (NCO Frequency = 14 MHz)
–50
–38
–28
–18 –10
0
10
50
06708-069
Mode
1
2
3
4
5
06708-067
Table 14 details the recommended downconverter modes of
operation in the AD6653.
Figure 68. Example AD6653 20 MHz Bandwidth Input Signal with the
Negative Image Filtered by the Half-Band and FIR Filters
The goal of the AD6653 digital filter block is to allow the sample
rate to be reduced by a factor of 2 while rejecting aliases that fall
into the band of interest. The half-band filter is designed to operate
as either a low-pass or high-pass filter and to provide greater
than 100 dB of alias protection for 22% of the input rate of the
structure. For an ADC sample rate of 150 MSPS, this provides
–50
0.25
12.5
22.5
50
06708-070
HALF-BAND DECIMATING FILTER AND FIR FILTER
Figure 69. Example AD6653 20 MHz Bandwidth Input Signal Tuned to
fADC/8 for Real Output
Rev. 0 | Page 31 of 80
AD6653
NUMERICALLY CONTROLLED OSCILLATOR (NCO)
FREQUENCY TRANSLATION
PHASE OFFSET
This processing stage comprises a digital tuner consisting of
a 32-bit complex numerically controlled oscillator (NCO). The
two channels of the AD6653 share a single NCO. The NCO is
optional and can be bypassed by clearing Bit 0 of Register 0x11D.
This NCO block accepts a real input from the ADC stage and
outputs a frequency translated complex (I and Q) output.
The NCO phase offset register at Address 0x122 and
Address 0x123 adds a programmable offset to the phase
accumulator of the NCO. This 16-bit register is interpreted
as a 16-bit unsigned integer. A 0x00 in this register corresponds
to no offset, and a 0xFFFF corresponds to an offset of 359.995°.
Each bit represents a phase change of 0.005°. This register
allows multiple NCOs to be synchronized to produce outputs
with predictable phase differences. Use the following equation
to calculate the NCO phase offset value:
The NCO frequency is programmed in Register 0x11E,
Register 0x11F, Register 0x120, and Register 0x121. These four
8-bit registers make up a 32-bit unsigned frequency programming
word. Frequencies between −CLK/2 and +CLK/2 are represented
using the following frequency words:
•
•
•
0x8000 0000 represents a frequency given by −CLK/2.
0x0000 0000 represents dc (frequency = 0 Hz).
0x7FFF FFFF represents CLK/2 − CLK/232.
NCO_FREQ = 2 ×
where:
NCO_PHASE is a decimal number equal to the 16-bit binary
number to be programmed at Register 0x122 and Register 0x123.
PHASE is the desired NCO phase in degrees.
NCO AMPLITUDE AND PHASE DITHER
Use the following equation to calculate the NCO frequency:
32
NCO_PHASE = 216 × PHASE/360
Mod( f , f CLK )
f CLK
where:
NCO_FREQ is a 32-bit twos complement number representing
the NCO frequency register.
f is the desired carrier frequency in hertz (Hz).
fCLK is the AD6653 ADC clock rate in hertz (Hz).
NCO SYNCHRONIZATION
The AD6653 NCOs within a single part or across multiple parts
can be synchronized using the external SYNC input. Bit 3 and
Bit 4 of Register 0x100 allow the NCO to be resynchronized on
every SYNC signal or only on the first SYNC signal after the
register is written. A valid SYNC causes the NCO to restart at
the programmed phase offset value.
The NCO block contains amplitude and phase dither to
improve the spurious performance. Amplitude dither improves
performance by randomizing the amplitude quantization errors
within the angular-to-Cartesian conversion of the NCO. This
option reduces spurs at the expense of a slightly raised noise
floor. With amplitude dither enabled, the NCO has an SNR of
>93 dB and an SFDR of >115 dB. With amplitude dither
disabled, the SNR is increased to >96 dB at the cost of SFDR
performance, which is reduced to 100 dB. The NCO amplitude
dither is recommended and is enabled by setting Bit 1 of
Register 0x11D.
Rev. 0 | Page 32 of 80
AD6653
DECIMATING HALF-BAND FILTER AND FIR FILTER
0
–10
–20
–30
AMPLITUDE (dBc)
The goal of the AD6653 half-band digital filter is to allow the
sample rate to be reduced by a factor of 2 while rejecting aliases
that fall into the band of interest. This filter is designed to operate
as either a low-pass or a high-pass filter and to provide >100 dB
of alias protection for 11% of the input rate of the structure.
Used in conjunction with the NCO and the FIR filter, the halfband filter can provide an effective band-pass. For an ADC
sample rate of 150 MSPS, this provides a maximum usable
bandwidth of 33 MHz.
Table 15. Fixed Coefficients for Half-Band Filter
Decimal Coefficient
(20-Bit)
844
−6189
25080
−79170
321584
524287
HALF-BAND FILTER FEATURES
In the AD6653, the half-band filter cannot be disabled. The
filter can be set for a low-pass or high-pass response. For a highpass filter, Bit 1 of Register 0x103 should be set; for a low-pass
response, this bit should be cleared. The low-pass response of
the filter with respect to the normalized output rate is shown in
Figure 70, and the high-pass response is shown in Figure 71.
0
–10
–20
–70
–110
0
0.1
0.2
0.3
0.4
FRACTION OF INPUT SAMPLE RATE
06708-072
–100
Figure 71. Half-Band Filter, High-Pass Response
The half-band filter has a ripple of 0.000182 dB and a rejection
of 100 dB. For an alias rejection of 100 dB, the alias protected
bandwidth is 11% of the input sample rate. If both the I and the
Q paths are used, a complex bandwidth of 22% of the input rate
is available.
In the event of even Nyquist zone sampling, the half-band filter
can be configured to provide a spectral reversal. Setting Bit 2
high in Address 0x103 enables the spectral reversal feature.
The half-band decimation phase can be selected such that the
half-band filter starts on the first or second sample following
synchronization. This shifts the output from the half-band between
the two input sample clocks. The decimation phase can be set to
0 or 1, using Bit 3 of Register 0x103.
FIXED-COEFFICIENT FIR FILTER
Following the half-band filters is a 66-tap, fixed-coefficient FIR
filter. This filter is useful in providing extra alias protection for
the decimating half-band filter. It is a simple sum-of-products
FIR filter with 66 filter taps and 21-bit fixed coefficients. Note
that this filter does not decimate. The normalized coefficients
used in the implementation and the decimal equivalent value of
the coefficients are listed in Table 16.
The user can either select or bypass this filter, but the FIR filter
can be enabled only when the half-band filter is enabled. Writing
Logic 0 to the enable FIR filter bit (Bit 0) in Register 0x102
bypasses this fixed-coefficient filter. The filter is necessary when
using the final NCO with a real output; bypassing it when using
other configurations results in power savings.
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
0.1
0.2
0.3
0.4
FRACTION OF INPUT SAMPLE RATE
06708-071
AMPLITUDE (dBc)
–60
–90
The 19-tap, symmetrical, fixed-coefficient half-band filter has low
power consumption due to its polyphase implementation. Table 15
lists the coefficients of the half-band filter. The normalized coefficients used in the implementation and the decimal equivalent
value of the coefficients are also listed. Coefficients not listed
in Table 15 are 0s.
Normalized
Coefficient
0.0008049
−0.0059023
0.0239182
−0.0755024
0.3066864
0.5
–50
–80
HALF-BAND FILTER COEFFICIENTS
Coefficient
Number
C0, C18
C2, C16
C4, C14
C6, C12
C8, C10
C9
–40
Figure 70. Half-Band Filter, Low-Pass Response
Rev. 0 | Page 33 of 80
AD6653
COMBINED FILTER PERFORMANCE
Normalized
Coefficient
0.0001826
0.0006824
0.0009298
0.0000458
−0.0012689
−0.0008345
0.0011806
0.0011387
−0.0018439
−0.0024557
0.0018063
0.0035825
−0.0021510
−0.0056810
0.0017405
0.0078602
−0.0013437
−0.0110626
−0.0000229
0.0146618
0.0018959
−0.0195594
−0.0053153
0.0255623
0.0104036
−0.0341468
−0.0192165
0.0471258
0.0354118
−0.0728111
−0.0768890
0.1607208
0.4396725
Decimal Coefficient
(21-Bit)
383
1431
1950
96
−2661
−1750
2476
2388
−3867
−5150
3788
7513
−4511
−11914
3650
16484
−2818
−23200
−48
30748
3976
−41019
−11147
53608
21818
−71611
−40300
98830
74264
−152696
−161248
337056
922060
SYNCHRONIZATION
The AD6653 half-band filters within a single part or across
multiple parts can be synchronized using the external SYNC
input. Bit 5 and Bit 6 of Register 0x100 allow the half-bands to
be resynchronized on every SYNC signal or only on the first
SYNC signal after the register is written. A valid SYNC causes
the half-band filter to restart at the programmed decimation
phase value.
The combined response of the half-band filter and the FIR filter
is shown in Figure 72. The act of bandlimiting the ADC data
with the half-band filter ideally provides a 3 dB improvement in
the SNR at the expense of the sample rate and available
bandwidth of the output data. As a consequence of finite math,
additional quantization noise is added to the system due to
truncation in the NCO and half-band. As a consequence of the
digital filter rejection of out-of-band noise (assuming no
quantization in the filters and with a white noise floor from the
ADC), there should be a 3.16 dB improvement in the ADC
SNR. However, the added quantization lessens improvement to
about 2.66 dB.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
0
0.1
0.2
0.3
0.4
FRACTION OF INPUT SAMPLE RATE
06708-073
Coefficient
Number
C0, C65
C1, C64
C2, C63
C3, C62
C4, C61
C5, C60
C6, C59
C7, C58
C8, C57
C9, C56
C10, C55
C11, C54
C12, C53
C13, C52
C14, C51
C15, C50
C16, C49
C17, C48
C18, C47
C19, C46
C20, C45
C21, C44
C22, C43
C23, C42
C24, C41
C25, C40
C26, C39
C27, C38
C28, C37
C29, C36
C30, C35
C31, C34
C32, C33
AMPLITUDE (dBc)
Table 16. FIR Filter Coefficients
Figure 72. Half-Band Filter and FIR Filter Composite Response
FINAL NCO
The output of the 32-bit fine tuning NCO is complex and
typically centered in frequency around dc. This complex output
is carried through the stages of the half-band and FIR filters to
provide proper antialiasing filtering. The final NCO provides a
means to move this complex output signal away from dc so that
a real output can be provided from the AD6653. The final NCO,
if enabled, translates the output from dc to a frequency equal to
the ADC sampling frequency divided by 8 (fADC/8). This provides
the user a decimated output signal centered at fADC/8 in frequency.
Optionally, this final NCO can be bypassed, and the dc-centered
I and Q values can be output in an interleaved fashion.
Rev. 0 | Page 34 of 80
AD6653
ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited
usefulness. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip actually occurs. In addition, because input
signals can have significant slew rates, latency of this function
is of major concern. Highly pipelined converters can have
significant latency. A good compromise is to use the output bits
from the first stage of the ADC for this function. Latency for
these output bits is very low, and overall resolution is not highly
significant. Peak input signals are typically between full scale
and 6 dB to 10 dB below full scale. A 3-bit or 4-bit output
provides adequate range and resolution for this function.
Using the SPI port, the user can provide a threshold above which
an overrange output is active. As long as the signal is below that
threshold, the output should remain low. The fast detect outputs
can also be programmed via the SPI port so that one of the pins
functions as a traditional overrange pin for customers who
currently use this feature. In this mode, all 14 bits of the converter
are examined in the traditional manner, and the output is high
for the condition normally defined as overflow. In either mode,
the magnitude of the data is considered in the calculation of the
condition (but the sign of the data is not considered). The threshold
detection responds identically to positive and negative signals
outside the desired range (magnitude).
FAST DETECT OVERVIEW
The AD6653 contains circuitry to facilitate fast overrange
detection, allowing very flexible external gain control implementations. Each ADC has four fast detect (FD) output pins
that are used to output information about the current state of
the ADC input level. The function of these pins is programmable
via the fast detect mode select bits and the fast detect enable bit
in Register 0x104, allowing range information to be output from
several points in the internal data path. These output pins can
also be set up to indicate the presence of overrange or underrange
conditions, according to programmable threshold levels. Table 17
shows the six configurations available for the fast detect pins.
Table 17. Fast Detect Mode Select Bit Settings
Fast Detect
Mode Select Bits
(Register 0x104[3:1])
000
001
010
011
100
101
Information Presented on
Fast Detect (FD) Pins of Each ADC1, 2
FD[3]
FD[2]
FD[1]
FD[0]
ADC fast magnitude (see Table 18)
OR
ADC fast magnitude
(see Table 19)
OR
F_LT
ADC fast
magnitude
(see Table 20)
C_UT
F_LT
ADC fast
magnitude
(see Table 20)
OR
C_UT
F_UT
F_LT
OR
F_UT
IG
DG
1
The fast detect pins are FD0A/FD0B to FD3A/FD3B for the CMOS mode
configuration and FD0+/FD0− to FD3+/FD3− for the LVDS mode
configuration.
2
See the ADC Overrange (OR) and Gain Switching sections for more
information about OR, C_UT, F_UT, F_LT, IG, and DG.
ADC FAST MAGNITUDE
When the fast detect output pins are configured to output the ADC
fast magnitude (that is, when the fast detect mode select bits are
set to 0b000), the information presented is the ADC level from
an early converter stage with a latency of only two clock cycles in
CMOS output modes. In LVDS output mode, the fast detect bits
have a latency of six cycles in all fast detect modes. Using the fast
detect output pins in this configuration provides the earliest
possible level indication information. Because this information is
provided early in the datapath, there is significant uncertainty in
the level indicated. The nominal levels, along with the uncertainty
indicated by the ADC fast magnitude, are shown in Table 18.
Because the DCO is at one-half the sample rate, the user can
obtain the fast detect information by sampling the fast detect
outputs on both the rising and falling edges of DCO (see Figure 2
for timing information).
Table 18. ADC Fast Magnitude Nomimal Levels
with Fast Detect Mode Select Bits = 000
ADC Fast
Magitude on
FD[3:0] Pins
0000
0001
0010
0011
0100
0101
0110
0111
1000
Rev. 0 | Page 35 of 80
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to −0.56
−0.56 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−8.52 to −4.08
−6.02 to −2.5
−4.08 to −1.16
−2.5 to FS
−1.16 to 0
AD6653
When the fast detect mode select bits are set to 0b001, 0b010, or
0b011, a subset of the fast detect output pins is available. In these
modes, the fast detect output pins have a latency of six clock
cycles, and the greater of the two input samples is output at the
DCO rate. Table 19 shows the corresponding ADC input levels
when the fast detect mode select bits are set to 0b001 (that is,
when the ADC fast magnitude is presented on the FD[3:1] pins).
Table 19. ADC Fast Magnitude Nomimal Levels
with Fast Detect Mode Select Bits = 001
ADC Fast
Magitude on
FD[2:0] Pins
000
001
010
011
100
101
110
111
Nominal Input
Magnitude
Below FS (dB)
<−24
−24 to −14.5
−14.5 to −10
−10 to −7
−7 to −5
−5 to −3.25
−3.25 to −1.8
−1.8 to 0
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −18.07
−30.14 to −12.04
−18.07 to −8.52
−12.04 to −6.02
−8.52 to −4.08
−6.02 to −2.5
−4.08 to −1.16
−2.5 to 0
Table 20. ADC Fast Magnitude Nomimal Levels
with Fast Detect Mode Select Bits = 010 or 011
Nominal Input
Magnitude
Below FS (dB)
<−14.5
−14.5 to −7
−7 to −3.25
−3.25 to 0
Coarse Upper Threshold (C_UT)
The coarse upper threshold indicator is asserted if the ADC fast
magnitude input level is greater than the level programmed in
the coarse upper threshold register (Address 0x105[2:0]). This
value is compared with the ADC Fast Magnitude Bits[2:0]. The
coarse upper threshold output is output two clock cycles after
the level is exceeded at the input and, therefore, provides a fast
indication of the input signal level. The coarse upper threshold
levels are shown in Table 21. This indicator remains asserted for a
minimum of two ADC clock cycles or until the signal drops
below the threshold level.
Table 21. Coarse Upper Threshold Levels
When the fast detect mode select bits are set to 0b010 or 0b011
(that is, when ADC fast magnitude is presented on the FD[2:1]
pins), the LSB is not provided. The input ranges for this mode
are shown in Table 20.
ADC Fast
Magitude on
FD[2:1] Pins
00
01
10
11
One such use is to detect when an ADC is about to reach full
scale with a particular input condition. The result is to provide
an indicator that can be used to quickly insert an attenuator that
prevents ADC overdrive.
Nominal Input
Magnitude
Uncertainty (dB)
Minimum to −12.04
−18.07 to −6.02
−8.52 to −2.5
−4.08 to 0
Coarse Upper Threshold
Register[2:0]
000
001
010
011
100
101
110
111
C_UT Is Active When Signal
Magnitude Below FS
Is Greater Than (dB)
<−24
−24
−14.5
−10
−7
−5
−3.25
−1.8
Fine Upper Threshold (F_UT)
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 12 ADC clock cycles. An overrange at the
input is indicated by this bit 12 clock cycles after it occurs.
GAIN SWITCHING
The AD6653 includes circuitry that is useful in applications either
where large dynamic ranges exist or where gain ranging converters
are employed. This circuitry allows digital thresholds to be set
such that an upper threshold and a lower threshold can be
programmed. Fast detect mode select bits = 010 through fast
detect mode select bits = 101 support various combinations of
the gain switching options.
The fine upper threshold indicator is asserted if the input
magnitude exceeds the value programmed in the fine upper
threshold register located in Register 0x106 and Register 0x107.
The 13-bit threshold register is compared with the signal
magnitude at the output of the ADC. This comparison is subject
to the ADC clock latency but is accurate in terms of converter
resolution. The fine upper threshold magnitude is defined by
the following equation:
dBFS = 20 log(Threshold Magnitude/213)
Fine Lower Threshold (F_LT)
The fine lower threshold indicator is asserted if the input
magnitude is less than the value programmed in the fine lower
threshold register located at Register 0x108 and Register 0x109.
The fine lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to ADC clock latency but is accurate
in terms of converter resolution. The fine lower threshold
magnitude is defined by the following equation:
dBFS = 20 log(Threshold Magnitude/213)
The operation of the fine upper threshold and fine lower
threshold indicators is shown in Figure 73.
Rev. 0 | Page 36 of 80
AD6653
Increment Gain (IG) and Decrement Gain (DG)
is compared with the magnitude at the output of the ADC. This
comparison is subject to the ADC clock latency but allows a
finer, more accurate comparison. The fine upper threshold
magnitude is defined by the following equation:
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external
gain control. The decrement gain indicator works in
conjunction with the coarse upper threshold bits, asserting
when the input magnitude is greater than the 3-bit value in the
coarse upper threshold register (Address 0x105). The increment
gain indicator, similarly, corresponds to the fine lower threshold
bits except that it is asserted only if the input magnitude is less
than the value programmed in the fine lower threshold register
after the dwell time elapses. The dwell time is set by the 16-bit
dwell time value located at Address 0x10A and Address 0x10B
and is set in units of ADC input clock cycles ranging from 1 to
65,535. The fine lower threshold register is a 13-bit register that
dBFS = 20 log(Threshold Magnitude/213)
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
The operation of the increment gain output and decrement gain
output is shown graphically in Figure 73.
UPPER THRESHOLD (COARSE OR FINE)
DWELL TIME
TIMER RESET BY
RISE ABOVE F_LT
FINE LOWER THRESHOLD
DWELL TIME
C_UT OR F_UT*
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
F_LT
DG
*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
Figure 73. Threshold Settings for C_UT, F_UT, F_LT, DG, and IG
Rev. 0 | Page 37 of 80
06708-074
IG
AD6653
SIGNAL MONITOR
The signal monitor result values can be obtained from the part by
reading back internal registers at Address 0x116 to Address 0x11B,
using the SPI port or the signal monitor SPORT output. The output
contents of the SPI-accessible signal monitor registers are set via
the two signal monitor mode bits of the signal monitor control
register (Address 0x112). Both ADC channels must be configured
for the same signal monitor mode. Separate SPI-accessible,
20-bit signal monitor result (SMR) registers are provided for
each ADC channel. Any combination of the signal monitor
functions can also be output to the user via the serial SPORT
interface. These outputs are enabled using the peak detector
output enable, the rms magnitude output enable, and the
threshold crossing output enable bits in the signal monitor
SPORT control register (Address 0x111).
For each signal monitor measurement, a programmable signal
monitor period register (SMPR) controls the duration of the
measurement. This time period is programmed as the number
of input clock cycles in a 24-bit signal monitor period register
located at Address 0x113, Address 0x114, and Address 0x115.
This register can be programmed with a period from 128 samples
to 16.78 (224) million samples.
current ADC input signal magnitude. This comparison continues
until the monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register (not accessible to the user), which can be read through
the SPI port or output through the SPORT serial interface. The
monitor period timer is reloaded with the value in the SMPR,
and the countdown is restarted. In addition, the magnitude of
the first input sample is updated in the peak level holding
register, and the comparison and update procedure, as
explained previously, continues.
Figure 74 is a block diagram of the peak detector logic. The
SMR register contains the absolute magnitude of the peak
detected by the peak detector logic.
FROM
MEMORY
MAP
POWER MONITOR
PERIOD REGISTER
TO
INTERRUPT
CONTROLLER
DOWN
COUNTER
IS COUNT = 1?
LOAD
FROM
INPUT
PORTS
CLEAR
MAGNITUDE
STORAGE
REGISTER
POWER MONITOR
HOLDING
REGISTER
LOAD
TO
MEMORY
MAP
LOAD
COMPARE
A>B
06708-075
The signal monitor block provides additional information
about the signal being digitized by the ADC. The signal monitor
computes the rms input magnitude, the peak magnitude, and/or
the number of samples by which the magnitude exceeds a
particular threshold. Together, these functions can be used to
gain insight into the signal characteristics and to estimate the
peak/average ratio or even the shape of the complementary
cumulative distribution function (CCDF) curve of the input
signal. This information can be used to drive an AGC loop to
optimize the range of the ADC in the presence of real-world
signals.
Figure 74. ADC Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE
PEAK DETECTOR MODE
In this mode, the root-mean-square (rms) or mean-square (ms)
magnitude of the input port signal is integrated (by adding an
accumulator) over a programmable time period (determined by
SMPR) to give the rms or ms magnitude of the input signal.
This mode is set by programming Logic 0 in the signal monitor
mode bits of the signal monitor control register or by setting the
rms magnitude output enable bit in the signal monitor SPORT
control register. The 24-bit SMPR, representing the period over
which integration is performed, must be programmed before
activating this mode.
The magnitude of the input port signal is monitored over a
programmable time period (determined by SMPR) to give the
peak value detected. This function is enabled by programming
a Logic 1 in the signal monitor mode bits of the signal monitor
control register or by setting the peak detector output enable bit
in the signal monitor SPORT control register. The 24-bit SMPR
must be programmed before activating this mode.
After enabling the rms/ms magnitude mode, the value in the
SMPR is loaded into a monitor period timer, and the
countdown is started immediately. Each input sample is
converted to floating-point format and squared. It is then
converted to 11-bit, fixed-point format and added to the
contents of the 24-bit accumulator. The integration continues
until the monitor period timer reaches a count of 1.
After enabling this mode, the value in the SMPR is loaded into
a monitor period timer, and the countdown is started. The magnitude of the input signal is compared with the value in the
internal peak level holding register (not accessible to the user),
and the greater of the two is updated as the current peak level.
The initial value of the peak level holding register is set to the
When the monitor period timer reaches a count of 1, the square
root of the value in the accumulator is taken and transferred
(after some formatting) to the signal monitor holding register,
which can be read through the SPI port or output through the
SPORT serial port. The monitor period timer is reloaded with
the value in the SMPR, and the countdown is restarted.
Because the dc offset of the ADC can be significantly larger
than the signal of interest (affecting the results from the signal
monitor), a dc correction circuit is included as part of the signal
monitor block to null the dc offset before measuring the power.
Rev. 0 | Page 38 of 80
AD6653
In addition, the first input sample signal power is updated in
the accumulator, and the accumulation continues with the
subsequent input samples. Figure 75 illustrates the rms
magnitude monitoring logic.
When the monitor period timer reaches a count of 1, the value
in the internal count register is transferred to the signal monitor
holding register, which can be read through the SPI port or
output through the SPORT serial port.
FROM
MEMORY
MAP
The monitor period timer is reloaded with the value in the
SMPR register, and the countdown is restarted. The internal
count register is also cleared to a value of 0. Figure 76 illustrates
the threshold crossing logic. The value in the SMR register is
the number of samples that have a magnitude greater than the
threshold register.
DOWN
COUNTER
IS COUNT = 1?
LOAD
CLEAR
ACCUMULATOR
LOAD
POWER MONITOR
HOLDING
REGISTER
TO
MEMORY
MAP
06708-076
FROM
INPUT
PORTS
Figure 75. ADC Input RMS Magnitude Monitoring Block Diagram
For rms magnitude mode, the value in the signal monitor result
(SMR) register is a 20-bit fixed-point number. The following
equation can be used to determine the rms magnitude in dBFS
from the MAG value in the register. Note that if the signal
monitor period (SMP) is a power of 2, the second term in the
equation becomes 0.
FROM
MEMORY
MAP
MAG
SMP
MS Magnitude = 10 log ⎛⎜ 20 ⎞⎟ − 10 log ⎡⎢ ceil [log 2 (SMP )] ⎤⎥
⎣2
⎦
⎝ 2 ⎠
THRESHOLD CROSSING MODE
In the threshold crossing mode of operation, the magnitude of
the input port signal is monitored over a programmable time
period (given by SMPR) to count the number of times it crosses
a certain programmable threshold value. This mode is set by
programming Logic 1x (where x is a don’t care bit) in the signal
monitor mode bits of the signal monitor control register or by
setting the threshold crossing output enable bit in the signal
monitor SPORT control register. Before activating this mode,
the user needs to program the 24-bit SMPR and the 13-bit
upper threshold register for each individual input port. The
same upper threshold register is used for both signal monitoring
and gain control (see the ADC Overrange and Gain Control
section).
After entering this mode, the value in the SMPR is loaded into
a monitor period timer, and the countdown is started. The magnitude of the input signal is compared with the upper threshold
register (programmed previously) on each input clock cycle.
If the input signal has a magnitude greater than the upper
threshold register, the internal count register is incremented by 1.
The initial value of the internal count register is set to 0. This
comparison and incrementing of the internal count register
continues until the monitor period timer reaches a count of 1.
DOWN
COUNTER
IS COUNT = 1?
LOAD
FROM
INPUT
PORTS
FROM
MEMORY
MAP
MAG
SMP
RMS Magnitude = 20 log ⎛⎜ 20 ⎞⎟ − 10 log ⎡⎢ ceil [log 2 (SMP )] ⎤⎥
⎣2
⎦
⎝ 2 ⎠
For ms magnitude mode, the value in the SMR is a 20-bit fixedpoint number. The following equation can be used to determine
the ms magnitude in dBFS from the MAG value in the register.
Note that if the SMP is a power of 2, the second term in the
equation becomes 0.
POWER MONITOR
PERIOD REGISTER
TO
INTERRUPT
CONTROLLER
CLEAR
A COMPARE
A>B
COMPARE
A>B
LOAD
POWER MONITOR
HOLDING
REGISTER
TO
MEMORY
MAP
B
UPPER
THRESHOLD
REGISTER
06708-077
POWER MONITOR
PERIOD REGISTER
TO
INTERRUPT
CONTROLLER
Figure 76. ADC Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS
For additional flexibility in the signal monitoring process, two
control bits are provided in the signal monitor control register.
They are the signal monitor enable bit and the complex power
calculation mode enable bit.
Signal Monitor Enable Bit
The signal monitor enable bit, located in Bit 0 of Register 0x112,
enables operation of the signal monitor block. If the signal
monitor function is not needed in a particular application, this
bit should be cleared to conserve power.
Complex Power Calculation Mode Enable Bit
When this bit is set, the part assumes that Channel A is
digitizing the I data and Channel B is digitizing the Q data for a
complex input signal (or vice versa). In this mode, the power
reported is equal to
I 2 + Q2
This result is presented in the Signal Monitor DC Value Channel A
register if the signal monitor mode bits are set to 00. The Signal
Monitor DC Value Channel B register continues to compute the
Channel B value.
DC CORRECTION
Because the dc offset of the ADC may be significantly larger
than the signal being measured, a dc correction circuit is included
to null the dc offset before measuring the power. The dc correction
circuit can also be switched into the main signal path, but this
may not be appropriate if the ADC is digitizing a time-varying
signal with significant dc content, such as GSM.
Rev. 0 | Page 39 of 80
AD6653
DC Correction Bandwidth
SIGNAL MONITOR SPORT OUTPUT
The dc correction circuit is a high-pass filter with a programmable
bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).
The bandwidth is controlled by writing the 4-bit dc correction
control register located at Register 0x10C, Bits[5:2]. The following
equation can be used to compute the bandwidth value for the dc
correction circuit:
The SPORT is a serial interface with three output pins: the SMI
SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and SMI
SDO (SPORT data output). The SPORT is the master and drives
all three SPORT output pins on the chip.
DC _ Corr _ BW = 2 −k −14 ×
SMI SCLK
f CLK
2× π
where:
k is the 4-bit value programmed in Bits[5:2] of Register 0x10C
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
fCLK is the AD6653 ADC sample rate in hertz (Hz).
DC Correction Readback
The current dc correction value can be read back in Register 0x10D
and Register 0x10E for Channel A and Register 0x10F and
Register 0x110 for Channel B. The dc correction value is a
14-bit value that can span the entire input range of the ADC.
DC Correction Freeze
Setting Bit 6 of Register 0x10C freezes the dc correction at its
current state and continues to use the last updated value as the
dc correction value. Clearing this bit restarts dc correction and
adds the currently calculated value to the data.
The data and frame sync are driven on the positive edge of the
SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4,
or 1/8 the ADC clock rate, based on the SPORT controls. The
SMI SCLK can also be gated off when not sending any data, based
on the SPORT SMI SCLK sleep bit. Using this bit to disable the
SMI SCLK when it is not needed can reduce any coupling errors
back into the signal path, if these prove to be a problem in the
system. Doing so, however, has the disadvantage of spreading
the frequency content of the clock. If desired the SMI SCLK can
be left running to ease frequency planning.
SMI SDFS
The SMI SDFS is the serial data frame sync, and it defines the
start of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
SMI SDO
The SMI SDO is the serial data output of the block. The data is
sent MSB first on the next positive edge after the SMI SDFS.
Each data output block includes one or more of rms magnitude,
peak level, and threshold crossing values from each datapath in
the stated order. If enabled, the data is sent, rms first, followed
by peak and threshold, as shown in Figure 77.
DC Correction Enable Bits
Setting Bit 0 of Register 0x10C enables dc correction for use in
the signal monitor calculations. The calculated dc correction value
can be added to the output data signal path by setting Bit 1 of
Register 0x10C.
GATED, BASED ON CONTROL
SMI SCLK
SMI SDFS
MSB
PK CH A
RMS/MS CH A LSB
20 CYCLES
16 CYCLES
THR CH A
MSB
16 CYCLES
RMS/MS CH B LSB
20 CYCLES
PK CH B
16 CYCLES
THR CH B
RMS/MS CH A
06708-078
SMI SDO
16 CYCLES
Figure 77. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)
GATED, BASED ON CONTROL
SMI SCLK
SMI SDFS
MSB
RMS/MS CH A LSB
20 CYCLES
THR CH A
16 CYCLES
MSB
RMS/MS CH B LSB
20 CYCLES
THR CH B
16 CYCLES
Figure 78. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)
Rev. 0 | Page 40 of 80
RMS/MS CH A
06708-079
SMI SDO
AD6653
CHANNEL/CHIP SYNCHRONIZATION
The AD6653 has a SYNC input that allows the user flexible
synchronization options for synchronizing the internal blocks.
The sync feature is useful for guaranteeing synchronized operation
across multiple ADCs. The input clock divider, NCO, half-band
filters, and signal monitor block can be synchronized using the
SYNC input. Each of these blocks, except for the signal monitor,
can be enabled to synchronize on a single occurrence of the
SYNC signal or on every occurrence.
The SYNC input is internally synchronized to the sample clock.
However, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be synchronized to
the input clock signal. The SYNC input should be driven using a
single-ended CMOS-type signal.
Rev. 0 | Page 41 of 80
AD6653
SERIAL PORT INTERFACE (SPI)
The AD6653 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
The SPI gives the user added flexibility and customization,
depending on the application. Addresses are accessed using
the serial port and can be written to or read from via the port.
Memory is organized into bytes that can be further divided into
fields. These fields are documented in the Memory Map section.
For detailed operational information, see Application Note
AN-877, Interfacing to High Speed ADCs via SPI, at
www.analog.com.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read command or a write
command is issued. This allows the serial data input/output (SDIO)
pin to change direction from an input to an output.
CONFIGURATION USING THE SPI
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this and
other features, see Application Note AN-877, Interfacing to High
Speed ADCs via SPI, at www.analog.com.
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Table 22). The SCLK/DFS
(serial clock) pin is used to synchronize the read and write data
presented from/to the ADC. The SDIO/DCS (serial data input/
output) pin is a dual-purpose pin that allows data to be sent and
read from the internal ADC memory map registers. The CSB
(chip select bar) pin is an active-low control that enables or
disables the read and write cycles.
Table 22. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
Function
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in
the timing frame.
Chip Select Bar. An active-low control that gates the
read and write cycles.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 79
and Table 5.
Other modes involving the CSB are available. The CSB can
be held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
HARDWARE INTERFACE
The pins described in Table 22 comprise the physical interface
between the user programming device and the serial port of the
AD6653. The SCLK pin and the CSB pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in Application Note AN-812, MicrocontrollerBased Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6653 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to AVDD or ground
during device power-on, they are associated with a specific
function. The Digital Outputs section describes the strappable
functions supported on the AD6653.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and its length is determined
by the W0 bit and the W1 bit.
Rev. 0 | Page 42 of 80
AD6653
CONFIGURATION WITHOUT THE SPI
SPI ACCESSIBLE FEATURES
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone CMOScompatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Table 24 provides a brief description of the general features
that are accessible via the SPI. These features are described in
Application Note AN-877, Interfacing to High Speed ADCs via
SPI (see www.analog.com). The AD6653 part-specific features
are described in the Memory Map Register Description section.
Table 23. Mode Selection
Clock
Offset
Pin
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND
(default)
AVDD
SDIO/DCS
SCLK/DFS
SMI SDO/OEB
SMI SCLK/PDWN
AGND
(default)
Feature Name
Modes
Configuration
Test I/O
Duty cycle stabilizer enabled
Duty cycle stabilizer disabled
Twos complement enabled
Offset binary enabled
Outputs in high impedance
Outputs enabled
Output Mode
Output Phase
Output Delay
VREF
Description
Allows the user to set either power-down
mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Allows the user to set the reference voltage.
Chip in power-down or
standby
Normal operation
tHIGH
tDS
tS
Table 24. Features Accessible Using the SPI
tDH
tCLK
tH
tLOW
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
06708-080
SDIO DON’T CARE
DON’T CARE
Figure 79. Serial Port Interface Timing Diagram
Rev. 0 | Page 43 of 80
AD6653
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the
channel index and transfer registers (Address 0x05 and
Address 0xFF); the ADC functions registers, including setup,
control, and test (Address 0x08 to Address 0x18); and the digital
feature control registers (Address 0x100 to Address 0x123).
An explanation of logic level terminology follows:
The memory map register table (see Table 25) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x18,
the VREF select register, has a hexadecimal default value of 0xC0.
This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s.
This setting is the default reference selection setting. The default
value uses a 2.0 V p-p reference. For more information on this
function and others, see Application Note AN-877, Interfacing to
High Speed ADCs via SPI. This document details the functions
controlled by Register 0x00 to Register 0xFF. The remaining
registers, from Register 0x100 to Register 0x123, are documented
in the Memory Map Register Description section.
Open Locations
All address and bit locations that are not included in Table 25
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 and Address 0x11E to
Address 0x123 are shadowed. Writes to these addresses do
not affect part operation until a transfer command is issued by
writing 0x01 to Address 0xFF, setting the transfer bit. This allows
these registers to be updated internally and simultaneously when
the transfer bit is set. The internal update takes place when the
transfer bit is set, and the bit autoclears.
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel.
In these cases, channel address locations are internally duplicated
for each channel. These registers and bits are designated in Table 25
as local. These local registers and bits can be accessed by setting
the appropriate Channel A or Channel B bits in Register 0x05.
If both bits are set, the subsequent write affects the registers of
both channels. In a read cycle, only Channel A or Channel B
should be set to read one of the two registers. If both bits are set
during an SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in Table 25 affect the entire
part or the channel features where independent settings are not
allowed between channels. The settings in Register 0x05 do not
affect the global registers and bits.
Default Values
After the AD6653 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 25.
Rev. 0 | Page 44 of 80
AD6653
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 25 are not currently supported for this device.
Table 25. Memory Map Registers
Addr.
Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0x00
0
SPI Port
Configuration
(Global)
0x01
Chip ID
(Global)
0x02
Chip Grade
(Global)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
Open
Speed Grade ID[4:3]
00 = 150 MSPS
01 = 125 MSPS
Default
Notes/
Comments
0x18
The nibbles
are mirrored
so that
LSB-first or
MSB-first
mode
registers
correctly,
regardless of
shift mode
Default is
unique chip
ID, different
for each
device; this is
a read-only
register
Speed grade
ID used to
differentiate
devices; this
is a read-only
register
0x0E
8-bit Chip ID[7:0]
(AD6653 = 0x0E)
(default)
Open
Default
Value
(Hex)
Open
Open
Open
Open
Channel Index and Transfer Registers
0x05
Open
Open
Channel
Index
Open
Open
Open
Open
Data
Channel B
(default)
Data
Channel A
(default)
0x03
0xFF
Transfer
Open
Open
Open
Open
Open
Open
Open
Transfer
0x00
ADC Functions Registers
0x08
Open
Power
Modes
Open
Open
Open
Open
Internal power-down
mode (local)
00 = normal operation
01 = full power-down
10 = standby
11 = normal operation
0x00
0x09
Global Clock
(Global)
Open
Open
External
powerdown pin
function
(global)
0 = pdwn
1 = stndby
Open
Open
Open
Open
Open
0x01
0x0B
Clock Divide
(Global)
Open
Open
Open
Open
Open
Rev. 0 | Page 45 of 80
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Duty
cycle
stabilize
(default)
0x00
Bits are
set to
determine
which device
on chip
receives the
next write
command;
applies to
local
registers
Synchronously
transfers data
from the
master shift
register to
the slave
Determines
various
generic
modes of
chip
operation
Clock divide
values other
than 000
automatically
activate
duty cycle
stabilization
AD6653
Addr.
(Hex)
0x0D
Register
Name
Test Mode
(Local)
Bit 7
(MSB)
Open
Bit 6
Open
0x10
Offset
Adjust
(Local)
Output Mode
Open
Open
Drive
strength
0 V to 3.3 V
CMOS or
ANSI
LVDS
1 V to 1.8 V
CMOS or
reduced
LVDS
(global)
Invert
DCO clock
Output
type
0 = CMOS
1 = LVDS
(global)
Interleaved
CMOS
(global)
Output
enable
bar
(local)
Open
Open
Open
Open
Open
Open
Open
Open
0x14
0x16
Clock Phase
Control
(Global)
0x17
DCO Output
Delay
(Global)
0x18
VREF Select
(Global)
Reference voltage
selection
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p
(default)
Digital Feature Control Registers
0x100
Sync Control
Signal
Half-band
monitor
next sync
(Global)
sync
only
enable
0x101
Open
Open
fS/8 Output
Mix Control
(Global)
0x102
Open
Open
FIR Filter
and Output
Mode
Control
(Global)
0x103
0x104
Digital Filter
Control
(Global)
Fast Detect
Control
(Local)
Bit 5
Reset
PN long
sequence
Bit 4
Reset
PN short
sequence
Bit 3
Open
Bit 0
(LSB)
Bit 2
Bit 1
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating
checkerboard
101 = PN long sequence
110 = PN short sequence
111 = one/zero word toggle
Offset adjust in LSBs from +31 to −32 (twos complement format)
Output
invert
(local)
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Open
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO clock delay
(delay = 2500 ps × register value/31)
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
Open
Open
Open
Open
Half-band
sync
enable
NCO32
next
sync only
NCO32
sync
enable
Clock
divider next
sync only
Open
Open
fS/8 start state
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Clock
divider
sync
enable
fS/8 next
sync only
FIR gain
fS/8 output
Complex
mix disable
output
0 = gain of
enable
2
1 = gain of
1
Half-band
Spectral
High-pass/
decimation reversal
low-pass
phase
select
Fast Detect Mode Select[2:0]
Rev. 0 | Page 46 of 80
Default
Value
(Hex)
0x00
Default
Notes/
Comments
When
enabled, the
test data is
placed on
the output
pins
in place of
ADC output
data
0x00
0x00
Configures
the outputs
and the
format of
the data
0x00
Allows
selection of
clock delays
into the
input clock
divider
0x00
0xC0
Master
sync
enable
0x00
fS/8 sync
enable
0x00
FIR filter
enable
0x00
Open
0x01
Fast
detect
enable
0x00
AD6653
Addr.
(Hex)
0x105
0x106
0x107
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
Register
Name
Coarse
Upper
Threshold
(Local)
Fine Upper
Threshold
Register 0
(Local)
Fine Upper
Threshold
Register 1
(Local)
Fine Lower
Threshold
Register 0
(Local)
Fine Lower
Threshold
Register 1
(Local)
Increase
Gain Dwell
Time
Register 0
(Local)
Increase
Gain Dwell
Time
Register 1
(Local)
Signal
Monitor DC
Correction
Control
(Global)
Signal
Monitor
DC Value
Channel A
Register 0
(Global)
Signal
Monitor
DC Value
Channel A
Register 1
(Global)
Signal
Monitor
DC Value
Channel B
Register 0
(Global)
Signal
Monitor
DC Value
Channel B
Register 1
(Global)
Signal
Monitor
SPORT
Control
(Global)
Bit 7
(MSB)
Open
Signal
Monitor
Control
(Global)
Bit 6
Open
Bit 5
Open
Bit 4
Open
Bit 0
Bit 2
Bit 1
(LSB)
Coarse Upper Threshold[2:0]
Bit 3
Open
Fine Upper Threshold[7:0]
Open
Open
Open
Open
Open
Fine Upper Threshold[12:8]
Open
0x00
0x00
Fine Lower Threshold[12:8]
0x00
Increase Gain Dwell Time[7:0]
0x00
In ADC clock
cycles
Increase Gain Dwell Time[15:8]
0x00
In ADC clock
cycles
DC Correction Bandwidth(k:[3:0])
DC
correction
freeze
DC
correction
for signal
path
enable
DC
correction
for signal
monitor
enable
0x00
DC Value Channel A[7:0]
Open
Default
Notes/
Comments
0x00
Fine Lower Threshold[7:0]
Open
Default
Value
(Hex)
0x00
Open
Read only
DC Value Channel A[13:8]
Read only
DC Value Channel B[7:0]
Open
Open
Open
RMS
magnitude
output
enable
Peak
detector
output
enable
Threshold
crossing
output
enable
Complex
power
calculation
mode
enable
Open
Open
Open
Read only
DC Value Channel B[13:8]
SPORT SMI SCLK divide
SPORT
SMI SCLK
00 = Undefined
sleep
01 = divide by 2
10 = divide by 4
11 = divide by 8
Signal monitor mode
Signal
monitor
00 = rms/ms magnitude
rms/ms
01 = peak detector
select
10 = threshold crossing
0 = rms
11 = threshold crossing
Rev. 0 | Page 47 of 80
Read only
Signal
monitor
SPORT
output
enable
0x04
Signal
monitor
enable
0x00
AD6653
Addr.
(Hex)
Register
Name
0x113
Signal
Monitor
Period
Register 0
(Global)
Signal
Monitor
Period
Register 1
(Global)
Signal
Monitor
Period
Register 2
(Global)
Signal
Monitor
Value
Channel A
Register 0
(Global)
Signal
Monitor
Value
Channel A
Register 1
(Global)
Signal
Monitor
Value
Channel A
Register 2
(Global)
Signal
Monitor
Value
Channel B
Register 0
(Global)
Signal
Monitor
Value
Channel B
Register 1
(global)
Signal
Monitor
Value
Channel B
Register 2
(Global)
NCO
Control
(Global)
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11D
0x11E
0x11F
0x120
0x121
0x122
0x123
NCO
Frequency 0
NCO
Frequency 1
NCO
Frequency 2
NCO
Frequency 3
NCO Phase
Offset 0
NCO Phase
Offset 1
Bit 7
(MSB)
Open
Bit 6
Open
Bit 5
Open
Default
Value
(Hex)
Default
Notes/
Comments
0x80
In ADC clock
cycles
Signal Monitor Period[15:8]
0x00
In ADC clock
cycles
Signal Monitor Period[23:16]
0x00
In ADC clock
cycles
Bit 4
Bit 3
Bit 2
1 = ms
Signal Monitor Period[7:0]
Bit 1
Bit 0
(LSB)
Signal Monitor Result Channel A[7:0]
Read only
Signal Monitor Result Channel A[15:8]
Read only
Open
Signal Monitor Result Channel A[19:16]
Read only
Signal Monitor Result Channel B[7:0]
Read only
Signal Monitor Result Channel B[15:8]
Read only
Open
Open
Open
Open
Open
Open
Open
Open
Signal Monitor Result Channel B[19:16]
Open
NCO32
phase
dither
enable
NCO32
amplitude
dither
enable
NCO32
enable
Read only
0x00
NCO Frequency Value[7:0]
0x00
NCO Frequency Value[15:8]
0x00
NCO Frequency Value[23:16]
0x00
NCO Frequency Value[31:24]
0x00
NCO Phase Value[7:0]
0x00
NCO Phase Value[15:8]
0x00
Rev. 0 | Page 48 of 80
AD6653
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0xFF, see Application Note AN-877, Interfacing to
High Speed ADCs via SPI, at www.analog.com.
fS/8 Output Mix Control (Register 0x101)
Bits[7:6]—Reserved
Bits[5:4]—fS/8 Start State
SYNC Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 5 and Bit 4 set the starting phase of the fS/8 output mix.
Bit 7 enables the sync pulse from the external sync input to the
signal monitor block. The sync signal is passed when Bit 7 and
Bit 0 are high. This is continuous sync mode.
Bit 1—fS/8 Next Sync Only
Bit 6—Half-Band Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the halfband sync enable bit (Register 0x100, Bit 5) are high, Bit 6 allows
the NCO32 to synchronize following the first sync pulse it receives
and ignore the rest. If Bit 6 is set, Bit 5 of Register 0x100 resets
after this sync occurs.
Bit 5—Half-Band Sync Enable
Bit 5 gates the sync pulse to the half-band filter. When Bit 5
is set high, the sync signal causes the half-band to resynchronize, starting at the half-band decimation phase selected in
Register 0x103, Bit 3. This sync is active only when the master
sync enable bit (Register 0x100, Bit 0) is high. This is continuous
sync mode.
Bit 4—NCO32 Next Sync Only
Bits[3:2]—Reserved
If the master sync enable bit (Register 0x100, Bit 0) and the fS/8
sync enable bit (Register 0x101, Bit 0) are high, Bit 1 allows the
fS/8 output mix to synchronize following the first sync pulse it
receives and ignore the rest. Bit 0 of Register 0x100 resets after it
synchronizes.
Bit 0—fS/8 Sync Enable
Bit 0 gates the sync pulse to the fS/8 output mix. This sync is
active only when the master sync enable bit (Register 0x100,
Bit 0) is high. This is continuous sync mode.
FIR Filter and Output Mode Control (Register 0x102)
Bits[7:4]—Reserved
Bit 3—FIR Gain
When Bit 3 is set high, the FIR filter path, if enabled, has a gain
of 1. When Bit 3 set low, the FIR filter path has a gain of 2.
Bit 2—fS/8 Output Mix Disable
If the master sync enable bit (Register 0x100, Bit 0) and the
NCO32 sync enable bit (Register 0x100, Bit 3) are high, Bit 4
allows the NCO32 to sync following the first sync pulse it receives
and ignores the rest. Bit 3 of Register 0x100 resets after a sync
occurs if Bit 4 is set.
Bit 2 disables the fS/8 output mix when enabled. Bit 2 should be
set along with Bit 1 to enable complex output mode.
Bit 1—Complex Output Mode Enable
Setting Bit 1 high enables complex output mode.
Bit 3—NCO32 Sync Enable
Bit 0—FIR Filter Enable
Bit 3 gates the sync pulse to the 32-bit NCO. When this bit is set
high, the sync signal causes the NCO to resynchronize, starting
at the NCO phase offset value. This sync is active only when the
master sync enable bit (Register 0x100, Bit 0) is high. This is
continuous sync mode.
When set high, Bit 0 enables the FIR filter. When Bit 0 is
cleared, the FIR filter is bypassed and shut down for power
savings.
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the clock
divider sync enable bit (Register 0x100, Bit 1) are high, Bit 2
allows the clock divider to synchronize following the first sync
pulse it receives and ignore the rest. Bit 1 of Register 0x100
resets after it synchronizes.
Digital Filter Control (Register 0x103)
Bits[7:4]—Reserved
Bit 3—Half-Band Decimation Phase
When set high, Bit 3 uses the alternate phase of the decimating
half-band filter.
Bit 2—Spectral Reversal
Bit 2 enables the spectral reversal feature of the half-band filter.
Bit 1—Clock Divider Sync Enable
Bit 1—High-Pass/Low-Pass Select
Bit 1 gates the sync pulse to the clock divider. The sync signal
is passed when Bit 1 and Bit 0 are high. This is continuous
sync mode.
Bit 1 enables the high-pass mode of the half-band filter when
set high. Setting this bit low enables the low-pass mode (default).
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Bit 0—Reserved
Bit 0 reads back as a 1.
Rev. 0 | Page 49 of 80
AD6653
Fast Detect Control (Register 0x104)
Bits[7:4]—Reserved
Signal Monitor DC Correction Control (Register 0x10C)
Bit 7—Reserved
Bits[3:1]—Fast Detect Mode Select
Bit 6—DC Correction Freeze
Bits[3:1] set the mode of the fast detect output bits according to
Table 17.
When Bit 6 is set high, the dc correction is no longer updated to
the signal monitor block, which holds the last dc value
calculated.
Bit 0—Fast Detect Enable
Bit 0 is used to enable the fast detect output pins. When the FD
outputs are disabled, the outputs go into a high impedance state.
In LVDS mode when the outputs are interleaved, the outputs go
high-Z only if both channels are turned off (power-down/
standby/output disabled). If only one channel is turned off
(power-down/standby/output disabled), the fast detect outputs
repeat the data of the active channel.
Coarse Upper Threshold (Register 0x105)
Bits[7:3]—Reserved
Bits[2:0]—Coarse Upper Threshold
These bits set the level required to assert the coarse upper
threshold indication (see Table 21).
Bits[5:2]—DC Correction Bandwidth
Bits[5:2] set the averaging time of the signal monitor dc correction
function. This 4-bit word sets the bandwidth of the correction
block, according to the following equation:
DC _ Corr _ BW = 2 − k − 14 ×
fCLK
2× π
where:
k is the 4 bit value programmed in Bits[5:2] of Register 0x10C
(values between 0 and 13 are valid for k; programming 14 or 15
provides the same result as programming 13).
fCLK is the AD6653 ADC sample rate in hertz (Hz).
Bit 1—DC Correction for Signal Path Enable
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x107, Bits[7:5]—Reserved
Register 0x107, Bits[4:0]—Fine Upper Threshold Bits[12:8]
Register 0x106, Bits[7:0]—Fine Upper Threshold Bits[7:0]
These registers provide a fine upper limit threshold. The 13-bit
value is compared with the 13-bit magnitude from the ADC
block and, if the ADC magnitude exceeds this threshold value,
the F_UT indicator is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x109, Bits[7:5]—Reserved
Setting this bit high causes the output of the dc measurement
block to be summed with the data in the signal path to remove
the dc offset from the signal path.
Bit 0—DC Correction for Signal Monitor Enable
This bit enables the dc correction function in the signal monitor
block. The dc correction is an averaging function that can be
used by the signal monitor to remove dc offset in the signal.
Removing this dc from the measurement allows a more
accurate power reading.
Register 0x109, Bits[4:0]—Fine Lower Threshold Bits[12:8]
Signal Monitor DC Value Channel A (Register 0x10D and
Register 0x10E)
Register 0x10E, Bits[7:6]—Reserved
Register 0x108, Bits[7:0]—Fine Lower Threshold Bits[7:0]
Register 0x10E, Bits[5:0]—DC Value Channel A[13:8]
These registers provide a fine lower limit threshold. This 13-bit
value is compared with the 13-bit magnitude from the ADC
block and, if the ADC magnitude is less than this threshold
value, the F_LT indicator is set.
Register 0x10D, Bits[7:0]—DC Value Channel A[7:0]
Increase Gain Dwell Time (Register 0x10A and
Register 0x10B)
Register 0x10B, Bits[7:0]—Increase Gain Dwell Time
Bits[15:8]
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel A.
Signal Monitor DC Value Channel B (Register 0x10F and
Register 0x110)
Register 0x110, Bits[7:6]—Reserved
Register 0x110, Bits[5:0]—Channel B DC Value Bits[13:8]
Register 0x10F, Bits[7:0]—Channel B DC Value Bits [7:0]
Register 0x10A, Bits[7:0]—Increase Gain Dwell Time
Bits[7:0]
These register values set the minimum time in ADC sample
clock cycles (after clock divider) that a signal needs to stay below
the fine lower threshold limit before the F_LT and IG are
asserted high.
These read-only registers hold the latest dc offset value computed
by the signal monitor for Channel B.
Signal Monitor SPORT Control (Register 0x111)
Bit 7—Reserved
Bit 6—RMS/MS Magnitude Output Enable
Bit 6 enables the 20-bit rms or ms magnitude measurement as
output on the SPORT.
Rev. 0 | Page 50 of 80
AD6653
Signal Monitor Result Channel A (Register 0x116 to
Register 0x118)
Register 0x118, Bits[7:4]—Reserved
Bit 5—Peak Detector Output Enable
Bit 5 enables the 13-bit peak measurement as output on the
SPORT.
Bit 4—Threshold Crossing Output Enable
Bit 4 enables the 13-bit threshold measurement as output on the
SPORT.
Bits[3:2]—SPORT SMI SCLK Divide
The values of these bits set the SPORT SMI SCLK divide ratio from
the input clock. A value of 0x01 sets divide-by-2 (default), a value
of 0x10 sets divide-by-4, and a value of 0x11 sets divide-by-8.
Bit 1—SPORT SMI SCLK Sleep
Setting Bit 1 high causes the SMI SCLK to remain low when the
signal monitor block has no data to transfer.
Register 0x118, Bits[3:0]—Signal Monitor Result
Channel A[19:16]
Register 0x117, Bits[7:0]—Signal Monitor Result
Channel A[15:8]
Register 0x116, Bits[7:0]—Signal Monitor Result
Channel A[7:0]
This 20-bit value contains the power value calculated by the
signal monitor block for Channel A. The content is dependent
on the settings in Register 0x112, Bits[2:1].
Bit 0—Signal Monitor SPORT Output Enable
Signal Monitor Result Channel B (Register 0x119 to
Register 0x11B)
Register 0x11B, Bits[7:4]—Reserved
When set, Bit 0 enables the signal monitor SPORT output to
begin shifting out the result data from the signal monitor block.
Register 0x11B, Bits[3:0]—Signal Monitor Result
Channel B[19:16]
Signal Monitor Control (Register 0x112)
Bit 7—Complex Power Calculation Mode Enable
Register 0x11A, Bits[7:0]—Signal Monitor Result
Channel B[15:8]
This mode assumes I data is present on one channel and Q data
is present on the alternate channel. The result reported is the
complex power measured as
Register 0x119, Bits[7:0]—Signal Monitor Result
Channel B[7:0]
I +Q
2
2
Bits[6:4]—Reserved
This 20-bit value contains the power value calculated by the
signal monitor block for Channel B. The content is dependent
on the settings in Register 0x112, Bits[2:1].
NCO Control (Register 0x11D)
Bits[7:3]—Reserved
Bit 3—Signal Monitor RMS/MS Select
Setting Bit 3 low selects rms power measurement mode. Setting
Bit 3 high selects ms power measurement mode.
Bits[2:1]—Signal Monitor Mode
Bit 2—NCO32 Phase Dither Enable
When Bit 2 is set, phase dither in the NCO is enabled. When
Bit 2 is cleared, phase dither is disabled.
Bit 2 and Bit 1 set the mode of the signal monitor for data
output to registers at Address 0x116 through Address 0x11B.
Setting these bits to 0x00 selects rms/ms magnitudde output,
setting these bits to 0x01 selects peak detector output, and
setting 0x10 or 0x11 selects threshold crossing output.
Bit 1—NCO32 Amplitude Dither Enable
Bit 0—Signal Monitor Enable
When Bit 0 is set, this bit enables the 32-bit NCO operating at
the frequency programmed into the NCO frequency register.
When Bit 0 is cleared, the NCO is bypassed and shuts down for
power savings.
Setting Bit 0 high enables the signal monitor block.
Signal Monitor Period (Register 0x113 to Register 0x115)
Register 0x115 Bits 7:0—Signal Monitor Period[23:16]
When Bit 1 is set, amplitude dither in the NCO is enabled.
When Bit 1 is cleared, amplitude dither is disabled.
Bit 0—NCO32 Enable
Register 0x114 Bits 7:0—Signal Monitor Period[15:8]
Register 0x113 Bits 7:0—Signal Monitor Period[7:0]
This 24-bit value sets the number of clock cycles over which the
signal monitor performs its operation. The minimum value for
this register is 128 cycles (programmed values less than 128
revert to 128).
Rev. 0 | Page 51 of 80
AD6653
NCO Frequency (Register 0x11E to Register 0x121)
Register 0x11E, Bits[7:0]—NCO Frequency Value[7:0]
NCO Phase Offset (Register 0x122 and Register 0x123)
Register 0x122, Bits[7:0]—NCO Phase Value[7:0]
Register 0x11F, Bits [7:0]—NCO Frequency Value[15:8]
Register 0x123, Bits[7:0]—NCO Phase Value[15:8]
Register 0x120, Bits[7:0]—NCO Frequency Value[23:16]
The 16-bit value programmed into the NCO phase value
register is loaded into the NCO block each time the NCO is
started or when an NCO SYNC signal is received. This process
allows the NCO to be started with a known nonzero phase.
Register 0x121, Bits[7:0]—NCO Frequency Value[31:24]
This 32-bit value is used to program the NCO tuning frequency.
The frequency value to be programmed is given by the following
equation:
Mod ( f , fCLK )
NCO_FREQ = 232 ×
fCLK
where:
NCO_FREQ is a 32-bit twos complement number representing
the NCO frequency register.
f is the desired carrier frequency in hertz (Hz).
fCLK is the AD6653 ADC clock rate in hertz (Hz).
Use the following equation to calculate the NCO phase offset value:
NCO_PHASE = 216 × PHASE/360
where:
NCO_PHASE is a decimal number equal to the 16-bit binary
number to be programmed at Register 0x122 and Register 0x123.
PHASE is the desired NCO phase in degrees.
Rev. 0 | Page 52 of 80
AD6653
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting system-level design and layout of the AD6653,
it is recommended that the designer become familiar with these
guidelines, which discuss the special circuit connections and
layout requirements needed for certain pins.
For the specifications provided in Table 2, the fS/2 spur, if in
band, is excluded from the SNR values. It is treated as a
harmonic, in terms of SNR. The fS/2 level is included in the
SFDR and worst other specifications.
–60
Power and Ground Recommendations
A single PCB ground plane should be sufficient when using the
AD6653. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
SFDR AND fS/2 SPUR (dBFS)
–70
–SFDR
–80
–90
fS/2 SPUR
–100
–110
06708-083
When connecting power to the AD6653, it is recommended
that two separate 1.8 V supplies be used: one supply should be
used for analog (AVDD) and digital (DVDD), and a separate
supply should be used for the digital outputs (DRVDD). The
AVDD and DVDD supplies, while derived from the same source,
should be isolated with a ferrite bead or filter choke and separate
decoupling capacitors. The designer can employ several different
decoupling capacitors to cover both high and low frequencies.
These capacitors should be located close to the point of entry
at the PC board level and close to the pins of the part with
minimal trace length.
–120
0
50
100
150
200
250
300
350
400
450
500
INPUT FREQUENCY (MHz)
Figure 80. AD6653-125 SFDR and fS/2 Spurious Level vs. Input Frequency (fIN)
with DRVDD = 1.8 V Parallel CMOS Output Mode
–60
Depending on the relationship of the IF frequency to the center
of the Nyquist zone, this spurious tone may or may not exist in the
AD6653 output band. Some residual fS/2 energy is present in
the AD6653, and the level of this spur is typically below the
level of the harmonics at clock rates of 125 MSPS and below.
Figure 80 shows a plot of the fS/2 spur level vs. analog input
frequency for the AD6653-125. At sampling rates above
125 MSPS, the fS/2 spur level increases and is at a higher level
than the worst harmonic as shown in Figure 81, which shows
the AD6653-150 fS/2 levels.
–SFDR
–80
fS/2 SPUR
–90
–100
–110
06708-084
Because the AD6653 output data rate is at one-half the sampling
frequency, there is significant fS/2 energy in the outputs of the
part. If this fS/2 spur falls in band, care must be taken to ensure
that this fS/2 energy does not couple into either the clock circuit
or the analog inputs of the AD6653. When fS/2 energy is coupled
in this fashion, it appears as a spurious tone reflected around fS/4,
3fS/4, 5fS/4, and so on. For example, in a 125 MSPS sampling
application with a 90 MHz single-tone analog input, this energy
generates a tone at 97.5 MHz. In this example, the center of the
Nyquist zone is 93.75 MHz; therefore, the 90 MHz input signal is
3.75 MHz from the center of the Nyquist zone. As a result, the fS/2
spurious tone appears at 97.5 MHz, or 3.75 MHz above the center
of the Nyquist zone. These frequencies are then tuned by the NCOs
before being output by the AD6653.
SFDR AND fS/2 SPUR (dBFS)
–70
fS/2 Spurious
–120
0
50
100
150
200
250
300
350
400
450
500
INPUT FREQUENCY (MHz)
Figure 81. AD6653-150 SFDR and fS/2 Spurious Level vs. Input Frequency (fIN)
with DRVDD = 1.8 V Parallel CMOS Output Mode
Operating the part with a 1.8 V DRVDD voltage rather than 3.3 V
DRVDD lowers the fS/2 spur. In addition, using LVDS, CMOS
interleaved, or CMOS IQ output modes also reduces the fS/2
spurious level.
LVDS Operation
The AD6653 defaults to CMOS output mode on power-up.
If LVDS operation is desired, this mode must be programmed
using the SPI configuration registers after power-up. When the
AD6653 powers up in CMOS mode with LVDS termination
resistors (100 Ω) on the outputs, the DRVDD current can be
higher than the typical value until the part is placed in LVDS
mode. This additional DRVDD current does not cause damage
to the AD6653, but it should be taken into account when considering the maximum DRVDD current for the part.
Rev. 0 | Page 53 of 80
AD6653
To avoid this additional DRVDD current, the AD6653 outputs
can be disabled at power-up by taking the OEB pin high. After
the part is placed into LVDS mode via the SPI port, the OEB
pin can be taken low to enable the outputs.
Exposed Paddle Thermal Heat Slug Recommendations
It is mandatory that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance. A continuous, exposed
(no solder mask), copper plane on the PCB should mate to the
AD6653 exposed paddle, Pin 0.
The copper plane should have several vias to achieve the lowest
possible resistive thermal path for heat dissipation to flow through
the bottom of the PCB. These vias should be filled or plugged with
nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
the PCB, a silkscreen should be overlaid to partition the continuous
plane on the PCB into several uniform sections. This provides
several tie points between the ADC and the PCB during the
reflow process. Using one continuous plane with no partitions
guarantees only one tie point between the ADC and the PCB.
See the evaluation board for a PCB layout example. For detailed
information about packaging and PCB layout of chip scale
packages, refer to Application Note AN-772, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP) (see www.analog.com).
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 48.
RBIAS
The AD6653 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and should have at least a 1% tolerance.
Reference Decoupling
The VREF pin should be externally decoupled to ground with
a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
SPI Port
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD6653 to keep these signals from transitioning at the converter
inputs during critical sampling periods.
Rev. 0 | Page 54 of 80
AD6653
EVALUATION BOARD
The AD6653 evaluation board provides all of the support circuitry
required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a double
balun configuration (default) or optionally through the AD8352
differential driver. The ADC can also be driven in a single-ended
fashion. Separate power pins are provided to isolate the DUT
from the AD8352 drive circuitry. Each input configuration can
be selected by proper connection of various components (see
Figure 83 to Figure 92). Figure 82 shows the typical bench
characterization setup used to evaluate the ac performance of
the AD6653.
External supplies can be used to operate the evaluation board
by removing L1, L3, L4, and L13 to disconnect the voltage
regulators supplied from the switching power supply. This enables
the user to individually bias each section of the board. Use P3
and P4 to connect a different supply for each section. At least
one 1.8 V supply is needed with a 1 A current capability for
AVDD and DVDD; a separate 1.8 V to 3.3 V supply is recommended for DRVDD. To operate the evaluation board using the
AD8352 option, a separate 5.0 V supply (AMP VDD) with
a 1 A current capability is needed. To operate the evaluation board
using the alternate SPI options, a separate 3.3 V analog supply
(VS) is needed, in addition to the other supplies. The 3.3 V
supply (VS) should have a 1 A current capability, as well. Solder
Jumper SJ35 allows the user to separate AVDD and DVDD,
if desired.
It is critical that the signal sources used for the analog input and
clock have very low phase noise (<<1 ps rms jitter) to realize the
optimum performance of the converter. Proper filtering of the
analog input signal to remove harmonics and lower the integrated
or broadband noise at the input is also necessary to achieve the
specified noise performance.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as the Rohde & Schwarz
SMA100A signal generators or the equivalent. Use 1 m long,
shielded, RG-58, 50 Ω coaxial cable for making connections to the
evaluation board. Enter the desired frequency and amplitude for
the ADC. The AD6653 evaluation board from Analog Devices,
Inc., can accept a ~2.8 V p-p or 13 dBm sine wave input for the
clock. When connecting the analog input source, it is recommended that a multipole, narrow-band, band-pass filter with 50 Ω
terminations be used. Band-pass filters of this type are available
from TTE, Allen Avionics, and K&L Microwave, Inc. Connect the
filter directly to the evaluation board, if possible.
See Figure 83 to Figure 100 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Connect
the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz
to 63 Hz. The output of the supply is a 2.1 mm inner diameter
circular jack that connects to the PCB at J16. Once on the PC
board, the 6 V supply is fused and conditioned before connection
to six low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
OUTPUT SIGNALS
The parallel CMOS outputs interface directly with the Analog
Devices standard ADC data capture board (HSC-ADC-EVALCZ).
For more information on the ADC data capture boards and their
optional settings, see www.analog.com/FIFO.
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
–
+
GND
VCP
AD6653
EVALUATION BOARD
12-BIT
PARALLEL
CMOS
12-BIT
PARALLEL
CMOS
CLK
SPI
Figure 82. Evaluation Board Connection
Rev. 0 | Page 55 of 80
HSC-ADC-EVALCZ
FPGA BASED
DATA
CAPTURE BOARD
PC RUNNING
VISUAL ANALOG
AND SPI
CONTROLLER
SOFTWARE
USB
CONNECTION
SPI
06708-108
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
+
VS
AINB
3.3V
–
GND
BAND-PASS
FILTER
3.3V
+
DRVDD IN
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
3.3V
–
GND
AINA
–
GND
BAND-PASS
FILTER
+
AMP VDD
ROHDE & SCHWARZ,
SMA100A,
2V p-p SIGNAL
SYNTHESIZER
1.8V
+
–
GND
5.0V
SWITCHING
POWER
SUPPLY
AVDD IN
6V DC
2A MAX
AD6653
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD6653 evaluation board.
POWER
Connect the switching power supply that is provided in the
evaluation kit between a rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz and P500.
VIN
The evaluation board is set up for a double balun configuration
analog input with optimum 50 Ω impedance matching from
70 MHz to 200 MHz. For more bandwidth response, the differential capacitor across the analog inputs can be changed or
removed (see Table 13). The common mode of the analog inputs
is developed from the center tap of the transformer via the CML
pin of the ADC (see the Analog Input Considerations section).
VREF
VREF is set to 1.0 V by tying the SENSE pin to ground by adding
a jumper on Header J5 (Pin 1 to Pin 2). This causes the ADC to
operate in 2.0 V p-p full-scale range. To place the ADC in 1.0 V p-p
mode (VREF = 0.5 V), a jumper should be placed on Header J4.
A separate external reference option is also included on the evaluation board. To use an external reference, connect J6 (Pin 1 to Pin 2)
and provide an external reference at TP5. Proper use of the VREF
options is detailed in the Voltage Reference section.
RBIAS
RBIAS requires a 10 kΩ resistor (R503) to ground and is used to
set the ADC core bias current.
CLOCK
CSB
The CSB pin is internally pulled up, setting the chip into
external pin mode, to ignore the SDIO and SCLK information.
To connect the control of the CSB pin to the SPI circuitry on the
evaluation board, connect J21, Pin 1 to J21, Pin 2.
SCLK/DFS
If the SPI port is in external pin mode, the SCLK/DFS pin sets the
data format of the outputs. If the pin is left floating, the pin is internally pulled down, setting the default data format condition to
offset binary. Connecting J2, Pin 1 to J2, Pin 2 sets the format to
twos complement. If the SPI port is in serial pin mode, connecting
J2, Pin 2 to J2, Pin 3 connects the SCLK pin to the on-board SPI
circuitry (see the Serial Port Interface (SPI) section).
SDIO/DCS
If the SPI port is in external pin mode, the SDIO/DCS pin sets
the duty cycle stabilizer. If the pin is left floating, the pin is
internally pulled up, setting the default condition to DCS enabled.
To disable the DCS, connect J1, Pin 1 to J1, Pin 2. If the SPI port
is in serial pin mode, connecting J1, Pin 2 to J1, Pin 3 connects
the SDIO pin to the on-board SPI circuitry (see the Serial Port
Interface (SPI) section).
ALTERNATIVE CLOCK CONFIGURATIONS
Two alternate clocking options are provided on the AD6653
evaluation board. The first option is to use an on-board crystal
oscillator (Y1) to provide the clock input to the part. To enable
this crystal, Resistor R8 (0 Ω) and Resistor R85 (10 kΩ) should
be installed, and Resistor R82 and Resistor R30 should be removed.
A second clock option is to use a differential LVPECL clock to
drive the ADC input using the AD9516 (U2). When using this
drive option, the AD9516 charge pump filter components need
to be populated (see Figure 87). Consult the AD9516 data sheet
for more information.
The default clock input circuitry is derived from a simple baluncoupled circuit using a high bandwidth 1:1 impedance ratio balun
(T5) that adds a very low amount of jitter to the clock path. The
clock input is 50 Ω terminated and ac-coupled to handle singleended sine wave inputs. The transformer converts the single-ended
input to a differential signal that is clipped before entering the
ADC clock inputs. When the AD6653 input clock divider is
utilized, clock frequencies up to 625 MHz can be input into the
evaluation board through Connector S5.
To configure the clock input from S5 to drive the AD9516
reference input instead of directly driving the ADC, the
following components need to be added, removed, and/or
changed.
1.
Remove R32, R33, R99, and R101 in the default
clock path.
PDWN
2.
Populate C78 and C79 with 0.001 μF capacitors and
R78 and R79 with 0 Ω resistors in the clock path.
To enable the power-down feature, connect J7, shorting the
PDWN pin to AVDD.
In addition, unused AD9516 outputs (one LVDS and one LVPECL)
are routed to optional Connector S8 through Connector S11 on
the evaluation board.
Rev. 0 | Page 56 of 80
AD6653
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
1.
Remove C1, C17, C18, and C117 in the default analog
input path.
This section provides a brief description of the alternative
analog input drive configuration using the AD8352. When
using this particular drive option, some additional components
need to be populated. For more details on the AD8352 differential
driver, including how it works and its optional pin settings,
consult the AD8352 data sheet.
2.
Populate C8 and C9 with 0.1 μF capacitors in the analog
input path. To drive the AD8352 in the differential input
mode, populate the T10 transformer; the R1, R37, R39,
R126, and R127 resistors; and the C10, C11, and C125
capacitors.
3.
Populate the optional amplifier output path with the
desired components including an optional low-pass filter.
Install 0 Ω resistors, R44 and R48. R43 and R47 should be
increased (typically to 100 Ω) to increase to 200 Ω the
output impedance seen by the AD8352.
To configure the analog input to drive the AD8352 instead of
the default transformer option, the following components need
to be added, removed, and/or changed for Channel A. For
Channel B the corresponding components should be changed.
Rev. 0 | Page 57 of 80
AIN+
AIN-
S2
2
1
R28
1
R1
57.6 OH M
R121
0 OH M
RES0402
R120
0 OH M
INA+
0.1U
C117
0.1U
C1
0 OH M
R2
INA+
0.1U
C47
INA -
0.1U
C9
T10
R54
0 OH M
P
S
3
2
1
DN P
R36
5
4
P
5
4
ETC1-1-1 3
T1
1ADT1_1W T6
2
3
T7
0 OH M
R110
S
1
2
3
CML
1
2
3
S
ETC1-1-1 3
T2
P
5
4
0.1U
C18
0.1U
C17
DEFAULT AMPLIFIER INPUT PATH
4
5
ETC1-1-1 3
0 OH M
F
0.1U
R29
R31
24.9 OH M
R35
C8
0.1U
C11
0.1U
C10
R126
INA-
0 OH M
R48
0 OH M
R44
C125
.3PF
R37
100 OH M
CML
4
3
2
1
0 OH M
R42
AMP+A
AMP-A
0 OH M
R39
DN P
R38
0 OH M
R127
4.12K
VIN
RDN
RGN
RGP
5
16
VIP
RDP
R40
6
ENB
15
A B
W1
10K OH M
7
GND
Z1
C3
0.1U
9
10
11
12
C22
0.1U
GND
VON
VCC
8
GND
VOP
VCC
13
AD8352
VCM
14
AMPVDD
R41
R5
OPTIONALAMPLIFIERINPUT PATH
F
S1
2
Figure 83. Evaluation Board Schematic, Channel A Analog Inputs
57.6 OH M
R43
R47
10K OH M
57.6 OH M
24.9 OH M
0 OH M
F
R4
33 OH M
33 OH M
Rev. 0 | Page 58 of 80
33 OH M
R27
33 OH M
R26
C23
0.1U
C27
10U
0.001U
C16
0.001U
C12
AMPVDD
C2
0.1U
C5
4.7PF
L15 1
IND0603
L14 1
IND0603
DNP
120N H
DNP
120N H
2
2
0 OH M
R49
DNP
180N H
DNP
R50
0 OH M
VIN+A
TP15
1
L16
180N H
VIN- A
TP14
1
L17 1
IND0603
C4
18PF
DNP
1
IND0603
2
2
AVDD
AVDD
AMP+A
C139
12PF
DNP
AMP-A
06708-090
AMPVDD
AD6653
SCHEMATICS
AIN+
AIN-
S4
S3
1
1
57.6OHM
R52
57.6OHM
R51
RES0402
0 OHM
R123
RES0402
0 OHM
R122
INB-
0.1U
C31
INB+
0.1U
C6
0.1U
C28
0 OHM
R67
INB-
4
5
S
3
2
1
DNP
0.1U
C38
0.1U
C39
.3PF
C128
0.1U
4
5
T8
P
T3
4
5
6
S
ETC1-1-13
3
2
1
ADT1_1W
T
0 OHM
R111
3
2
1
CML
4
5
P
T4
S
ETC1-1-13
3
2
1
DNP
R133
0 OHM
R132
R6
0 OHM
DEFAULT AMPLIFIER INPUT PATH
0 OHM
R55
T11
C51
P
ETC1-1-13
0 OHM
F
0.1U
R134
R135
INB+
24.9OHM
24.9OHM
R66
R128
C30
R129
OPTIONAL AMPLIFIER INPUT PATH
F
2
R68
F
Figure 84. Evaluation Board Schematic, Channel B Analog Inputs
2
100OHM
0.1U
C82
0.1U
C7
4
3
2
1
VIN
RDN
RGN
RGP
RDP
5
16
VIP
Z2
7
AMP+B
0 OHM
R96
AMP-B
GND
VON
VCC
8
GND
R53
VOP
VCC
13
AMPVDD
AD8352
VCM
14
GND
0 OHM
R95
CML
0 OHM
R94
6
ENB
15
A B
C60
0.1U
9
10
11
12
R70
R71
4.12 K
R69
10KOHM
33OHM
33OHM
Rev. 0 | Page 59 of 80
0 OHM
C61
0.1U
C24
0.1U
C62
10U
C83
0.1U
R72
R131
AMPVDD
0.001U
C140
0.001U
C46
57.6OHM
10KOHM
W2
R73
33OHM
R74
33OHM
L19 1
IND0603
L18 1
IND0603
120NH
DNP
120NH
DNP
2
2
C84
4.7PF
L21 1
IND0603
C19
18PF
DNP
L20 1
IND0603
180NH
DNP
180NH
DNP
2
2
R80
R81
0 OHM
0 OHM
TP17
1
TP16
1
AMP-B
C29
12PF
DNP
AMP+B
VIN+B
VIN-B
AVDD
AVDD
06708-091
AMPVDD
AD6653
S6
SMA200U P
ENC\
ENC
1
1
R30
R7
R8
57.6OHM
57.6OHM
0 OHM
R85
R82
R90
10KOHM
10KOHM
0 OHM
R3
0 OHM
Figure 85. Evaluation Board Schematic, DUT Clock Input
0.001U
C77
0.001U
C94
0.001U
C63
0.001U
4
5
0.1U
OPT_CLK-
3
S 2
T5
ETC1-1-13
P
1
6 T9
5
4
ADT1_1W
T
1
2
3
C56
OPT_CLK+
0.1U
R32
0.001U
C79
0 OHM
R33
0 OHM
0.001U
C78
OPT_CLK-
ALTCLK-
OPT_CLK+
ALTCLK+
R78
0 OHM
R79
0 OHM
R101
0 OHM
R99
0 OHM
R83
0.1U
C21
24.9OHM
R84
0.1U
C20
24.9OHM
C145
1
C64
F
S5
SMA200U P
2
2
Rev. 0 | Page 60 of 80
2
VS
CLK-
CLK+
AD6653
06708-092
TP2
DNP
R34
1
S7
1
CLK IN
AD9516
TEST
2
C104
0.1U
VS_OUT_D R
VCXO_CLK-
RES0402
0 OH M
R125
RES0402
R10
0 OH M
C100
0.1U
0 OH M
R124
VCXO_CLK+
LD
R89
C101
0.1U
C98
0.1U
0.1U
C143
0.1U
C142
C80
18PF
C99
0.1U
VS
SCLK
VCP
BYPASS_LDO
9
BYPASS_LDO
CLK
NC1
C96
0.1U
SCLK
16
15
CLKB
14
13
C97
0.1U
VS_CLK_DIST
12
VS_VCO
11
10
LF
SYNCB
LF
REF_SEL
7
STATUS
6
8
STATUS
CP
VCP
5
4
LD
REFMON
3
2
VS_PLL_1
1
SYNCB
CP
VCP
REFMON
TP18
TEST
1
REF_SEL
TP19
TEST
1
VS
OPT_CLK +
R1 2
AGND
GND_REF59
4.12K
VS
OUT056
U2
AD9516_64LFCS
P
OUT0B55
26
OUT4B
TP20
49.9 OH M
VS_OUT_DR
VS_OUT01_DRV54
27
VS_OUT45_DR
V
VS
OUT153
OUT5
28
OPT_CLK -
REFIN64
CSB
17
CSB_2
R1 1
REFINB63
5.1K
NC2
18
CP_RSET62
NC3
19
VS_PLL_261
NC4
20
VS_PRESCALE
R60
SDO
21
SDO
SDIO
22
SDI
OUT1B52
OUT5B
29
RSET_CLOC
K58
RESETB
23
RESETB
VS_OUT67_250
VS_OUT45_DIV
30
VS_OUT01_DIV51
VS_OUT89_1
VS_REF57
PDB
24
PDB
OUT4
25
Figure 86. Evaluation Board Schematic, Optional AD9516 Clock Circuit
VS_OUT_DR
VS_OUT67_149
VS_OUT89_2
Rev. 0 | Page 61 of 80
31
VS
38
37
36
35
34
33
GND_OUT89_DI
V
OUT9B
OUT9
OUT8B
OUT8
VS
39
OUT3B
R88
200
AGND
VS
R92
200
R91
200
40
OUT3
VS_OUT23_DIV
41
R86
200
ALTCLK+
42
OUT2B
VS_OUT23_DR
V
VS_OUT_DR
ALTCLK-
43
LVPEC L
TO ADC
1TP8
0.001U
C141
44
AGND
R9
OUT2
45
46
47
48
100 OH M
GND_ESD
OUT7B
OUT7
OUT6B
OUT6
OUT6N
SYNC
0.1U
C86
0.1U
C85
0.1U
C87
0.1U
C88
1
1
1
1
S8
S9
S10
S11
2
32
2
PAD
2
LVDS
LVPEC L
OUTPU T
OUTPU T
06708-093
OUT6P
AD6653
2
100 OH M
R75
R45
Rev. 0 | Page 62 of 80
Figure 87. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input
BYPASS_LDO
R98
VAL
C89
SEL
VAL
R93
VAL
R137
VAL
C90
SEL
57.6OHM
SEL
C91
C144
SEL
0.1U
Charge Pump Filter
1
RES060 3
R136
SYNC
2
VAL
R97
3
2
A2
U3
NL27WZ04
C92
SEL
GND
A1
Y1
4
5
RES0402
0 OHM
R117
RES0402
LF
RES0402
R87
OSCVECTRON_VS50 0
RES0402
0 OHM
R104
U25
OUT2
3
GND
4
5
6
VCC
OUT1
24.9OHM
2
OUT_DISABLE
VS-500
1
FREQ_CTRL_V
33OHM
R46
TP1
1
6
0 OHM
R116
Y2
VCC
SYNC
R106
R108
1
R107
R109
C25
LD
10KOHM
10KOHM
S12
SMA200U P
RES040 2
RES040 2
VS
10KOHM
10KOHM
C26
0.1U
RES040 2
RES040 2
R76
200
R114
RES0402
0 OHM
0 OHM
R139
RES0402
VCP
VCP
RES040 2
10KOHM
R100
VCXO_CLK-
VCXO_CLK+
VS
REF_SE L
VS
PD B
VS
SYNC B
VS
RESET B
06708-094
VS
AD6653
AC
RES040 2
10KOHM
R105
RES040 2
10KOHM
R103
RES040 2
10KOHM
R102
Rev. 0 | Page 63 of 80
Figure 88. Evaluation Board Schematic, DUT
NC
D7A
NC
DVDD2
FD3B
FD2B
FD1B
D11A_MSB_
FD0B
FD0A
SYNC
FD1A
SPI_CSB
FD2A
CLK-
FD3A
CLK+
57
52
51
50
49
C137
0.001U
D6A
C121
0.1U
C120
0.1U
D0B_LSB
U1
SPI_SCLK/DFS
DRVDD1
C109
0.1U
C40
0.1U
48
SPI_SDIO/DCS
AVDD3
D1B
C122
0.001U
C126
0.001U
SPI_SCLK
47
46
AVDD2
VIN+B
DRGND1
C127
0.001U
R64
AVDD
SPI_SDIO
45
44
VIN-B
RBIAS
CML
0.001U
D2B
D1A
D2A
63
62
61
60
59
58
56
55
54
53
R57
22ohm
9
10
11
12
13
14
15
16
RPAK8
DRVDD
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B_MSB
DCOB
DCOA
NC
NC
D0A_LSB
64
AVDD
1
AVDD
VIN+B
43
42
41
40
C36
0.1U
C35
DRVDD
D5A
DVDD
TP6
R63RES0402
0 OHM
VIN-B
CML
TP3
AD6653
D10A
SENSE
VREF
D9A
10KOHM
RES0402
0.1U
39
38
VIN-A
VIN+A
1
D8A
AVDD
C32
VIN-A
R112
AVDD1
32
37
31
36
30
DVDD1
TP5
AVDD
29
VIN+A
28
C14
0.1U
27
SMI_SDFS
26
PWR_SDF
SMI_SCLK/PDWN
RES0402
25
35
RES040 2
SMI_SDO/OEB
R62
24
34
33
0 OHM
R115
0 OHM
23
1
C15
1U
J4 - INSTALLFOR 0.5V VREF/IV INPUTSPAN
J5 - INSTALLFORIV VREF/2VINPUTSPAN
J6 - INSTALLFOR EXTERNALREFERENCEMODE
J7 - INSTALLFOR PDWN
J8 - INSTALLFOROUTPUTDISABLE
RES0402
RPAK8
R113
22ohm
PWR_SCL
K
PWR_SD
FD3A
FD2A
FD1A
FD0A
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
0 OHM
22
D3B
CLK+
21
DRGND
CLK-
DVDD
20
D4A
SPI_CSB
19
D3A
SYNC
18
DVDD
17
8
7
6
5
4
3
2
1
1
2
3
4
5
6
7
8
9
DRVDD
10
11
12
13
14
15
16
5
6
7
8
RPAK4
22ohm
SPARE2
SPARE1
FD3B
FD2B
FD1B
FD0B
R58
C34
R59
RPAK8
22ohm
4
3
2
1
0.001U
9
10
11
12
13
14
15
16
R60
RPAK8
22ohm
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
0.1U
R61
RPAK8
22ohm
C33
9
10
11
12
13
14
15
16
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
D3B
D2B
D1B
D0B
1
1
1
1
D11A
D10A
D9A
D8A
D7A
D6A
D5A
D4A
D11B
D10B
D9B
D8B
D7B
D6B
D5B
D4B
D3A
D2A
D1A
D0A
SPARE4
SPARE3
DCOA
DCOB
06708-095
DRVDD
AD6653
D5A
D4A
Figure 89. Evaluation Board Schematic, Digital Output Interface
FD1B
FD0B
V_DIG
SPARE2
SPARE1
FD3B
FD2B
D3B
D2B
V_DIG
D1B
D0B
D5B
D4B
D7B
D6B
D11B
D10B
V_DIG
D9B
D8B
SPARE4
SPARE3
DCOA
DCOB
D3A
D2A
V_DIG
D1A
D0A
D7A
D6A
D11A
D10A
V_DIG
D9A
D8A
FD3A
FD2A
FD1A
FD0A
V_DIG
PWR_SDO
PWR_SDFS
PWR_SCLK
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U17
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
74VCX162244MTD
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
74VCX162244MTD
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
U16
74VCX162244MTD
V_DIG
V_DIG
V_DIG
V_DIG
SDO_OUT
SDFS_OUT
SCLK_OUT
OUT6P
OUT6N
J11
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
CSB
TYCO_HM-ZD
CHANNELB
B1
C10
D10
C9
D9
A9
B9
C8
D8
A8
B8
C7
D7
A7
B7
C6
D6
A6
B6
A10
B10
C5
D5
A5
B5
C4
D4
A4
B4
C3
D3
A3
B3
C2
D2
A2
B2
C1
D1
A1
CSB_2
SCLK
TYCO_HM-ZD
J10
BG1
BG2
BG3
BG4
BG5
BG6
BG7
BG8
BG9
BG10
DG1
DG2
DG3
DG4
DG5
DG6
DG7
DG8
DG9
DG10
R140
RES0402
0 OHM
R145
RES0402
0 OHM
R144
VS
0 OHM
SCLK_OUT
OUT6N
TP22
TEST
1
TP23 TEST
1
TP24 TEST
1
OUT6P
SYNC
SDI
RES0402
R143
0 OHM
SDO_OUT
SDFS_OU
T
RES0402
0 OHM
R142
RES0402
0 OHM
R119
R141
RES0402
SDO
RESETB
TP21
TEST
1
VS
R118
CHANNELA
B1
C10
D10
C9
D9
A9
B9
C8
D8
A8
B8
C7
D7
A7
B7
C6
D6
A6
B6
A10
B10
C5
D5
A5
B5
C4
D4
A4
B4
C3
D3
A3
B3
C2
D2
A2
B2
C1
D1
A1
A1
D1
C1
B2
A2
D2
C2
B3
A3
D3
C3
B4
A4
D4
C4
B5
A5
D5
C5
B10
A10
B6
A6
D6
C6
B7
A7
D7
C7
B8
A8
D8
C8
B9
A9
D9
C9
D10
C10
B1
J12
DG10
DG9
DG8
DG7
DG6
DG5
DG4
DG3
DG2
DG1
BG10
BG9
BG8
BG7
BG6
BG5
BG4
BG3
BG2
BG1
TYCO_HM-ZD
V_DIG
V_DIG
C65
0.1U
C66
0.1U
C72
0.1U
C67
0.1U
C73
0.1U
C68
0.1U
C74
0.1U
C69
0.1U
C75
0.1U
C70
0.1U
C76
0.1U
C71
0.1U
06708-096
DIGITAL/HSC-ADC-EVALCZ INTERFACE
10KOHM
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RES040 2
U15
R130
VAL
R77
Rev. 0 | Page 64 of 80
100OHM
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AD6653
RES040 2
10KOHM
Rev. 0 | Page 65 of 80
CSB
SDO
SDI
SCLK
CSB_2
V_DIG
RES0402
CSB
SCLK
10KOHM
R18
C13
0.1U
R24
A2
GND
A1
3
2
1
RES0402
A2
Y1
U8
Y2
Y2
VCC
NC7WZ16P6 X
GND
A1
Y1
VCC
NC7WZ07P6 X
RES0603
10KOHM
3
2
1
RES040 2
R19
U7 1KOHM
4
5
6
4
5
6
SDO
V_DIG
C81
0.1U
V_DIG
V_DIG
V_DIG
RES0603
1KOHM
R21
RES0603
1KOHM
R20
R17
Figure 90. Evaluation Board Schematic, SPI Circuitry
RES0603
100KOHM
VS
V_DIG
R22
3
RES0603
SPI_CSB
100KOHM
R23
RES0603
100KOHM
J2
3
1
J1
SPI_SCLK
SPI_SDIO
1
V_DIG
J1 - JUMPERPINS 2 TO 3 FOR SPI OPERATION
JUMPERPINS 1 TO 2 FORDCS ENABLE
J2 - JUMPERPINS 2 TO 3 FOR SPI OPERATION
JUMPERPINS 1 TO 2 FOR TWOS COMPLIMENTOUTPUT
J21 - INSTALLJUMPERFOR SPI OPERATION
06708-097
SDI
AD6653
10KOHM
R65
POWER_JAC K
2
Figure 91. Evaluation Board Schematic, Power Supply
Rev. 0 | Page 66 of 80
P4
P3
P2
P1
VCP
VS
DRVDDIN
SJ35
P4
P66
5
P5
4
P4
3
P3
2
P2
1
1
AVDDIN
SMDC110F
C41
10U
F2
OPTIONALPOWERSUPPLYINPUTS
P3
1
P1
1
3
L6
IND1210
10UH
10uh
L10
IND1210
L9
IND1210
10UH
1
2
1
2
2
CR7
2
C53
10U
C102
10U
C52
10U
BNX-016
3 PSG
1 BIAS
C58
0.1U
C103
0.1U
C57
0.1U
CG6
CG5
CG 4
CB 2
1
CR8
10uh
IND1210
L11
1
R16
DRVDD
2
PWR_IN
DVDD
AVDD
2
C54
10U
RES060 3
SHOT_RECT
261OHM
TP25
1
C59
0.1U
1
2
V_DIG
CR10
S2A_RECT
1
CR11
S2A_RECT
1
C42
1U
1TP4
1
1
TP13
1
TP12
1
TP10
1
1TP9
SD
6
8 IN
7 IN2
ADP3334
2
C44
1U
CR12
S2A_RECT
GND TESTPOINTS
2
3
VR3
PAD
5
GND
OUT
VR1
OUT 1
OUT2 2
FB 3
IN
4
GND
1
F1
C43
1U
1
10uh
DRVDD
3.3
2.5
1.8
R13
140K
107K
76.8K
2
C93
0.001U
L3
IND1210
R14
78.7K
94.0K
147K
DRVDDSETTING
ADP333 9
R13
J16
76.8KOHM
R14
S2A_REC
T
147KOHM
AC
C45
1U
AVDDIN
1
10uh
L4
IND1210
2
DRVDDIN
06708-098
POWERINPUT
6V, 2A MAX
AD6653
PWR_IN
PWR_IN
Rev. 0 | Page 67 of 80
Figure 92. Evaluation Board Schematic, Power Supply (Continued)
PAD
ADP333 9
VCP
5
C119
10U
GND
OUT 1
OUT2 2
FB 3
VR2
OUT
OUT
C124
10U
VS_OUT_D
R
Power Supply ByPass Capaci tors
VCP
SD
6
8 IN
7 IN2
ADP3334
C132
1U
IN
VR6
C135
1U
3
C133
1U
PAD
ADP333 9
4
GND
1
4
GND
1
IN
VS
C136
1U
C134
1U
C118
10U
R25
VR5
140KOHM
R15
0.001U
C95
SJ36
78.7KOHM
1
1
1
2
2
C131
1U
L13
IND1210
10uh
L12
IND1210
10uh
L8
IND1210
10UH
2
VS
VCP
VS
VS_OUT_DR
C110
0.1U
PWR_IN
C112
0.1U
C108
0.1U
C129
1U
3
IN
PAD
ADP333 9
VR4
4
GND
C111
0.1U
1
3
C115
0.1U
OUT
C114
0.1U
C113
0.1U
C130
1U
1
2
C107
0.1U
L1
IND1210
10UH
C116
0.1U
C105
0.1U
AMPVDD
06708-099
PWR_IN
AD6653
SJ37
AD6653
06708-100
EVALUATION BOARD LAYOUTS
Figure 93. Evaluation Board Layout, Primary Side
Rev. 0 | Page 68 of 80
06708-101
AD6653
Figure 94. Evaluation Board Layout, Ground Plane
Rev. 0 | Page 69 of 80
06708-102
AD6653
Figure 95. Evaluation Board Layout, Power Plane
Rev. 0 | Page 70 of 80
06708-103
AD6653
Figure 96. Evaluation Board Layout, Power Plane
Rev. 0 | Page 71 of 80
06708-104
AD6653
Figure 97. Evaluation Board Layout, Ground Plane
Rev. 0 | Page 72 of 80
06708-105
AD6653
Figure 98. Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. 0 | Page 73 of 80
06708-106
AD6653
Figure 99. Evaluation Board Layout, Silkscreen, Primary Side
Rev. 0 | Page 74 of 80
06708-107
AD6653
Figure 100. Evaluation Board Layout, Silkscreen, Secondary Side
Rev. 0 | Page 75 of 80
AD6653
BILL OF MATERIALS
Table 26. Evaluation Board Bill of Materials (BOM) 1, 2
Item
1
2
Qty
1
55
3
1
Reference
Designator
AD6653CE_REVB
C1 to C3, C6, C7,
C13, C14, C17, C18,
C20 to C26, C32,
C57 to C61, C65
to C76, C81 to
C83, C96 to C101,
C103, C105, C107,
C108, C110 to
C116, C145
C80
4
2
C5, C84
5
10
6
13
7
10
8
1
C33, C35, C63,
C93 to C95, C122,
C126, C127, C137
C15, C42 to C45,
C129 to C136
C27, C41, C52 to
C54, C62, C102,
C118, C119, C124
CR5
Schottky diode HSMS2822, SOT23
SOT23
Avago Technologies
HSMS-2822-BLKG
9
2
CR6, CR9
LED RED, SMT, 0603, SS-type
LED0603
Panasonic
LNJ208R8ARA
Description
PCB
0.1 μF, 16 V ceramic
capacitor, SMT 0402
Package
PCB
C0402SM
Manufacturer
Analog Devices
Murata
Mfg. Part Number
GRM155R71C104KA88D
18 pF, COG, 50 V, 5% ceramic
capacitor, SMT 0402
4.7 pF, COG, 50 V, 5% ceramic
capacitor, SMT 0402
0.001 μF, X7R, 25 V, 10%
ceramic capacitor, SMT 0402
C0402SM
Murata
GJM1555C1H180JB01J
C0402SM
Murata
GJM1555C1H4R7CB01J
C0402SM
Murata
GRM155R71H102KA01D
1 μF, X5R, 25 V, 10% ceramic
capacitor, SMT 0805
10 μF, X5R, 10 V, 10% ceramic
capacitor, SMT 1206
C0805
Murata
GR4M219R61A105KC01D
C1206
Murata
GRM31CR61C106KC31L
10
4
CR7, CR10 to CR12
50 V, 2 A diode
DO_214AA
Micro Commercial Components
S2A-TP
11
1
CR8
30 V, 3 A diode
DO_214AB
Micro Commercial Components
SK33-TP
12
1
F1
EMI filter
FLTHMURATABNX01
Murata
BNX016-01
13
1
F2
L1206
Tyco Raychem
NANOSMDC150F-2
14
2
J1, J2
HDR3
Samtec
TWS-1003-08-G-S
15
9
HDR2
Samtec
TWS-102-08-G-S
16
3
J4 to J9, J18, J19,
J21
J10 to J12
6.0 V, 3.0 A, trip current
resettable fuse
3-pin, male, single row,
straight header
2-pin, male, straight header
Interface connector
TYCO_HM_ZD
Tyco
6469169-1
17
1
J14
CNBERG2X4H350LD
Samtec
TSW-104-08-T-D
18
1
J16
8-pin, male, double row,
straight header
DC power jack connector
PWR_JACK1
Cui Stack
PJ-002A
19
10
10 μH, 2 A bead core, 1210
1210
Panasonic
EXC-CL3225U1
20
1
L1, L3, L4, L6, L8
to L13
P3
6-terminal connector
PTMICRO6
Weiland Electric, Inc.
Z5.531.3625.0
21
1
P4
4-terminal connector
PTMICRO4
Weiland Electric, Inc.
Z5.531.3425.0
22
3
R7, R30, R45
R0603
NIC Components
NRC06F57R6TRF
23
27
R0402SM
NIC Components
NRC04ZOTRF
24
1
R2, R3 R4, R32,
R33, R42, R64, R67,
R69, R90, R96, R99,
R101, R104, R110
to R113, R115,
R119, R121, R123,
R141 to R145
R13
57.6 Ω, 0603, 1/10 W,
1% resistor
0 Ω, 1/16 W, 5% resistor
76.8 kΩ, 0603, 1/10 W, 1% resistor
R0603
NIC Components
NRC06F7682TRF
25
1
R25
140 kΩ, 0603, 1/10 W, 1% resistor
R0603
NIC Components
NRC06F1403TRF
26
1
R14
147 kΩ, 0603, 1/10 W, 1% resistor
R0603
NIC Components
NRC06F1473TRF
27
1
R15
78.7 kΩ, 0603, 1/10 W,
1% resistor
R0603
NIC Components
NRC06F7872TRF
Rev. 0 | Page 76 of 80
AD6653
Item
28
Qty
1
Reference
Designator
R16
29
3
30
7
31
3
32
9
33
Description
261 Ω, 0603, 1/10 W, 1% resistor
Package
R0603
Manufacturer
NIC Components
Mfg. Part Number
NRC06F2610TRF
R17, R22, R23
100 kΩ, 0603, 1/10 W, 1% resistor
R0603
NIC Components
NRC06F1003TRF
R18, R24, R63, R65,
R82, R118, R140
R19, R21
10 kΩ, 0402, 1/16 W, 1% resistor
R0402SM
NIC Components
NRC04F1002TRF
1 kΩ, 0603, 1/10 W, 1% resistor
R0603
NIC Components
NRC06F1001TRF
33 Ω, 0402, 1/16 W, 5% resistor
R0402SM
NIC Components
NRC04J330TRF
5
R26, R27, R43,
R46, R47, R70,
R71, R73, R74
R57, R59 to R62
22 Ω, 16-pin, 8-resistor,
resistor array
R_742
CTS Corporation
742C163220JPTR
34
1
R58
RES_ARRY
CTS Corporation
742C083220JPTR
35
1
R76
R0402SM
NIC Components
NCR04F2000TRF
36
4
S2, S3, S5 ,S12
SMA_EDGE
142-0701-201
SLDR_PAD2MUYLAR
Emerson Network
Power
NIC Components
NRC10ZOTRF
TRAN6B
M/A-COM
MABA-007159-000000
AD6653BCPZ
37
1
SJ35
22 Ω, 8-pin, 4-resistor,
resistor array
200 Ω, 0402, 1/16 W,
1% resistor
SMA, inline, male,
coaxial connector
0 Ω, 1/8 W, 1% resistor
38
5
T1 to T5
Balun
39
1
U1
IC, AD6653
LFCSP64-9X9-9E
Analog Devices
40
1
U2
Clock distribution, PLL IC
LFCSP64-9X9
Analog Devices
AD9516-4BCPZ
41
1
U3
Dual inverter IC
SC70_6
Fairchild Semiconductor
NC7WZ04P6X_NL
42
1
U7
SC70_6
Fairchild Semiconductor
NC7WZ07P6X_NL
43
1
U8
Dual buffer IC,
open-drain circuits
UHS dual buffer IC
SC70_6
Fairchild Semiconductor
NC7WZ16P6X_NL
44
3
U15 to U17
16-bit CMOS buffer IC
TSOP48_8_1MM
Fairchild Semiconductor
74VCX16244MTDX_NL
45
2
VR1, VR2
Adjustable regulator
LFCSP8-3X3
Analog Devices
ADP3334ACPZ
46
1
VR3
1.8 V high accuracy regulator
SOT223-HS
Analog Devices
ADP3339AKCZ-1.8
47
1
VR4
5.0 V high accuracy regulator
SOT223-HS
Analog Devices
ADP3339AKCZ-5.0
48
2
VR5, VR6
3.3 V high accuracy regulator
SOT223-HS
Analog Devices
ADP3339AKCZ-3.3
49
1
Y1
Oscillator clock, VFAC3
OSC-CTS-CB3
Valpey Fisher
VFAC3-BHL
50
2
Z1, Z2
High speed IC, op amp
LFCSP16-3X3-PAD
Analog Devices
AD8352ACPZ
1
2
This bill of materials is RoHS compliant.
The bill of materials lists only those items that are normally installed in the default condition. Items that are not installed are not included in the BOM.
Rev. 0 | Page 77 of 80
AD6653
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
64 1
49
48
PIN 1
INDICATOR
PIN 1
INDICATOR
8.75
BSC SQ
TOP VIEW
0.50
BSC
0.50
0.40
0.30
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
16
17
33
32
0.25 MIN
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
051007-C
1.00
0.85
0.80
7.25
7.10 SQ
6.95
EXPOSED PAD
(BOTTOM VIEW)
Figure 101. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD6653BCPZ-150 1
AD6653BCPZ-1251
AD6653-125EBZ1
AD6653-150EBZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board with AD6653 and Software
Evaluation Board with AD6653 and Software
Z = RoHS Compliant Part.
Rev. 0 | Page 78 of 80
Package Option
CP-64-3
CP-64-3
AD6653
NOTES
Rev. 0 | Page 79 of 80
AD6653
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06708-0-11/07(0)
Rev. 0 | Page 80 of 80
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