AD AD9627BCPZ-125

12-Bit, 80/105/125/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9627
Preliminary Technical Data
FEATURES
APPLICATIONS
SNR = 69.5 dBc (70.5dBFS) to 70 MHz @ 150 MSPS
SFDR = 85 dBc to 70 MHz @ 150 MSPS
Low Power: 780 mW
1.8V analog supply operation
1.8V to 3.3V CMOS output supply or 1.8V LVDS supply
Integer 1 to 8 Input Clock Divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input: 1 V p-p to 2 V p-p range
Differential analog inputs with 650MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial Port Control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated Receive Features:
Fast Detect/Threshold Bits
Composite Signal monitor
Communications
Diversity radio systems
Multimode digital receivers:
GSM, EDGE, PHS, UMTS, WCDMA, CDMA-ONE,
IS95, CDMA2000, IMT-2000, WiMax
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
CMOS
Output Buffer
CMOS
Output Buffer
FUNCTIONAL BLOCK DIAGRAM
Figure 1. AD9627 Functional Block Diagram
Rev. PrA
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Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9627
Preliminary Technical Data
TABLE OF CONTENTS
General Description ......................................................................... 3
Gain Switching............................................................................ 24
Product Highlights ....................................................................... 3
SIGNAL Monitor............................................................................ 26
Specifications..................................................................................... 4
Peak Detector Mode (Mode Bits 01) ....................................... 26
ADC DC Specifications ............................................................... 4
RMS/MS Magnitude Mode (Mode Bits 00)............................ 26
ADC AC Specifications ............................................................... 5
Threshold Crossing Mode (Mode Bits 1x).............................. 27
Digital specifications.................................................................... 6
Additional Control Bits ............................................................. 27
switching specifications ............................................................... 7
DC Correction ............................................................................ 28
Absolute Maximum Ratings............................................................ 8
Signal monitor SPORT OUTPUT............................................ 28
Thermal Characteristics .............................................................. 8
Built-In Self-Test (BIST) and Output test ................................... 29
ESD Caution.................................................................................. 8
Built in self test (BIST)............................................................... 29
Pin Configuration and Function Descriptions............................. 9
output test modes ....................................................................... 29
Equivalent circuits .......................................................................... 12
Channel/Chip Synchronization.................................................... 30
Typical Performance Characteristics ........................................... 13
Serial Port Interface (SPI).............................................................. 31
Timing Diagrams............................................................................ 14
Configuration Using the SPI..................................................... 31
Terminology .................................................................................... 15
Hardware Interface..................................................................... 31
Theory of Operation ...................................................................... 16
Configuration WITHOUT the SPI.......................................... 32
ADC Architecture ...................................................................... 16
Memory Map .............................................................................. 32
Analog Input Considerations.................................................... 16
SPI Accessible Features.............................................................. 32
Voltage Reference ....................................................................... 18
External memory MaP................................................................... 34
Clock Input Considerations ...................................................... 19
memory map register description............................................ 37
Power Dissipation and Standby Mode..................................... 21
Applications..................................................................................... 38
Digital Outputs ........................................................................... 21
Design Guidelines ...................................................................... 38
Timing.......................................................................................... 22
AD9627 Evaluation Board and Software..................................... 39
ADC OVERRANGE and GaIN control ...................................... 23
Outline Dimensions ....................................................................... 40
Fast detect overview ................................................................... 23
Ordering Guide .......................................................................... 40
ADC Fast Magnitude ................................................................. 23
ADC overrange (OVR).............................................................. 24
Rev. PrA | Page 2 of 40
Preliminary Technical Data
AD9627
GENERAL DESCRIPTION
The AD9627 is a dual 12-Bit 150 MSPS ADC. The AD9627 is
designed to support communications applications where low
cost, small size, and versatility are desired.
The dual ADC core features a multistage differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
The AD9627 has several functions which simply the AGC
function in the system receiver. The fast detect feature allows
fast overrange detection by outputting 4 bits of input level
information with very short latency. Additionally, the
programmable threshold detector allows monitoring of the
incoming signal power from the ADC’s 4 fast detect bits with
very low latency. If the input signal level exceeds the
programmable threshold, the decrement gain indicator will go
high. Because this threshold is set from the 4 MSB’s this allows
the user to quickly turn down the system gain to avoid an
overrange condition. The second AGC related function is the
Signal monitor. This block allows the user to monitor the
composite magnitude of the incoming signal which aids in
setting the gain to optimize the dynamic range of the overall
system.
12-bit output ports. These outputs can be set from 1.8V to
3.3V CMOS. Or 1.8V LVDS.
Flexible power-down options allow significant power savings,
when desired.
PRODUCT HIGHLIGHTS
•
Integrated dual 12-Bit 150 MSPS ADC.
•
Fast Over-range Detect and Signal monitor with Serial
Output
•
Signal monitor block with dedicate serial output mode.
•
Proprietary, differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
•
The AD9627 operates from a single 1.8 Volt supply and
features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
•
A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
•
The AD9627 is pin compatible with the AD9640, allowing
a simple migration from 12 to 14 Bits.
The ADC output data can be routed directly to the two external
Rev. PrA | Page 3 of 40
AD9627
Preliminary Technical Data
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, Fast Detect Outputs disabled, Signal Monitor disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential
Nonlinearity (DNL) 1
Integral Nonlinearity
(INL)1
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE
REFERENCE
Output Voltage Error
(1 V Mode)
Load Regulation @ 1.0
mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0
V
Input Capacitance 2
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS
Mode)
Supply Current
IAVDD1
IDVDD1
IDRVDD1 (3.3V)
IDRVDD1 (1.8V)
PSRR
POWER CONSUMPTION
DC Input
Sine Wave Input1
(DRVDD=1.8V)
Sine Wave Input1
(DRVDD=3.3V)
Standby Power 3
Powerdown Power
1
2
3
Temp
Full
AD9627BCPZ-80
Min
Typ
Max
12
Full
Full
Full
Full
Guaranteed
±0.3
±2.0
AD9627BCPZ-105
Min
Typ
Max
12
AD9627BCPZ-125
Min
Typ
Max
12
Guaranteed
±0.3
±TBD
±2.0
±TBD
Guaranteed
±0.3
±TBD
±1.7
±TBD
±TBD
±TBD
Guaranteed
±0.3
±1.7
Bits
±TBD
% FSR
% FSR
LSB
±TBD
LSB
LSB
±0.4
25°C
±2
±1.8
±2
±2
LSB
Full
Full
±15
±95
±15
±95
±15
±95
±15
±95
ppm/°C
ppm/°C
Full
TBD
TBD
TBD
TBD
mV
Full
TBD
TBD
TBD
TBD
mV
25°C
TBD
TBD
TBD
TBD
LSB rms
Full
2
2
2
2
V p-p
Full
Full
8
8
6
6
8
6
8
6
pF
kΩ
±TBD
1.7
1.7
1.8
3.3
1.9
3.6
±0.4
±TBD
Unit
25°C
Full
Full
Full
±0.4
AD9627BCPZ-150
Min
Typ
Max
12
±TBD
1.7
1.7
1.8
3.3
1.9
3.6
±0.4
±TBD
1.7
1.7
1.8
3.3
1.9
3.6
1.7
1.7
1.8
3.3
1.9
3.6
V
V
Full
Full
Full
219
29
27
292
37
34
363
45
42
384
47.5
47.6
mA
mA
mA
Full
Full
TBD
±0.01
TBD
±0.01
TBD
±0.01
TBD
±0.01
mA
% FSR
Full
Full
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mW
mW
Full
536
705
873
934
mW
Full
Full
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mW
mW
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure x for the equivalent analog input structure.
Standby power is measured with a dc input, the CLK pins inactive (set to AVDD or AGND).
Rev. PrA | Page 4 of 40
Preliminary Technical Data
AD9627
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
Enabled, Fast Detect Outputs disabled, Signal Monitor disabled, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
SIGNAL-TO-NOISE-AND
DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
EFFECTIVE NUMBER OF BITS
(ENOB)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
WORST SECOND OR THIRD
HARMONIC
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
TWO TONE SFDR
fIN = 30 MHz, 31 MHz (−7 dBFS )
fIN = 170 MHz, 171 MHz (−7
dBFS )
CROSSTALK
ANALOG INPUT BANDWIDTH
MATCHING CHARACTERISTIC
Offset Error
Gain Error
Temp
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
Min
AD9627BCPZ-80
Typ
Max
AD9627BCPZ-105
Min
Typ
Max
AD9627BCPZ-125
Min
Typ
Max
AD9627BCPZ-150
Min
Typ
Max
69.5
69.5
69.5
69.5
69.5
TBD
69.5
TBD
69.5
TBD
69.5
TBD
69.4
68.9
69.4
68.9
69.4
68.9
69.4
68.9
69.2
69.2
69.2
69.2
Unit
dB
dB
dB
dB
dB
dB
69.1
68.6
69.1
68.6
69.1
68.6
69.1
68.6
dB
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
11.4
11.4
11.4
11.3
11.4
11.4
11.4
11.3
11.4
11.4
11.4
11.3
11.4
11.4
11.4
11.3
Bits
Bits
Bits
Bits
25°C
Full
25°C
Full
25°C
25°C
90
90
90
90
85
85
85
85
85
83.5
85
83.5
85
83.5
83
82
dBc
dBc
dBc
dBc
dBc
dBc
25°C
Full
25°C
Full
25°C
25°C
90
90
90
90
85
85
85
85
85
84
85
83.4
85
83
83
80
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dBc
dBc
Full
25°C
95
650
95
650
95
650
TBD
TBD
TBD
TBD
TBD
TBD
25°C
25°C
69.2
TBD
69.2
69.2
TBD
TBD
1
69.2
TBD
95
650
TBD
TBD
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure x for the equivalent analog input structure.
3
Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).
2
Rev. PrA | Page 5 of 40
dB
MHz
%FSR
%FSR
AD9627
Preliminary Technical Data
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+,
CLK-)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUTS (CSB, SCLK/DCS, OE,
PWDN)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DFS)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage
(IOH = 50 μA)
High Level Output Voltage
(IOH = 0.5 mA)
Low Level Output Voltage (IOL
= 1.6 mA)
Low Level Output Voltage (IOL
= 50 μA)
DRVDD = 1.8 V
High Level Output Voltage
(IOH = 50 μA)
High Level Output Voltage
(IOH = 0.5 mA)
Low Level Output Voltage (IOL
= 1.6 mA)
Low Level Output Voltage (IOL
= 50 μA)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9627BCPZ-80
Min
Typ
Max
AD9627BCPZ-105
Min
Typ
Max
AD9627BCPZ-125
Min
Typ
Max
AD9627BCPZ-150
Min
Typ
Max
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDDAVDD+
0.3
1.5
1.1V
AVDD
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDDAVDD+
0.3
1.5
1.1V
AVDD
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDDAVDD+
0.3
1.5
1.1V
AVDD
CMOS/LVDS/LVPECL
1.2
0.2
6
AVDDAVDD+
0.3
1.5
1.1V
AVDD
TBD
TBD
TBD
TBD
−10
−10
8
TBD
10
0.8
+10
+10
−10
−10
12
8
TBD
TBD
10
0.8
+10
+10
−10
−10
12
8
TBD
0.8
+10
+10
−10
−10
12
8
TBD
10
12
0.8
+10
+10
−10
−10
TBD
TBD
1.2
0.8
+10
+10
TBD
0.8
+10
+10
−10
−10
TBD
TBD
1.2
−10
−10
TBD
0.8
+10
+10
−10
−10
TBD
TBD
TBD
10
0.8
+10
+10
TBD
TBD
V
V
V
μA
μA
pF
ΚΩ
V
V
μA
μA
kΩ
pF
−10
−10
Full
3.29
3.29
3.29
3.29
V
Full
3.25
3.25
3.25
3.25
V
0.8
+10
+10
−10
−10
TBD
TBD
1.2
V
Vp-p
V
Full
Full
Full
Full
Full
Full
0.8
+10
+10
1.2
Unit
0.8
+10
+10
−10
−10
TBD
TBD
0.8
+10
+10
−10
−10
TBD
TBD
TBD
TBD
V
V
μA
μA
kΩ
pF
Full
0.2
0.2
0.2
0.2
V
Full
0.05
0.05
0.05
0.05
V
Full
1.79
1.79
1.79
1.79
V
Full
1.75
1.75
1.75
1.75
V
Full
0.2
0.2
0.2
0.2
V
Full
0.05
0.05
0.05
0.05
V
Rev. PrA | Page 6 of 40
Preliminary Technical Data
AD9627
SWITCHING SPECIFICATIONS
Table 4.
Parameter
Temp
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period(tCLK)
CLK Pulse Width High 1(tCLKH)
CLK Pulse Width Low1 (tCLKL)
CLK Pulse Width High 2(tCLKH)
CLK Pulse Width Low2(tCLKL)
DATA OUTPUT PARAMETERS
Data Propagation Delay
(tPD) 3
DCO Propagation Delay
(tDCO)
Setup Time (tS)
Hold Time (tH)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter,
tJ)
Wake-Up Time 4
OUT-OF-RANGE RECOVERY
TIME
Full
Full
Full
Full
Full
Full
Full
AD9627BCPZ-80
Min
Typ
Max
80
AD9627BCPZ-105
Min
Typ
Max
AD9627BCPZ-125
Min
Typ
Max
AD9627BCPZ-150
Min
Typ
Max
Unit
105
125
150
tCLK/2
tCLK/2
tCLK/2
tCLK/2
MSPS
MSPS
ns
ns
ns
ns
ns
10
12.5
TBD
TBD
TBD
TBD
tCLK/2
tCLK/2
tCLK/2
tCLK/2
10
9.5
TBD
TBD
TBD
TBD
10
8
TBD
TBD
TBD
TBD
tCLK/2
tCLK/2
tCLK/2
tCLK/2
10
6.66
TBD
TBD
TBD
TBD
tCLK/2
tCLK/2
tCLK/2
tCLK/2
Full
TBD
TBD
TBD
TBD
ns
Full
TBD
TBD
TBD
TBD
ns
Full
Full
Full
Full
Full
8.5
8.5
12
TBD
0.1
8.5
8.5
12
TBD
0.1
8.5
8.5
12
TBD
0.1
8.5
8.5
12
TBD
0.1
ns
ns
Cycles
ns
ps rms
Full
Full
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ms
Parameter (Conditions)
Min
Typ
Max
Unit
RESET TIMING REQUIREMENTS
tRESL
RESET Width Low
SYNC TIMING REQUIREMENTS
tSS
SYNC to ↑CLK Setup Time
SYNCto ↑CLK Hold Time
SPI TIMING REQUIREMENTS
tDS
Set-up time between the data and the rising edge of SCLK
tDH
Hold time between the data and the rising edge of SCLK
tCLK
Period of the SCLK
tS
Set-up time between CSB and SCLK
tH
Hold time between CSB and SCLK
tHI
Minimum period that SCLK should be in a logic high state
tLO
Minimum period that SCLK should be in a logic low state
tHS
TBD
ns
TBD
ns
TBD
ns
5
5
40
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
ns
1
With duty cycle stabilizer (DCS) enabled.
With duty cycle stabilizer (DCS) disabled.
3
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
4
Wake-up time is dependant on the value of the decoupling capacitors.
2
Rev. PrA | Page 7 of 40
AD9627
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
VIN+A/B, VIN-A/B to AGND
CSB to AGND
D0A/B through D13A/B to DRGND
FD0A/B through FD3A/B to DRGND
DCOA/B to DRGND
VREF to AGND
SENSE to AGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range (Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.2 V
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 6. Thermal Resistance
−40°C to +85°C
Package Type
64 lead LFCSP 9 mm sq.
(CP-64-3)
150°C
−65°C to +150°C
θJA
24
θJC
TBD
Unit
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, and through holes, ground, and power planes,
reduces the θJA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrA | Page 8 of 40
Preliminary Technical Data
AD9627
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DRGND
D3B
D2B
D1B
D0B (LSB)
NC
NC
DVDD
FD3B
FD2B
FD1B
FD0B
SYNC
CSB
CLK-
CLK+
Table 7. LFCSP Parallel CMOS Pin Configuration (Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRVDD
1
48
SCLK/DFS
D4B
2
47
SDIO/DCS
D5B
3
46
AVDD
D6B
4
45
AVDD
D7B
5
44
VIN+B
D8B
6
43
VIN-B
D9B
7
42
RBIAS
D10B
8
41
CML
D11B (MSB)
9
40
SENSE
DCOB
10
39
VREF
DCOA
11
38
VIN-A
NC
12
37
VIN+A
NC
13
36
AVDD
D0A (LSB)
14
35
SMI SDFS
D1A
15
34
SMI SCLK/
PDWN
D2A
16
33
SMI SDO/
OEB
Parallel CMOS
26
27
28
29
30
31
32
FD1A
FD2A
FD3A
DRVDD
25
FD0A
DRGND
24
D11A (MSB)
D5A
23
D10A
D4A
22
D9A
21
D8A
20
DVDD
19
D7A
18
D6A
17
D3A
Top View
(not to scale)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
20, 64
1, 21
24, 57
36, 45, 46
0
12, 13, 58, 59
Mnemonic
Type
Function
DRGND
DRVDD
DVDD
AVDD
AGND
NC
Gnd
Supply
Supply
Supply
Gnd
Digital Output Ground
Digital Output Driver Supply (1.8V to 3.3V)
Digital Power Supply (1.8V Nominal)
Analog Power Supply (1.8V Nominal)
Analog Ground (Pin 0 is the exposed thermal pad on the bottom of the package)
Do Not Connect
Rev. PrA | Page 9 of 40
AD9627
Pin No.
ADC INPUTS
37
38
44
43
39
40
42
41
49
50
Preliminary Technical Data
Mnemonic
Type
Function
VIN+A
VIN-A
VIN+B
VIN−B
VREF
SENSE
RBIAS
CML
CLK+
Input
Input
Input
Input
I/O
Input
Input
Output
Input
CLK-
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select (See Table x for details)
External Reference Bias Resistor
Common Mode Level Bias Output for Analog Inputs
ADC Master Clock – True (ADC Clock can be driven using single ended CMOS – See
Figure x.x for recommended connection)
ADC Master Clock - Complement (ADC Clock can be driven using single ended
CMOS – See Figure x.x for recommended connection)
ADC Fast Detect Outputs
29
FD0A
30
FD1A
31
FD2A
32
FD3A
53
FD0B
54
FD1B
55
FD2B
56
FD3B
Digital INPUTS
52
SYNC
Digital OUTPUTS
D0A-D11A
14, 15, 16,
17, 18, 19,
22, 23, 25,
26, 27, 28
D0B-D11B
60, 61, 62,
63, 2, 3, 4,
5, 6, 7, 8, 9
11
DCOA
10
DCOB
SPI CONTROL
48
SCLK/DFS
47
51
Serial Port
33
35
34
Output
Output
Output
Output
Output
Output
Output
Output
Channel A Fast Detect Indicator (See Table x for full detials)
Channel A Fast Detect Indicator (See Table x for full detials)
Channel A Fast Detect Indicator (See Table x for full detials)
Channel A Fast Detect Indicator (See Table x for full detials)
Channel B Fast Detect Indicator (See Table x for full detials)
Channel B Fast Detect Indicator (See Table x for full detials)
Channel B Fast Detect Indicator (See Table x for full detials)
Channel B Fast Detect Indicator (See Table x for full detials)
Input
Digital Synchronization Pin(Slave Mode Only)
Output
Channel A CMOS output data
Output
Channel B CMOS output data
Output
Output
Channel A Data Clock Output
Channel B Data Clock Output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode
SDIO/DCS
CSB
I/O
Input
SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode
SPI Chip Select (Active Low)
SMI SDO/OEB
I/O
SMI SDFS
SMI SCLK/PDWN
Output
I/O
Signal monitor Serial Data Output/Output Enable Input (Active Low) in External Pin
Mode
Signal monitor Serial Data Frame Sync
Signal monitor Serial Clock Output/Power Down Input in External Pin Mode
Rev. PrA | Page 10 of 40
Preliminary Technical Data
AD9627
DRGND
NC
NC
FD3+
FD3-
FD2+
FD2-
DVDD
FD1+
FD1-
FD0+
FD0-
SYNC
CSB
CLK-
CLK+
Table 9. LFCSP LVDS Pin Configuration (Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRVDD
1
48
SCLK/DFS
NC
2
47
SDIO/DCS
NC
3
46
AVDD
D0- (LSB)
4
45
AVDD
D0+
5
44
VIN+B
D1-
6
43
VIN-B
D1+
7
42
RBIAS
D2-
8
41
CML
D2+
9
40
SENSE
DCO-
10
39
VREF
DCO+
11
38
VIN-A
D3-
12
37
VIN+A
D3+
13
36
AVDD
D4-
14
35
SMI SDFS
D4+
15
34
SMI SCLK/
PDWN
D5-
16
33
SMI SDO/
OEB
Parallel LVDS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D5+
D6-
D6+
DRGND
DRVDD
D7-
D7+
DVDD
D8-
D8+
D9-
D9+
D10-
D10+
D11-
D11+(MSB)
Top View
(not to scale)
Rev. PrA | Page 11 of 40
AD9627
Preliminary Technical Data
EQUIVALENT CIRCUITS
VIN
1kΩ
SCLK/DFS
05491-004
30kΩ
Figure 2. Analog Input Circuit
AVDD
Figure 6. Equivalent SCLK/DFS Input Circuit
1.2V
10kΩ
10kΩ
1kΩ
SENSE
CLK–
05491-011
05491-005
CLK+
Figure 3. Equivalent Clock lInput Circuit
Figure7. Equivalent SENSE Circuit
AVDD
26kΩ
1kΩ
05491-010
CSB
Figure 4. Digital Output
Figure 8. Equivalent CSB Input Circuit
AVDD
DRVDD
VREF
1kΩ
05491-006
6kΩ
Figure 9. Equivalent VREF Circuit
Figure5x. Equivalent SDIO/DCS Input Circuit
Rev. PrA | Page 12 of 40
05491-012
SDIO/DCS
Preliminary Technical Data
AD9627
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V; DVDD =1.8V; DRVDD = 1.8 V; Sample Rate = 150 MSPS, DCS enabled, 1 V internal reference; 2 V p-p differential input;
VIN = -1.0 dBFS; 64k sample; TA = 25°C, unless otherwise noted.
Rev. PrA | Page 13 of 40
AD9627
Preliminary Technical Data
TIMING DIAGRAMS
N+2
N+1
N+3
N
N+4
tA
N+8
N+5
N+6
N+7
N–7
N–6
tCLK
CLK+
CLK–
tPD
N – 13
tS
N – 12
N – 11
tH
N – 10
N–9
N–8
tDCO
tCLK
DCO
Figure18. Data and Fast Detect Output Timing
Figure 39. Reset Timing Requirements
Figure 20. SYNC Input Timing
Rev. PrA | Page 14 of 40
N–5
N–4
05491-002
DATA
Preliminary Technical Data
AD9627
TERMINOLOGY
Crosstalk
Coupling onto one channel being driven by a (−0.5 dBFS) signal
when the adjacent interfering channel is driven by a full-scale
signal. Measurement includes all spurs resulting from both
direct coupling and mixing components.
IF Sampling (Undersampling)
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Frequencies above Nyquist are aliased and
appear in the first Nyquist zone (dc to Sample Rate/2). Care
must be taken to limit the bandwidth of the sampled signal so
that it does not overlap Nyquist zones and alias onto itself. IF
sampling performance is limited by the bandwidth of the input
SHA (sample-and-hold amplifier) and clock jitter. (Jitter adds
more noise at higher input frequencies.)
Nyquist Sampling (Oversampling)
Oversampling occurs when the frequency components of the
analog input signal are below the Nyquist frequency (Fclock/2),
and requires that the analog input frequency be sampled at least
two samples per cycle.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the analogto-digital converter (ADC) to reacquire the analog input after a
transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Signal-to-Noise Ratio (SNR)
The ratio of the rms value of the measured input signal to the
rms sum of all other spectral components within the programmed DDC filter bandwidth, excluding the first six
harmonics and dc. The value for SNR is expressed in
decibels (dB).
Two-Tone IMD Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product; reported
in dBc.ADC Equivalent Circuits
Rev. PrA | Page 15 of 40
AD9627
Preliminary Technical Data
THEORY OF OPERATION
The AD9627 dual ADC design may be used for diversity
reception of signals, where the ADCs are operating identically
on the same carrier but from two separate antennae. The ADCs
can also be operated with independent analog inputs. The user
can sample any fs/2 frequency segment from dc to 100 MHz
using appropriate low-pass or band-pass filtering at the ADC
inputs with little loss in ADC performance. Operation to 200
MHz analog input is permitted, but at the expense of increased
ADC distortion.
In non-diversity applications, the AD9627 can be used as a
baseband receiver where one ADC is used for I input data and
the other used for Q input data.
Synchronizaton capability is provided to allow synchronized
timing between multiple channels or multiple devices.
sample capacitors and settling within one-half of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC’s input; therefore,
the precise values are dependant upon the application.
In IF undersampling applications, any shunt capacitors should
be reduced. In combination with the driving source impedance,
they would limit the input bandwidth. See the application notes
AN-742 and AN-827, and the Analog Dialogue article
“Transformer-Coupled Front-End for Wideband A/D Converters”
for more information on this subject. In general, the precise
values are dependent on the application.
Programming and control of the AD9627 is accomplished using
a 3-bit SPI compatible serial interface.
ADC ARCHITECTURE
The AD9627 architecture consists of a dual front-end sample
and hold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The quantized outputs from each stage are
combined into a final 12-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample, while the remaining stages
operate on preceding samples. Sampling occurs on the rising
edge of the clock.
Figure21. Switched-Capacitor SHA Input
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched.
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing
adjustment of the output voltage swing. During power-down,
the output buffers go into a high impedance state.
The analog inputs of the AD9627 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD is
recommended for optimum performance, but the device
functions over a wider range with reasonable performance (see
Figure x). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD).
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9627 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the
ADC core. The span of the ADC core is set by the buffer to be
2X VREF.
Input Common Mode
Differential Input Configurations
The clock signal alternatively switches the SHA between sample
mode and hold mode (see x). When the SHA is switched into
sample mode, the signal source must be capable of charging the
Optimum performance is achieved while driving the AD9627
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
Rev. PrA | Page 16 of 40
Preliminary Technical Data
AD9627
voltage of the AD8352 is easily set with the CML pin of the
AD9627 (see Figure 4), and the driver can be configured in a
Sallen-Key filter topology to provide band limiting of the input
signal.
499 Ω
1V p-p
49.9 Ω
VIN+
C
AD8138
0.1 μ F
AVDD
R
499 Ω
AD9627
R
523 Ω
VIN –
CML
499 Ω
Figure 6. Differential Double Balun Input Configuration
Figure 4. Differential Input Configuration Using the AD8138
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 5. The CML
voltage can be connected to the center tap of the transformer’s
secondary winding to bias the analog input.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Figure 7. Differential Input Configuration Using the AD8352
R
2V p-p
C
49.9 Ω
R
An alternative to using a transformer coupled input at
frequencies in the second Nyquist zone is to use the AD8352
differential driver. An example is shown in Figure 7. See the
AD8352 datsheet for more information.
VIN+
AD9627
VIN–
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and source impedance and
may need to be reduced or removed. Table 1 displays
recommended values to set the RC network. However, these
values will be dependant on the input signal and should only be
used as a starting guide.
CML
0.1μF
Figure 5. Differential Transformer-Coupled Configuration
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9627. For applications
where SNR is a key parameter, differential double balun
coupling is the recommended input configuration. An example
is shown in Figure 6.
Table 1 Example RC Network
Frequency Range
MHz
0-70
70-200
200-300
>
R series
(Ω, each)
33
33
15
15
C differential
(pF)
15
5
5
Open
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input
common-mode swing. If the source impedances on each input
are matched, there should be little effect on SNR performance.
Rev. PrA | Page 17 of 40
AD9627
Preliminary Technical Data
Figure 8 details a typical single-ended input configuration.
10µF
AVDD
1kΩ
R
VIN+
2V p-p
49.9Ω
0.1µF 1kΩ
AVDD
1kΩ
C
ADC
AD9627
R
VIN–
10µF
0.1µF
1kΩ
Figure 8. Single-Ended Input Configuration
Table 2. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Resulting VREF (V)
N/A
0.5
Internal Fixed Reference
AGND to 0.2 V
1.0
R 2 ⎞ (See Figure 10)
0 . 5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
Resulting Differential
Span (V p-p)
2 × External Reference
1.0
2 × VREF
2.0
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9627.
The input range can be adjusted by varying the reference
voltage applied to the AD9627, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are summarized in the next few
sections. The Reference Decoupling section describes the best
practices PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9627 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table x. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 9), setting VREF to 1 V. Connecting
the SENSE pin to VREF switches the reference amplifier output
to the SENSE pin, completing the loop and providing a 0.5 V
reference output. If a resistor divider is connected external to
the chip as shown in Figure 10, the switch again sets to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
R2 ⎞
VREF = 0.5 × ⎛⎜1+
⎟
⎝ R1 ⎠
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
Rev. PrA | Page 18 of 40
Figure 9. Internal Reference Configuration
Preliminary Technical Data
AD9627
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
TBD kΩ load. The internal buffer generates the positive and
negative full-scale references for the ADC core. Therefore, the
external reference must be limited to a maximum of 1 V.
VIN+A/VIN+B
VIN-A/VIN-B
ADC
CORE
CLOCK INPUT CONSIDERATIONS
VREF
1.
0
uF
0.
1
uF
R2
SENSE
For optimum performance, the AD9627 sample clock inputs
(CLK+ and CLK-) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK- pins
via a transformer or capacitors. These pins are biased internally
(See Figure 13) and require no external bias.
SELECT
LOGI
C
R1
0.5V
AVDD
AD9627
Figure 10. Programmable Reference Configuration
If the internal reference of the AD9627 is used to drive multiple
converters to improve gain matching, the loading of the
reference by the other converters must be considered. Figure 11
depicts how the internal reference voltage is affected by loading.
1.2V
CLK-
CLK+
2pF
2pF
Figure
Figure 13.Equivalent Clock Input Circuit
Clock Input Options
The AD9627 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.
Figure 11. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
characteristics. Figure 12 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes.
Figure 14 shows one preferred method for clocking the AD9627
(at clock rates to 150MSPS). A low jitter clock source is
converted from single-ended to differential signal using an RF
transformer. The back-to-back Schottky diodes across the
transformer secondary limit clock excursions into the AD9627
to approximately 0.8 Vp-p differential. This helps prevent the
large voltage swings of the clock from feeding through to other
portions of the AD9627 while preserving the fast rise and fall
times of the signal, which are critical to a low jitter
performance.
CLOCK
INPUT
MIN-CIRCUITS
ADT1–1WT, 1:1Z
0.1µF
0.1µF
XFMR
100kΩ
50kΩ
0.1µF
0.1µF
Figure 12. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
Rev. PrA | Page 19 of 40
CLK
ADC
AD9627
~ CLK
SCHOTTKY
DIODES:
HMS2812
AD9627
Preliminary Technical Data
Figure 14. Transformer Coupled Differential Clock(up to 150MSPS)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 15. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515 family of clock drivers offers
excellent jitter performance.
0.1µF
0.1µF
CLOCK
INPUT
AD9510/1/2/3/4/5
~ CLOCK
INPUT
100kΩ
0.1µF
50kΩ
240kΩ
ADC
AD9627
Figure 15. Differential PECL Sample Clock (up to 150MSPS)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins as shown in Figure 16. The
AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515 family of
clock drivers offers excellent jitter performance.
0.1µF
CLOCK
INPUT
CLK
100kΩ
0.1µF
AD9510/1/2/3/4/5
0.1µF LVDS DRIVER
~ CLOCK
INPUT
50kΩ
ADC
AD9627
Figure 16 Differential LVDS Sample Clock (up to 150MSPS)
In some applications it may acceptable to drive the sample clock
inputs with a single ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, while the
CLK- pin should be bypassed to ground with a 0.1uF capacitor
in parallel with a 39 kΩ resistor (see Figure 17). CLK+ may be
directly driven from a CMOS gate. Although the CLK+ input
circuit supply is AVDD (1.8 V), this input is designed to
withstand input voltages up to 3.6V, making the selection of the
drive logic voltage very flexible.
VCC
0.1µF
CLOCK
INPUT
50kΩ
OPTIONAL
100Ω 0.1µF
1kΩ
1kΩ
AD9510/1/2/3/4/5
CMOS DRIVER
CLK
ADC
ADC
AD9627
~CLK
The AD9627 clock divider can be synchronized using the
external SYNC input. Register 0x100 bits bits 1 and 2 allow the
clock divider to be re-synchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input
sampling.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance
characteristics. The AD9627 contains a duty cycle stabilizer
(DCS) that retimes the nonsampling, or falling, edge, providing
an internal clock signal with a nominal 50% duty cycle. This
allows the user to provide a wide range of clock input duty
cycles without affecting the performance of the AD9627. Noise
and distortion performance are nearly flat for a wide range of
duty cycles with the DCS on, as shown in Figure x.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately TBD clock cycles to
allow the DLL to acquire and lock to the new rate.
Jitter Considerations
AD9627
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fINPUT) due to jitter (tJ) can be calculated by:
~ CLK
0.1µF
0.1µF
Clock Duty Cycle
~ CLK
50kΩ
CLK
The AD9627 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected the duty cycle stabilizer will
be automatically enabled.
240kΩ
0.1µF
1kΩ
AD9510/1/2/3/4/5
CMOS DRIVER
Input Clock Divider
~ CLK
50kΩ
50kΩ
OPTIONAL
0.1µF
100Ω
1kΩ
CLOCK
INPUT
Figure 18 Single-ended 3.3V CMOS Sample Clock (up to 150MSPS)
CLK
0.1µF PECL DRIVER
VCC
0.1µF
39kΩ
SNR = −20 log[2πf INPUT × t J ]
Figure 17. Single-ended 1.8V CMOS Sample Clock (up to 150MSPS)
In the equation, the rms aperture jitter represents the rootmean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter, as
Rev. PrA | Page 20 of 40
Preliminary Technical Data
AD9627
illustrated in Figure 19.
Figure 20. Power vs. Clock [email protected] 30 MHz
Figure 19. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9627. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last
step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs. See www.analog.com.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 20, the power dissipated by the AD9627 is
proportional to its sample rate. In CMOS output mode, the
digital power dissipation is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as:
I DRVDD = VDRVDD × C LOAD × f CLK × N
where N is the number of output bits, 12 in the case of the
AD9627. This maximum current occurs when every output bit
switches on every clock cycle, that is, a full-scale square wave at
the Nyquist frequency, fCLK/2. In practice, the DRVDD current
is established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption. The data in Figure 20 was taken with the same
operating conditions as the Typical Performance Characteristics
with a 5 pF load on each output driver.
By asserting the PDWN mode (either through the SPI port or
by asserting the PDWN pin high), the AD9627 is placed in
power-down mode. In this state, the ADC typically dissipates
TBD mW. During power-down, the output drivers are placed in
a high impedance state. Asserting the PDWN pin low returns
the AD9627 to its normal operational mode. This pin is both
1.8V and 3.3V tolerant.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, the wake-up time is related to
the time spent in power-down mode and shorter power-down
cycles result in proportionally shorter wake-up times. It takes
approximately TBD sec to fully discharge the internal reference
buffer decoupling capacitors and TBD ms to restore full
operation.
When using the SPI port interface, the user can place the ADC
in power-down or standby modes. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the SPI Register Map
Description section for more details.
DIGITAL OUTPUTS
The AD9627 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the CLK/DFS pin when
operating in the external pin mode (see Table 3). As detailed in
the memory map register description section the data format
can be selected for either offset binary, twos complement, or
Rev. PrA | Page 21 of 40
AD9627
Preliminary Technical Data
Gray code when using the SPI control.
Table 3. CLK/DFS Mode Selection (external pin mode)
Voltage at pin
AGND (default)
AVDD
SCLK/DFS
Binary
Twos Complement
SDIO/DCS
DCS Disabled
DCS Enabled
Digital Output Enable Function (OEB)
The AD9627 has a flexible three-state ability for the digital
output pins. The three-state mode can be enabled using the
OEB pin or through the SPI interface. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. It is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
When using the SPI interface each channel’s data and fast detect
outputs can be independently three-stated by using the Output
Enable Bar bit in register 0x14.
Figure 21. OR Relation to Input Voltage and Output Data
TIMING
The AD9627 provides latched data with a pipeline delay of
twelve clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9627.
These transients can degrade the converter’s dynamic performance.
The AD9627 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO. See Figure x for a graphical
timing description.
The lowest typical conversion rate of the AD9627 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can
degrade.
Table 4. Output Data Format
Input (V)
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
Condition (V)
< –VREF – 0.5 LSB
= –VREF
=0
= +VREF – 1.0 LSB
> +VREF – 0.5 LSB
Binary Output Mode
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
1111 1111 1111
Rev. PrA | Page 22 of 40
Twos Complement Mode
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
OR
1
0
0
0
1
Preliminary Technical Data
AD9627
ADC FAST MAGNITUDE
ADC OVERRANGE AND GAIN CONTROL
It is desirable to have a mechanism to reliably determine when
the converter is about to be clipped. The standard overflow
indicator provides after the fact information which is of limited
usefulness. Therefore it is useful to have a programmable
threshold below full-scale that would allow time to reduce the
gain before the clip actually occurs. In addition, since input
signals can have significant slew rates, latency of this function is
a big concern. Highly pipelined converters can have significant
latency. A good compromise of this function is to use the
output bits from the first stage of the ADC for this function.
Latency for these output bits is very low, and overall resolution
is not highly significant. Peak input signals are typically
between full-scale and 6 to 10 dB below full-scale. A 3 or 4 bit
output should give more than adequate range and resolution for
this function.
Via the SPI port, the user can provide a threshold above which a
fast over-range output would be active. As long as the signal is
below that threshold, the output should remain low. This pin
could also be programmed via the SPI port to function as a
traditional over-range pin for customers who currently use this
feature. In this mode, all 12 bits of the converter would be
examined in the traditional manner and the output would be
high for the condition normally defined as overflow. In either
mode, the sign of the data is not considered in the calculation of
the condition. The threshold detection responds identically to
positive and negative signals outside the desired range
(magnitude).
FAST DETECT OVERVIEW
The AD9627 contains circuitry to facilitate fast over-range
detection allowing very flexible external gain control
implementations. Each ADC has four Fast Detect (FD) bits that
are utilized to output information about the current state of the
ADC input level. The FD bit function is programmable
allowing range information to be output from several points in
the internal data path. These bits can also be set up to indicate
the presence of overrange or underrange conditions according
to programmable threshold levels. Table X.x below shows the 6
configurations available for the Fast Detect bits. These
configurations are selecting by setting bits 3:1 in the register at
SPI address 0x104.
Table xx. Fast Detect Bit Configuration Settings
Fast Detect Mode
Select - Register
104h<3:1>
000
001
010
011
100
101
Information Presented on
FD Bits[3:0]
ADC Fast Magnitude[3:0]
ADC Fast Magnitude[2:0], OVR
ADC Fast Magnitude[2:1], OVR, F_LT
ADC Fast Magnitude[2:1], C_UT, F_LT
OVR, C_UT, F_UT, F_LT
OVR, F_UT, IG, DG
When the FD bits are configured to output the ADC fast
magnitude the information presented is the ADC level with
only a 1 clock cycle latency. Using the FD bits in this
configuration provides the earliest possible level indication
information. Since this information is provided from early in
the data path there is a significant uncertainty in the level
indicated. The nominal levels along with the uncertainty
indicated by the ADC fast magnitude are shown in table x.x.
Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using
Mag[3:0])
ADC_Fast_Mag[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
Nominal Input
magnitude in
dB below FS
-30.14
-18.07
-12.04
-8.52
-6.02
-4.08
-2.5
-1.16
-0.28
Nominal Input
magnitude
Uncertainty in dB
+12.07 to Min
+6.03/-12.07
+3.52/-6.03
+2.5/-3.52
+1.94/-2.5
+1.58/-1.94
+1.34/-1.58
+1.16/-1.34
+0.28/-0.88
When fast detect modes 001, 010, or 011 are selected a subset of
the FD bits are available. Table xx shows the corresponding
ADC input levels when Fast Magnitude[2:0] is selected using
001.
Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using
Mag[2:0])
ADC_Fast_Mag[2:0]
000
001
010
011
100
101
110
111
Nominal Input
magnitude in
dB below FS
-30.14
-18.07
-12.04
-8.52
-6.02
-4.08
-2.5
-1.16
Nominal Input
magnitude
Uncertainty in dB
+12.07 to Min
+6.03/-12.07
+3.52/-6.03
+2.5/-3.52
+1.94/-2.5
+1.58/-1.94
+1.34/-1.58
+1.16/-1.34
When ADC Fast Magnitude[2:1] is selected the LSB is not
provided. The Input ranges for this mode are shown in Table x.
Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using
Mag[2:1])
ADC_Fast_Mag[2:1]
00
01
10
11
Rev. PrA | Page 23 of 40
Nominal Input
magnitude in
dB below FS
-22.14
-10.10
-5.00
-1.48
Nominal Input
magnitude
Uncertainty in dB
+10.1 to Min
+4.08/-7.97
+2.5/-3.52
+1.48/-2.6
AD9627
Preliminary Technical Data
ADC OVERRANGE (OVR)
The ADC Overrange bit becomes active when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipline and is therefore
subject to the TBD ADC clock cycle latency. So an overrange at
the input would be indicated by this bit TBD clock cycles after it
occurred.
is a 13 bit threshold register that is compared with the
magnitude at the output of the ADC. This comparison is
subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine threshold magnitude is defined
by equation x.x.
dBFS = 20 log (threshold mag/2^13)
GAIN SWITCHING
Fine Lower Threshold (F_LT)
The AD9627 includes circuitry that is useful in applications
where either large dynamic ranges exist or where gain ranging
converters are employed. This circuitry allows digital thresholds
to be set such that an upper and a lower threshold can be
programmed. Fast detect modes 2 through 7 support various
combinations of the gain switching options.
The Fine Lower Threshold bit will be asserted if the input
magnitude is less than value programmed in the Fine Lower
Threshold Register located at addresses 0x108 and 0x109. The
fine lower threshold register is a 13 bit register that is compared
with the magnitude at the output of the ADC. This comparison
is delayed by the ADC clock latency but provides an accurate
comparison. The fine threshold magnitude is defined by
equation x.x.
One such use of this may be to detect when an ADC is about to
reach full scale with a particular input condition. The results
would be to provide a flag that could be used to quickly insert
an attenuator that would prevent ADC overdrive.
dBFS = 20 log (threshold mag/2^13)
Coarse Upper Threshold (C_UT)
The coarse upper threshold bit is asserted if the input level
present on the ADC Fast Magnitude bits is greater than the level
programmed in the coarse upper threshold register at address
0x105 bits [2:0]. This value is compared with the ADC Fast
Magnitude Bits [2:0]. The coarse upper threshold levels are
shown in Table x.x. This bit remains asserted for a minimum of
2 ADC clock cycles or until the signal drops below the
threshold level.
Table xx. Fast Magnitude Nominal Threshold Levels
Coarse Upper
Threshold Register
[2:0]
000
001
010
011
100
101
110
111
C_UT active when
signal magnitude
in dB below FS is
greater than
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Fine Upper Threshold (F_UT)
The Fine Upper Threshold bit will be asserted if the input
magnitude exceeds the value programmed in the Fine Upper
Threshold Register located at addresses 0x106 and 0x107. This
Increment Gain (IG) and Decrement Gain (DG)
The Increment Gain and decrement gain outputs are intended
to be used together to provide information to enable external
gain control. The Decrement Gain output works identically to
the Coarse Upper Threshold output. This bit is asserted when
the input magnitude is greater than the three bit value in the
Coarse Upper Threshold Register. The Increment Gain output
is similar to the Fine Lower Threshold bit except that it will be
asserted only if the input magnitude is less than value
programmed in the Fine Lower Threshold Register for greater
than the 16 bit Dwell Time value located at addresses 0x10A
and 0x10B. The dwell time is set in units of ADC input clock
cycles ranging from 1 to 65535. The fine lower threshold
register is a 13 bit register that is compared with the magnitude
at the output of the ADC. This comparison is subject to the
ADC clock latency but allows a finer, more accurate
comparison. The fine threshold magnitude is defined by
equation x.x.
The decrement gain output works off the ADC fast detect bits
providing a fast indication of potential overrange conditions.
The increment gain uses the comparison at the output of the
ADC requiring the input magnitude to remain below an
accurate programmable level for a predefined period before
signaling external circuitry to increase the gain.
The operation of the increment gain and decrement gain bits is
shown in Figure x.x.
Rev. PrA | Page 24 of 40
Preliminary Technical Data
Counter Restarts
"High"
Mantissa
AD9627
Upper Threshold
"Low"
Dwell Time
Lower Threshold
Time
Figure 22. Threshold Settings for IG and DG
Rev. PrA | Page 25 of 40
AD9627
Preliminary Technical Data
SIGNAL MONITOR
The signal monitor result values can be obtained from the part
by either reading back internal registers at addresses 0x116 to
0x11B using the SPI port or by using the signal monitor SPORT
output. The output contents of the SPI accessible signal monitor
registers is set via the 2 power-monitor mode bits of the signal
monitor control register. Both ADC channels must be
configured for the same signal monitor mode. Separate SPI
accessible 20 bit Signal monitor Value (PMV) output registers
are provided for each ADC channel. Any combination of the
signal monitor functions can also be output to the user via a
serial SPORT interface. These outputs are enabled using the
Peak Power Output Enable, RMS Magnitude Output Enable,
and Threshold Crossing Output Enable bits in the Signal
monitor SPORT Control Register.
For each of the signal monitor measurements a programmable
Signal Monitor Period Register (SMPR) controls the duration
of the measurement. This time period is programmed as the
number of input clock cycles in a 24-bit ADC monitor period
register located at addresses 0x113, 0x114, and 0x115. This
register can be programmed with a period from 128 samples to
16.78 (2^24) million samples.
Since the DC offset of the ADC can be significantly larger than
the signal of interest a simple DC correction circuit is included
as part of the signal monitor block to null the DC offset before
measuring the power.
PEAK DETECTOR MODE (MODE BITS 01)
The magnitude of the input port signal is monitored over a
programmable time period (given by SMPR) to give the peak
value detected. This function is enabled by programming a logic
1 in the power-monitor mode bits of the power-monitor control
register or by setting the Peak Power Output Enable bit in the
Signal monitor SPORT Control Register. The 24-bit SMPR must
be programmed before activating this mode.
After enabling this mode, the value in the SMPR is loaded into a
monitor period timer and the countdown is started. The
magnitude of the input signal is compared to the internal peak
level holding register, and the greater of the two is updated back
into the peak level holding register. The initial value of the peak
level holding register is set to the current ADC input signal
magnitude. This comparison continues until the monitor
period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13 bit
value in the peak level holding register is transferred to a
holding register, which can be read through the SPI port or
output through the SPORT serial interface. The monitor period
timer is reloaded with the value in the SMPR, and the
countdown is started. Also, the first input sample’s magnitude is
updated in the peak level holding register, and the comparison
and update procedure, as explained above, continues.
Figure 23 is a block diagram of the peak detector logic. The
PMV contains the absolute magnitude of the peak detected by
the peak detector logic.
FROM
MEMORY
MAP
POWER MONITOR
PERIOD REGISTER
DOWN
COUNTER
IS COUNT = 1?
TO
INTERRUPT
CONTROLLER
LOAD
FROM
INPUT
PORTS
CLEAR
MAGNITUDE
STORAGE
REGISTER
LOAD
POWER MONITOR
HOLDING
REGISTER
TO
MEMORY
MAP
LOAD
COMPARE
A>B
04998-0-026
The Signal monitoring block serves to characterize the signal
being digitized by the ADC. It operates in one to three modes
to compute the RMS Input Magnitude, Peak Magnitude, and/or
the number of samples that the Magnitude crosses a particular
threshold. Together these functions can be used to gain insight
into the signal characteristics and can be used to estimate the
Peak/Average ratio or even the shape of the CCDF curve (peak
to average ratio) of the input signal. This information can be
used to drive an AGC loop and to optimize the range of the
ADC in the presence of real world signals.
Figure 23. ADC Input Peak Detector Block Diagram
RMS/MS MAGNITUDE MODE (MODE BITS 00)
In this mode, the RMS or MS magnitude of the input port
signal is integrated (by adding an accumulator) over a
programmable time period (given by SMPR) to give the RMS or
MS magnitude of the input signal. This mode is set by
programming Logic 0 in the signal monitor mode bits of the
signal monitor control register or by setting the RMS
Magnitude Output Enable bit in the Signal monitor SPORT
Control Register. The 24-bit SMPR, representing the period
over which integration is performed, must be programmed
before activating this mode.
After enabling this mode, the value in the SMPR is loaded into a
monitor period timer, and the countdown is started
immediately. Each input sample is converted to floating point
format and squared. It is then converted to 11 bit fixed point
format and is added to the contents of a 24-bit holding register,
thus performing an accumulation. The integration continues
until the monitor period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the square
root of the value in the holding register is taken and transferred
to the power-monitor holding register (after some formatting),
which can be read through the SPI port or output through the
Rev. PrA | Page 26 of 40
Preliminary Technical Data
AD9627
For RMS magnitude mode, the value in the PMV is a 20 bit
fixed point number. The equation shown below can be used to
determine the RMS magnitude in dBFS from the MAG value in
the register. Note that if the signal monitor period (SMP) is a
power of 2, the 2nd term in the equation goes to zero.
MAG ⎞
SMP
⎤
⎡
⎜ 20 ⎟ − 10⋅ log⎢ ceil⎡⎣log2( SMP )⎤⎦ ⎥
⎝ 2 ⎠
⎣2
⎦
RMS_Magnitude := 20⋅ log⎛
For MS magnitude mode, the value in the PMV is a 20 bit fixed
point number. The equation shown below can be used to
determine the MS magnitude in dBFS from the MAG value in
the register. Note that if the signal monitor period (SMP) is a
power of 2, the 2nd term in the equation goes to zero.
MAG ⎞
SMP
⎤
⎡
⎜ 20 ⎟ − 10⋅ log⎢ ceil⎡⎣log2( SMP )⎤⎦ ⎥
⎝ 2 ⎠
⎣2
⎦
MS_Magnitude := 10⋅ log⎛
After entering this mode, the value in the SMPR is loaded into a
monitor period timer, and the countdown is started. The
magnitude of the input signal is compared to the upper
threshold register (programmed previously) on each input clock
cycle. If the input signal has magnitude greater than the upper
threshold register, then the internal count register is
incremented by 1. The initial value of the internal count register
is set to 0. This comparison and increment of the internal count
register continues until the monitor period timer reaches a
count of 1.
When the monitor period timer reaches a count of 1, the value
in the internal count register is transferred to the signal monitor
holding register, which can be read through the SPI port or
output through the SPORT serial port. The monitor period
timer is reloaded with the value in the SMPR, and the
countdown is started. The internal count register is also cleared
to a value of 0. Figure 25 illustrates the threshold crossing logic.
The value in the PMV is the number of samples that have a
magnitude greater than the threshold register.
FROM
MEMORY
MAP
POWER MONITOR
PERIOD REGISTER
DOWN
COUNTER
IS COUNT = 1?
TO
INTERRUPT
CONTROLLER
LOAD
FROM
INPUT
PORTS
FROM
MEMORY
MAP
CLEAR
A COMPARE
A>B
COMPARE
A>B
LOAD
POWER MONITOR
HOLDING
REGISTER
TO
MEMORY
MAP
B
UPPER
THRESHOLD
REGISTER
04998-0-028
SPORT serial port. The monitor period timer is reloaded with
the value in the SMPR, and the countdown is restarted. Also,
the first input sample signal power is updated in the holding
register, and the accumulation continues with the subsequent
input samples. Figure 24 illustrates the RMS magnitude
monitoring logic.
Figure 25. ADC Input Threshold Crossing Block Diagram
ADDITIONAL CONTROL BITS
For additional flexibility in the signal monitoring process, two
control bits are provided in the power-monitor control register.
They are the signal monitor enable bit and the complex power
bit.
Figure 24. ADC Input RMS Magnitude Monitoring Block Diagram
THRESHOLD CROSSING MODE (MODE BITS 1X)
Signal monitor Enable Bit
In this mode of operation, the magnitude of the input port
signal is monitored over a programmable time period (given by
SMPR) to count the number of times it crosses a certain
programmable threshold value. This mode is set by programming Logic 1x (where x is a don’t care bit) in the power-monitor
mode bits of the signal monitor control register or by setting the
Threshold Crossing Output Enable bit in the Signal monitor
SPORT Control Register. Before activating this mode, the user
needs to program the 24-bit SMPR and the 13-bit upper
threshold register for each individual input port. The same
upper threshold register is used for both signal monitoring and
gain control (see the ADC Overrange and Gain Control
section).
The signal monitor enable bit located in bit 0 or register 0x112
enables operation of the signal monitor block. If the signal
monitor function is not needed in a particular application then
this bit should be cleared to conserver power.
Measure Complex Power Bit
When this bit is set the part assumes that Channel A is
digitizing the I data and Channel B is digitizing the Q data for a
complex input signal (or vice versa). In this mode the power
reported is the sqrt(I^2 + Q^2). This complex power
measurement result is presented in the Channel A signal
monitor value register if the signal monitor mode bits are set to
00. The channel B signal monitor will continue to compute the
channel B value.
Rev. PrA | Page 27 of 40
AD9627
Preliminary Technical Data
DC CORRECTION
Since the DC offset of the ADC can be significantly larger than
the signal we are trying to measure a simple DC correction
circuit is included to null the DC offset before measuring the
power. The DC Correction circuit can also be switched into the
main signal path but this may not be appropriate if the ADC is
digitizing a time-varying signal with significant DC content
such as GSM.
DC Correction Bandwidth
The DC correction circuit is basically a HP filter with a
programmable BW ranging between 0.15Hz and 1.2kHz. The
BW is controlled by writing the 4-bit DC correction register
located in bits 5:2 at address 0x10C. Table xx shows the BW
values for each of the 16 possible programmed values.
Table xx. DC Correction Bandwidth Settings
DC Correction Factor
reg.10C<5:2>
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Setting bit 0 of register 0x10C enables the DC correction for use
in the Signal monitor calculations. The calculated DC
correction value can be added to the output data signal path by
setting bit 1 of register 0x10C.
SIGNAL MONITOR SPORT OUTPUT
The SPORT is a serial interface with three output pins, the SMI
SCLK (SPORT clock), SMI_SDFS (SPORT frame sync) and
SMI_SDO (SPORT data). The SPORT is the master, and drives
all three pins out of the chip.
SMI SCLK
The data and frame sync are driven on the positive edge of the
SMI SCLK. The SMI SCLK has three possible baud rates. They
are ½, ¼, or 1/8 the ADC clock rate, based on the SPORT
controls. The SMI SCLK can also be gated off when not sending
any data, based on the SMI SCLK sleep bit. Gating off the SMI
SCLK when it is not needed will reduce the coupling errors
back into the signal path if these prove to be a problem in the
system. This has the disadvantage of spreading the frequency
content of the clock so this can be left running to ease
frequency planning if desired.
SMI SDFS
Bandwidth (Hz)
1218.56
609.28
304.64
152.32
76.16
38.08
19.04
9.52
4.76
2.38
1.19
0.60
0.30
0.15
0.15
0.15
The SMI_SDFS is the Serial Data Frame Sync, and defines the
start of a frame. One SPORT frame includes data from both
datapaths. The data from Datapath A is sent just after the frame
sync, followed by data from Datapath B.
SMI SDO
The SMI_SDO is the serial data out of the block. The data is
sent MSB first on the next positive edge after the SMI_SDFS.
Each data output block includes one or more of RMS
magnitude, Peak level, and Threshold Crossing values from
both datapaths in the stated order. If enabled the data is sent
RMS first, followed by Peak, and Threshold as shown in Figure
x.
DC Correction Readback
The current DC correction value can be read back in registers
0x10D and 0x10E for channel A and registers 0x10F and 0x110
for channel B. The DC correction value is a 14 bit value that
can span the entire input range of the ADC.
Figure 26. Signal monitor SPORT Output Timing (RMS, Peak, and Threshold
Enabled)
DC Correction Freeze
Setting the DC Correction Freeze bits freezes the DC correction
at its current state and continues to use the last updated value as
the DC correction value. Clearing this bit restarts the DC
correction and adds the currently calculated value to the data.
DC Correction Enable Bits
Figure 27. Signal monitor SPORT Output Timing (RMS and Threshold
Enabled)
Rev. PrA | Page 28 of 40
Preliminary Technical Data
AD9627
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9627 includes built-in test features to enable verification
of the integrity of each channel as well as to facilitate board level
debugging. A BIST (built-in self-test) feature is included which
verifies the integrity of the digital data path of the AD9627.
Various output test options are also provided to place
predictable values on the outputs of the AD9627.
BUILT IN SELF TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9627 signal path. When enabled, the test runs from a user
selectable internal source (PN or sine) through the digital data
path starting at the ADC block output. The BIST sequence will
run for 256 cycles and stop. The BIST signature value for
channel A or B will be placed in registers 0x024 and 0x025. If
one channel is chosen, its BIST signature is written to the two
registers. If both channels are chosen, the two channels’ results
are XOR’ed and placed in the BIST signature register. The
outputs are not disconnected during this test, so the PN
sequence can be observed as it runs. The PN sequence can be
continued from its last value or start from the beginning based
on the value programmed in register 0x00E bit 2. The BIST
signature result will vary based on the channel configuration.
OUTPUT TEST MODES
The output test options are shown in table x.x. When an output
test mode is enabled, the analog section of the ADC is
disconnected from the digital backend blocks and the test
pattern is run through the output formatting block. As
indicated in table x.x some of the test patterns are subject to
output formatting and some are not. The seed value for the PN
sequence tests can be forced if the PN reset bits are used to hold
the generator in reset mode by setting bits 4 or 5 of register
0x0D. These tests can be performed with or without an analog
signal, but do require an encode clock.
Rev. PrA | Page 29 of 40
AD9627
Preliminary Technical Data
CHANNEL/CHIP SYNCHRONIZATION
The AD9627 has a SYNC input that allows the user flexible
synchronization options for syncing the internal blocks. The
sync feature is useful to guarantee synchronized operation
across multiple ADCs. The input clock divider and the signal
monitor block can be synchronized using the SYNC input. The
input clock divider can be enabled to sync on a single
occurrence of the sync signal or on every occurrence. The
signal monitor syncs on every SYNC input.
The SYNC input is internally synchronized to the sample clock,
however to ensure there is no timing uncertainty between
multiple parts the SYNC input signal should be synchronized to
the input clock signal. The SYNC input should be driven using
a single ended CMOS type signal.
Rev. PrA | Page 30 of 40
Preliminary Technical Data
AD9627
SERIAL PORT INTERFACE (SPI)
The AD9627 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This gives the user added flexibility and customization
depending on the application. Addresses are accessed via the
serial port and may be written to or read from via the port.
Memory is organized into bytes that can be further divided
down into fields, which are documented in the Memory Map
section. Detailed operational information can be found in the
Analog Devices user manual titled Interfacing to High Speed
ADCs via SPI at www.analog.com.
port to be used both to program the chip as well as read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an
output at the appropriate point in the serial frame.
Data may be sent in MSB or in LSB first mode. MSB first is
default on power up and may be changed via the configuration
register. For more information about this and other features see
“Interfacing to High Speed ADCs via SPI” at www.analog.com.
Table xx. SPI Timing Diagram Specifications
Spec
Name
Meaning
CONFIGURATION USING THE SPI
tDS
Setup time between data and rising edge of SCLK
There are three pins that define the SPI of this ADC. They are
the SCLK/DFS, SDIO/DCS, and CSB pins (summarized inTable
x). The SCLK/DFS (serial clock) is used to synchronize the read
and write data presented from/to the ADC. The SDIO/DCS
(serial data input/output) is a dual purpose pin that allows data
to be sent and read from the internal ADC memory map
registers. The CSB (chip select bar) is an active low control that
enables or disables the read and write cycles.
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
tS
Setup time between CSB and SCLK
tH
Hold time between CSB and SCLK
tHI
Minimum period that SCLK should be in a logic high
state
tLO
Minimum period that SCLK should be in a logic low
state
Table xx. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
Function
SCLK (Serial Clock) is the serial shift clock in. SCLK is
used to synchronize serial interface reads and writes.
SDIO (Serial Data Input/Output) is a dual purpose pin.
The typical role for this pin is an input and output
depending on the instruction being sent and the
relative position in the timing frame.
CSB (Chip Select Bar) is active low controls that gates
the read and write cycles.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure x
and Table x.
Other modes involving the CSB are available. The CSB can be
held low indefinitely which permanently enabling the device,
this is called streaming. The CSB may stall high between bytes
to allow for additional external timing. When CSB is tied high,
SPI functions are placed in a high impedance more. This mode
turns on any SPI pin secondary functions.
During an instruction phase a 16bit instruction is transmitted.
Data follows the instruction phase and it’s length is determined
by the W0 and W1 bits. All data is composed of 8bit words. The
first bit of each individual byte of serial data indicates whether a
read or write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
HARDWARE INTERFACE
The pins described in Table xError! Reference source not
found. comprise the physical interface between the user’s
programming device and the serial port of the AD9627. All
serial pins are inputs, which should be tied to an external pullup or pull-down resistor (suggested value 10 kΩ).
The SPI interface is flexible enough to be controlled by either
FPGAs or mirocontrollers. This provides the user the ability use
an alternate method to program the ADC other than a
dedicated SPI controller.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Since the
SCLK, CSB and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade the converter’s
performance. If the on board SPI Bus is utilized for other
devices it may be necessary to provide buffers between this bus
and the AD9627 in order to keep these signals from
transitioning at the converter inputs during critical sampling
periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to AVDD or ground
during device power on, they are associated with a specific
function. The TBD section describes the strappable functions
supported on the AD9627.
Rev. PrA | Page 31 of 40
AD9627
Preliminary Technical Data
CONFIGURATION WITHOUT THE SPI
Memory Map Table.
In applications that do not interface to the SPI control registers,
the SDIO/DCS, SCLK/DFS, MON SDO/OEB, and MON
SCLK/PDWN pins serve as stand alone CMOS compatible
control pins. When the device is powered up, it is assumed that
the user intends to use the pins as static control lines for the
duty cycle stabilizer, output data format, output enable, and
power down feature control. In this mode the CSB chip select
should be connected to AVDD, which will disable the serial
port interface.
Logic Levels
Table 5. Mode Selection
Pin
SDIO/DCS
SCLK/DFS
MON SDO/
OEB
MON SCLK/
PDWN
External
Voltage
AVDD (default)
AGND
AVDD
AGND (default)
AVDD
AGND (default)
AVDD
AGND (default)
Configuration
Duty Cycle Stabilizer Enabled
Duty Cycle Stabilizer Disabled
Twos Complement Enabled
Offset Binary Enabled
Outputs in High Impedance
Outputs Enabled
Chip in PowerDown/Standby
Normal Operation
MEMORY MAP
Reading the Memory Map Table
Each row in the memory map table has eight bit locations. The
memory map is roughly divided into four sections: chip
configuration and ID register map (Address 0x00 to Address
0x05), ADC setup, control and test (Addresses 0x08 to Address
0x25), transfer register map (Address 0xFF), and digital feature
control (Address 0x100 to Address 0x11B).
Starting from the right hand column, the memory map register
in Table x documents the default hex value for each hex address
shown. The column with the heading Bit 7 (MSB) is the start of
the default hex value given. For example, hex address 0x18,
reference select, has a hex default value of 0xC0. This means Bit
7 = 1, Bit 6 = 1, and the remaining bits are zeros. This setting is
the default reference selection setting. The default value uses a
2.0V peak to peak reference. For more information on this
function and others consult “Interfacing to High Speed ADCs via
SPI” at www.analog.com.
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Transfer Register Map
Addresses 0x08 to 0x18 are shadowed. Writes to these
addresses do not affect the part operation until a transfer
command is issued by writing a 0x01 to address 0xFF setting
the transfer bit. This allows these registers to be updated
internally simultaneously when the transfer bit is set. The
internal update takes place when the transfer bit is set and the
bit autoclears.
Channel Specific Registers
Some channel setup functions such as the signal monitor
thresholds can be programmed differently for each channel. In
these cases channel address locations are internally duplicated
for each channel. These registers are designated in the
‘Parameter Name’ column of Table x as (local) registers. These
local registers can be accessed by setting the appropriate
Channel A or Channel B bits in register 0x05. If both bits are
set the subsequent write will affect both channels’ registers. In a
read cycle only Channel A or Channel B should be set to read
one of the two registers. If both bits are set during a SPI read
cycle the part returns the value for channel A. Registers
designated as (global) in the ‘Parameter Name’ column of Table
x affect the entire part or the channel features where
independent settings are not allowed between the channels.
The settings in register 0x05 do not affect the global registers.
SPI ACCESSIBLE FEATURES
A brief description of all features accessible via the SPI follows.
They are described in great detail in the Analog Devices user
manual titled Interfacing to High Speed ADCs via SPI at
www.analog.com.
Modes: Allows the user to set either power-down or standby
mode.
Clock:
Allows the user to access the DCS via the SPI.
All address and bit locations that are not included in Table x are
currently not supported for this device. Unused bits of a valid
address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), then this address location
should not be written.
Offset:
Allows the user to digitally adjust the converter offset.
Default Values
Output Delay: Allows user to vary the strength of the output
drivers.
Open Locations
Coming out of reset, critical registers are loaded with default
values. The default values for the registers are given in the
Test IO: Allows the user to set test modes to have known data
on output bits.
Output Mode: Allows the user to setup outputs.
Output phase: Allows user to set the output clock polarity.
Vref:
Rev. PrA | Page 32 of 40
Allows the user to set the reference voltage.
Preliminary Technical Data
AD9627
Figure 28. Serial Port Interface Timing Diagram
Rev. PrA | Page 33 of 40
AD9627
Preliminary Technical Data
EXTERNAL MEMORY MAP
Table 6. Memory Map Register
Addr. Parameter
Bit 7
(Hex) Name
(MSB)
Chip Configuration Registers
0
00
SPI Port
Configuration
(global)
01
Chip ID
(global)
02
Chip Grade
(global)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
8-bit Chip ID Bits 7:0
(AD9627 = 0x12), (default)
X
X
Speed Grade ID 4:3
11 = 80 MSPS
10 = 105 MSPS
01 = 125 MSPS
00 = 150 MSPS
Default
Value
(Hex)
Default
Notes/
Comments
0x18
The nibbles
should be
mirrored so
that LSB- or
MSB-first
mode registers
correctly
regardless of
shift mode.
Default is
unique chip
ID, different
for each
device. This is
a read-only
register.
Speed Grade
ID used to
differentiate
devices.
0x0F
Read
Only
X
X
X
X
Read
only
Channel Index and Transfer Registers
05
Channel Index
X
X
X
X
X
X
Data
Channel B
(default)
Data
Channel A
(default)
0x03
FF
X
X
X
X
X
X
X
Transfer
0x00
ADC Functions
08
Power modes
X
X
X
X
Internal power-down
mode
(local)
00—normal operation
01—full power-down
10—standby
11—normal operation
0x00
09
Global clock
(global)
X
X
External
Power
Down Pin
Function
(global)
0 = pdwn
1 = stndby
X
X
X
0B
Clock divide
(global)
X
X
X
X
X
Device Update
Rev. PrA | Page 34 of 40
X
X
Clock Divide Ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
Duty cycle
stabilize
(default)
Bits are set to
determine
which device
on chip
receives the
next write
command.
Applies to
local registers.
Synchronously
transfers data
from the
master shift
register to the
slave.
Determines
various
generic
modes of chip
operation.
0x01
0x00
Clock divide
values other
than 000
automatically
causes the
Duty Cycle
Stabilization
to become
active
Preliminary Technical Data
AD9627
Addr.
(Hex)
0D
Parameter
Name
Test Mode
(local)
Bit 7
(MSB)
X
Bit 6
X
Bit 5
Reset PN23
gen
Bit 4
Reset
PN9 gen
Bit 3
X
0E
Bist enable
(local)
X
X
X
X
X
10
Offset adjust
(local)
Output Mode
X
X
Drive
Strength
0—3.3V
CMOS or
ANSI LVDS
1—1.8V
CMOS or
Reduced
LVDS
(global)
X
Output
Type
0 = CMOS
1 = LVDS
(global)
Interleaved
CMOS
(global)
Output
Enable
Bar
(local)
X
X
X
X
X
X
X
X
X
X
14
15
Output Adjust
(global)
16
Clock Phase
Control
(global)
Invert DCO
Clock
18
Vref Select
(global)
Reference Voltage
Selection
00 = 1.25V pk-pk
01 = 1.5V pk-pk
10 = 1.75V pk-pk
11 = 2.0V pk-pk (default)
24
BIST Signature
lsb (local)
BIST Signature
msb (local)
Synch_Control
(global)
25
Bit 0
(LSB)
Bit 2
Bit 1
Output test mode
000—off (default)
001—midscale short
010—+positive FS
011—−negative FS
100—alternating checker board
101—PN 23 sequence
110—PN 9 sequence
111—one/zero word toggle
Reset
X
BIST
BIST
Enable
Sequence
Offset Adjust in LSBs from +31 to -32 (twos compliment format)
Default
Notes/
Comments
When set, the
test data is
placed on the
output pins in
place of
normal data.
0x00
0x00
Output
invert
(local)
00—offset binary 01—
twos complement
01—greycode 11—
offset binary (local)
0x00
Configures the
outputs and
the format of
the data.
CMOS 3.3V Drive
Strength (00 is lowest
drive and 11 is highest
drive)
CMOS 1.8 V Drive
Strength (00 is lowest
drive and 11 is highest
drive)
0x02
Determines
CMOS output
drive strength
– Selecting
higher drive
strengths can
affect
converter
performance
On devices
that utilize
global clock
divide, allows
selection of
clock delays
into the
dividerb.
X
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
X
X
X
0x00
0x30
BIST Signature [7:0]
0x00
Read Only
BIST Signature [15:8]
0x00
Read Only
Master
Sync
Enable
0x00
Enable
Fast
Detect
Coarse Upper Threshold [2:0]
0x00
104
Fast Detect
Control (local)
X
X
X
X
Clock
Clock
Divider
Divider
Sync
Next
Enable
Sync
Only
Fast Detect Mode Select [2:0]
105
Coarse Upper
Threshold (local)
X
X
X
X
X
100
Default
Value
(Hex)
0x00
PM Sync
Enable
X
X
X
Rev. PrA | Page 35 of 40
X
0x00
AD9627
Addr.
(Hex)
106
107
108
109
10A
10B
10C
10D
10E
10F
110
111
Parameter
Name
Fine Upper
Threshold
Register 0 (local)
Fine Upper
Threshold
Register 1 (local)
Fine Lower
Threshold
Register 0 (local)
Fine Lower
Threshold
Register 1 (local)
Increase Gain
Dwell Time
Register 0 (local)
Increase Gain
Dwell Time
Register 1 (local)
Signal monitor
DC Correction
Control (global)
Signal monitor
DC Value
Channel A
Register 0
(global)
Signal monitor
DC Value
Channel A
Register 1
(global)
Signal monitor
DC Value
Channel B
Register 0
(global)
Signal monitor
DC Value
Channel B
Register 1
(global)
Signal monitor
SPORT Control
(global)
112
Signal monitor
Control (global)
113
Signal monitor
Period Register 0
(global)
Signal monitor
Period Register 1
(global)
Signal monitor
Period Register 2
(global)
Signal monitor
114
115
116
Preliminary Technical Data
Bit 7
(MSB)
Bit 6
Bit 5
X
X
X
Bit 4
Bit 3
Fine Upper Threshold [7:0]
Bit 2
Bit 1
Bit 0
(LSB)
Fine Upper Threshold [12:8]
X
X
X
0x00
Fine Lower Threshold [12:8]
DC
Correction
Freeze
0x00
IncreaseGain Dwell Time [7:0]
0x00
In ADC Clock
Cycles
IncreaseGain Dwell Time [15:8]
0x00
In ADC Clock
Cycles
DC Correction Bandwidth [3:0]
DC
Correction
for Signal
Path
Enable
DC
Correction
for PM
Enable
0x00
DC Value Channel A [7:0]
X
X
Read only
DC Value Channel A [13:8]
Read only
DC Value Channel B [7:0]
Read only
DC Value Channel A [13:8]
X
RMS
Magnitude
Output
Enable
Peak
Power
Output
Enable
Enable
Complex
Power
Calculation
Mode
X
X
Default
Notes/
Comments
0x00
Fine Lower Threshold [7:0]
X
Default
Value
(Hex)
0x00
SPORT
SPORT Clock Divide
SCLK
00 = Undefined
Sleep
01 = divide by 2
10 = divide by 4
11 = divide by 8
Signal monitor Mode
X
MS Mode
00 = RMS/MS
0 = RMS
Magnitude
1 = MS
01 = Peak Power
1x = Threshold Count
Signal monitor Period [7:0]
Threshold
Crossing
Output
Enble
Read only
SPORT
Enable
0x04
Signal
monitor
Enable
0x00
0x80
In ADC Clock
Cycles
Signal monitor Period [15:8]
0x00
In ADC Clock
Cycles
Signal monitor Period [23:16]
0x00
In ADC Clock
Cycles
Signal monitor Value Channel A [7:0]
Rev. PrA | Page 36 of 40
Read only
Preliminary Technical Data
Addr.
(Hex)
117
118
119
11A
11B
Parameter
Name
Value Channel A
Register 0
(global)
Signal monitor
Value Channel A
Register 1
(global)
Signal monitor
Value Channel A
Register 2
(global)
Signal monitor
Value Channel B
Register 0
(global)
Signal monitor
Value Channel B
Register 1
(global)
Signal monitor
Value Channel B
Register 2
(global)
Bit 7
(MSB)
AD9627
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Signal monitor Value Channel A [15:8]
X
X
X
X
X
X
X
Signal monitor Value Channel A [19:16]
Default
Value
(Hex)
Default
Notes/
Comments
Read only
Read only
Signal monitor Value Channel B [7:0]
Read only
Signal monitor Value Channel B [15:8]
Read only
X
MEMORY MAP REGISTER DESCRIPTION
Rev. PrA | Page 37 of 40
Signal monitor Value Channel B [19:16]
Read only
AD9627
Preliminary Technical Data
APPLICATIONS
DESIGN GUIDELINES
When designing the AD9627 into a system, it is recommended
that, before starting design and layout, the designer become
familiar with these guidelines, which discuss the special circuit
connections and layout requirements required for certain pins.
Power and Ground Recommendations
When connecting power to the AD9627, it is recommended
that two separate 1.8 V supplies be used: one supply should be
used for analog (AVDD) and digital (DVDD) and a separate
supply for the digital outputs (DRVDD). The AVDD and
DVDD supplies, while derived from the same source, should be
isolated with a ferrite bead or filter choke and separate
decoupling capacitors. The user can employ several different
decoupling capacitors to cover both high and low frequencies.
These should be located close to the point of entry at the PC
board level and close to the part’s pins with minimal trace
length.
To maximize the coverage and adhesion between the ADC and
PCB, overlay a silkscreen to partition the continuous plane on
the PCB into several uniform sections. This provides several tie
points between the two during the reflow process. Using one
continuous plane with no partitions only guarantees one tie
point between the ADC and PCB. See the evaluation board for a
PCB layout example. For detailed information on packaging
and the PCB layout of chip scale packages, see the AN-772
Application Note, “A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP),” at www.analog.com.
CML
The CML pin should be decoupled to ground with a 0.1uF
capacitor, as shown in Figure 5.
RBIAS
The AD9627 requires the user to place a 10KΩ resistor between
the RBIAS pin and ground. This resister sets the master current
reference of the ADC core and should have at least a 1%
tolerance.
A single PC board ground plane should be sufficient when
using the AD9627. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections,
optimum performance is easily achieved.
Reference Decoupling
Exposed Paddle Thermal Heat Slug Recommendations
SPI Port
It is mandatory that the exposed paddle on the underside of the
ADC is connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9627. A
continuous exposed (no solder mask) copper plane on the PCB
should mate to the AD9627 exposed paddle, Pin 0. The copper
plane should have several vias to achieve the lowest possible
resistive thermal path for heat dissipation to flow through the
bottom of the PCB. These vias should be filled or plugged with
nonconductive epoxy.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Since the
SCLK, CSB and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade the converter’s
performance. If the on board SPI Bus is utilized for other
devices it may be necessary to provide buffers between this bus
and the AD9627 in order to keep these signals from
transitioning at the converter inputs during critical sampling
periods.
The VREF pin should be externally decoupled to ground with a
low ESR 1.0uF capacitor in parallel with a 0.1uF ceramic low
ESR capacitor.
Rev. PrA | Page 38 of 40
Preliminary Technical Data
AD9627
AD9627 EVALUATION BOARD AND SOFTWARE
The AD9627 evaluation board kit contains a fully populated
AD9627 PCB, schematic diagrams, operating software, and a
comprehensive instruction manual.
Users can preview the evaluation board schematic, the software,
and the instruction manual on the product Web page of the
Analog Devices website.
Rev. PrA | Page 39 of 40
OUTLINE DIMENSIONS
9.00
BSC SQ
0.30
0.25
0.18
0.60 MAX
0.60 MAX
64 1
48 49
PIN 1
INDICATOR
PIN 1
INDICATOR
8.75
BSC SQ
TOP
VIEW
0.50
0.40
0.30
33
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
17 16
32
0.25 MIN
0.05 MAX
0.02 NOM
SEATING
PLANE
0.50 BSC
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
063006-B
1.00
0.85
0.80
7.25
7.10 SQ
6.95
EXPOSED PAD
(BOTTOM VIEW)
Figure 29. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9mm x 9mm Body, Very Thin Quad
(CP-64-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9627BCPZ-150
AD9627BCPZ-125
AD9627BCPZ-105
AD9627BCPZ-80
AD9627/PCB
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board with AD9627 and Software
© 2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06547-0-12/06(PrA)
Rev. PrA | Page 40 of 40
Package Option
CP-64-3
CP-64-3
CP-64-3
CP-64-3