RFIP RFIN BIAS CH 1 ΦSEL LOGIC PH13 0° Medical imaging (CW ultrasound beamforming) Phased array systems (radar and adaptive antennas) Communication receivers Φ I1NO I1PO Φ Q1PO Q1NO Φ Q2NO Q2PO Φ I2PO I2NO COMM 90° 4LOP BUF ÷4 90° 4LON 0° PH23 PH22 CH 2 ΦSEL LOGIC 05543-001 PH12 RF2P RF2N APPLICATIONS ENBL FUNCTIONAL BLOCK DIAGRAM Dual integrated I/Q demodulator 16 phase select options on each output (22.5° per step) Quadrature demodulation accuracy Phase accuracy: ±0.1° Amplitude balance: ±0.05 dB Bandwidth 4 × LO: 10 kHz to 200 MHz RF: dc to 50 MHz Baseband: determined by external filtering Output dynamic range: 159 dB/Hz LO drive > 0 dBm (50 Ω); 4 × LO > 1 MHz Supply: ±5 V Power consumption: 190 mW/channel (380 mW total) Power-down PH11 FEATURES PH10 Data Sheet DC to 50 MHz, Dual I/Q Demodulator and Phase Shifter AD8333 Figure 1. GENERAL DESCRIPTION The AD8333 1 is a dual phase-shifter and I/Q demodulator that enables coherent summing and phase alignment of multiple analog data channels. It is the first solid-state device suitable for beamformer circuits, such as those used in high performance medical ultrasound equipment featuring CW Doppler. The RF inputs interface directly with the outputs of the dual-channel, low noise preamplifiers included in the AD8332. A divide-by-4 circuit generates the internal 0° and 90° phases of the local oscillator (LO) that drive the mixers of a pair of matched I/Q demodulators. The AD8333 can be applied as a major element in analog beamformer circuits in medical ultrasound equipment. The AD8333 features an asynchronous reset pin. When used in arrays, the reset pin sets all the LO dividers in the same state. Sixteen discrete phase rotations in 22.5° increments can be selected independently for each channel. For example, if Channel 1 is used as a reference and the RF signal applied to Channel 2 has an I/Q phase lead of 45°, Channel 2 can be phase aligned with Channel 1 by choosing the correct code. Phase shift is defined by the output of one channel relative to another. For example, if the code of Channel 1 is adjusted to 0000 and that of Channel 2 is adjusted to 0001 and the same signal is applied to both RF inputs, the output of Channel 2 leads that of Channel 1 by 22.5°. The I and Q outputs are provided as currents to facilitate summation. The summed current outputs are converted to voltages by a high dynamic range, current-to-voltage (I-V) converter, such as the AD8021, configured as a transimpedance amplifier. The resultant signal is then applied to a high resolution ADC, such as the AD7665 (16 bit/570 kSPS). The two I/Q demodulators can be used independently in other nonbeamforming applications. In that case, a transimpedance amplifier is needed for each of the I and Q outputs, four in total for the dual I/Q demodulator. The dynamic range is 159 dB/Hz at the I and Q outputs, but the following transimpedance amplifier is an important element in maintaining the overall dynamic range, and attention needs to be paid to optimal component selection and design. The AD8333 is available in a 32-lead LFCSP (5 mm × 5 mm) package for the industrial temperature range of −40°C to +85°C. 1 Protected by US Patent 7,760,833. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8333 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Channel Summing ..................................................................... 21 Applications ....................................................................................... 1 Dynamic Range Inflation .......................................................... 23 Functional Block Diagram .............................................................. 1 Disabling the Current Mirror and Decreasing Noise ............ 23 General Description ......................................................................... 1 Applications Information .............................................................. 25 Revision History ............................................................................... 3 Logic Inputs and Interfaces ....................................................... 25 Specifications..................................................................................... 4 Reset Input .................................................................................. 25 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Connecting to the LNA of the AD8331/AD8332/AD8334/AD8335 VGAs............................ 25 Pin Configuration and Function Descriptions ............................. 7 Interfacing to Other Amplifiers ............................................... 26 Equivalent Input Circuits ................................................................ 8 LO Input ...................................................................................... 26 Typical Performance Characteristics ............................................. 9 Evaluation Board ............................................................................ 27 Test Circuits ..................................................................................... 15 Features and Options ................................................................. 27 Theory of Operation ...................................................................... 18 Measurement Setup.................................................................... 28 Quadrature Generation ............................................................. 18 Evaluation Board Schematic and Artwork.................................. 29 I/Q Demodulator and Phase Shifter ........................................ 18 Board Layout ............................................................................... 31 Dynamic Range and Noise ........................................................ 19 Outline Dimensions ....................................................................... 32 Summation of Multiple Channels (Analog Beamforming) .. 20 Ordering Guide .......................................................................... 32 Phase Compensation and Analog Beamforming ................... 20 Rev. F | Page 2 of 32 Data Sheet AD8333 REVISION HISTORY 5/2016—Rev. E to Rev. F Change to Features Section and General Description Section......... 1 Change to Quiescent Power Parameter, Table 1............................ 5 Changes to Figure 2 and Table 3 ..................................................... 7 Change to Figure 52 ........................................................................18 Change to Figure 61 ........................................................................28 Change to Figure 64 ........................................................................29 Updated Outline Dimensions ........................................................32 Changes to Ordering Guide ...........................................................32 8/2012—Rev. D to Rev. E Changes to Figure 1 and General Description Section ................ 1 Moved Revision History Section ..................................................... 3 Changes to Table 3 ............................................................................ 7 Changes to Table 5 ..........................................................................27 Updated Outline Dimensions ........................................................33 9/2010—Rev. C to Rev. D Change to I2NO, Q2NO, Q1NO, and I1NO Pin Description, Table 3 ................................................................................................. 6 Changes to Figure 62, Features and Options Section, Table 5, Phase Nibble Section, and Enable and Reset Switches Section ..............................................................................................26 Changes to Reset Input Section, Measurement Setup Section, and Figure 63 ...................................................................................27 Changes to Figure 64 ......................................................................28 Changes to Figure 65 ......................................................................29 Changes to Figure 66 Through Figure 70 ....................................30 Deleted Ordering Information Section ........................................37 Deleted Table 7; Renumbered Sequentially .................................37 9/2008—Rev. B to Rev. C Changes to Figure 1........................................................................... 1 Changes to General Description Section ....................................... 1 Change to Table 2 .............................................................................. 5 Changes to Figure 4 and Figure 6.................................................... 7 Change to Figure 18 .......................................................................... 9 Changes to Dynamic Range and Noise Section .......................... 18 Changes to Connecting to the LNA of the AD8331/AD8332/ AD8334/AD8335 VGAs Section ................................................... 24 Added Interfacing to Other Amplifiers Heading........................ 25 Changes to Figure 61 ...................................................................... 25 Incorporated AD8333-EVALZ Data Sheet .................................. 26 Changes to Evaluation Board Section .......................................... 26 Changes to Features and Options Section ................................... 26 Changes to Table 5 .......................................................................... 26 Replaced the Phase Bits Section with the Phase Nibble Section .............................................................................................. 26 Deleted Table 2 .................................................................................. 3 Changes to LNA Input Impedance Section ................................. 26 Changes to Current Summing Section......................................... 26 Changes to Measurement Setup Section ...................................... 27 Moved Figure 63; Changes to Figure 63....................................... 27 Changes to Figure 64 ...................................................................... 28 Moved Figure 70 .............................................................................. 30 Changes to Table 7 .......................................................................... 31 Deleted Figure 62; Renumbered Sequentially ............................. 26 Updated Outline Dimensions........................................................ 32 Changes to Ordering Guide ........................................................... 32 5/2007—Rev. A to Rev. B Changes to Features and Figure 1 ................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Figure 41 to Figure 43 ................................................ 14 Changes to Figure 44 to Figure 47 ................................................ 15 Changes to Figure 48 to Figure 51 ................................................ 16 Changes to Figure 55 ...................................................................... 20 Changes to Evaluation Board Section .......................................... 25 Changes to Ordering Guide ........................................................... 27 5/2006—Rev. 0 to Rev. A Changes to Figure 62 ...................................................................... 26 10/2005—Revision 0: Initial Version Rev. F | Page 3 of 32 AD8333 Data Sheet SPECIFICATIONS VS = ±5 V, TA = 25°C, f4LO = 20 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO ≥ 0 dBm, single-ended, sine wave; per channel performance, dBm (50 Ω), unless otherwise noted (see Figure 41). Table 1. Parameter OPERATING CONDITIONS LO Frequency Range RF Frequency Range Baseband Bandwidth LO Input Level VSUPPLY (VS) Temperature Range DEMODULATOR PERFORMANCE RF Differential Input Impedance LO Differential Input Capacitance Transconductance Dynamic Range Maximum RF Input Swing Peak Output Current (No Filtering) Input P1dB Third-Order Intermodulation (IM3) Equal Input Levels Unequal Input Levels Third-Order Input Intercept (IP3) LO Leakage Conversion Gain Input-Referred Noise Output Current Noise Noise Figure Bias Current LO Common-Mode Voltage Range RF Common-Mode Voltage Output Compliance Range PHASE ROTATION PERFORMANCE Phase Increment Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching Test Conditions/Comments Min 4× internal LO at Pin 4LOP and Pin 4LON Square wave Sine wave, see Figure 22 Mixing Limited by external filtering See Figure 22 0.01 2 DC DC ±4.5 −40 Demodulated IOUT/VIN, each I or Q output after low-pass filtering measured from RF inputs, all phases IP1dB, input-referred noise (dBm) Differential; inputs biased at 2.5 V; Pin RFxP and Pin RFxN 0° phase shift 45° phase shift Reference = 50 Ω Reference = 1 V rms fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Baseband tones: −7 dBm at 8 kHz and 13 kHz Baseband tones: −1 dBm at 8 kHz and −31 dBm at 13 kHz fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Measured at RF inputs, worst phase, measured into 50 Ω (limited by measurement) Measured at baseband outputs, worst phase, AD8021 disabled, measured into 50 Ω All codes Output noise/conversion gain Output noise ÷ 787 Ω With AD8332 LNA RS = 50 Ω, RFB = ∞ RS = 50 Ω, RFB = 1.1 kΩ RS = 50 Ω, RFB = 274 Ω Pin 4LOP and Pin 4LON Pin RFxP and Pin RFxN Pin 4LOP and Pin 4LON (each pin) For maximum differential swing; Pin RFxP and Pin RFxN (dc-coupled to AD8332 LNA output) Pin IxPO and Pin QxPO One channel is reference; the other channel is stepped 16 phase steps per channel I1xO to Q1xO and I2xO to Q2xO, 1σ I1xO to Q1xO and I2xO to Q2xO, 1σ Phase match I1xO/I2xO and Q1xO/Q2xO; −40°C < TA < 85°C Amplitude match I1xO/I2xO and Q1xO/Q2xO; −40°C < TA < 85°C Rev. F | Page 4 of 32 Typ 0 ±5 Max Unit 200 200 50 50 13 ±6 +85 MHz MHz MHz MHz dBm V °C 6.7||6.5 0.6 2.17 kΩ||pF pF mS 159 2.8 ±4.7 ±6.6 14.5 1.5 dB/Hz V p-p mA mA dBm dBV −75 −77 30 <−97 dBc dBc dBm dBm −60 dBm 4.7 10 22 dB nV/√Hz pA/√Hz 7.8 9.0 11.0 −3 −70 dB dB dB µA µA V V 0.2 3.8 2.5 −1.5 −2 +0.7 22.5 ±0.1 ±0.05 ±1 ±0.25 +2 V Degrees Degrees dB Degrees dB Data Sheet Parameter LOGIC INTERFACES Logic Level High Logic Level Low Bias Current Pin PHxx and Pin ENBL Pin RSET Input Resistance Reset Hold Time Minimum Reset Pulse Width Reset Response Time Phase Shifting Response Time Enable Response Time POWER SUPPLY Supply Voltage Quiescent Current, All Phase Bits = 0 Over Temperature Quiescent Power Disable Current AD8333 Test Conditions/Comments Min Pin PHxx, Pin RSET, and Pin ENBL Pin PHxx, Pin RSET, and Pin ENBL 1.7 0 Logic high Logic low Logic high Logic low Pin PHxx and Pin ENBL Pin RSET Reset is asynchronous; clock disabled when RSET goes high until 300 ns after RSET goes low; see Figure 58 10 −30 50 −70 Typ 40 −7 120 −20 60 20 Max Unit 5 1.3 V V 90 +10 180 0 µA µA µA µA kΩ kΩ ns 300 300 See Figure 35 See Figure 38 See Figure 34 Pin VPOS and Pin VNEG At 25°C Pin VPOS Pin VNEG −40°C < TA < 85°C Pin VPOS, all phase bits = 0 Pin VNEG Per channel, all phase bits = 0 Per channel, any 0 or 1 combination of phase bits All channels disabled Pin VPOS Pin VNEG ns ns µs ns 300 5 300 ±4.5 ±5 ±6 V 38 −24 44 −20 51 −16 mA mA 54 −19 mA mA mW mW 1.5 −100 mA µA 40 −24 160 190 1.0 −300 1.25 −200 PSRR Pin VPOS to I/Q outputs (measured at AD8021 output) Pin VNEG to I/Q outputs (measured at AD8021 output) Rev. F | Page 5 of 32 −81 −75 dB dB AD8333 Data Sheet ABSOLUTE MAXIMUM RATINGS Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 2. Parameter Voltages Supply Voltage, VS RF Pins Input LO Inputs Code Select Inputs Voltage Thermal Data1 θJA θJB θJC ΨJT ΨJB Maximum Junction Temperature Maximum Power Dissipation (Exposed Pad Soldered to PC Board) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) 1 Rating 6V VS, GND VS, GND VS, GND ESD CAUTION 41.0°C/W 23.6°C/W 4.4°C/W 0.4°C/W 22.4°C/W 150°C 1.5 W −40°C to +85°C −65°C to +150°C 300°C 4-layer JEDEC board no airflow (exposed pad soldered to PCB). Rev. F | Page 6 of 32 Data Sheet AD8333 32 31 30 29 28 27 26 25 PH11 PH10 VPOS RF1P RF1N VPOS ENBL I1NO PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD8333 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 I1PO Q1PO Q1NO VNEG COMM Q2NO Q2PO I2PO NOTES 1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED THAT THE PADDLE BE SOLDERED TO THE GROUND PLANE. 05543-002 PH21 PH20 VPOS RF2P RF2N VPOS RSET I2NO 9 10 11 12 13 14 15 16 PH12 PH13 COMM 4LOP 4LON LODC PH23 PH22 Figure 2. 32-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 2, 7, 8 3, 20 4, 5 Mnemonic PH12, PH13, PH23, PH22 COMM 4LOP, 4LON 6 9, 10, 31, 32 11, 14, 27, 30 LODC PH21, PH20, PH10, PH11 VPOS 12, 13, 28, 29 RF2P, RF2N, RF1N, RF1P 15 RSET 16, 19, 22, 25 17, 18, 23, 24 I2NO, Q2NO, Q1NO, I1NO I2PO, Q2PO, Q1PO, I1PO 21 VNEG 26 ENBL EPAD Description Quadrant Select LSB, MSB. Binary code. These logic inputs select the quadrant: 0° to 90°, 90° to 180°, 180° to 270°, 270° to 360° (see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). Ground. These two pins are internally tied together. LO Inputs. No internal bias; therefore, these pins need to be biased by external circuitry. For optimum performance, these inputs must be driven differentially with a signal level that is not less than what is shown in Figure 22. Bias current is only −3 µA. Single-ended drive is also possible if the inputs are biased correctly (see Figure 4). Decoupling Pin for LO. A 0.1 µF capacitor must be connected between this pin and ground (see Figure 5). Phase Select LSB, MSB. Binary code. These logic inputs select the phase for a given quadrant: 0°, 22.5°, 45°, 67.5° (see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). Positive Supply. These pins must be decoupled with a ferrite bead in series with the supply, plus a 0.1 µF and 100 pF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected, one set of supply decoupling components for all four pins must be sufficient. RF Inputs. These pins are biased internally; however, it is recommended that they be biased by dc coupling to the output pins of the AD8332 LNA. The optimum common-mode voltage for maximum symmetrical input differential swing is 2.5 V if ±5 V supplies are used (see Figure 6 and Figure 60). Reset for Divide-by-4 in LO Interface. Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). Reset when high, enable when low. Negative I/Q Outputs. Not connected for typical applications. Positive I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via a transimpedance amplifier. Multiple outputs can be summed together by connecting them together. The bias voltage must be set to 0 V or less by the transimpedance amplifier (see Figure 7). Negative Supply. This pin must be decoupled with a ferrite bead in series with the supply, plus a 0.1 µF and 100 pF capacitor between the pin and ground. Chip Enable. Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3). Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the paddle be soldered to the ground plane. Rev. F | Page 7 of 32 AD8333 Data Sheet EQUIVALENT INPUT CIRCUITS VPOS VPOS RFxP PHxx ENBL RSET LOGIC INTERFACE 05543-006 05543-003 COMM RFxN COMM Figure 3. Logic Inputs Figure 6. RF Inputs COMM VPOS IxNO QxNO IxPO QxPO 4LOP COMM VNEG Figure 7. Output Drivers Figure 4. Local Oscillator Inputs VPOS COMM 05543-005 LODC Figure 5. Local Oscillator Decoupling Pin Rev. F | Page 8 of 32 05543-007 05543-004 4LON AD8333 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VS = ±5 V, TA = 25°C, f4LO = 20 MHz, fLO = 5 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO ≥ 0 dBm (50 Ω); single-ended sine wave; per channel performance, differential voltages, dBm (50 Ω), phase select code = 0000, unless otherwise noted (see Figure 41). 2 f = 1MHz 1.0 f = 5MHz CODE 0100 CODE 0011 Q I 1 CODE 0010 PHASE ERROR (Degrees) CODE 0001 0.5 CODE 1000 CODE 0000 0 –0.5 0 –1 –2 2 f = 1MHz 1 CODE 1100 –1.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 05543-011 0 –1.0 05543-008 IMAGINARY PHASE (Normalized) 1.5 –1 –2 0000 2.0 0010 REAL PHASE (Normalized) 0100 0110 1000 1010 1100 1111 1110 CODE (Binary) Figure 8. Normalized Vector Plot of Phase, Channel 2 with Respect to Channel 1; Channel 1 Is Fixed at 0°, Channel 2 Stepped 22.5°/Step, All Codes Displayed Figure 11. Phase Error of Channel 2 with Respect to Channel 1 vs. Code at 1 MHz and 5 MHz 360 500mV 1MHz 5MHz 315 PHASE (Degrees) 270 225 180 135 0 0000 05543-009 45 0010 0100 0110 1000 1010 1100 1110 20µs 05543-012 90 1111 CODE (Binary) Figure 9. Phase of Channel 2 with Respect to Channel 1 vs. Code at 1 MHz and 5 MHz Figure 12. I or Q Output of Channel 2 with Respect to Channel 1, First Quadrant Shown 1.0 7 CHANNEL 1, I OUTPUT SHOWN f = 5MHz 0.5 6 CODE 0000 CODE 0001 CODE 0010 CODE 0011 –0.5 GAIN (dB) –1.0 1.0 f = 1MHz 5 0.5 4 05543-010 0 –0.5 –1.0 0000 0010 0100 0110 1000 1010 1100 1110 3 1M 1111 CODE (Binary) 05543-013 AMPLITUDE ERROR (dB) 0 10M 50M RF FREQUENCY (Hz) Figure 10. Amplitude Error of Channel 2 with Respect to Channel 1 vs. Code at 1 MHz and 5 MHz Rev. F | Page 9 of 32 Figure 13. Conversion Gain vs. RF Frequency, First Quadrant, Baseband Frequency = 10 kHz AD8333 Data Sheet 0.5 0.4 I/Q AMPLITUDE IMBALANCE (dB) 1.5 0.5 0 –0.5 –1.0 –1.5 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 10M –0.4 –0.5 100 100M 1k 2.0 1.5 1.5 1.0 1.0 AMPLITUDE MATCH (dB) 2.0 0.5 0 –0.5 –1.0 –1.5 1k 10k fBB = 10kHz I2/I1 DISPLAYED CODE 0000 –40°C +25°C +85°C CODE 0001 –40°C +25°C +85°C 0.5 0 CODE 0010 –40°C +25°C +85°C –0.5 –1.0 CODE 0011 –40°C +25°C +85°C –1.5 –2.0 1M 100k 10M BASEBAND FREQUENCY (Hz) Figure 18. Typical I2xO/I1xO or Q2xO/Q1xO Amplitude Match vs. RF Frequency, First Quadrant, at Three Temperatures 0.5 8 0.4 6 PHASE ERROR (Degrees) 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 4 CODE 0000 –40°C +25°C +85°C CODE 0010 –40°C +25°C +85°C CODE 0001 –40°C +25°C +85°C CODE 0011 –40°C +25°C +85°C 2 0 –0.4 10M 50M RF FREQUENCY (Hz) 05543-043 –2 05543-016 I/Q AMPLITUDE IMBALANCE (dB) 50M RF FREQUENCY (Hz) Figure 15. Representative Range of Quadrature Phase Error vs. Baseband Frequency, Channel 1 and Channel 2 (see Figure 43) –0.5 1M 100k Figure 17. Representative Range of I/Q Amplitude Imbalance vs. Baseband Frequency, Channel 1 and Channel 2 (see Figure 43) 05543-015 QUADRATURE PHASE ERROR (Degrees) Figure 14. Representative Range of Quadrature Phase Errors vs. RF Frequency, Channel 1 or Channel 2, All Codes –2.0 100 10k BASEBAND FREQUENCY (Hz) RF FREQUENCY (Hz) 05543-018 –2.0 1M 05543-017 1.0 05543-014 QUADRATURE PHASE ERROR (Degrees) 2.0 fBB = 10kHz I2/I1 DISPLAYED –4 1M 10M 50M RF FREQUENCY (Hz) Figure 16. Representative Range of I/Q Amplitude Imbalance vs. RF Frequency, Channel 1 or Channel 2, All Codes Figure 19. I2xO/I1xO or Q2xO/Q1xO Phase Error vs. RF Frequency, Baseband Frequency = 10 kHz, at Three Temperatures Rev. F | Page 10 of 32 Data Sheet AD8333 10 2.8 CHANNEL 1, I OUTPUT SHOWN TRANSCONDUCTANCE = [(VBB/787Ω)V RF] GAIN = VBB/VRF 5 +85°C +25°C –40°C 0 2.6 CODE 0000 CODE 0001 CODE 0010 CODE 0011 –5 2.4 –10 2.3 –15 2.2 –20 2.1 –25 2.0 1M 10M 05543-019 GAIN (dB) 2.5 05543-020 –30 0 50M 10 20 0 18 f = 5MHz GAIN = VBB/VRF 1.5 2.0 2.5 3.0 3.5 4.0 5.0 4.5 16 14 IP1dB (dBm) –20 GAIN (dB) 1.0 Figure 23. LO Common-Mode Range at Three Temperatures Figure 20. Transconductance vs. RF Frequency, First Quadrant –10 0.5 COMMON-MODE VOLTAGE (V) RF FREQUENCY (Hz) –30 CODE 0000 CODE 0001 CODE 0010 CODE 0011 –40 –50 12 10 8 6 –60 05543-021 4 –70 –80 –20 –5 –10 –15 05543-023 TRANSCONDUCTANCE (mS) 2.7 2 0 1M 0 10M 50M RF FREQUENCY (Hz) POWER (dBm) Figure 21. Conversion Gain vs. LO Level, First Quadrant Figure 24. IP1dB vs. RF Frequency, Baseband Frequency = 10 kHz, First Quadrant (see Figure 42) 5 0 BOTH CHANNELS ALL CODES 0 –10 –20 IM3 (dBc) –10 –15 –20 –30 8 13 18 3 IM3 PRODUCTS –40 LO = 5.023MHz RF1 = 5.015MHz RF2 = 5.010MHz –50 –25 –60 –30 –70 –35 –40 100k 1M 10M 100M 05543-024 REGION OF USEABLE LO LEVELS 05543-022 MINIMUM LO LEVEL (dBm) –7dBm –5 –80 –90 1M 10M RF FREQUENCY (Hz) RF FREQUENCY (Hz) Figure 25. Representative Range of IM3 vs. RF Frequency, First Quadrant (see Figure 49) Figure 22. Minimum LO Level vs. RF Frequency, Single-Ended, Sine Wave LO Drive to Pin 4LOP or Pin 4LON Rev. F | Page 11 of 32 50M AD8333 Data Sheet 0 40 LO LEVEL = 0dBm BOTH CHANNELS 35 –20 LO LEAKAGE (dBm) OIP3 (dBm) 30 25 20 15 –40 –60 RF1P RF2P RF1N RF2N –80 –100 10 0 1M 10M –140 1M 50M RF FREQUENCY (Hz) 10M 50M RF FREQUENCY (Hz) Figure 26. Representative Range of OIP3 vs. RF Frequency, First Quadrant (see Figure 49) Figure 29. LO Leakage vs. RF Frequency at RF Inputs 35 16 30 14 –142.9 –144.1 NOISE (nV/ Hz) CHANNEL 1 RF CHANNEL 2 RF 20 15 12 –145.4 10 –147.0 8 –148.9 6 –151.4 4 –154.9 2 –161.0 NOISE (dBm) I1 Q1 25 OIP3 (dBm) 05543-028 –120 05543-025 5 05543-026 5 0 1k 10k 0 1M 100k 10M BASEBAND FREQUENCY (Hz) 05543-029 10 50M RF FREQUENCY (Hz) Figure 27. OIP3 vs. Baseband Frequency (see Figure 48) Figure 30. Input-Referred Noise vs. RF Frequency 0 20 LO LEVEL = 0dBm 18 –10 16 –40 NOISE FIGURE (dB) –30 I1 I2 Q1 Q2 –50 14 12 10 8 6 –60 –80 1M 10M 50M RF FREQUENCY (Hz) 05543-064 4 –70 05543-027 LO LEAKAGE (dBm) –20 2 0 1M 10M RF FREQUENCY (Hz) Figure 28. LO Leakage vs. RF Frequency at Baseband Outputs Figure 31. Noise Figure vs. RF Frequency with AD8332 LNA Rev. F | Page 12 of 32 50M Data Sheet 172 170 AD8333 I1 Q1 I1 + I2 Q1 + Q2 2V DYNAMIC RANGE (dB) 168 166 164 162 160 158 154 152 1M 10M 500mV 200ns 05543-046 05543-030 156 50M RF FREQUENCY (Hz) Figure 35. Reset Response—Top: Signal at RSET Pin, Bottom: Output Signal (see Figure 45) Figure 32. Dynamic Range vs. RF Frequency, IP1dB Minus Noise Level, Single Channel and Two Channels Summed 6 5V 4 GAIN = VBB/VRF 2 CODE 0000 CODE 0010 –2 –4 –10 –3.0 05543-044 –8 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1V 1V 40µs 05543-047 –6 1.0 VOLTAGE (V) Figure 33. Output Compliance Range (IxPO, QxPO) (see Figure 50) Figure 36. Phase Switching Response—Channel 2 Leads Channel 1 by 45°, Top: Input to PH21, Select Code = 0010; Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase Shifted 45°, Channel 1 Reference Phase Select Code = 0000 500mV 200ns Figure 34. Enable Response—Top: Enable Signal, Bottom: Output Signal (see Figure 44) 1V 1V 40µs 05543-048 2V 5V 05543-045 GAIN (dB) 0 Figure 37. Phase Shifting Response—Channel 2 Leads Channel 1 by 90°, Top: Input to PH21, Select Code = 0100; Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase Shifted 90°, Channel 1 Reference Phase Code = 0000 Rev. F | Page 13 of 32 AD8333 Data Sheet 60 40µs 50 VPOS 40 30 20 VNEG 10 0 –50 05543-051 1V 05543-049 1V QUIESCENT SUPPLY CURRENT (mA) 5V –30 –10 10 30 50 70 TEMPERATURE (°C) Figure 38. Phase Shifting Response—Channel 2 Leads Channel 1 by 180°, Top: Input to PH23 Select Code = 1000; Bottom (Red): Reference Channel 1 IOUT; Bottom (Gray): Channel 2 IOUT Phase Shifted 180°, Channel 1 Reference Phase Code = 0000 0 –10 –20 –40 –50 –60 –70 VNEG VPOS 05543-050 PSRR (dB) –30 –80 –90 100k 1M 10M 50M FREQUENCY (Hz) Figure 39. PSRR vs. Frequency (see Figure 51) Rev. F | Page 14 of 32 Figure 40. Quiescent Supply Current vs. Temperature 90 Data Sheet AD8333 TEST CIRCUITS AD8021 120nH 0.1µF FB 787Ω AD8332 LNA 20Ω RFxP LPF 2.2nF IxxO AD8333 50Ω 0.1µF 20Ω RFxN 2.2nF 4LOP SIGNAL GENERATOR OSCILLOSCOPE QxxO 787Ω 50Ω 05543-032 AD8021 SIGNAL GENERATOR Figure 41. Default Test Circuit AD8021 120nH 0.1µF FB 100Ω AD8332 LNA 20Ω RFxP LPF 10nF IxxO AD8333 50Ω 0.1µF 20Ω RFxN 10nF 4LOP SIGNAL GENERATOR OSCILLOSCOPE QxxO 100Ω 50Ω 05543-033 AD8021 SIGNAL GENERATOR Figure 42. P1dB Test Circuit AD8021 120nH 1µF FB AD8332 LNA 20Ω RFxP LPF 787Ω IxxO AD8333 50Ω 1µF 20Ω RFxN 787Ω QxxO OSCILLOSCOPE 4LOP SIGNAL GENERATOR 50Ω AD8021 05543-034 SIGNAL GENERATOR Figure 43. Phase and Amplitude vs. Baseband Frequency AD8021 AD8332 LNA 20Ω RFxP LPF 50Ω SIGNAL GENERATOR 787Ω IxxO AD8333 1µF 20Ω RFxN ENBL 50Ω SIGNAL GENERATOR 787Ω QxxO OSCILLOSCOPE 4LOP 50Ω AD8021 SIGNAL GENERATOR Figure 44. Enable Response Rev. F | Page 15 of 32 05543-035 120nH 1µF FB AD8333 Data Sheet AD8021 AD8332 LNA 20Ω RFxP LPF 787Ω IxxO AD8333 50Ω 1µF RFxN 20Ω 4LOP RST SIGNAL GENERATOR 50Ω OSCILLOSCOPE 787Ω QxxO 50Ω AD8021 SIGNAL GENERATOR SIGNAL GENERATOR 05543-036 120nH 1µF FB Figure 45. Reset Response 120nH FB 0.1µF AD8332 LNA 20Ω RFxP IxxO OSCILLOSCOPE LPF AD8333 50Ω 0.1µF 20Ω RFxN QxxO 4LOP SIGNAL GENERATOR 50Ω 50Ω 50Ω 05543-037 SIGNAL GENERATOR Figure 46. RF Input Range AD8021 6.98kΩ 270pF RFxP IxxO AD8333 0.1µF RFxN SPECTRUM ANALYZER 270pF QxxO 4LOP 6.98kΩ 50Ω SIGNAL GENERATOR 05543-052 AD8021 Figure 47. Noise Test Circuit AD8021 COMBINER AD8332 –6dB 120nH LNA 20Ω 0.1µF FB SIGNAL GENERATOR 787Ω RFxP 100pF IxxO AD8333 50Ω 0.1µF 20Ω RFxN 100pF SPECTRUM ANALYZER QxxO 4LOP SIGNAL GENERATOR 787Ω 50Ω SIGNAL GENERATOR Figure 48. OIP3 vs. Baseband Frequency Rev. F | Page 16 of 32 AD8021 05543-053 50Ω Data Sheet AD8333 AD8021 787Ω COMBINER AD8332 –6dB 120nH LNA 20Ω 0.1µF FB 50Ω 2.2nF RFxP SIGNAL GENERATOR IxxO AD8333 0.1µF 50Ω RFxN 20Ω SPECTRUM ANALYZER 2.2nF QxxO 4LOP SIGNAL GENERATOR 787Ω 50Ω SIGNAL GENERATOR 05543-054 AD8021 Figure 49. OIP3 and IM3 vs. RF Frequency AD8021 120nH 0.1µF FB 787Ω AD8332 LNA 20Ω RFxP LPF 2.2nF IxxO AD8333 50Ω 0.1µF RFxN 20Ω 2.2nF 4LOP SIGNAL GENERATOR OSCILLOSCOPE QxxO 787Ω 50Ω 05543-055 AD8021 SIGNAL GENERATOR Figure 50. Output Compliance Range AD8332 LNA 20Ω LPF 50Ω SIGNAL GENERATOR RFxP IxxO AD8333 0.1µF 20Ω RFxN NETWORK ANALYZER QxxO 4LOP 50Ω SIGNAL GENERATOR Figure 51. PSRR Test Circuit Rev. F | Page 17 of 32 05543-056 120nH 0.1µF FB AD8333 Data Sheet THEORY OF OPERATION The AD8333 is a dual I/Q demodulator with a programmable phase shifter for each channel. The primary applications are phased array beamforming in medical ultrasound, phased array radar, and smart antennae for mobile communications. The AD8333 can also be used in applications that require two wellmatched I/Q demodulators. PH11 PH10 VPOS RF1P RF1N VPOS ENBL I1NO Figure 52 shows the block diagram and pinout of the AD8333. Three analog and nine quasilogic level inputs are required. Two RF inputs accept signals from the RF sources and a local oscillator (applied to the differential input pins marked 4LOx) common to both channels constitute the analog inputs. Four logic inputs per channel define one of 16 delay states/360° (or 22.5°/step), selectable with PHx0 to PHx3. The reset input is used to synchronize AD8333 devices used in arrays. 32 31 30 29 28 27 26 25 BIAS PH13 2 COMM 3 CHANNEL 1 Φ SEL LOGIC 0° Φ AD8333 Φ BUF ÷4 23 Q1PO 22 Q1NO 21 VNEG Φ 20 COMM LODC 6 0° Φ 19 Q2NO 10 11 12 13 14 15 16 VPOS RF2P RF2N VPOS RSET I2NO PH21 9 PH20 CHANNEL 2 Φ SEL LOGIC 18 Q2PO 17 I2PO The minimum LO level is frequency dependent (see Figure 22). For optimum noise performance, it is important to ensure that the LO source has very low phase noise (jitter) and adequate input level to ensure stable mixer-core switching. The gain through the divider determines the LO signal level vs. RF frequency. The AD8333 can be operated to very low frequencies at the LO inputs if a square wave is used to drive the LO. Beamforming applications require a precise channel-to-channel phase relationship for coherence among multiple channels. A reset pin (RSET) is provided to synchronize the 4LOx divider circuits when AD8333 devices are used in arrays. The RSET pin resets the counters to a known state after power is applied to multiple AD8333 devices. A logic input must be provided to the RSET pin when using more than one AD8333. See the Reset Input section for more details. I/Q DEMODULATOR AND PHASE SHIFTER 90° 4LON 5 PH22 8 I1PO 90° 4LOP 4 PH23 7 24 05543-057 PH12 1 For optimum performance, the 4LOx inputs are driven differentially but can also be driven in a single-ended fashion. A good choice for a drive is an LVDS device. The common-mode range on each pin is approximately 0.2 V to 3.8 V with nominal ±5 V supplies. Figure 52. Block Diagram and Pinout Each of the current formatted I and Q outputs sum together for beamforming applications. Multiple channels are summed and converted to a voltage using a transimpedance amplifier. If desired, channels can also be used individually. QUADRATURE GENERATION The internal 0° and 90° LO phases are digitally generated by a divide-by-4 logic circuit. The divider is dc-coupled and inherently broadband; the maximum LO frequency is limited only by its switching speed. The duty cycle of the quadrature LO signals is intrinsically 50% and is unaffected by the asymmetry of the externally connected 4LOx inputs. Furthermore, the divider is implemented such that the 4LOx signals reclock the final flipflops that generate the internal LO signals and thereby minimizes noise introduced by the divide circuitry. The I/Q demodulators consist of double-balanced Gilbert cell mixers. The RF input signals are converted into currents by transconductance stages that have a maximum differential input signal capability of 2.8 V p-p. These currents are then presented to the mixers, which convert them to baseband: RF − LO and RF + LO. The signals are phase shifted according to the code applied to Pin PHx0 to Pin PHx3 (see Table 4). The phase shift function is an integral part of the overall circuit (patent pending). The phase shift listed in Column 1 of Table 4 is defined as being between the baseband I or Q channel outputs. As an example, for a common signal applied to the RF inputs of an AD8333, the baseband outputs are in phase for matching phase codes. However, if the phase code for Channel 1 is 0000 and that of Channel 2 is 0001, Channel 2 leads Channel 1 by 22.5°. Following the phase shift circuitry, the differential current signal is converted from differential to single ended via a current mirror. An external transimpedance amplifier is needed to convert the I and Q outputs to voltages. Rev. F | Page 18 of 32 Data Sheet AD8333 Judicious selection of the RF amplifier ensures the least degradation in dynamic range. The input-referred spectral voltage noise density (en) of the AD8333 is nominally 9 nV/√Hz to 10 nV/√Hz. For the noise of the AD8333 to degrade the system noise figure (NF) by 1 dB, the combined noise of the source and the LNA must be about twice that of the AD8333, or 18 nV/√Hz. If the noise of the circuitry before the AD8333 is <18 nV/√Hz, the system NF degrades more than 1 dB. For example, if the noise contribution of the LNA and source is equal to the AD8333, or 9 nV/√Hz, the degradation is 3 dB. If the circuit noise preceding the AD8333 is 1.3× as large as that of the AD8333 (or about 11.7 nV/√Hz), the degradation is 2 dB. For a circuit noise of 1.45× that of the AD8333 (13.1 nV/√Hz), the degradation is 1.5 dB. Table 4. Phase Nibble Select Codes φ Shift 0° 22.5° 45° 67.5° 90° 112.5° 135° 157.5° 180° 202.5° 225° 247.5° 270° 292.5° 315° 337.5° PHx3 PHx2 PHx1 PHx0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 To determine the input-referred noise, it is important to know the active low-pass filter (LPF) values RFILT and CFILT, shown in Figure 53. Typical filter values (for example, those used on the evaluation board) are 787 Ω and 2.2 nF and implement a 90 kHz single-pole LPF. If the RF and LO are offset by 10 kHz, the demodulated signal is 10 kHz and is passed by the LPF. The single-channel mixing gain from the RF input to the AD8021 output (for example, ΣI, ΣQ) is approximately 1.7 × 4.7 dB. This together with the 9 nV/√Hz AD8333 noise results in about 15.3 nV/√Hz at the AD8021 output. Because the AD8021, including the 787 Ω feedback resistor, contributes another 4.4 nV/√Hz, the total output-referred noise is about 16 nV/√Hz. This value can be adjusted by increasing the filter resistor while maintaining the corner frequency, thereby increasing the gain. The factor limiting the magnitude of the gain is the output swing and drive capability of the operational amplifier selected for the I-to-V converter, in this instance the AD8021. DYNAMIC RANGE AND NOISE Figure 53 is an interconnection block diagram of the AD8333. For optimum system noise performance, the RF input signal is provided by a very low noise amplifier, such as the LNA of an AD8332 or the preamplifier of an AD8335. In beamformer applications, the I and Q outputs of a number of receiver channels are summed (for example, the two channels illustrated in Figure 53). The dynamic range of the system increases by the factor 10 log10(N), where N is the number of channels (assuming random uncorrelated noise). The noise in the two-channel example of Figure 53 is increased by 3 dB while the signal doubles (6 dB), yielding an aggregate SNR improvement of (6 dB − 3 dB) = 3 dB. RFB TRANSMITTER T/R SW AD8332 LNA OR AD8335 PREAMP TRANSDUCER CHANNEL 1 PHASE SELECT CH1 RF AD8333 0° 2 4 2 Φ CFILT 2 I1 2 Q1 AD8021 2 Q2 CFILT 2 I2 * 2 90° CLOCK GENERATOR Φ ΣI 2 Φ * 2 0° 2 CH2 RF TRANSMITTER T/R SW ΣQ ADC 16-BIT 570kSPS Q DATA AD8021 4 CHANNEL 2 PHASE SELECT *UP TO EIGHT CHANNELS PER AD8021 05543-038 AD8332 LNA OR AD8335 PREAMP Φ RFILT ADC 16-BIT I DATA 570kSPS AD7665 OR AD7686 ÷4 90° TRANSDUCER RFILT RFB Figure 53. Interconnection Block Diagram Rev. F | Page 19 of 32 AD8333 Data Sheet Beamforming, as applied to medical ultrasound, is defined as the phase alignment and summation of signals generated from a common source but received at different times by a multielement ultrasound transducer. Beamforming has two functions: it imparts directivity to the transducer, enhancing its gain, and it defines a focal point within the body from which the location of the returning echo is derived. The primary application for the AD8333 is in analog beamforming circuits for ultrasound. PHASE COMPENSATION AND ANALOG BEAMFORMING Modern ultrasound machines used for medical applications employ a 2n binary array of receivers for beamforming, with typical array sizes of 16 or 32 receiver channels phase-shifted and summed together to extract coherent information. When used in multiples, the desired signals from each of the channels can be summed to yield a larger signal (increased by a factor N, where N is the number of channels), while the noise is increased by the square root of the number of channels. This technique enhances the signal-to-noise performance of the machine. The critical elements in a beamformer design are the means to align the incoming signals in the time domain and the means to sum the individual signals into a composite whole. In traditional analog beamformers incorporating Doppler, a V-to-I converter per channel and a crosspoint switch precede passive delay lines used as a combined phase shifter and summing circuit. The system operates at the receive frequency (RF) through the delay line, and then the signal is down-converted by a very large dynamic range I/Q demodulator. The resultant I and Q signals are filtered and sampled by two high resolution ADCs. The sampled signals are processed to extract the relevant Doppler information. Alternatively, the RF signal can be processed by downconversion on each channel individually, phase shifting the downconverted signal and then combining all channels. The AD8333 provides the means to implement this architecture. The downconversion is done by an I/Q demodulator on each channel, and the summed current output is the same as in the delay line approach. The subsequent filters after the I-to-V conversion and the ADCs are similar. The AD8333 integrates the phase shifter, frequency conversion, and I/Q demodulation into a single package and directly yields the baseband signal. To illustrate this, Figure 54 is a simplified diagram showing two channels. The ultrasound wave (USW) is received by two transducer elements, TE1 and TE2, in an ultrasound probe and generates the E1 and E2 signals. In this example, the phase at TE1 leads the phase at TE2 by 45°. TRANSDUCER ELEMENTS TE1 AND TE2 CONVERT USW TO ELECTRICAL AD8332 USW AT TE1 SIGNALS LEADS USW ES1 LEADS AT TE2 BY ES2 BY 45° 19dB 45° 45° LNA AD8333 PHASE BIT SETTINGS CH 1 REF (NO PHASE LEAD) E1 E2 S1 AND S2 ARE NOW IN PHASE SUMMED OUTPUT S1 + S2 S1 19dB LNA CH 2 PHASE LEAD 45° S2 05543-063 SUMMATION OF MULTIPLE CHANNELS (ANALOG BEAMFORMING) Figure 54. Simplified Example of the AD8333 Phase Shifter In a real application, the phase difference depends on the element spacing, λ (wavelength), speed of sound, angle of incidence, and other factors. The ES1 and ES2 signals are amplified 19 dB by the low noise amplifiers in the AD8332. For optimum signal-tonoise performance, the output of the LNA is applied directly to the input of the AD8333. To sum the ES1 and ES2 signals, ES2 is shifted 45° relative to ES1 by setting the phase code in Channel 2 to 0010. The phase-aligned current signals at the output of the AD8333 are summed in an I-to-V converter to provide the combined output signal with a theoretical improvement in dynamic range of 3 dB for the sum of two channels. Rev. F | Page 20 of 32 Data Sheet AD8333 When determining the large signal requirements of the firstorder summing amplifiers and low-pass filters, the very small CW signal can be ignored. The number of channels that can be summed is limited by the output drive current capacity of the operational amplifier selected: 60 mA to 70 mA for a linear output current for ±5 V and ±12 V, respectively, for the AD8021. Because the AD8021 implements an active LPF together with R1x and C1x, it must absorb the worst-case current provided by the AD8333, for example, 6.6 mA. Therefore, the maximum number of channels that the AD8021 can sum is 10 for ±12 V or eight for ±5 V supplies. In practical applications, CW channels are used in powers of two, thus the maximum number per AD8021 is eight. CHANNEL SUMMING In a beamformer using the AD8333, the bipolar currents at the I and Q outputs are summed directly. Figure 55 illustrates 16 summed channels (for clarity, these channels are shown as current sources) as an example of an active current summing circuit using the AD8333. This figure also illustrates the AD8021 as first-order current summing circuits and AD797 devices as low noise second-order summing circuits. Beginning with the operational amplifiers, there are a few important considerations in the circuit shown in Figure 55. The operational amplifiers selected for the first-order summing amplifiers must have good frequency response over the full operating frequency range of the AD8333 devices and be able to source the current required at the AD8333 I and Q outputs. Another consideration for the operational amplifier selected as an I-to-V converter is the compliance voltage of the AD8333 I and Q outputs. The maximum compliance voltage is 0.5 V, and a dc bias must be provided at these pins. The AD8021 active LPF satisfies these requirements; it keeps the outputs at 0 V via the virtual ground at the operational amplifier inverting input while providing any needed dc bias current. The total current of each AD8333 is 6.6 mA for the multiples of the 45° phase settings (Code 0010, Code 0110, Code 1010, and Code 1110) and is divided nearly equally between the baseband frequencies (including a dc component) and the second harmonic of the local oscillator frequency. The desired CW signal tends to be much less (<40 dB) than the unwanted interfering signals. FIRST-ORDER SUMMING AMPLIFIERS C1A 18nF EIGHT AD8333 I OR Q OUTPUTS, 6.6mA PEAK EACH (IF THE PHASE SETTING IS 45°) 3.3mA AT DC + 3.3mA AT 2 × LO R1A 100Ω LPF1A 88kHz +2.8V BASEBAND SIGNAL +5V 2 – 0.1µF ΣA 3 + AD8021 HPF1A 100Hz C2A R2A 1µF 698Ω –5V LPF2A 81kHz R3A 698Ω C3A 5.6nF SECOND-ORDER SUMMING AMPLIFIER 0.1µF R4 +10V 2 C1B 18nF 3 R1B 100Ω – 0.1µF ΣB 3 + AD8021 + –10V +5V 2 AD797 C2B R2B 1µF 698Ω –5V 0.1µF Figure 55. A 16-Channel Beamformer Rev. F | Page 21 of 32 0.1µF R3B 698Ω C3B 5.6nF 05543-058 (SAME AS ABOVE) – 0.1µF AD8333 Data Sheet As previously noted, a typical CW signal has a large dc and very low frequency component compared with its desired low CW Doppler baseband frequency, and another unwanted component at the 2 × LO. The dc component flows through the gain resistors R1x, and the 2 × LO flows through the capacitors C1x. The smaller desired CW Doppler baseband signal is in the frequency range of 1 kHz to 50 kHz. Because the output current of the AD8333 contains the baseband frequency, a dc component, and the 2 × LO frequency voltages, the desired small amplitude baseband signal must be extracted after a series of filters. These are shown in Figure 55 as LPFnA, HPFnA, and gain stages. Before establishing the value of CLPF1, the resistor RLPF1 is selected based on the peak operating current and the linear range of the operational amplifier. Because the peak current for each AD8333 is 6.6 mA and there are eight channels to be summed, the total peak current required is 52.8 mA. Approximately half of this current is dc, and the other half is at a frequency of 2 × LO. Therefore, about 26.4 mA flows through the resistor, and the remaining 26.4 mA flows through the capacitor. R1 was selected as 100 Ω and, after filtering, generates a peak dc and very low frequency voltage of 2.64 V at the AD8021 output. For power supplies of ±5 V, 100 Ω is a good choice for R1. However, because the CW signal needs to be amplified as much as possible and the noise degradation of the signal path minimized, the value of R1 must be as large as possible. A larger supply helps in this regard, and the only factor limiting the largest supply voltage is the required power. For a ±10 V supply on the AD8021, R1 can be increased to 301 Ω to realize the same headroom as with a ±5 V supply. If a higher value of R1 is used, C1 must be adjusted accordingly (in this example, 1/3 the value of the original value) to maintain the desired LPF roll-off. The principal advantage of a higher supply is greater dynamic range, and the trade-off is power consumption. The user must weigh the trade-offs associated with the supply voltage, R1, C1, and the following circuitry. A suggested design sequence is as follows: Select a low noise, high speed operational amplifier. The spectral density noise (en) must be <2 nV/√Hz, and the 3 dB bandwidth must be ≥3× the expected maximum 2 × LO frequency. Divide the maximum linear output current by 6.6 mA to determine the maximum number of AD8333 channels that can be summed. Select the largest value of R1 that permits the output voltage swing within the power supply rails. Calculate the value of C1 to implement the LPF corner that allows the CW Doppler signal to pass with maximum attenuation of the 2 × LO signal. The filter LPF1A establishes the upper frequency limit of the baseband frequency and is selected well below the 2 × LO frequency, typically 100 kHz or less (for example, 88 kHz in Figure 55). A useful equation for calculating C1 is C1 = 1 2πR1f LPF1 (1) As previously mentioned, the AD8333 output current contains a dc current component. This dc component is converted to a large dc voltage by the AD8021 LPF. Capacitor C2 filters this dc component and, with R2 + R3, establishes a high-pass filter with a low frequency cutoff of about 100 Hz. Capacitor C3 is much smaller than C2 and, consequently, can be neglected. C2 can be calculated by C2 = 1 2π(R2 + R3) f HPF1 (2) To achieve maximum attenuation of the 2 × LO frequency, a second low-pass filter, LPF2, is established using the parallel combination of R2 and R3, and C3. Its −3 dB frequency is f LPF 2 = 1 2π(R2 || R3)C 3 (3) In the example shown in Figure 55, fLPF2 = 81 kHz. Finally, the feedback resistor of the AD797 must be calculated. This is a function of the input current (number of channels) and the supply voltage. The second-order summing amplifier requires a very low noise operational amplifier, such as the AD797, with 0.9 nV/√Hz, because the amplifier gain is determined by Feedback Resistor R4 divided by the parallel combination of the LPF2A resistors seen looking back toward the AD8021 devices. Referring to Figure 55, the AD797 in-band (100 Hz to 88 kHz) gain is expressed as R4 [(R2A + R3A) || (R2B + R2B)] (4) The AD797 noise gain can increase to unacceptable levels because the denominator of the gain equation is the parallel resistance of all the R2 + R3 resistors in the AD8021 outputs. For example, for a 64-channel beamformer, the resistance seen looking back toward the AD8021 devices is about 1.4 kΩ/8 = 175 Ω. For this reason, the value of (R2x + R3x) must be as large as possible to minimize the noise gain of the AD797. (Note that this is the case for the AD8021 stages because they look back into the high impedance current sources of the AD8333 devices.) Due to these considerations, it is advantageous to increase the gain of the AD8021 devices as much as possible because the value of (R2x + R3x) can be increased proportionally. Resistors (R2x + R3x) convert the CW voltages to currents that are summed at the inverting inputs of the AD797 operational amplifier, and then amplified and converted to voltages by R4. Rev. F | Page 22 of 32 Data Sheet AD8333 1. 2. 3. 4. 5. 6. 7. Determine the number of AD8021 first-order summing amplifiers. In Figure 55, there are two; for a 32-channel beamformer, there must be four, and for a 64-channel beamformer, there must be eight. Determine the output noise from the AD8021 devices. A first-order calculation can be based on a value of AD8333 output current noise of about 20 pA/√Hz. For the values in Figure 55, this results in about 6 nV/√Hz for eight channels after the AD8021 devices. Adding the noise of the AD8021 and the 100 Ω feedback resistor results in about 6.5 nV/√Hz total noise after the AD8021 LPF in the CW Doppler band. Determine the noise of the circuitry after the AD797 and determine the desired signal level. Determine the voltage and current noise of the secondorder summing amplifiers. Choose a value for (R2x + R3x) and for R4. Determine the resulting output noise after the AD797 for one channel, and then multiply this value by the square root of the number of summed AD8021 devices. Next, check AD797 output noise (both current and voltage noise). Ideally, the sum of the noise of the resistors and the AD797 must be less than a factor of 3 than the noise due to the AD8021 outputs. Check the following stages output noise against the calculated noise from the combiner circuit and AD8333 devices. Ideally, the noise from the following stage must be less than 1/3 of the calculated noise. If the combined noise is too large, experiment with increasing/decreasing values for (R2x + R3x) and R4. The summed signal level increases by a factor of N, whereas the noise increases only as √N. In the case of 64 channels, this is an increase in dynamic range of 18 dB. Note that the AD8333 dynamic range is already about 160 dB/Hz; the summed dynamic range is 178 dB/Hz (equivalent to about 29.5 bits/Hz). In a 50 kHz noise bandwidth, this is 131 dB (21.7 bits). DISABLING THE CURRENT MIRROR AND DECREASING NOISE The noise contribution of the AD8333 can potentially be reduced if the current mirrors that convert the internal differential signals to single-ended signals are bypassed (see Figure 56). Current mirrors interface to the AD8021 I-V converters shown in Figure 53, and output capacitors across the positive and negative outputs provide low-pass filtering. The AD8021 devices force the AD8333 output voltage to 0 V and then process the bipolar output current; however, the internal current mirrors introduce a significant amount of noise. This noise can be reduced if the mirrors are disabled and the outputs are externally biased. The mirrors are disabled by connecting VNEG to ground and providing external bias networks, as shown in Figure 56. The larger the drop across the resistors, the less noise they contribute to the output; however, the voltage on the I and Q output nodes cannot exceed 0.5 V. Voltages exceeding approximately 0.7 V turn on the PNP devices and forward bias the ESD protection diodes. Inductors provide an alternative to resistors, enabling reduced static power by eliminating the power dissipation in the bias resistors. COMM To simplify, the user can also simulate or build a combiner circuit for optimum performance. It must be noted that the ~20 pA/√Hz output from the AD8333 is for the AD8333 with shorted RF inputs. In an actual system, the current noise output from the AD8333 is most likely dominated by the noise from the AD8332 LNA and the noise from the source and other circuitry before the LNA. This helps ease the design of the combiner. The preceding procedures for determining the optimum values for the combiner are based on the noise floor of the AD8333 only. As an example, for a 32-channel beamformer using four lowpass filters, as shown in Figure 55, (R2x + R3x) = 1.4 kΩ and R4 = 6.19 kΩ. The theoretical noise increase of √N is degraded by only about 1 dB. DYNAMIC RANGE INFLATION Although all 64 channels can theoretically be summed together at a single amplifier, it is important to realize that the dynamic range of the summed output increases by 10 log10(N) if all channels have uncorrelated noise, where N is the number of channels to be summed. IxNO QxNO OTHER CHANNELS I-V I-V IxPO QxPO VNEG1 1NOTE THAT PIN VNEG AND PIN COMM ARE CONNECTED TOGETHER. 05543-039 The value of R4 needs to be chosen iteratively as follows: Figure 56. Bypassing the Internal Current Mirrors With inductors, the main limitation might be low frequency operation, as is the case in CW Doppler in ultrasound where the frequency range of interest goes from a few hundred hertz to about 30 kHz. In addition, it is still important to provide enough gain through the I-to-V circuitry to ensure that the bias resistor and I-to-V converter noise do not contribute significantly to the noise from the AD8333 outputs. Another approach is to provide a single external current mirror that combines all channels; it is also possible to implement a high-pass filter with this circuit to help with offset and low frequency reduction. Rev. F | Page 23 of 32 AD8333 Data Sheet The main disadvantage of the external bias approach is that two I-V amplifiers are needed because of the differential output (see Figure 56). For beamforming applications, the outputs are still summed, but there is twice the number of lines. Only two bias resistors are needed for all outputs that are connected together. The resistors are scaled by dividing the value of a single output bias resistor through N, the number of channels connected in parallel. The bias current depends on the phase selected: for phase 0°, it is about 2.5 mA per side, whereas in the case of 45°, it is about 3.5 mA per side. The bias resistors must be chosen based on the larger bias current value of 3.5 mA and the chosen VNEG. VNEG must be at least −5 V and can be larger for additional noise reduction. Excessive noise or distortion at high signal levels degrades the dynamic range of the signal. Transmitter leakage and echoes from slow moving tissue generate the largest signal amplitudes in ultrasound CW Doppler mode and are largest near dc and at low frequencies. A high-pass filter introduced immediately following the AD8333 reduces the dynamic range. This is shown by the two coupling capacitors after the external bias resistors in Figure 56. Users have to determine what is acceptable for a particular application. Care must be taken in designing the external circuitry to avoid introducing noise via the external bias and low frequency reduction circuitry. Rev. F | Page 24 of 32 Data Sheet AD8333 APPLICATIONS INFORMATION The AD8333 is the key component of a phase-shifter system that aligns time-skewed information contained in RF signals. Combined with a variable gain amplifier (VGA) and low noise amplifier (LNA), the AD8333 forms a complete analog receiver for a high performance ultrasound system. Figure 57 is a block diagram of a complete receiver using the AD8333, AD8331, AD8332, and AD8334. AD8332 I1 Q1 LNA2 FROM TRANSDUCER T/R SWITCH AD8333 16-BIT ADC 4 × LO PROCESSOR RSET I2 Q2 16-BIT ADC PROCESSOR HS ADC PROCESSOR tPW-MIN tHOLD THE TIMING OF THE RISING EDGE OF RSET IS NOT CRITICAL AS LONG AS THE tPW-MIN IS SATISFIED 05543-060 LNA1 FROM TRANSDUCER T/R SWITCH The rising edge of the active high RSET pulse can occur at any time, but the duration must be ≥300 ns minimum (tPW-MIN). When the RSET pulse transitions from high to low, the LO dividers are reactivated; however, there is a short delay until the divider recovers to a valid state. To guarantee synchronous operation of an array of AD8333 devices, the 4 × LO clock must be disabled when the RSET transitions high, and then remain disabled for at least 300 ns after RSET transitions low. PROCESSOR Figure 57. Block Diagram—Ultrasound Receiver Using the AD8333 and AD8332 LNA As a major element of an ultrasound system, it is important to consider the many input/output options of the AD8333 that are necessary to perform its intended function. Figure 61 shows the basic connections. LOGIC INPUTS AND INTERFACES The logic inputs of the AD8333 are all bipolar-level sensitive inputs. They are not edge triggered, nor are they to be confused with classic TTL or other logic family input topologies. The voltage threshold for these inputs is VPOS × 0.3, so for a 5 V supply the threshold is 1.5 V, with a hysteresis of ±0.2 V. Although the inputs are not of themselves logic inputs, any 5 V logic family can drive them. Figure 58. Timing of the RSET Signal to 4 × LO Synchronization of multiple AD8333 devices can be checked as follows: 1. 2. 3. Set the phase code of all AD8333 channels to the same setting, for example, 0000. Apply a test signal to a single channel that generates a sine wave in the baseband output, and then measure the output. Apply the same test signal to all channels simultaneously, and then measure the output. Because all the phase codes of the AD8333 devices are the same, the combined signal must be N times bigger than the single channel. The combined signal is less than N times one channel if any of the LO phases of individual AD8333 devices are in error. CONNECTING TO THE LNA OF THE AD8331/AD8332/AD8334/AD8335 VGAs +5V RESET INPUT The RSET pin is used to synchronize the LO dividers in AD8333 arrays. Because they are driven by the same internal LO, the two channels in any AD8333 are inherently synchronous. However, when multiple AD8333 devices are used, it is possible that their dividers wake up in different phase states. The function of the RSET pin is to phase align all the LO signals in multiple AD8333 devices. The 4 × LO divider of each AD8333 can initiate in one of four possible states: 0°, 90°, 180°, or 270°. The internally generated I/Q signals of each AD8333 LO are always at a 90° angle relative to each other, but a phase shift can occur during power-up between the internal LOs of the different AD8333 devices. RFxP AD8332 LNA AD8333 RFxN –5V 05543-061 HS ADC 05543-059 tHOLD = HOLD TIME tPW-MIN = MINIMUM PULSE WIDTH Figure 59. Connecting the AD8333 to the LNA of an AD8332 The RFxx inputs (Pin 12, Pin 13, Pin 28, and Pin 29) are optimized for maximum dynamic range when dc-coupled to the differential output pins of the LNA of the AD8331/AD8332/ AD8334 or the AD8335 series of VGAs and can be connected directly, as shown in Figure 59. The RSET pin provides an asynchronous reset of the LO dividers by forcing the internal LO to hang. This mechanism also allows the measurement of nonmixing gain from the RF input to the output. Rev. F | Page 25 of 32 AD8333 Data Sheet To realize the full range of performance, the AD8333 must be driven from a differential source. Using a single-ended source is strongly discouraged because of internal supply headroom constraints. INTERFACING TO OTHER AMPLIFIERS If amplifiers other than the AD8332 LNA are connected to the input, attention must be paid to their bias and drive levels. For maximum input signal swing, the optimum bias level is 2.5 V, and the RF input must not exceed 5 V to avoid turning on the ESD protection circuitry. If ac coupling is used, a bias circuit, such as that illustrated in Figure 60, is recommended. An internal bias network is provided; however, additional external biasing can center the RF input at 2.5 V. LO INPUT The LO input is a high speed, fully differential analog input that responds to differences in the input levels, not in the logic levels. The LO inputs can be driven with a low common-mode voltage amplifier, such as the National Semiconductor DS90C401 LVDS driver. +5V Figure 22 and Figure 23 show the range of common-mode voltages and useable LO levels when the LO input is driven with a singleended sine wave. Logic families, such as TTL or CMOS, are unsuitable for direct coupling to the LO input. 5.23kΩ 1.4kΩ AD8333 0.1µF RFxP RF IN 0.1µF RFxN 3.74kΩ 05543-062 1.4kΩ –5V Figure 60. AC Coupling the AD8333 RF Input VPOS 120nH FB CHANNEL 1 – RF IN + +5V CHANNEL 1 PHASE SELECT BITS 0.1µF 4 0.1µF 5 – 31.6kΩ 31.6kΩ 0.1µF 6 7 8 CHANNEL 2 PHASE SELECT BITS 25 ENBL VPOS RF1P RF1N PH10 26 I1NO I1PO PH13 Q1PO COMM Q1NO 4LOP VNEG AD8333 4LON COMM LODC Q2NO PH23 Q2PO PH22 PH21 9 10 11 12 13 14 RSET 0.1µF 27 VPOS + 3 28 RF2N LOCAL OSCILLATOR 33.2kΩ 29 RF2P 33.2kΩ 2 30 VPOS * PH11 PH12 PH20 1 +5V 31 VPOS 32 15 I2PO I2NO 24 23 22 CHANNEL 1 + I OUT CHANNEL 1 + Q OUT 120nH FB 21 –5V 20 0.1µF 19 18 17 CHANNEL 2 + Q OUT CHANNEL 2 + I OUT 16 + CHANNEL 2 – RF IN 0.1µF VPOS *OPTIONAL BIAS NETWORK. THESE COMPONENTS CAN BE DELETED IF THE LO IS DC-COUPLED FROM AN LVDS SOURCE BIASED AT 1.2V. Figure 61. AD8333 Basic Connections Rev. F | Page 26 of 32 05543-040 RESET INPUT Data Sheet AD8333 EVALUATION BOARD The AD8333-EVALZ evaluation board provides a platform for test and evaluation of the AD8333 I/Q demodulator and phase shifter. The board is shipped fully assembled and tested and is signal ready. A pair of AD8332 low-noise amplifiers (LNA) provide input matching and amplification for the differential input of the AD8333. A photograph of the board is shown in Figure 62 and a schematic diagram is shown in Figure 64. The board requires dual 5 V supplies capable of supplying 300 mA or greater. Except for the optional components shown in grayscale, the board is completely built and tested. Phase Nibble The phase nibble configures the phase delay for each channel in sixteen 22.5° increments from 0° to 337.5°. The increments increase proportionally in a simple binary format from 0H (hexadecimal) to FH. Table 4 lists the phase shift and corresponding code for each bit. The bits are labeled 0 and 1, corresponding to low and high, respectively, on the silkscreen. The switches select the desired state. Enable and Reset Switches For normal operation, place a switch in the upper position of ENBL. To disable the AD8333, move the switch to the lower position. For normal operation, the switch for RST is in its right position. When the switch is in the left position, the device counter is held in reset and no mixing occurs. Fixed Options Several options can be realized by adding or changing resistors. LNA Input Impedance 05543-067 The shipping configuration of the input impedance of the LNA is 50 Ω to match the output impedance of most signal generators. Input impedances up to 6 kΩ are obtained by selecting the R9 and R10 values. Details concerning this circuit feature are found in the AD8332 data sheet. For reference, Table 6 lists common values of input impedance and corresponding feedback resistor values. Table 6. LNA External Component Values for Typical Values of Source Impedance Figure 62. Evaluation Board (Actual Size) FEATURES AND OPTIONS The evaluation board has several user-configurable features and options. Table 5 lists the configuration switches and their functions. Table 5. Switch Functions Switch ENBL PH10 PH11 PH12 PH13 PH20 PH21 PH22 PH23 RST Function Enable or disable the AD8333 Channel 1 Phase Bit 0 (LSB) Channel 1 Phase Bit 1 Channel 1 Phase Bit 2 Channel 1 Phase Bit 3 (MSB) Channel 2 Phase Bit 0 (LSB) Channel 2 Phase Bit 1 Channel 2 Phase Bit 2 Channel 2 Phase Bit 3 (MSB) Reset Configuration Bottom = disable; top = enable Top = 0; bottom = 1 Top = 0; bottom = 1 Top = 0; bottom = 1 Top = 0; bottom = 1 Top = 1; bottom = 0 Top = 1; bottom = 0 Top = 1; bottom = 0 Top = 1; bottom = 0 RIN (Ω) 50 75 100 200 500 6k RFB, Nearest STD 1% Value (Ω) 280 412 562 1.13 k 3.01 k ∞ CSH (pF) 22 12 8 1.2 None None Current Summing The output transimpedance amplifiers, A1 through A4, are configured as I-to-V converters to convert the output current of the AD8333 to a voltage. The low-pass filters formed by the feedback components are designed for single-channel operation with ±5 V supplies. Optional Resistors R4 and R5 sum the two channels. With R4 and R5 installed, R2 and R3 are removed, and then the sum of the outputs is seen at the I1xO and Q1xO output SMA connectors. The user has the option to adjust the values of R39, R40, R41, or R42 according to the power supply voltages and expected input current levels. For the same supply voltages, if two channels are summed together, the feedback resistors are halved and the filter capacitor values doubled to optimize the output swing. Left = run; right = reset Rev. F | Page 27 of 32 AD8333 Data Sheet Filter Capacitors C26, C29, C31, and C 32 establish the roll-off characteristic according to the following well-known equation: f 1 RC where R is the value of R39, R40, R41, or R42, and C is the value of C26, C29, C31, or C32. Reset Input For normal operation, the reset input is high (no reset). To drive the reset with a dynamic signal, a provision is made to connect a signal generator at the RST input. A 49.9 Ω, 0603 surface-mount resistor can be installed at R15 to terminate the reset input for pulsed experiments. In this configuration, the switch at RST is not used and must be removed to avoid loading the power supply. MEASUREMENT SETUP Take care to avoid overdriving the LNA input of the AD8332. The LNA gain is 19 dB (9.5×) and the maximum output swing must not be exceeded; −10 dBm suffices for many experiments. The f4LO input is ac-coupled to a 5 V LVDS buffer to provide an ideal interface to the AD8333. The f4LO level is frequency dependent; refer to Figure 22 for minimum signal levels, and then adjust the generator output level accordingly. 05543-066 Figure 63 is a layout of the AD8333-EVALZ showing the connectors and switches. Figure 65 shows a typical board and test equipment setup with two signal generators, a power splitter, and a ±5 V, 300 mA (minimum) power supply. For ease in observing waveforms, the signal generators can be synchronized. Remember that the f4LO signal generator frequency is four times that of the nominal frequency of the RF source. For example, to detect signals with a nominal center frequency of 5 MHz, an f4LO frequency of 20 MHz is applied to the oscillator input. For an applied RF signal of 5.01 MHz, the mix frequencies are 10 kHz and 10.01 MHz. Because of the lowpass active filter of the transconductance amplifiers (A1 through A4), the 10.01 MHz component is suppressed, and only the 10 kHz is observed at the output. G Figure 63. Evaluation Board Assembly Rev. F | Page 28 of 32 Rev. F | Page 29 of 32 Figure 64. Evaluation Board Schematic IN2 L2 120 NH FB IN1 L1 120 NH FB TP1 1 R10 274Ω VPS LOP1 LMD2 LMD1 INH1 VPS1 LON1 31 LOP2 9 10 8 LON2 7 VPS2 6 INH2 5 4 3 VPS 2 C5 0.1 µF C40 .018 µF C3 22 PF C4 TP2 0.1 µF C6 0.1 µF C2 22 PF TP3 C1 TP4 0.1 µF 32 COM1 COM 2 C39 .018 µF 30 VIP1 11 VIP2 29 28 C14 0.1 µF Z1 13 26 5 1 6 7 R23 20Ω R22 20Ω 3 LOP 4 R1 100Ω C43 1 NF 2 C17 0.1µF R13 49.9Ω R7 1.5KΩ 8 7 6 5 4 2 3 +5V 1 L5 120 NH FB C9 0.1 µF Z3 DS90C401 R6 3.48KΩ RCLMP 15 16 C13 0.1 µF COMM 17 VOH2 18 VOL2 19 NC 20 VOH1 23 VPS C42 VOL1 22 0.1 µF VPSV 21 COMM 24 ENBV 25 VPS +5V C12 0.1 µF Z3 SPARE 8 C11 0.1 µF 12 14 AD8332 27 HILO MODE R9 274Ω ENBL GAIN R25 20Ω H H H H 9 10 30 H 11 28 C7 10µF 10V DUT 13 + H 26 C24 0.1µF 27 C8 10µF 10V 23 24 TP8 TP7 RST R15 OPT C51 0.1µF +5VS I2NO R2 0Ω 14 15 16 VPOS H +5V RST +5VS C41 0.1µF L +5VS + 3 4 +5VS 5 6 C26 2.2NF R39 787Ω + 3 4 C33 5PF C52 0.1µF 5 6 C32 2.2NF R42 787Ω -5VS C31 2.2NF 2 7 1 A4 8 AD8021 C50 0.1µF C48 0.1µF R41 787Ω A3 6 8 AD8021 5 C30 3 + 4 5PF 2 7 1 C49 0.1µF C36 0.1µF R5 OPT +5VS 5 C28 5PF 6 C29 2.2NF R40 787Ω -5VS I1 -5VS R38 0Ω I2 R35 0Ω Q2 -5V R33 0Ω Q1 -5VS C47 0.1µF L4 120NHFB 2 7 1 A2 8 AD8021 + 3 4 R32 0Ω L7 C27 5PF 120NHFB -5V C45 0.1µF 2 7 1 A1 8 AD8021 C46 0.1µF 22 R4 Q1NO OPT 21 VNEG 20 COMM 19 Q2NO 18 Q2PO R3 17 I2PO 0Ω Q1PO I1PO I1NO 25 ENBL +5VS C44 0.1µF L6 +5VS 120NH FB -5V L3 120NH FB TP5 TP6 AD8333 12 PH23 +5V PH22 L H PH21 L H 29 VPOS PH20 L H L PH22 PH21 PH23 LODC 4LON 4LOP COMM PH13 PH12 32 31 PH11 L PH10 L PH11 L PH12 L PH13 VPOS VPOS R26 20Ω PH10 PH20 + RF2P +5V RFIN RF2N VIN1 VIN2 RFIP -5V VPOS VCM1 VCM 2 VPOS +5V ENBL RSET GND1 GND2 GND3 GND4 Data Sheet AD8333 EVALUATION BOARD SCHEMATIC AND ARTWORK 05543-042 AD8333 Data Sheet TOP GENERATOR: SIGNAL GENERATOR FOR f4LO INPUT, TYPICAL SETTING: 20MHz SIGNAL 1V p-p BOTTOM GENERATOR: SIGNAL GENERATOR FOR RF INPUT, TYPICAL SETTING: 5.01MHz POWER SUPPLY +5V –5V POWER SPLITTER 05543-065 SIGNAL INPUT(S) Figure 65. Typical Board Test Connections (One Channel Shown) Rev. F | Page 30 of 32 Data Sheet AD8333 BOARD LAYOUT 05543-068 05543-070 The AD8333 evaluation board has four layers. The interconnecting circuitry is located on the outer layers with the inner layers dedicated as power and ground planes. Figure 66, Figure 67, Figure 69, and Figure 70 illustrate the copper patterns. Figure 69. Ground Plane Copper 05543-069 05543-071 Figure 66. Component Side Copper Figure 70. Power Plane Copper 05543-072 Figure 67. Wiring Side Copper Figure 68. Component Side Silkscreen Rev. F | Page 31 of 32 Data Sheet AD8333 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 1 24 0.50 BSC TOP VIEW 0.80 0.75 0.70 8 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD 17 0.50 0.40 0.30 PIN 1 INDICATOR 9 BOTTOM VIEW 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 71. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body and 0.75 mm Package Height (CP-32-7) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 AD8333ACPZ-REEL AD8333ACPZ-REEL7 AD8333ACPZ-WP AD8333-EVALZ 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. WP = waffle pack. ©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05543-0-5/16(F) Rev. F | Page 32 of 32 Package Option CP-32-7 CP-32-7 CP-32-7