Digital Blocks DB9000AXI Semiconductor IP AXI Bus TFT LCD Controller General Description The Digital Blocks DB9000AXI TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a TFT LCD panel. The DB9000AXI contains a selectable 256 / 128 / 64 / 32-bit AXI Master Interface that targets higher resolution, higher color depth TFT LCD panels, with their resulting high frame buffer memory data bandwidth requirements. The DB9000AXI IP Core can be implemented in an ASIC, ASSP, or FPGA device with an embedded microprocessor, an AMBA AXI Interconnect fabric, and SDRAM Controller for access to frame buffer memory. Typically, the microprocessor is an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, or Tensilica processor and frame buffer memory is off-chip DDR / DDR2 / DDR3 / DDR4 SDRAM. Figure 1 depicts the system view of the DB9000AXI TFT LCD Controller IP Core embedded within an integrated circuit device. ASIC, ASSP, or FPGA Device DB9000AXI TFT LCD Controller TFT LCD Panel Processor Slave Port Master Port AMBA Interconnect Fabric DDR / DDR2 / DDR3 / DDR4 SDRAM Controller DDR / DDR2 / DDR3 / DDR SDRAM Memory Chip Figure 1: DB9000AXI TFT LCD Controller – System Diagram DB9000AXI-DS-V0.1 1 5/6/2016 Digital Blocks, Inc. DB9000AXI AXI Bus LCD Controller Features Wide range of programmable LCD Panel resolutions: o Maximum programmable resolutions of 8192x8192 o Horizontal pixel resolutions from 16 to 8192 pixels in 16 pixel increments. Example LCD Panel high resolutions: o Digital Cinema Systems (DCI) 2048 x 1080 2K image, 4096 x 2160 4K image, & Cinema Scope HD 2560 x 1080 o 7680x4320, 4096x2560, 3840x2160, 2560x2048, 2048x2048, 2048x1536, 1920x1200, 1920x1080, 1680x1050, 1600x1200 o 1600x900, 1440x900, 1366x768, 1280x1024, 1280×768, 1080x1920, 1024x768, 1024x600, 1024x576, 960x540, 800x600, 800x480 Example LCD Panel medium / small resolutions: o 640x480, 640x400, 640x240, 640x200, 480x800, 480x640, 480x272 o 480x234, 240x400, 240x320, 240x240, 320x200, 320x240 Programmable 1 Port or 2 Port TFT LCD Panel interfaces Interface for 1 Port TFT LCD Panel: o 18-bit digital (6-bits/color) LVDS / CMOS o 24-bit digital (8 bits/color) LVDS / CMOS Interface for 2 Port LVDS TFT LCD Panel: o Two 24-bit digital (8 bits/color) LVDS / CMOS ports Interface to LVDS, DVI, HDMI, & DisplayPort Transmitters / Receivers Programmable frame buffer bits-per-pixel (bpp) color depths: o 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel o 16, 18, bpp directly drive 18-bit LCD pixel o 24 bpp directly drive 24-bit LCD pixel Color Palette RAM to reduce Frame Buffer memory storage requirements and AXI Bus bandwidth (for lower color applications): o 256 entry by 16-bit RAM, implemented as 128 entry by 32-bits o Loaded via the Slave Bus Interface statically by the microprocessor or the Master Bus Interface dynamically with each frame by the DMA controller Programmable Output format support: o RGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface o RGB 8:8:8 on 24-bit digital interface Programmable horizontal timing parameters: o horizontal front porch, back porch, sync width, pixels-per-line o horizontal sync polarity Programmable vertical timing parameters: o vertical front porch, back porch, sync width, lines-per-panel DB9000AXI -DS-V0.1 2 5/6/2016 Digital Blocks, Inc. DB9000AXI AXI Bus LCD Controller o vertical sync polarity Programmable pixel clock: o pixel clock divider from 1 to 128 of Bus Clock o pixel clock polarity Programmable Data Enable timing signal: o Derived from horizontal and vertical timing parameters o display enable polarity AMBA AXI / AHB / APB Interconnect: o Selectable 256 / 128 / 64 / 32-bit AXI Master Port for DB9000AXI DMA access of frame buffer memory for driving the display o Selectable 256 / 128 / 64 / 32-bit AXI (or AHB / APB) Slave Port for control & status interface to microprocessor Three memories: o 32-word x 64 bit input FIFO, decoupling AXI bus & LCD panel clock rates. Integrated with DMA controller. o 256-word x 16-bit Color Palette RAM o 16-word output FIFO o FIFOs parameterizable in depth and width Power up and down sequencing support 9 sources of internal interrupts with masking control Little-endian, big-endian, or Windows CE mode AHB / APB Bus - Compliance with AMBA Specification (Rev 2.0) AXI Bus - Designed to AMBA AXI Protocol Specification (V1.0) Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, No gated clocks, and No internal tri-states. High-Resolution TFT LCD Panel support features by AXI Interconnect / Protocol: o Up to 16 overlap outstanding reads requests to the SDRAM Controller o Wide AXI Master Port data width, up to 256-bits DB9000AXI -DS-V0.1 3 5/6/2016 Digital Blocks, Inc. DB9000AXI AXI Bus LCD Controller Block Diagram AXI / AHB / APB Bus Slave Interface LCD Timing & Control LCD Timing and Pixel Clock Generation Processor Status & Control Registers AMBA Interconnect DMA Controller AXI Bus Master Interface Input FIFO 32 Words x 128/64/32 bits Pixel Unpack Palette (256w x 16/24b) Output FIFO 16 Words x 18/24-bits LCD Data Output Formatter Interrupt Interrupt Status & Mask Registers Figure 2: DB9000AXI AMBA Interconnect TFT LCD Controller DB9000AXI -DS-V0.1 4 5/6/2016 Pin Description The DB9000AXI contains three interfaces: LCD Panel Interface AMBA AXI Master Interface AMBA Slave Interface (optional AXI or AHB or APB) (Please Contact Digital Blocks with requirements) The LCD Interface & AXI Master Interface are listed in Tables 1 & 2 respectively. Name LCD_PCLK LCD_HSYNC LCD_VSYNC LCD_DE LCD_PE LCD_R[7:0] LCD_G[7:0] LCD_B[7:0] I/O Type Description LCD Panel Interface – Port 1 Output Pixel Clock Output Horizontal Sync Pulse Output Vertical Sync Pulse Output Display Enable Output Power Enable Output Red Data Output Green Data Output Blue Data LCD Panel Interface – Port 2 Note: Port 2 shares the common control signals with Port 1: LCD_PCLK LCD_HSYNC LCD_VSYNC LCD_DE LCD_PE Output Red Data LCD_R_2[7:0] Output Green Data LCD_G_2[7:0] Output Blue Data LCD_B_2[7:0] Table 1: DB9000AXI – I/O Pin Description for Interface to LCD Panel DB9000AXI-DS-V0.1 5 5/6/2016 Digital Blocks, Inc. Name ARESETn ACLK ARID[3:0] ARADDR[31:0] ARLEN[3:0] ARSIZE[2:0] ARBURST[1:0] ARLOCKM ARCACHE[3:0] ARPROT[2:0] ARVALID ARREADY RID[3:0] RDATA[63:0] RRESP[1:0] RLAST RVALID RREADY DB9000AXI AXI Bus LCD Controller I/O AXI Global Signals Description Reset – Active LOW Reset for AXI Master and DB9000 core. Bus Clock – Clock for AXI Master and one of two programmable clock sources generating I PCLK. All AXI Master logic, including DMA Controller and ingress part of Input FIFO triggered on ACLK rising edge. AXI Read Address Channel Signals O Read Address ID Read Address Bus - Address bus to the AXI O Bus for reading of Frame Buffer Memory. Burst Length – Indicates number of word O transfers in a burst. DB9000 AXI Master supports 1, 4, 8, 16 word transfers. Transfer Size – Indicates the size of the O transfer. DB9000 supports only word (8bytes/64-bit) transfer sizes. Burst Type – Burst Type, coupled with size information, details how address for each O transfer within burst is calculated. DB9000 supports only burst type INCR – Incrementing Burst Type. Locked Type – Unused by DB9000. Cache Type – Unused by DB9000. Protection Type – Unused by DB9000. Read Address Valid – When asserted HIGH O indicates read address and control information valid on AXI bus. Read Address Ready – When HIGH indicates I Slave ready to accept address and associated control information. AXI Read Data Channel Signals I Read ID Tag Read Data Bus - Contains read data from I Frame Buffer Memory. Read Response – Provides additional I information on the status of a transfer. Read Last – Indicates the last transfer in a read I burst. Read Valid – HIGH indicates required read I data available and DB9000 can accept the data word. Read Ready – HIGH indicates the DB9000 can O accept read data and response information. I T Table 2: DB9000AXI – I/O Pin Description for Interface to AXI Master Bus DB9000AXI -DS-V0.1 6 5/6/2016 Digital Blocks, Inc. DB9000AXI AXI Bus LCD Controller Verification Method The DB9000AXI contains a simulation test suite with AXI Bus functional models that program the DB9000AXI control & status registers via the AXI/AHB/APB Slave Bus, generates frame buffer data in response to AXI Master requests, and checks expected results. Customer Evaluation Digital Blocks offers a variety of methods for prospective customers to evaluate the DB9000AXI. Please contact Digital Blocks for additional information. Deliverables The DB9000AXI is available in synthesizable RTL Verilog, along with a simulation test bench with expected results, datasheet, and user manual. Ordering Information Please contact Digital Blocks for additional technical, pricing, evaluation, and support information. Digital Blocks, Inc. PO Box 192 587 Rock Rd Glen Rock, NJ 07452 USA Phone: +1-201-251-1281 eFax: +1-702-552-1905 [email protected] Copyright © Digital Blocks, Inc. 2007-2016, ALL RIGHTS RESERVED ### Digital BlocksTM is a trademark of Digital Blocks, Inc. ARM and AMBA are registered trademarks of ARM Limited. DB9000AXI -DS-V0.1 7 5/6/2016