Digital Blocks DB9000AHB-Lite Semiconductor IP AHB-Lite Bus TFT LCD Controller General Description The Digital Blocks DB9000AHB-Lite TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 3.0 AHB-Lite Bus V1.0 to a TFT LCD panel. In an FPGA, ASIC, or ASSP device, the microprocessor is typically an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, or Tensilica processor and frame buffer memory is either on-chip SRAM memory or larger off-chip SRAM or SDRAM. Figure 1 depicts the system view of the DB9000AHB-Lite TFT LCD Controller IP Core embedded within an integrated circuit device. FPGA, ASIC, ASSP Device DB9000AHB-Lite TFT LCD Controller Processor AHB-Lite Slave Port TFT LCD Panel AHB-Lite Master Port AMBA 3.0 AHB-Lite Bus V1.0 SDRAM Controller On-Chip Memory SRAM Memory Chip SDRAM Memory Chip Figure 1: DB9000AHB-Lite TFT LCD Controller – System Diagram Although Figure 1 depicts the DB9000AHB-Lite connecting to a memory controller via an AMBA AHB interconnect, the DB9000AHB-Lite can connect directly to a multi-port memory controller with an AHB-Lite port interface. DB9000AHB-Lite-DS-V1.2 1 5/6/2016 Digital Blocks, Inc. DB9000AHB-Lite AHB Bus LCD Controller Features Wide range of programmable LCD Panel resolutions: o Maximum programmable resolutions of 4096x4096 o Horizontal pixel resolutions from 16 to 4096 pixels in 16 pixel increments. Example LCD Panel high resolutions: o 4096x2560, 3840x2160, 2560x2048, 2048x2048, 2048x1536, 1920x1200, 1920x1080, 1680x1050, 1600x1200 o 1600x900, 1440x900, 1366x768, 1280x1024, 1280×768, 1080x1920, 1024x768, 1024x600, 1024x576, 960x540, 800x600, 800x480 Example LCD Panel medium / small resolutions: o 640x480, 640x400, 640x240, 640x200, 480x800, 480x640, 480x272 o 480x234, 240x400, 240x320, 240x240, 320x200, 320x240 Support for 1 Port TFT LCD Panel interfaces: o 18-bit digital (6-bits/color) & 24-bit digital (8-bits/color) Programmable frame buffer bits-per-pixel (bpp) color depths: o 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel o 16, 18, bpp directly drive 18-bit LCD pixel o 24 bpp directly drive 24-bit LCD pixel Color Palette RAM to reduce Frame Buffer memory storage requirements and AHB Bus bandwidth: o 256 entry by 16-bit RAM, implemented as 128 entry by 32-bits o Loaded via the Slave Bus Interface statically by the microprocessor or the Master Bus Interface dynamically with each frame by the DMA controller Programmable Output format support: o RGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface o RGB 8:8:8 on 24-bit digital interface Programmable horizontal timing parameters: o horizontal front porch, back porch, sync width, pixels-per-line o horizontal sync polarity Programmable vertical timing parameters: o vertical front porch, back porch, sync width, lines-per-panel o vertical sync polarity Programmable pixel clock: o pixel clock divider from 1 to 128 of Bus Clock o pixel clock polarity Programmable Data Enable timing signal: o Derived from horizontal and vertical timing parameters DB9000AHB-Lite-DS-V1.2 2 5/6/2016 Digital Blocks, Inc. DB9000AHB-Lite AHB Bus LCD Controller display enable polarity Three memories: o 16-word x 32 bit input FIFO, decoupling AHB bus & LCD panel clock rates. Integrated with DMA controller. o 256-word x 16-bit Color Palette RAM o 16-word output FIFO o FIFOs parameterizable in depth and width Power up and down sequencing support 9 sources of internal interrupts with masking control Little-endian, big-endian, or Windows CE mode Compliance with AMBA 3.0 AHB-Lite Protocol Specification (v 1.0) Fully-synchronous, synthesizable Verilog RTL core, with rising-edge clocking, No gated clocks, and No internal tri-states. DB9000AHB-Lite-DS-V1.2 3 5/6/2016 Digital Blocks, Inc. DB9000AHB-Lite AHB Bus LCD Controller Block Diagram AHB-Lite Bus Slave Interface Processor Status & Control Registers LCD Timing & Control LCD Timing and Pixel Clock Generation AMBA 3.0 AHB-Lite Bus v1.0 DMA Controller AHB-Lite Bus Master Interface Input FIFO 64 Words x 128/64/32b Pixel Unpack Palette (256 x 16) Output FIFO 16 Words x 18/24-bits LCD Data Output Formatter Interrupt Interrupt Status & Mask Registers Figure 2: DB9000AHB-Lite AMBA 3.0 AHB-Lite v1.0 Bus TFT LCD Controller Pin Description In addition to the AMBA 3.0 AHB-Lite v1.0 Master and Slave Bus interfaces, which include the input HCLK and HRESETN signals and the output INTR (interrupt) signal, the interface to the LCD panel is listed in Table 1. Note that if the panel is 18-bits data, the lower 6-bits of LCD_R, LCD_G, and LCD_B should be connected. Name LCD_PCLK LCD_HSYNC LCD_VSYNC LCD_DE LCD_PE LCD_R[7:0] LCD_G[7:0] LCD_B[7:0] Type Description LCD Panel Interface Output Pixel Clock Output Horizontal Sync Pulse Output Vertical Sync Pulse Output Display Enable Output Power Enable Output Red Data Output Green Data Output Blue Data Table 1: DB9000AHB-Lite – I/O Pin Description for Interface to LCD Panel DB9000AHB-Lite-DS-V1.2 4 5/6/2016 Digital Blocks, Inc. DB9000AHB-Lite AHB Bus LCD Controller Verification Method The DB9000AHB-Lite contains a test suite with AHB-Lite Bus functional models that program the DB9000AHB-Lite control & status registers, generates frame buffer data in response AHB-Lite Master requests, and checks expected results. The DB9000AHB-Lite IP Core has been verified in an FPGA, driving a variety of TFT LCD panels, including NEC & Sharp 320x240, 480x272, 640x480, 800x600, and 1280x768 resolution panels with an 18-bit or 24-bit digital interface. Customer Evaluation Digital Blocks offers a variety of methods for prospective customers to evaluate the DB9000AHB-Lite. Please contact Digital Blocks for additional information. Deliverables The DB9000AHB-Lite is available in technology-specific netlists for FPGAs or synthesizable RTL Verilog, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual. Ordering Information Please contact Digital Blocks for additional technical, pricing, evaluation, and support information. Digital Blocks, Inc. PO Box 192 587 Rock Rd Glen Rock, NJ 07452 USA Phone: +1-201-251-1281 eFax: +1-702-552-1905 [email protected] Copyright © Digital Blocks, Inc. 2007-2016, ALL RIGHTS RESERVED ### Digital Blocks is a registered trademark of Digital Blocks, Inc. ARM and AMBA are registered trademarks of ARM Limited. All other trademarks are the property of their respective owners. DB9000AHB-Lite-DS-V1.2 5 5/6/2016