DS0138: IGLOO2 Automotive Grade 1 Datasheet

IGLOO2 FPGA Automotive Grade 1
DS0138 Datasheet
IGLOO2 FPGA Automotive Grade 1
Table of Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2. Device Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3. Product Briefs and Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4. General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
1
2
4.1. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4.2. Overshoot/Undershoot Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3.1
4.3.2
4.3.3
4.3.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Theta-JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Theta-JB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Theta-JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
6
6
6
5. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1. Quiescent Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.2. Programming Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6. Average Fabric Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . 9
7. Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8. User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8.1. Input Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2. Output Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3. Tristate Buffer and AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4. I/O Speeds
................................................................
8.5. Detailed I/O Characteristics
.................................................
8.6. Single-Ended I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) . . . . . . . . . . . . . . . . . . . . . . .
3.3 V LVCMOS/LVTTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 V PCI/PCIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
12
13
13
15
15
15
16
17
21
25
28
30
8.7. Voltage Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.7.1
8.7.2
8.7.3
8.7.4
8.7.5
High-Speed Transceiver Logic (HSTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stub-Series Terminated Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stub-Series Terminated Logic 2.5 V (SSTL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stub-Series Terminated Logic 1.8 V (SSTL18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stub-Series Terminated Logic 1.5 V (SSTL15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
34
34
37
39
8.8. Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mini-LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RSDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LVPECL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 1
41
43
45
46
48
49
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IGLOO2 FPGA Automotive Grade 1
Table of Contents
8.9. I/O Register Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.9.1 Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.9.2 Output/Enable Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.10. DDR Module Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.10.1
8.10.2
8.10.3
8.10.4
8.10.5
Input DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
55
56
57
59
9. Logic Element Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1. 4-input LUT (LUT-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.1.1 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.2. Sequential Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.2.1 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10. Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
11. FPGA Fabric SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
11.1. FPGA Fabric Large SRAM (LSRAM)
11.2. FPGA Fabric Micro SRAM (uSRAM)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12. Embedded NVM (eNVM) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14. On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15. Clock Conditioning Circuits (CCC)
.........................................
16. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17. DEVRST_N Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18. System Controller SPI Characteristics
......................................
19. Mathblock Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20. Flash*Freeze Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21. IGLOO2 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
80
81
82
86
86
87
88
90
91
21.1. HPMS Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
21.2. IGLOO2 Serial Peripheral Interface (SPI) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
22. List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
23. Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
23.1. Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.2. Product Brief . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.3. Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.4. Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23.5. Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
95
95
95
95
24. Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . 96
25. Microsemi Corporate Headquarters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Revision 1
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IGLOO2 FPGA Automotive Grade 1
List of Figures
Figure 1. High Temperature Data Retention (HTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Input Buffer AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Output Buffer AC Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Tristate Buffer for Enable Path Test Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Timing Model for Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 7. I/O Register Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 8. Timing Model for Output/Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 9. I/O Register Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10. Input DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 11. Input DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 12. Output DDR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 13. Output DDR Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 14. LUT-4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 15. Sequential Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 16. Sequential Module Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 17. SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1) . . . . . . . . . . . . . . . . . . 93
Revision 1
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IGLOO2 FPGA Automotive Grade 1
List of Tables
Table 1. IGLOO2 FPGA Device Status ..................................................................................................1
Table 2. Absolute Maximum Ratings ......................................................................................................2
Table 3. Recommended Operating Conditions ......................................................................................2
Table 4. FPGA Operating Limits .............................................................................................................3
Table 5. Embedded Flash Limits ............................................................................................................3
Table 6. Device Storage Temperature and Retention ............................................................................4
Table 7. High Temperature Data Retention (HTR) Lifetime ...................................................................4
Table 8. Package Thermal Resistance ...................................................................................................5
Table 9. Quiescent Supply Current Characteristics ................................................................................7
Table 10. IGLOO2 Quiescent Supply Current – Typical Process ...........................................................7
Table 11. IGLOO2 Quiescent Supply Current – Worst-Case Process ...................................................8
Table 12. Currents During Program Cycle, 0°C < = TJ <= 85°C, Typical Process .................................8
Table 13. Currents During Verify Cycle, 0°C <= TJ <= 85°C, Typical Process .......................................8
Table 14. Inrush Currents at Power up, -40°C <= TJ <= 135°C, Typical Process ..................................8
Table 15. Average Temperature and Voltage Derating Factors for Fabric Timing Delays .....................9
Table 16. Timing Model Parameters ....................................................................................................10
Table 17. Maximum Data Rate Summary for Worst-Case Automotive Grade 1 Conditions ................13
Table 18. Maximum Frequency Summary for Worst-Case Automotive Grade 1 Conditions ...............14
Table 19. Input Capacitance and Leakage Current ..............................................................................15
Table 20. I/O Weak Pull-Up/Pull-Down Resistance Values for DDRIO, MSIO, and MSIOD Banks .....15
Table 21. Schmitt Trigger Input Hysteresis ..........................................................................................15
Table 22. LVTTL/LVCMOS 3.3 V DC Voltage Specification (Applicable to MSIO I/O Bank Only) .......16
Table 23. LVTTL/LVCMOS 3.3 V Maximum Switching Speeds (Applicable to MSIO I/O Bank Only) .16
Table 24. LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO Bank Only) 16
Table 25. LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications
(Applicable to MSIO Bank* Only) .........................................................................................................16
Table 26. LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Banks (Input Buffers) .........17
Table 27. LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers) ......................................................................................................................................................17
Table 28. LVCMOS 2.5 V DC Voltage Specification ............................................................................17
Table 29. LVCMOS 2.5 V Maximum AC Switching Speeds .................................................................18
Table 30. LVCMOS 2.5 V AC Test Parameters and Driver Impedance Specifications ........................18
Table 31. LVCMOS 2.5 V Transmitter Drive Strength Specifications ...................................................18
Table 32. LVCMOS 2.5 V AC Switching Characteristics for Receiver (Input Buffers) ..........................19
Table 33. LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 20
Table 34. LVCMOS 1.8 V DC Voltage Specification ............................................................................21
Table 35. LVCMOS 1.8 V Maximum AC Switching Speeds .................................................................21
Table 36. LVCMOS 1.8 V Transmitter Drive Strength Specifications ...................................................22
Table 37. LVCMOS 1.8 V Transmitter Drive Strength Specifications ...................................................22
Table 38. LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications ........................23
Table 39. LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers) ..........................23
Table 40. LVCMOS 1.8 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 24
Table 41. LVCMOS 1.5 V Minimum and Maximum DC Input and Output Levels ................................25
Table 42. LVCMOS 1.5 V Maximum AC Switching Speeds .................................................................25
Table 43. LVCMOS 1.5 V AC Switching Characteristics for Receiver (Input Buffers) ..........................26
Table 44. LVCMOS 1.5 V AC Test Parameters and Driver Impedance Specifications ........................26
Table 45. LVCMOS 1.5 V Transmitter Drive Strength Specifications ...................................................26
Table 46. LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 27
Table 47. LVCMOS 1.2 V Minimum and Maximum DC Input and Output Levels ................................28
Table 48. LVCMOS 1.2 V Maximum AC Switching Speeds .................................................................28
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Table 49. LVCMOS 1.2 V AC Switching Characteristics for Receiver (Input Buffers) ..........................29
Table 50. LVCMOS 1.2 V AC Calibrated Impedance and Test Parameters Specifications .................29
Table 51. LVCMOS 1.2 V Transmitter Drive Strength Specifications ...................................................29
Table 52. LVCMOS 1.2 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers) 30
Table 53. PCI/PCI-X DC Voltage Specification (Applicable to MSIO Bank Only) ................................30
Table 54. PCI/PCI-X AC Specifications (Applicable to MSIO Bank Only) ............................................31
Table 55. PCI/PCIX AC Switching Characteristics for Receiver (Input Buffers) ...................................31
Table 56. PCI/PCIX AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ........31
Table 57. HSTL DC Voltage Specification (Applicable to DDRIO I/O Bank Only) ................................32
Table 58. HSTL AC Specifications (Applicable to DDRIO Bank Only) .................................................32
Table 59. HSTL15 AC Switching Characteristics for Receiver (Input Buffers) .....................................33
Table 60. HSTL 15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) .........33
Table 61. SSTL2 Minimum and Maximum DC Input and Output Levels ..............................................34
Table 62. SSTL2 AC Specifications .....................................................................................................35
Table 63. SSTL2 AC Switching Characteristics for Receiver (Input Buffers) .......................................36
Table 64. SSTL2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ............36
Table 65. SSTL18 AC/DC Minimum and Maximum Input and Output Levels Specification .................37
Table 66. SSTL18 AC Specifications (Applicable to DDRIO Bank Only) .............................................37
Table 67. SSTL18 AC Switching Characteristics for Receiver (Input Buffers) .....................................38
Table 68. SSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ..........39
Table 69. SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only) ...........................................39
Table 70. SSTL15 AC Specifications ...................................................................................................40
Table 71. STTL15 AC Switching Characteristics for Receiver (Input Buffers) .....................................41
Table 72. SSTL15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ..........41
Table 73. LVDS DC Voltage Specification ...........................................................................................41
Table 74. LVDS25 Receiver Characteristics ........................................................................................42
Table 75. LVDS AC Specifications .......................................................................................................42
Table 76. LVDS25 Transmitter Characteristics ....................................................................................43
Table 77. LVDS33 Receiver Characteristics ........................................................................................43
Table 78. LVDS33 Transmitter Characteristics ....................................................................................43
Table 79. B-LVDS DC Voltage Specification ........................................................................................43
Table 80. B-LVDS AC Switching Characteristics for Receiver (Input Buffers) .....................................44
Table 81. B-LVDS AC Specifications ...................................................................................................44
Table 82. B-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ..........45
Table 83. M-LVDS DC Voltage Specification .......................................................................................45
Table 84. M-LVDS AC Specifications ...................................................................................................45
Table 85. M-LVDS AC Switching Characteristics for Receiver (Input Buffers) .....................................46
Table 86. M-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ..........46
Table 87. Mini-LVDS DC Voltage Specification ....................................................................................46
Table 88. Mini-LVDS AC Specifications ...............................................................................................47
Table 89. Mini-LVDS AC Switching Characteristics for Receiver (Input Buffers) .................................47
Table 90. Mini-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) ......48
Table 91. RSDS DC Voltage Specification ...........................................................................................48
Table 92. RSDS AC Specifications ......................................................................................................48
Table 93. RSDS AC Switching Characteristics for Receiver (Input Buffers) ........................................49
Table 94. RSDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers) .............49
Table 95. LVPECL DC Voltage Specification (Applicable to MSIO I/O Banks Only) ............................49
Table 96. LVPECL Receiver Characteristics ........................................................................................50
Table 97. LVPECL Maximum AC Switching Speeds (Applicable to MSIO I/O Banks Only) ................50
Table 98. Input Data Register Propagation Delays ..............................................................................51
Table 99. Output/Enable Data Register Propagation Delays ...............................................................53
Table 100. Input DDR Propagation Delays ..........................................................................................56
Table 101. Output DDR Propagation Delays ........................................................................................59
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Table 102. Combinatorial Cell Propagation Delays ..............................................................................60
Table 103. Register Delays ..................................................................................................................62
Table 104. M2GL090 Device Global Resource ....................................................................................62
Table 105. M2GL060 Device Global Resource ....................................................................................62
Table 106. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18 ...............................63
Table 107. M2GL025 Device Global Resource ....................................................................................63
Table 108. M2GL010 Device Global Resource ....................................................................................63
Table 109. M2GL005 Device Global Resource ....................................................................................63
Table 110. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2Kx9 .................................65
Table 111. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4Kx4 .................................66
Table 112. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8Kx2 .................................67
Table 113. RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16Kx1 ...............................68
Table 114. RAM1K18 – Two-Port Mode for Depth × Width Configuration 512x36 ..............................69
Table 115. uSRAM (RAM64x18) in 64x18 Mode .................................................................................71
Table 116. uSRAM (RAM64x16) in 64x16 Mode .................................................................................72
Table 117. uSRAM (RAM128x9) in 128x9 Mode .................................................................................73
Table 118. uSRAM (RAM128x8) in 128x8 Mode .................................................................................74
Table 119. uSRAM (RAM256x4) in 256x4 Mode .................................................................................76
Table 120. uSRAM (RAM512x2) in 512x2 Mode .................................................................................77
Table 121. uSRAM (RAM1024x1) in 1024x1 Mode .............................................................................78
Table 122. eNVM Read Performance ..................................................................................................80
Table 123. eNVM Page Programming ..................................................................................................80
Table 124. Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz) ................80
Table 125. Electrical Characteristics of the Crystal Oscillator – Medium Gain Mode (2 MHz) .............80
Table 126. Electrical Characteristics of the 50 MHz RC Oscillator .......................................................81
Table 127. Electrical Characteristics of the Crystal Oscillator – Low Gain Mode (32 kHz) ..................81
Table 128. Electrical Characteristics of the 1 MHz RC Oscillator .........................................................82
Table 129. IGLOO2 FPGAs CCC/PLL Specification ............................................................................82
Table 130. IGLOO2 FPGAs CCC/PLL Jitter Specifications .................................................................83
Table 131. Programming Times ...........................................................................................................84
Table 132. Programming Times ...........................................................................................................85
Table 133. JTAG 1532 .........................................................................................................................86
Table 134. DEVRST_N Characteristics ................................................................................................86
Table 135. System Controller SPI Characteristics ...............................................................................87
Table 136. Supported I/O Configurations for System Controller SPI (for MSIO Bank Only) ................87
Table 137. Mathblocks With All Registers Used ...................................................................................88
Table 138. Mathblock With Input Bypassed and Output Registers Used .............................................88
Table 139. Mathblock With Input Register Used and Output in Bypass Mode .....................................89
Table 140. Mathblock With Input and Output in Bypass Mode .............................................................89
Table 141. Flash*Freeze Entry and Exit Times ....................................................................................90
Table 142. Maximum Frequency for HPMS Main Clock .......................................................................91
Table 143. SPI Characteristics .............................................................................................................91
Revision 1
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IGLOO2 FPGA Automotive Grade 1
IGLOO2 Automotive Grade 1 AC/DC Electrical
Characteristics
1. Introduction
Microsemi's automotive grade IGLOO®2 FPGAs offer the best-in-class security, industry leading high reliability and
lowest static power in a flash-based fabric. With a strong heritage of supplying to Military and Aviation customers,
Microsemi automotive grade devices are ideally suited to meet the demands of the automotive industry providing the
lowest total-cost-of-ownership. These next-generation devices integrate an industry standard 4-input lookup
table-based (LUT) FPGA fabric with integrated mathblocks, and multiple embedded memory blocks on a single chip
with extended temperature support.
Automotive grade IGLOO2 devices offer up to 90 K logic elements, up to 5 MB of embedded RAM with on-chip flash,
32 kbyte embedded SRAM, and multiple DMA controllers. IGLOO2 FPGAs are the best alternative to ASICs and
SRAM based FPGAs with their advantages of Zero FIT reliability, tamper-free advanced security, industry's lowest
static power and supply assurance for long product lifetime support.
2. Device Status
The following IGLOO2 devices are available. For more information on device status, refer to the "Datasheet
Categories".
Table 1 •
IGLOO2 FPGA Device Status
Design Security Device Densities
Status
005
Production
010
Production
025
Production
060
Production
090
Production
3. Product Briefs and Pin Descriptions
The product brief and pin descriptions are published separately:
•
Automotive Grade 1 IGLOO2 FPGAs Product Brief (to be released)
•
DS0124: IGLOO2 Pin Descriptions
Revision 1
1
IGLOO2 FPGA Automotive Grade 1
4. General Specifications
4.1 Operating Conditions
Stresses beyond those listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Absolute maximum ratings are stress ratings only; functional operation of the device at these or any other conditions
beyond those listed under the recommended operating conditions specified in Table 2 is not implied.
Table 2 •
Absolute Maximum Ratings
Limits
Symbol
Parameter
Min
Max
Units
Notes
VDD
DC core supply voltage. Must always power this pin.
–0.3
1.32
V
–
VPP
Power supply for charge pumps (for normal operation
and programming). Must always power this pin.
–0.3
3.63
V
–
CCC_XX[01]_PLL_VDDA
Analog power pad for PLL0–5
–0.3
3.63
V
–
DC FPGA I/O buffer supply voltage for MSIO I/O Bank
–0.3
3.63
V
–
DC FPGA I/O buffer supply voltage for MSIOD/DDRIO
I/O Banks
–0.3
2.75
V
–
I/O Input voltage for MSIO I/O Bank
–0.3
3.63
V
–
I/O Input voltage for MSIOD/DDRIO I/O Bank
–0.3
2.75
V
–
VPPNVM
Analog sense circuit supply of embedded nonvolatile
memory (eNVM). Must be shorted to VPP.
–0.3
3.63
V
–
TSTG
Storage temperature
–65
150
°C
*
TJ
Junction temperature
–
145
°C
–
VDDIx
VI
Note: * For flash programming and retention maximum limits, refer to Table 4 on page 3. For recommended operating
conditions, refer to Table 3 on page 2.
Table 3 •
Symbol
Recommended Operating Conditions
Parameter
Operating Junction Temperature
Tj
VDD
VPP
Conditions
Min
Typ
Max
Automotive
Grade 1
-40
25
135
°C
–
–
0
25
85
°C
–
–
-40
25
100
°C
1
–
1.14
1.2
1.26
V
–
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
Programming Junction
Temperature
DC core supply voltage. Must
always power this pin.
Power Supply for Charge Pumps
(for Normal Operation and
Programming) for 005, 010, 025,
and 060 Devices
Power Supply for Charge Pumps
(for Normal Operation and
Programming) for 090 devices
Revision 1
Units Notes
2
IGLOO2 FPGA Automotive Grade 1
Table 3 •
Recommended Operating Conditions (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
2.5 V
Range
2.375
2.5
2.625
V
–
3.3 V
Range
3.15
3.3
3.45
V
–
1.2 V DC supply voltage
–
1.14
1.2
1.26
V
–
1.5 V DC supply voltage
–
1.425
1.5
1.575
V
–
1.8 V DC supply voltage
–
1.71
1.8
1.89
V
–
2.5 V DC supply voltage
–
2.375
2.5
2.625
V
–
3.3 V DC supply voltage
–
3.15
3.3
3.45
V
–
LVDS differential I/O
–
2.375
2.5
3.45
V
–
BLVDS,
MLVDS,
Mini-LVDS,
RSDS differential I/O
–
2.375
2.5
2.625
V
–
LVPECL differential I/O
–
3.15
3.3
3.45
V
–
VREFx
Reference Voltage Supply for
DDRIO Banks
–
0.51
0.5
0.49
VDDIx VDDIx VDDIx
V
–
2.5 V
Range
2.375
2.5
2.625
V
–
VPPNVM
Analog sense circuit supply of
embedded nonvolatile memory
(eNVM). Must be shorted to VPP
3.3 V
Range
3.15
3.3
3.45
V
–
CCC_XX[01]_PLL_VDDA Analog power pad for PLL0-5
VDDIx
Units Notes
Notes:
1. Programming at this temperature range is available only with VPP in 3.3 V range.
2. Power supply ramps must all be strictly monotonic, without plateaus.
Table 4 •
Product
Grade
Automotive
Grade 1
FPGA Operating Limits
Element
FPGA
Programming
Temperature
Operating
Temperature
Retention
Digest (Biased/
Cycles Unbiased) Note
Programming
Cycles
Digest
Temperature
Min TJ = -40°C
Min TJ = 0°C
Max TJ = 85°C Max TJ = 135°C
500
Min TJ = -40°C
Max TJ = 100°C
2000
6 Years
–
Min TJ = -40°C Min TJ = -40°C
Max TJ = 100°C Max TJ = 135°C
500
Min TJ = -40°C
Max TJ = 100°C
2000
6 Years
*
Note: * Programming in -40°C to 100°C temperature range is available only with VPP in 3.3 V range.
Table 5 •
Embedded Flash Limits
Product Grade
Automotive Grade 1
Element
Programming
Temperature
Embedded
flash
Min TJ = -40°C
Max TJ = 135°C
Maximum
Operating
Temperature
Programming
Cycles
< 10,000 cycles
Min TJ = -40°C per pages, up to
Max TJ = 135°C one million cycles
per eNVM array
Retention
(Biased/Unbiased)
6 Years
Note: If accelerated programming cycles are required as part of your product qualification, refer to the RT0001:
Microsemi Corporation - SoC Products Reliability Report on recommended methodologies.
Revision 1
3
IGLOO2 FPGA Automotive Grade 1
Table 6 •
Device Storage Temperature and Retention
Product Grade
Automotive Grade 1
Table 7 •
Note:
Storage Temperature (Tstg)
Retention
Min TJ = -40°C
Max TJ = 135°C
6 Years
High Temperature Data Retention (HTR) Lifetime
Tj (C)
HTR Lifetime* (Years)
90
38.0
95
28.0
100
20.5
105
17.0
110
15.0
115
13.0
120
11.5
125
10.0
130
8.0
135
6.0
140
4.5
145
3.0
150
1.5
* HTR Lifetime is the period during which a verify failure is not expected due to flash leakage.
Figure 1 • High Temperature Data Retention (HTR)
Revision 1
4
IGLOO2 FPGA Automotive Grade 1
4.2 Overshoot/Undershoot Limits
For AC signals, the input signal may undershoot during transitions to -1.0 V for no longer than 10% or the period. The
current during the transition must not exceed 100 mA.
For AC signals, the input signal may overshoot during transitions to VCCI + 1.0 V for no longer than 10% of the period.
The current during the transition must not exceed 100 mA.
Note: The above specification does not apply to the PCI standard. The IGLOO2 PCI I/Os are compliant to the PCI
standard including the PCI overshoot/undershoot specifications.
4.3 Thermal Characteristics
4.3.1 Introduction
The temperature variable in the Microsemi SoC Products Group Designer software refers to the junction temperature,
not the ambient, case, or board temperatures. This is an important distinction because dynamic and static power
consumption will cause the chip's junction temperature to be higher than the ambient, case, or board temperatures.
EQ 1 through EQ 3 give the relationship between thermal resistance, temperature gradient, and power.
TJ – TA
 JA = -----------------P
EQ 1
 JB
TJ – TB
= -----------------P
 JC
TJ – TC
= -----------------P
EQ 2
EQ 3
where
JA = Junction-to-air thermal resistance
JB = Junction-to-board thermal resistance
JC = Junction-to-case thermal resistance
TJ
= Junction temperature
TA
= Ambient temperature
TB
= Board temperature (measured 1.0 mm away from the package edge)
TC
= Case temperature
P
= Total power dissipated by the device
Table 8 •
Package Thermal Resistance
JA
Product M2GL
Still Air
1.0 m/s
2.5 m/s
JB
JC
Units
19.36
15.81
14.63
9.74
5.27
°C/W
18.22
14.83
13.62
8.83
4.92
°C/W
17.03
13.66
12.45
7.66
4.18
°C/W
005
FGG484
010
FGG484
025
FGG484
Revision 1
5
IGLOO2 FPGA Automotive Grade 1
Table 8 •
Package Thermal Resistance (continued)
JA
Product M2GL
Still Air
1.0 m/s
2.5 m/s
JB
JC
Units
15.40
12.06
10.85
6.14
3.15
°C/W
14.64
11.37
10.16
5.43
2.77
°C/W
060
FGG484
090
FGG484
4.3.2 Theta-JA
Junction-to-ambient thermal resistance (JA) is determined under standard conditions specified by JEDEC (JESD-51),
but it has little relevance in actual performance of the product. It should be used with caution, but it is useful for
comparing the thermal performance of one package to another.
The maximum power dissipation allowed is calculated using EQ 4.
T J(MAX) – T A(MAX)
Maximum Power Allowed = ------------------------------------------- JA
EQ 4
The absolute maximum junction temperature is 135°C. EQ 5 shows a sample calculation of the absolute maximum
power dissipation allowed for the M2GL060TS-1FGG484 package at Automotive Grade 1 temperature and in still air,
where:
JA
= 15.4°C/W (taken from Table 8 on page 5).
TA
= 105°C
– 105°C- = 1.9 W
Maximum Power Allowed = 135°C
--------------------------------------15.4°C/W
EQ 5
The power consumption of a device can be calculated using the Microsemi SoC Products Group power calculator. The
device's power consumption must be lower than the calculated maximum power dissipation by the package.
If the power consumption is higher than the device's maximum allowable power dissipation, a heat sink can be
attached on top of the case, or the airflow inside the system must be increased.
4.3.3 Theta-JB
Junction-to-board thermal resistance (JB) measures the ability of the package to dissipate heat from the surface of the
chip to the PCB. As defined by the JEDEC (JESD-51) standard, the thermal resistance from junction to board uses an
isothermal ring cold plate zone concept. The ring cold plate is simply a means to generate an isothermal boundary
condition at the perimeter. The cold plate is mounted on a JEDEC standard board with a minimum distance of 5.0 mm
away from the package edge.
4.3.4 Theta-JC
Junction-to-case thermal resistance (JC) measures the ability of a device to dissipate heat from the surface of the chip
to the top or bottom surface of the package. It is applicable for packages used with external heat sinks. Constant
temperature is applied to the surface in consideration and acts as a boundary condition.
Revision 1
6
IGLOO2 FPGA Automotive Grade 1
This only applies to situations where all or nearly all of the heat is dissipated through the surface in consideration.
5. Power Consumption
5.1 Quiescent Supply Current
Table 9 •
Quiescent Supply Current Characteristics
Modes and Configurations
Power Supplies/Blocks
Non-Flash*Freeze Mode Flash*Freeze Mode Notes
FPGA Core
On
Off
–
VDD
On
On
–
VPP / VPPNVM
On
On
–
CCC_XX[01]_PLL_VDDA
0V
0V
–
VDDIx
On
On
1, 2
VREFx
On
On
–
32 kHz
32 kHz
–
On
Sleep state
–
HPMS Controller
50 MHz
50 MHz
–
50 MHz Oscillator (enable/disable)
Enabled
Disabled
–
1 MHz Oscillator (enable/disable)
Disabled
Disabled
–
Crystal Oscillator (enable/disable)
Disabled
Disabled
–
HPMS_CLK
RAM
Notes:
1. VDDIx has been set to ON for test conditions as described. Banks on the east side should always be powered with the
appropriate VDDI Bank supplies. For details on bank power supplies, refer to the “Recommendation for Unused Bank
Supplies” table in the AC393: SmartFusion2 and IGLOO2 Board Design Guidelines Application Note.
2. No Differential (that is to say, LVDS) I/O’s or ODT attributes to be used.
Table 10 • IGLOO2 Quiescent Supply Current – Typical Process
005
Parameter
Modes
Conditions
Typical
(TJ = 25°C)
IDC1
IDC2
010
025
060
VDD=1.2 V VDD=1.2 V VDD=1.2 V VDD=1.2 V
090
VDD=1.2 V
Units
6.2
6.9
8.9
15.3
15.4
mA
81.3
97.5
142.6
289.6
292.5
mA
Typical
(TJ = 25°C)
1.4
2.6
3.7
5.0
5.1
mA
Flash*Freeze Automotive
Grade 1
(TJ= 135°C)
45.3
75.3
100.4
133.3
134.6
mA
NonFlash*Freeze Automotive
Grade 1
(TJ = 135°C)
Revision 1
7
IGLOO2 FPGA Automotive Grade 1
Table 11 • IGLOO2 Quiescent Supply Current – Worst-Case Process
005
Parameter
010
025
060
090
Modes
Conditions
VDD=1.26 V VDD=1.26 V VDD=1.26 V VDD=1.26 V VDD=1.26 V Units
IDC1
NonFlash*Freeze
Automotive
Grade 1
(TJ= 135°C)
154.0
203.5
306.1
591.4
597.3
mA
IDC2
Flash*Freeze
Automotive
Grade 1
(TJ= 135°C)
109.8
172.0
195.1
261.2
263.9
mA
5.2 Programming Currents
The tables below represent programming, verify and Inrush currents for IGLOO2 FPGA devices.
Table 12 • Currents During Program Cycle, 0°C < = TJ <= 85°C, Typical Process
Power Supplies
Voltage (V)
005
010
025
060
090
Units
Notes
VDD
1.26
46
53
55
30
42
mA
–
VPP
3.46
8
11
6
9
12
mA
–
VPPNVM
3.46
1
2
2
3
3
mA
*
2.62
31
16
17
12
12
mA
–
3.46
62
31
36
12
17
mA
–
7
8
8
10
9
–
–
VDDI
Number of banks
Note: * VPP and VPPNVM are internally shorted.
Table 13 • Currents During Verify Cycle, 0°C <= TJ <= 85°C, Typical Process
Power Supplies
Voltage (V)
005
010
025
060
090
Units
Notes
VDD
1.26
44
53
55
33
41
mA
–
VPP
3.46
6
5
3
8
11
mA
–
VPPNVM
3.46
1
0
0
1
1
mA
–
2.62
31
16
17
12
11
mA
–
3.46
61
32
36
12
17
mA
–
7
8
8
10
9
–
–
VDDI
Number of banks
Table 14 • Inrush Currents at Power up, -40°C <= TJ <= 135°C, Typical Process
Power Supplies
Voltage (V)
005
010
025
060
090
Units
VDD
1.26
36
53
78
45
98
mA
VPP
3.46
35
57
50
13
36
mA
VDDI
2.62
134
141
161
93
283
mA
7
8
8
10
9
–
Number of banks
Revision 1
8
IGLOO2 FPGA Automotive Grade 1
6. Average Fabric Temperature and Voltage Derating Factors
Table 15 • Average Temperature and Voltage Derating Factors for Fabric Timing Delays
(Normalized to TJ = 135°C, Worst-Case VDD = 1.14 V)
Array Voltage VDD (V)
Junction Temperature (°C)
–55°C
–40°C
0°C
25°C
70°C
85°C
100°C
125°C
135°C
1.14
0.91
0.91
0.93
0.93
0.95
0.96
0.97
1.00
1.00
1.2
0.82
0.82
0.84
0.84
0.86
0.87
0.88
0.90
0.90
1.26
0.75
0.75
0.76
0.77
0.79
0.80
0.80
0.82
0.83
7. Timing Model
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Figure 2 • Timing Model
Revision 1
9
IGLOO2 FPGA Automotive Grade 1
Table 16 • Timing Model Parameters
Description
Speed
Grade –1
Units
Propagation Delay of SSTL15 Receiver
2.71
ns
Refer to page 41 for more
information
tICLKQ
Clock-to-Q of the Input Data Register
0.166
ns
Refer to page 51 for more
information
tISUD
Setup Time of the Input Data Register
0.37
ns
Refer to page 51 for more
information
tRCKH
Input High Delay for Global Clock
1.915
ns
Refer to page 62 - 63 for more
information
tRCKL
Input Low Delay for Global Clock
1.08
ns
Refer to page 62 - 63 for more
information
3.085
ns
Refer to page 42 for more
information
Index Parameter
A
tPY
B
C
D
tPY
Input Propagation
Receiver
E
tDP
Propagation Delay of a three input AND
Gate
0.218
ns
Refer to page 60 for more
information
F
tDP
Propagation Delay of a OR Gate
0.17
ns
Refer to page 60 for more
information
G
tDP
Propagation
Transmitter
2.324
ns
Refer to page 43 for more
information
H
tDP
Propagation Delay of a three input XOR
Gate
0.234
ns
Refer to page 60 for more
information
I
tDP
Propagation Delay of LVCMOS 2.5 V
Transmitter, Drive strength of 16mA on
the MSIO Bank
2.746
ns
Refer to page 20 for more
information
J
tDP
Propagation Delay of a two input NAND
Gate
0.17
ns
Refer to page 60 for more
information
K
tDP
Propagation Delay of LVCMOS 2.5 V
Transmitter, Drive strength of 8mA on
the MSIO Bank
2.622
ns
Refer to page 20 for more
information
tCLKQ
Clock-to-Q of the Data Register
0.112
ns
Refer to page 51 for more
information
tSUD
Setup Time of the Data Register
0.263
ns
Refer to page 51 for more
information
tDP
Propagation Delay of a two input AND
gate
0.17
ns
Refer to page 60 for more
information
tOCLKQ
Clock-to-Q of the Output Data Register
0.273
ns
Refer to page 53 for more
information
tOSUD
Setup Time of the Output Data Register
0.197
ns
Refer to page 53 for more
information
Delay
Delay
of
of
a
LVDS
Notes
LVDS
L
M
N
Revision 1
10
IGLOO2 FPGA Automotive Grade 1
Table 16 • Timing Model Parameters (continued)
Index Parameter
Description
Speed
Grade –1
Units
Notes
O
tDP
Propagation Delay of SSTL2, Class I
Transmitter on the MSIO Bank
2.308
ns
Refer to page 36 for more
information
P
tDP
Propagation Delay of LVCMOS 1.5 V
Transmitter, Drive strength of 12mA, fast
slew on the DDRIO Bank
3.742
ns
Refer to page 27 for more
information
8. User I/O Characteristics
There are three types of I/Os supported in the IGLOO2 FPGA family: MSIO, MSIOD, and DDRIO I/O banks. The I/O
standards supported by the different I/O banks is described in the “I/Os” section of the UG0445: IGLOO2 FPGA and
SmartFusion2 SoC FPGA Fabric User Guide. For board design considerations, output slew rates extraction, detailed
output buffer resistances and I/V Curve use the corresponding IBIS models located at:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
8.1 Input Buffer and AC Loading
tPY
tPYS
PAD
Note: tPYS = Schmitt Trigger Input
Y
IN
tPY = MAX(tPY(R), tPY(F))
tPYS = MAX(tPYS(R), tPYS(F))
VIH
Vtrip
IN
Vtrip
VIL
VDD
50%
50%
Y
GND
tPY
tPY
(R)
(F)
tPYS
(R)
tPYS
(F)
Figure 3 • Input Buffer AC Loading
Revision 1
11
IGLOO2 FPGA Automotive Grade 1
8.2. Output Buffer and AC Loading
Single-Ended I/O Test Setup
HSTL/PCI Test Setup
tDP
tDP
PAD
OUT
D
VTT/VDDI
PAD
OUT
D
Rtt_test
Cload
Cload
tDP = MAX(tDP(R), tDP(F))
tDP = MAX(tDP(R), tDP(F))
Voltage-Referenced, Singled-Ended I/O Test Setup
tDP
D
VTT
OUT
PAD
Rtt_test
Cload
tDP = MAX(tDP(R), tDP(F))
Differential I/O Test Setup
tDP
OUT
tPY
PAD_P
PAD_P
D
IN
PAD_N
PAD_N
tPY = MAX(tPY(R), tPY(F))
tDP = MAX(tDP(R), tDP(F))
tPYS = MAX(tPYS(R), tPYS(F))
Figure 4 • Output Buffer AC Loading
Revision 1
12
IGLOO2 FPGA Automotive Grade 1
8.3. Tristate Buffer and AC Loading
The tristate path for enable path loadings is described in the respective specifications. The methodology of
characterization is illustrated by the enable path test point, as shown in Figure 5.
tZL, tZH, tHZ, tLZ
E
OUT
D
Rent to VDDI for tZL, tLZ
PAD
Cent tZL, tLZ, tZH, tHZ
Rent to GND for tZH, tHZ
Data
(D)
Enable
(E)
50%
tZL
PAD
50%
50%
tHZ
50%
tLZ
tZH
90% VDDI
90% VDDI
10% VDDI
10% VDDI
Figure 5 • Tristate Buffer for Enable Path Test Point
8.4 I/O Speeds
Table 17 • Maximum Data Rate Summary for Worst-Case Automotive Grade 1 Conditions
Single-Ended I/O
MSIO
MSIOD
DDRIO
Units
PCI 3.3 V
560
–
–
Mbps
LVTTL 3.3 V
540
–
–
Mbps
LVCMOS 3.3 V
540
–
–
Mbps
LVCMOS 2.5 V
360
370
360
Mbps
LVCMOS 1.8 V
260
360
360
Mbps
LVCMOS 1.5 V
140
190
210
Mbps
LVCMOS 1.2 V
100
140
180
Mbps
MSIO
MSIOD
DDRIO
Units
HSTL1.5 V
–
–
360
Mbps
SSTL 2.5 V
450
480
360
Mbps
SSTL 1.8 V
–
–
600
Mbps
SSTL 1.5 V
–
–
600
Mbps
Voltage-Referenced I/O
Revision 1
13
IGLOO2 FPGA Automotive Grade 1
Table 17 • Maximum Data Rate Summary for Worst-Case Automotive Grade 1 Conditions (continued)
Differential I/O
MSIO
MSIOD
DDRIO
Units
LVPECL (input only)
810
–
–
Mbps
LVDS 3.3 V
480
480
–
Mbps
LVDS 2.5 V
480
480
–
Mbps
RSDS
460
480
–
Mbps
BLVDS
450
–
–
Mbps
MLVDS
450
–
–
Mbps
Mini-LVDS
460
480
–
Mbps
Table 18 • Maximum Frequency Summary for Worst-Case Automotive Grade 1 Conditions
Single-Ended I/O
MSIO
MSIOD
DDRIO
Units
PCI 3.3 V
280
–
–
MHz
LVTTL 3.3 V
270
–
–
MHz
LVCMOS 3.3 V
270
–
–
MHz
LVCMOS 2.5 V
180
185
180
MHz
LVCMOS 1.8 V
130
180
180
MHz
LVCMOS 1.5 V
70
95
105
MHz
LVCMOS 1.2 V
50
70
90
MHz
MSIO
MSIOD
DDRIO
Units
HSTL1.5 V
–
–
180
MHz
SSTL 2.5 V
225
240
180
MHz
SSTL 1.8 V
–
–
300
MHz
SSTL 1.5 V
–
–
300
MHz
MSIO
MSIOD
DDRIO
Units
LVPECL (input only)
405
–
–
MHz
LVDS 3.3 V
240
240
–
MHz
LVDS 2.5 V
240
240
–
MHz
RSDS
230
240
–
MHz
BLVDS
225
–
–
MHz
MLVDS
225
–
–
MHz
Mini-LVDS
230
240
–
MHz
Voltage-Referenced I/O
Differential I/O
Revision 1
14
IGLOO2 FPGA Automotive Grade 1
8.5. Detailed I/O Characteristics
Table 19 • Input Capacitance and Leakage Current
Symbol
Definition
Min
Max
Units
CIN
Input Capacitance
–
10
pF
IIL (dc)
Input Current LOW
(Applicable to all digital inputs)
–
10
uA
IIH (dc)
Input Current HIGH
(Applicable to all digital inputs)
–
10
uA
Table 20 • I/O Weak Pull-Up/Pull-Down Resistance Values for DDRIO, MSIO, and MSIOD Banks
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values at VOH/VOL Level
VDDI
Domain
DDRIO I/O Bank
MSIO I/O Bank
MSIOD I/O Bank
R(WEAK
R(WEAK
R(WEAK
R(WEAK
R(WEAK
R(WEAK
PULL-UP)
PULL-DOWN)
PULL-UP)
PULL-DOWN)
PULL-UP)
PULL-DOWN)
at VOH ()
at VOL ()
at VOH ()
at VOL ()
at VOH ()
at VOL ()
Min
Max
Min
Max
Min
3.3 V
N/A
N/A
N/A
N/A
9.9 K
2.5 V
10 K
Min
Max
Min
Max
Notes
17.1 K 9.98 K 17.5 K
N/A
N/A
N/A
N/A
–
18 K
10 K
17.6 K 10.1 K 18.4 K
9.6 K
16.6 K 9.5 K 16.4 K
1, 2
1.8 V
10.3 K 19.1 K 10.3 K 19.5 K 10.4 K 19.1 K 10.4 K 20.4 K
9.7 K
17.3 K 9.7 K 17.1 K
1, 2
1.5 V
10.6 K 20.2 K 10.6 K 21.1 K 10.7 K 20.4 K 10.8 K 22.2 K
9.9 K
9.8 K 17.6 K
1,2
1.2 V
11.1 K 22.7 K 11.2 K 24.6 K 11.3 K 23.2 K 11.5 K 26.7 K 10.3 K 19.6 K 10 K 19.1 K
1, 2
17.8 K 9.98 K
Max
Min
Max
18 K
Notes:
1. R(WEAK PULL-DOWN) = (VOLspec)/I(WEAK PULL-DOWN MAX)
2. R(WEAK PULL-UP) = (VDDImax - VOHspec)/I(WEAK PULL-UP MIN)
Table 21 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value for Schmitt Trigger Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (Typical, unless otherwise noted)
3.3 V LVTTL / LVCMOS / PCI / PCI-X
0.05 × VDDI (Worst-case)
2.5 V LVCMOS
0.05 × VDDI (Worst-case)
1.8 V LVCMOS
0.1 × VDDI (Worst-case)
1.5 V LVCMOS
60 mV
1.2 V LVCMOS
20 mV
8.6 Single-Ended I/O Standards
8.6.1 Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined by JEDEC
(JESD 8-5). The LVCMOS standards supported in IGLOO2 FPGAs are: LVCMOS12, LVCMOS15, LVCMOS18,
LVCMOS25, and LVCMOS33.
Revision 1
15
IGLOO2 FPGA Automotive Grade 1
8.6.2 3.3 V LVCMOS/LVTTL
LVCMOS 3.3 V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3 V applications.
8.6.2.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 22 • LVTTL/LVCMOS 3.3 V DC Voltage Specification (Applicable to MSIO I/O Bank Only)
Symbol
Parameters
Min
Typ
Max
Units
Notes
3.3
3.45
V
–
LVTTL/LVCMOS 3.3 V Recommended DC Operating Conditions
VDDI
Supply voltage
3.15
LVTTL/LVCMOS 3.3 V DC Input Voltage Specification
VIH (DC)
DC input logic High
2.0
–
3.45
V
–
VIL (DC)
DC input logic Low
–0.3
–
0.8
V
–
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
–
LVCMOS 3.3 V DC Output Voltage Specification
VOH
DC output logic High
2.4
–
–
V
*
VOL
DC output logic Low
–
–
0.4
V
*
LVTTL 3.3 V DC Output Voltage Specification
VOH
DC output logic High
2.4
–
–
V
–
VOL
DC output logic Low
–
–
0.4
V
–
Note: * The VOH/VOL test points selected ensure compliance with LVCMOS 3.3 V JESD8-B requirements.
Table 23 • LVTTL/LVCMOS 3.3 V Maximum Switching Speeds (Applicable to MSIO I/O Bank Only)
Symbol
Parameters
Conditions
Min
Typ
Max
Units
–
–
540
Mbps
LVTTL/LVCMOS 3.3 V Maximum Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load, maximum
drive/slew
Table 24 • LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications (Applicable to MSIO Bank Only)
LVTTL/LVCMOS 3.3 V AC Test Parameter Specifications
Symbol
Parameters
Min
Typ
Max
Units
Vtrip
Measuring/trip point for data path
–
1.4
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Table 25 • LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications
(Applicable to MSIO Bank* Only)
Output Drive Selection
VOH (V)
VOL (V)
IOH (at VOH) mA
IOL (at VOL) mA
2 mA
2.4
0.4
2
2
4 mA
2.4
0.4
4
4
8 mA
2.4
0.4
8
8
Revision 1
16
IGLOO2 FPGA Automotive Grade 1
Table 25 • LVTTL/LVCMOS 3.3 V Transmitter Drive Strength Specifications
(Applicable to MSIO Bank* Only) (continued)
Output Drive Selection
VOH (V)
VOL (V)
IOH (at VOH) mA
IOL (at VOL) mA
12 mA
2.4
0.4
12
12
16 mA
2.4
0.4
16
16
20 mA
2.4
0.4
18
18
Note: * Software Configurator GUI displays the Commercial/Industrial numeric values. The actual drive capability at
temperature is defined in Table 25.
8.6.2.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 26 • LVTTL/LVCMOS 3.3 V Receiver Characteristics for MSIO I/O Banks (Input Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
On-Die Termination
(ODT) in 
tPY
tPYS
Units
None
2.435
2.463
ns
LVTTL/LVCMOS 3.3 V (for MSIO I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 27 • LVTTL/LVCMOS 3.3 V Transmitter Characteristics for MSIO I/O Bank (Output and Tristate Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
Output Drive Selection
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
2 mA
slow
3.552
3.867
3.277
4.402
2.954
ns
4 mA
slow
2.591
2.979
2.804
5.181
3.013
ns
8 mA
slow
2.373
2.596
2.555
4.794
3.035
ns
12 mA
slow
2.284
2.349
2.411
4.967
3.041
ns
16 mA
slow
2.298
2.311
2.394
5.007
3.058
ns
20 mA
slow
2.396
2.23
2.33
5.153
3.088
ns
8.6.3 2.5 V LVCMOS
LVCMOS 2.5 V is a general standard for 2.5 V applications and is supported in IGLOO2 FPGAs in compliance to the
JEDEC specification JESD8-5A.
8.6.3.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 28 • LVCMOS 2.5 V DC Voltage Specification
Symbol
Parameters
Min
Typ
Max
Units
Notes
2.375
2.5
2.625
V
–
1.7
–
2.625
V
–
LVCMOS 2.5 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVCMOS 2.5 V DC Input Voltage Specification
VIH (DC)
DC input logic High (for MSIOD and
DDRIO I/O Bank)
Note: * The VOH/VOL test points selected ensure compliance with LVCMOS 2.5 V JEDEC8-5A requirements.
Revision 1
17
IGLOO2 FPGA Automotive Grade 1
Table 28 • LVCMOS 2.5 V DC Voltage Specification (continued)
Symbol
Parameters
Min
Typ
Max
Units
Notes
VIH (DC)
DC input logic High (for MSIO I/O
Bank)
1.7
–
2.75
V
–
VIL (DC)
DC input logic Low
–0.3
–
0.7
V
–
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
–
LVCMOS 2.5 V DC Output Voltage Specification
VOH
DC output logic High
1.7
–
–
V
*
VOL
DC output logic Low
–
–
0.7
V
*
Note: * The VOH/VOL test points selected ensure compliance with LVCMOS 2.5 V JEDEC8-5A requirements.
Table 29 • LVCMOS 2.5 V Maximum AC Switching Speeds
Symbol
Parameters
Conditions
Min
Typ
Max
Units
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
360
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
360
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
370
Mbps
Table 30 • LVCMOS 2.5 V AC Test Parameters and Driver Impedance Specifications
Symbols
Parameters
Min
Typ
Max
Units
–
75, 60, 50,
33, 25, 20
–

LVCMOS 2.5 V Calibrated Impedance Option
Supported output driver calibrated
impedance (for DDRIO I/O Bank)
Rodt_cal
LVCMOS 2.5 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
1.2
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Table 31 • LVCMOS 2.5 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIO
MSIOD
I/O Bank
DDRIO I/O Bank
(With Software Default
Fixed Code)
VOH (V)
Min
VOL (V)
Max
OH (at VOH)
mA
OL (at VOL)
mA
2 mA
2 mA
2 mA
1.7
0.7
2
2
4 mA
4 mA
4 mA
1.7
0.7
4
4
6 mA
6 mA
6 mA
1.7
0.7
6
6
8 mA
8 mA
8 mA
1.7
0.7
8
8
I/O Bank
Revision 1
18
IGLOO2 FPGA Automotive Grade 1
Table 31 • LVCMOS 2.5 V Transmitter Drive Strength Specifications (continued)
Output Drive Selection
MSIO
MSIOD
I/O Bank
DDRIO I/O Bank
(With Software Default
Fixed Code)
VOH (V)
Min
VOL (V)
Max
OH (at VOH)
mA
OL (at VOL)
mA
12 mA
12 mA
12 mA
1.7
0.7
12
12
16 mA
N/A
16 mA
1.7
0.7
16
16
I/O Bank
8.6.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 32 • LVCMOS 2.5 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
On-Die Termination
(ODT) in 
tPY
tPYS
Units
LVCMOS 2.5 V (for DDRIO I/O Bank)
None
1.915
2.034
ns
LVCMOS 2.5 V (for MSIO I/O Bank)
None
2.71
2.719
ns
LVCMOS 2.5 V (for MSIOD I/O Bank)
None
2.465
2.479
ns
Revision 1
19
IGLOO2 FPGA Automotive Grade 1
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 33 • LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Output Drive
Selection
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
LVCMOS 2.5 V (for DDRIO I/O Bank with Fixed Codes)
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
slow
4.009
3.703
4.028
3.441
3.005
ns
medium
3.664
3.416
3.686
2.98
2.545
ns
medium_fast
3.522
3.293
3.544
2.728
2.328
ns
fast
3.495
3.287
3.517
2.707
2.307
ns
slow
3.407
2.973
3.398
3.536
3.184
ns
medium
3.096
2.73
3.091
3.055
2.645
ns
medium_fast
2.957
2.593
2.951
2.761
2.381
ns
fast
2.941
2.586
2.936
2.748
2.361
ns
slow
3.223
2.744
3.202
3.664
3.279
ns
medium
2.917
2.499
2.906
3.13
2.689
ns
medium_fast
2.778
2.38
2.767
2.819
2.414
ns
fast
2.76
2.37
2.748
2.794
2.388
ns
slow
3.166
2.674
3.142
3.709
3.332
ns
medium
2.862
2.432
2.85
3.159
2.715
ns
medium_fast
2.727
2.316
2.714
2.836
2.434
ns
fast
2.713
2.306
2.699
2.816
2.417
ns
slow
3.045
2.53
3.016
3.7598
3.327
ns
medium
2.749
2.308
2.735
3.193
2.709
ns
medium_fast
2.62
2.198
2.605
2.848
2.436
ns
fast
2.608
2.189
2.593
2.823
2.42
ns
slow
2.967
2.441
2.933
3.859
3.428
ns
medium
2.689
2.229
2.673
3.241
2.77
ns
medium_fast
2.563
2.125
2.546
2.896
2.48
ns
fast
2.55
2.115
2.532
2.869
2.457
ns
LVCMOS 2.5 V (for MSIO I/O Bank)
2 mA
slow
3.975
4.398
4.265
5.147
3.257
ns
4 mA
slow
2.937
3.459
3.545
5.662
3.313
ns
6 mA
slow
2.716
3.027
3.188
5.714
3.342
ns
8 mA
slow
2.622
2.908
3.102
6.003
3.336
ns
12 mA
slow
2.651
2.761
2.975
5.978
3.34
ns
16 mA
slow
2.746
2.645
2.87
6.188
3.375
ns
Revision 1
20
IGLOO2 FPGA Automotive Grade 1
Table 33 • LVCMOS 2.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V (continued)
Speed Grade
–1
Output Drive
Selection
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
LVCMOS 2.5 V (for MSIOD I/O Bank)
2 mA
slow
2.428
2.953
2.921
2.5
2.401
ns
4 mA
slow
2.018
2.472
2.495
2.506
2.399
ns
6 mA
slow
1.88
2.354
2.401
2.551
2.437
ns
8 mA
slow
1.799
2.168
2.232
2.594
2.466
ns
12 mA
slow
1.823
2.061
2.131
2.619
2.475
ns
8.6.4 1.8 V LVCMOS
LVCMOS 1.8 is a general standard for 1.8 V applications and is supported in IGLOO2 FPGAs in compliance to the
JEDEC specification JESD8-7A.
8.6.4.1 Minimum and Maximum AC/DC Input and Output Levels
Table 34 • LVCMOS 1.8 V DC Voltage Specification
Symbols
Parameters
Min
Typ
Max
Units
1.710
1.8
1.89
V
Recommended DC Operating Conditions
VDDI
Supply Voltage
LVCMOS 1.8 V DC Input Voltage Specification
VIH(DC)
DC input Logic HIGH (for MSIOD and
0.65 x VDDI
DDRIO I/O Banks)
–
1.89
V
VIH(DC)
DC input Logic HIGH (for MSIO I/O
0.65 x VDDI
Bank)
–
2.75
V
VIL(DC)
DC input Logic LOW
–
0.35 × VDDI
V
IIH(DC)
Input Current HIGH
Refer to Table 19 on page 15
–
IIL(DC)
Input Current LOW
Refer to Table 19 on page 15
–
-0.3
LVCMOS 1.8 V DC Output Voltage Specification
VOH
DC output Logic HIGH
VDDI - 0.45
–
–
V
VOL
DC output Logic LOW
–
–
0.45
V
Table 35 • LVCMOS 1.8 V Maximum AC Switching Speeds
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVCMOS 1.8 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
360
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
260
Mbps
Revision 1
21
IGLOO2 FPGA Automotive Grade 1
Table 35 • LVCMOS 1.8 V Maximum AC Switching Speeds (continued)
Symbols
Dmax
Parameters
Conditions
Min
Typ
Max
Units
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
360
Mbps
Note: * Maximum data rate applies for drive strength 8mA and above, all slews
Table 36 • LVCMOS 1.8 V Transmitter Drive Strength Specifications
Output Drive Selection
VOH (V)
VOL (V)
MSIOD I/O Bank
Min
Max
IOH (at VOH) mA
IOL (at VOL) mA
2 mA
2 mA
VDDI – 0.45
0.45
2
2
4 mA
4 mA
VDDI – 0.45
0.45
4
4
6 mA
6 mA
VDDI – 0.45
0.45
6
6
8 mA
8 mA
VDDI – 0.45
0.45
8
8
10 mA
10 mA
VDDI – 0.45
0.45
10
10
12 mA
N/A
VDDI – 0.45
0.45
12
12
MSIO I/O
Bank
Table 37 • LVCMOS 1.8 V Transmitter Drive Strength Specifications
Output Drive
Selection
VOH (V)
VOL (V)
DDRIO Bank*
Min
Max
2 mA
VDDI – 0.45
0.45
2
2
–
4 mA
VDDI – 0.45
0.45
4
4
–
6 mA
VDDI – 0.45
0.45
6
6
**
8 mA
VDDI – 0.45
0.45
6
6
**
10 mA
VDDI – 0.45
0.45
8
8
–
12 mA
VDDI – 0.45
0.45
10
10
–
16 mA
VDDI – 0.45
0.45
12
12
–
IOH (at VOH) mA IOL (at VOL) mA
Notes
Notes:
* Software Configurator GUI will display the Commercial/Industrial numeric values. The actual drive capability at
temperature is defined by Table 37.
** DDRIO has two 6mA drive strength settings. The setting that corresponds to Output Drive Selection value of 8mA
has a shorter propagation delay.
Revision 1
22
IGLOO2 FPGA Automotive Grade 1
Table 38 • LVCMOS 1.8 V AC Test Parameters and Driver Impedance Specifications
LVCMOS 1.8 V AC Calibrated Impedance Option
Symbols
Rodt_cal
Parameters
Supported output driver
impedance
(for DDRIO I/O Bank)
Min
Typ
Max
Units
–
75, 60, 50, 33,
25, 20
–

calibrated
LVCMOS 1.8 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.9
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
8.6.4.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 39 • LVCMOS 1.8 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.71 V
LVCMOS 1.8 V
(for DDRIO I/O Bank with Fixed Codes)
LVCMOS 1.8 V (for MSIO I/O Bank)
LVCMOS 1.8 V (for MSIOD I/O Bank)
Speed Grade
–1
ODT
(On Die Termination) in 
tPY
tPYS
Units
None
2.085
2.228
ns
None
3.212
3.197
ns
50
3.423
3.425
ns
75
3.35
3.343
ns
150
3.279
3.266
ns
None
2.85
2.835
ns
50
3.068
3.077
ns
75
2.991
2.987
ns
150
2.921
2.909
ns
Revision 1
23
IGLOO2 FPGA Automotive Grade 1
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 40 • LVCMOS 1.8 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.71 V
Speed Grade
–1
Output Drive Selection
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
slow
4.73
4.06
4.739
4.286
3.607
ns
medium
4.255
3.637
4.264
3.752
3.177
ns
medium_fast
4.02
3.428
4.028
3.413
2.896
ns
fast
3.994
3.409
4.003
3.385
2.874
ns
slow
4.401
3.696
4.393
4.402
3.802
ns
medium
3.927
3.281
3.921
3.828
3.24
ns
medium_fast
3.694
3.082
3.686
3.468
2.93
ns
fast
3.673
3.065
3.665
3.441
2.908
ns
slow
4.148
3.458
4.136
4.455
3.808
ns
medium
3.719
3.082
3.707
3.856
3.228
ns
medium_fast
3.513
2.898
3.5
3.484
2.934
ns
fast
3.487
2.879
3.474
3.45
2.909
ns
slow
4.057
3.355
4.04
4.528
3.894
ns
medium
3.627
2.978
3.612
3.895
3.272
ns
medium_fast
3.419
2.79
3.402
3.506
2.957
ns
fast
3.392
2.775
3.376
3.476
2.932
ns
slow
3.928
3.214
3.905
4.661
4.012
ns
medium
3.522
2.852
3.504
3.968
3.341
ns
medium_fast
3.315
2.67
3.295
3.545
2.997
ns
fast
3.292
2.655
3.272
3.521
2.967
ns
slow
3.835
3.129
3.813
4.621
3.957
ns
medium
3.444
2.793
3.425
3.95
3.31
ns
medium_fast
3.249
2.626
3.228
3.536
2.98
ns
fast
3.229
2.611
3.208
3.505
2.959
ns
slow
3.783
3.068
3.758
4.723
4.059
ns
medium
3.393
2.74
3.374
3.99
3.354
ns
medium_fast
3.209
2.573
3.186
3.567
3.007
ns
fast
3.189
2.558
3.166
3.531
2.986
ns
2 mA
slow
4
4.836
5.078
7.67
3.997
ns
4 mA
slow
3.707
4.207
4.534
7.71
4.018
ns
6 mA
slow
3.624
4.038
4.405
8.173
4.026
ns
LVCMOS 1.8 V (for DDRIO I/O Bank with Fixed Codes)
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
LVCMOS 1.8 V (for MSIO I/O Bank)
Revision 1
24
IGLOO2 FPGA Automotive Grade 1
Table 40 • LVCMOS 1.8 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.71 V (continued)
Speed Grade
–1
Output Drive Selection
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
8 mA
slow
3.654
3.823
4.207
8.251
4.03
ns
10 mA
slow
3.701
3.772
4.165
8.319
4.077
ns
12 mA
slow
3.79
3.654
4.05
8.413
4.156
ns
2 mA
slow
3.08
3.732
3.939
2.997
2.947
ns
4 mA
slow
2.527
3.121
3.323
3.075
2.948
ns
6 mA
slow
2.248
2.776
2.968
3.129
2.991
ns
8 mA
slow
2.257
2.749
2.934
3.164
3.016
ns
10 mA
slow
2.287
2.604
2.788
3.193
3.027
ns
LVCMOS 1.8 V (for MSIOD I/O Bank)
8.6.5 1.5 V LVCMOS
LVCMOS 1.5 is a general standard for 1.5 V applications and is supported in IGLOO2 FPGAs in compliance to the
JEDEC specification JESD8-11A.
8.6.5.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 41 • LVCMOS 1.5 V Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Min
Typ
Max
Units
1.425
1.5
1.575
V
LVCMOS 1.5 V Recommended DC Operating Conditions
VDDI
Supply voltage
LVCMOS 1.5 V DC Input Voltage Specification
VIH (DC)
DC input logic High for (MSIOD and DDRIO I/O banks)
0.65 × VDDI
–
1.575
V
VIH (DC)
DC input logic High (for MSIO I/O Bank)
0.65 × VDDI
–
2.75
V
VIL (DC)
DC input logic Low
–0.3
–
0.35 × VDDI
V
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
IIL (DC
Input current Low
Refer to Table 19 on page 15
–
LVCMOS 1.5 V DC Output Voltage Specification
VOH
DC output logic High
VDDI × 0.75
–
–
V
VOL
DC output logic Low
–
–
VDDI × 0.25
V
Conditions
Min
Typ
Max
Units
Table 42 • LVCMOS 1.5 V Maximum AC Switching Speeds
Symbols
Parameters
LVCMOS 1.5 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
210
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
140
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
190
Mbps
Revision 1
25
IGLOO2 FPGA Automotive Grade 1
Table 43 • LVCMOS 1.5 V AC Test Parameters and Driver Impedance Specifications
Symbols
Parameters
Min
Typ
Max
Units
–
75, 60, 50,
40
–

–
0.75
–
V
–
2k
–

LVCMOS 1.5 V AC Calibrated Impedance Option
Rodt_cal
Supported output driver calibrated
impedance (for DDRIO I/O Bank)
LVCMOS 1.5 V AC Test Parameters Specifications
Vtrip
Rent
Measuring/trip point for data path
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Table 44 • LVCMOS 1.5 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIO I/O Bank
VOH (V)
VOL (V)
Min
Max
DDRIO I/O Bank
MSIOD I/O Bank (with Fixed Code)
IOH (at VOH) IOL (at VOL)
mA
mA
2 mA
2 mA
2 mA
VDDI × 0.75
VDDI × 0.25
2
2
4 mA
4 mA
4 mA
VDDI × 0.75
VDDI × 0.25
4
4
6 mA
6 mA
6 mA
VDDI × 0.75
VDDI × 0.25
6
6
8 mA
N/A
8 mA
VDDI × 0.75
VDDI × 0.25
8
8
N/A
N/A
10 mA
VDDI × 0.75
VDDI × 0.25
10
10
N/A
N/A
12 mA
VDDI × 0.75
VDDI × 0.25
12
12
8.6.5.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 45 • LVCMOS 1.5 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.425 V
Speed Grade
–1
LVCMOS 1.5 V (for DDRIO I/O Bank
with Fixed Codes)
LVCMOS 1.5 V (for MSIO I/O Bank)
LVCMOS 1.5 V (for MSIOD I/O Bank)
ODT (On Die Termination)
in 
tPY
tPYS
Units
None
2.205
2.232
ns
None
3.711
3.684
ns
50
4.189
4.163
ns
75
4.019
3.988
ns
150
3.857
3.824
ns
None
3.289
3.255
ns
50
3.792
3.771
ns
75
3.585
3.55
ns
150
3.423
3.387
ns
Revision 1
26
IGLOO2 FPGA Automotive Grade 1
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 46 • LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.425 V
Output Drive
Selection
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
LVCMOS 1.5 V (for DDRIO I/O Bank with Fixed Codes)
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
slow
5.774
4.847
5.796
4.791
4.916
ns
medium
5.149
4.32
5.168
4.382
3.638
ns
medium_fast
4.844
4.055
4.861
4.033
3.382
ns
fast
4.813
4.022
4.831
3.995
3.361
ns
slow
5.019
4.177
5.008
4.998
4.184
ns
medium
4.459
3.658
4.447
4.457
3.764
ns
medium_fast
4.189
3.394
4.175
4.08
3.451
ns
fast
4.16
3.374
4.146
4.051
3.425
ns
slow
4.795
3.911
4.778
5.201
4.416
ns
medium
4.257
3.418
4.239
4.56
3.831
ns
medium_fast
3.993
3.168
3.972
4.139
3.484
ns
fast
3.961
3.143
3.94
4.1
3.456
ns
slow
4.652
3.73
4.633
5.247
4.461
ns
medium
4.125
3.276
4.105
4.575
3.826
ns
medium_fast
3.869
3.047
3.844
4.154
3.485
ns
fast
3.845
3.026
3.821
4.12
3.459
ns
slow
4.568
3.65
4.547
5.352
4.559
ns
medium
4.069
3.211
4.047
4.645
3.876
ns
medium_fast
3.816
2.98
3.79
4.182
3.509
ns
fast
3.787
2.96
3.761
4.145
3.481
ns
slow
4.504
3.6
4.48
5.389
4.644
ns
medium
4.007
3.163
3.985
4.657
3.917
ns
medium_fast
3.771
2.943
3.743
4.199
3.531
ns
fast
3.742
2.923
3.715
4.163
3.501
ns
LVCMOS 1.5 V (for MSIO I/O Bank)
2 mA
slow
5.172
6.329
6.599
9.361
4.697
ns
4 mA
slow
4.707
5.233
5.71
10.259
4.757
ns
6 mA
slow
4.743
4.942
5.446
10.308
4.743
ns
8 mA
slow
4.928
4.712
5.237
10.738
4.811
ns
Revision 1
27
IGLOO2 FPGA Automotive Grade 1
Table 46 • LVCMOS 1.5 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.425 V (continued)
Output Drive
Selection
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
LVCMOS 1.5 V (for MSIOD I/O Bank)
2 mA
slow
3.117
3.835
4.129
3.622
3.514
ns
4 mA
slow
2.76
3.401
3.67
3.718
3.557
ns
6 mA
slow
2.771
3.196
3.453
3.762
3.586
ns
8.6.6 1.2 V LVCMOS
LVCMOS 1.2 is a general standard for 1.2 V applications and is supported in IGLOO2 FPGAs in compliance to the
JEDEC specification JESD8-12A.
8.6.6.1 Minimum and Maximum Input and Output Levels Specification
Table 47 • LVCMOS 1.2 V Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Min
Typ
Max
Units
1.140
1.2
1.26
V
LVCMOS 1.2 V Recommended DC Operating Conditions
VDDI
Supply
voltage
LVCMOS 1.2 V DC Input Voltage Specification
VIH (DC)
DC input logic High (for MSIOD and
DDRIO I/O Banks)
0.65 × VDDI
–
1.26
V
VIH (DC)
DC input logic High (for MSIO I/O
Bank)
0.65 × VDDI
–
2.75
V
VIL (DC)
DC input logic Low
–0.3
–
0.35 × VDDI
V
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
LVCMOS 1.2 V DC Output Voltage Specification
VOH
DC output logic High
VDDI × 0.75
–
–
V
VOL
DC output logic Low
–
–
VDDI × 0.25
V
Table 48 • LVCMOS 1.2 V Maximum AC Switching Speeds
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVCMOS 1.2 V Maximum AC Switching Speed
Dmax
Maximum data rate
(for DDRIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
180
Mbps
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
100
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 17 pF load,
maximum drive/slew
–
–
140
Mbps
Revision 1
28
IGLOO2 FPGA Automotive Grade 1
Table 49 • LVCMOS 1.2 V AC Calibrated Impedance and Test Parameters Specifications
Symbols
Parameters
Min
Typ
Max
Units
–
75, 60,
50, 40
–

LVCMOS 1.2 V AC Calibrated Impedance Option
Rodt_cal
Supported output driver calibrated
impedance
(for DDRIO I/O Bank)
LVCMOS 1.2 V AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
0.6
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
2k
–

Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
5
–
pF
Cload
Capacitive loading for data path (tDP)
–
5
–
pF
Table 50 • LVCMOS 1.2 V Transmitter Drive Strength Specifications
Output Drive Selection
MSIO I/O Bank
VOH (V)
VOL (V)
Min
Max
DDRIO I/O Bank
MSIOD I/O Bank (with Fixed Code)
IOH (at VOH)
mA
IOL (at VOL)
mA
2 mA
2 mA
2 mA
VDDI × 0.75 VDDI × 0.25
2
2
4 mA
4 mA
4 mA
VDDI × 0.75 VDDI × 0.25
4
4
N/A
6 mA
VDDI × 0.75 VDDI × 0.25
6
6
N/A
8.6.6.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 51 • LVCMOS 1.2 V AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.14 V
LVCMOS 1.2 V (for DDRIO I/O Bank
with Fixed Codes)
LVCMOS 1.2 V (for MSIO I/O Bank)
LVCMOS 1.2 V (for MSIOD I/O Bank)
Speed Grade
–1
ODT (On Die Termination)
in 
tPY
tPYS
Units
None
2.557
2.574
ns
None
4.932
4.889
ns
50
6.746
6.667
ns
75
5.978
5.901
ns
150
5.339
5.283
ns
None
4.32
4.273
ns
50
6.872
6.786
ns
75
5.697
5.616
ns
150
4.857
4.797
ns
Revision 1
29
IGLOO2 FPGA Automotive Grade 1
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 52 • LVCMOS 1.2 V AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.14 V
Output Drive
Selection
Speed Grade
–1
Slew Control
tDP
tZL
tZH
tHZ
tLZ
Units
LVCMOS 1.2 V (for DDRIO I/O Bank with Fixed Code)
2 mA
4 mA
6 mA
slow
7.012
5.659
7.022
6.507
6.722
ns
medium
6.175
4.866
6.179
5.889
4.819
ns
medium_fast
5.736
4.456
5.737
5.383
4.462
ns
fast
5.693
4.426
5.694
5.348
4.431
ns
slow
6.395
4.944
6.384
6.788
5.663
ns
medium
5.597
4.237
5.58
5.998
4.959
ns
medium_fast
5.173
3.873
5.152
5.456
4.534
ns
fast
5.126
3.846
5.105
5.414
4.499
ns
slow
6.157
4.731
6.14
7.009
5.877
ns
medium
5.399
4.058
5.377
6.123
5.034
ns
medium_fast
5.002
3.699
4.974
5.508
4.574
ns
fast
4.955
3.661
4.928
5.449
4.533
ns
LVCMOS 1.2 V (for MSIO I/O Bank)
2 mA
slow
7.126
7.94
8.633
13.977
6.504
ns
4 mA
slow
7.464
7.102
7.898
15.496
6.708
ns
LVCMOS 1.2 V (for MSIOD I/O Bank)
2 mA
slow
4.091
5.178
5.612
4.995
4.792
ns
4 mA
slow
3.982
4.453
4.866
5.064
4.859
ns
8.6.7 3.3 V PCI/PCIX
Peripheral Component Interface (PCI) for 3.3 V standards specify support for 33 MHz and 66 MHz PCI bus
applications.
8.6.7.1 Minimum and Maximum Input and Output Levels Specification
Table 53 • PCI/PCI-X DC Voltage Specification (Applicable to MSIO Bank Only)
Symbols
Parameters
Min
Typ
Max
Units
3.15
3.3
3.45
V
0
–
3.45
V
PCI/PCIX Recommended DC Operating Conditions
VDDI
Supply voltage
PCI/PCIX DC Input Voltage Specification
VI
DC input voltage
IIH(DC)
Input current High
Refer to Table 19 on page 15
–
IIL(DC)
Input current Low
Refer to Table 19 on page 15
–
Revision 1
30
IGLOO2 FPGA Automotive Grade 1
Table 53 • PCI/PCI-X DC Voltage Specification (Applicable to MSIO Bank Only) (continued)
Symbols
Parameters
Min
Typ
Max
Units
PCI/PCIX DC Output Voltage Specification
VOH
DC output logic High
Per PCI Specification
V
VOL
DC output logic Low
Per PCI Specification
V
Table 54 • PCI/PCI-X AC Specifications (Applicable to MSIO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
560
Mbps
PCI/PCI-X AC Specifications
Dmax
Maximum data rate (MSIO I/O AC Loading: per JEDEC
Bank)
specifications
PCI/PCI-X AC Test Parameters Specifications
Vtrip
Measuring/trip point for data
path (falling edge)
–
–
0.615 × VDDI
–
V
Vtrip
Measuring/trip point for data
path (rising edge)
–
–
0.285 × VDDI
–
V
Rtt_test
Resistance for data test path
–
–
25
–

Rent
Resistance for enable path (tZH,
tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable
path (tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
Cload
Capacitive loading for data path
(tDP)
–
–
10
–
pF
8.6.7.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 55 • PCI/PCIX AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
ODT
(On Die Termination)
in 
tPY
tPYS
Units
None
2.397
2.405
ns
PCI/PCIX
(for MSIO I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 56 • PCI/PCIX AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
PCI/PCIX (for MSIO I/O Bank)
tDP
tZL
tZH
tHZ
tLZ
Units
2.419
2.298
2.34
5.371
2.333
ns
Revision 1
31
IGLOO2 FPGA Automotive Grade 1
8.7. Voltage Referenced I/O Standards
8.7.1 High-Speed Transceiver Logic (HSTL)
The High-Speed Transceiver Logic (HSTL) standard is a general purpose high-speed bus standard sponsored by IBM
(EIA/JESD8-6). IGLOO2 FPGA devices support two classes of the 1.5 V HSTL. These differential versions of the
standard require a differential amplifier input buffer and a push-pull output buffer.
8.7.1.1 Minimum and Maximum Input and Output Levels Specification
Table 57 • HSTL DC Voltage Specification (Applicable to DDRIO I/O Bank Only)
Symbols
Parameters
Min
Typ
Max
Units
HSTL Recommended DC Operating Conditions
VDDI
Supply voltage
1.425
1.5
1.575
V
VTT
Termination voltage
0.698
0.750
0.803
V
VREF
Input reference voltage
0.698
0.750
0.803
V
HSTL DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF + 0.1
–
1.575
V
VIL (DC)
DC input logic Low
–0.3
–
VREF – 0.1
V
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
HSTL DC Output Voltage Specification
HSTL Class I
VOH
DC output logic High
VDDI – 0.4
–
–
V
VOL
DC output logic Low
–
–
0.4
V
IOH at VOH
Output
current
–7.0
–
–
mA
IOL at VOL
Output minimum sink current
7.0
–
–
mA
minimum
source
DC
HSTL Class II
VOH
DC output logic High
VDDI – 0.4
–
–
V
VOL
DC output logic Low
–
–
0.4
V
IOH at VOH
Output
current
–15.0
–
–
mA
IOL at VOL
Output minimum sink current
15.0
–
–
mA
0.2
–
–
V
minimum
source
DC
HSTL DC Differential Voltage Specifications
VID (DC)
DC input differential voltage
Table 58 • HSTL AC Specifications (Applicable to DDRIO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
HSTL AC Differential Voltage Specifications
VDIFF
AC input differential voltage
–
0.4
–
–
V
Vx
AC differential cross point voltage
–
0.68
–
0.9
V
Revision 1
32
IGLOO2 FPGA Automotive Grade 1
Table 58 • HSTL AC Specifications (Applicable to DDRIO Bank Only) (continued)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
360
Mbps
HSTL Maximum AC Switching Speed
Dmax
AC loading:
specifications
Maximum data rate
per
JEDEC
HSTL Impedance Specification
Rref
Supported output driver calibrated
Reference resistance = 191 
impedance (for DDRIO I/O Bank)
–
25.5,
47.8
–

RTT
Effective impedance value (ODT for
Reference resistance = 191 
DDRIO I/O Bank only)
–
47.8
–

HSTL AC Test Parameters Specification
Vtrip
Measuring/trip point for data path
–
–
0.75
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
Rtt_test
Reference resistance for data test
path for HSTL15 Class I (tDP)
–
–
50
–

Rtt_test
Reference resistance for data test
path for HSTL15 Class II (tDP)
–
–
25
–

Cload
Capacitive loading for data path
(tDP)
–
–
5
–
pF
8.7.1.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 59 • HSTL15 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.425 V
tPY
ODT (On Die Termination)
in 
Speed Grade
–1
Units
HSTL (for DDRIO I/O Bank with Fixed Code)
Pseudo-Differential
None
1.683
ns
True-Differential
None
1.703
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 60 • HSTL 15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.425 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.953
2.941
2.935
3.375
2.808
ns
Differential
2.937
2.786
2.785
5.796
4.844
ns
HSTL Class I (for DDRIO I/O Bank)
Revision 1
33
IGLOO2 FPGA Automotive Grade 1
Table 60 • HSTL 15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.425 V (continued)
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.847
2.764
2.764
4.628
4.128
ns
Differential
2.857
2.84
2.833
3.402
2.826
ns
HSTL Class II (for DDRIO I/O Bank)
8.7.2 Stub-Series Terminated Logic
Stub-Series Terminated Logic (SSTL) for 2.5 V (SSTL2), 1.8 V (SSTL18), and 1.5 V (SSTL15) is supported in IGLOO2
FPGAs. SSTL2 is defined by JEDEC standard JESD8-9B and SSTL18 is defined by JEDEC standard JESD8-15.
8.7.3 Stub-Series Terminated Logic 2.5 V (SSTL2)
SSTL2 Class I and Class II are supported in IGLOO2 FPGAs. IGLOO2 FPGA I/Os support both standards for singleended signaling and differential signaling for SSTL2. This standard requires a differential amplifier input buffer and a
push-pull output buffer.
8.7.3.1 Minimum and Maximum DC Input and Output Levels Specification
Table 61 • SSTL2 Minimum and Maximum DC Input and Output Levels
Symbols
Parameters
Min
Typ
Max
Units
Recommended DC Operating Conditions
VDDI
Supply voltage
2.375
2.5
2.625
V
VTT
Termination voltage
1.164
1.250
1.339
V
VREF
Input reference voltage
1.164
1.250
1.339
V
SSTL2 DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF + 0.15
–
2.625
V
VIL (DC)
DC input logic Low
–0.3
–
VREF – 0.15
V
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
SSTL2 DC Output Voltage Specification
SSTL2 Class I
VOH
DC output logic High
VTT + 0.608
–
–
V
VOL
DC output logic Low
–
–
VTT – 0.608
V
IOH at VOH
Output minimum
current
8.1
–
–
mA
IOL at VOL
Output minimum sink current
–8.1
–
–
mA
source
DC
SSTL2 Class – Applicable to MSIO and DDRIO I/O Banks Only
VOH
DC output logic High
VTT + 0.81
–
–
V
VOL
DC output logic Low
–
–
VTT – 0.81
V
IOH at VOH
Output minimum
current
16.2
–
–
mA
IOL at VOL
Output minimum sink current
–16.2
–
–
mA
source
DC
Revision 1
34
IGLOO2 FPGA Automotive Grade 1
Table 61 • SSTL2 Minimum and Maximum DC Input and Output Levels (continued)
Symbols
Parameters
Min
Typ
Max
Units
0.3
–
–
V
SSTL2 DC Differential Voltage Specification
VID (DC)
DC input differential voltage
Table 62 • SSTL2 AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
360
Mbps
SSTL2 Maximum AC Switching Speeds
Dmax
Maximum data
DDRIO I/O Bank)
rate
Dmax
Maximum data rate (for MSIO
AC loading: 17pF load
I/O Bank)
–
–
450
Mbps
Dmax
Maximum data
MSIOD I/O Bank)
–
–
480
Mbps
rate
(for AC loading: per JEDEC
specifications
(for
AC loading: 17pF load
SSTL2 AC Differential Voltage Specifications
VDIFF
AC Input Differential Voltage
–
0.7
–
–
V
Vx
AC Differential Cross Point
Voltage
–
0.5 × VDDI 0.2
–
0.5 ×
VDDI +
0.2
V
–
20,
42
–

SSTL2 Impedance Specifications
Supported
output
driver
Reference resistor =
calibrated impedance (for
150 
DDRIO I/O Bank)
SSTL2 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data
path
–
–
1.25
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable
path (tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
Rtt_test
Reference resistance for data
test path for SSTL2 Class I
(tDP)
–
–
50
–

Rtt_test
Reference resistance for data
test path for SSTL2 Class II
(tDP)
–
–
25
–

Cload
Capacitive loading for data
path (tDP)
–
–
5
–
pF
Revision 1
35
IGLOO2 FPGA Automotive Grade 1
8.7.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 63 • SSTL2 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
ODT (On Die Termination) in 
tPY
Units
Pseudo-Differential
None
1.621
ns
True-Differential
None
1.656
ns
Pseudo-Differential
None
3.106
ns
True-Differential
None
3.053
ns
Pseudo-Differential
None
2.742
ns
True-Differential
None
2.73
ns
SSTL2 (DDRIO I/O Bank)
SSTL2 (MSIO I/O Bank)
SSTL2 (MSIOD I/O Bank)
Table 64 • SSTL2 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.484
2.169
2.16
4.995
4.827
ns
Differential
2.48
2.406
2.401
3.004
3.017
ns
Single Ended
2.308
2.279
2.267
2.648
2.552
ns
Differential
2.46
2.731
2.72
2.64
2.546
ns
Single Ended
1.663
1.608
1.606
2.462
2.286
ns
Differential
1.792
1.951
1.946
2.455
2.277
ns
Single Ended
2.343
2.082
2.076
4.286
4.14
ns
Differential
2.344
2.237
2.234
3.225
3.052
ns
Single Ended
2.591
2.232
2.213
2.676
2.567
ns
Differential
2.732
2.593
2.582
2.663
2.566
ns
SSTL2 Class I
DDRIO I/O Bank
MSIO I/O Bank
MSIOD I/O Bank
SSTL2 Class II
DDRIO I/O Bank
MSIO I/O Bank
Revision 1
36
IGLOO2 FPGA Automotive Grade 1
8.7.4 Stub-Series Terminated Logic 1.8 V (SSTL18)
SSTL18 Class I and Class II are supported in IGLOO2 FPGAs. IGLOO2 FPGA I/Os support both standards for singleended signaling and differential signaling for SSTL18. This standard requires a differential amplifier input buffer and a
push-pull output buffer.
8.7.4.1 Minimum and Maximum Input and Output Levels Specification
Table 65 • SSTL18 AC/DC Minimum and Maximum Input and Output Levels Specification
Symbols
Parameters
Min
Typ
Max
Units
Notes
Recommended DC Operating Conditions
VDDI
Supply voltage
1.71
1.8
1.89
V
–
VTT
Termination voltage
0.838
0.900
0.964
V
–
VREF
Input reference voltage
0.838
0.900
0.964
V
–
SSTL18 DC Input Voltage Specification
VIH (DC)
DC input logic High
VREF + 0.125
–
1.89
V
–
VIL (DC)
DC input logic Low
–0.3
–
VREF – 0.125
V
–
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
–
SSTL18 DC Output Voltage Specification
SSTL18 Class I
VOH
DC output logic High
VTT + 0.603
–
–
V
–
VOL
DC output logic Low
–
–
VTT– 0.603
V
–
IOH at VOH
Output minimum source DC
current (DDRIO I/O Bank only)
6.0
–
–
mA
–
IOL at VOL
Output minimum sink current
(DDRIO I/O Bank only)
–6.0
–
–
mA
–
SSTL18 Class II
–
VOH
DC output logic High
VTT + 0.603
–
–
V
–
VOL
DC output logic Low
–
–
VTT– 0.603
V
–
IOH at VOH
Output minimum source DC
current (DDRIO I/O Bank only)
12.0
–
–
mA
–
IOL at VOL
Output minimum sink current
(DDRIO I/O Bank only)
–12.0
–
–
mA
–
0.3
–
–
V
–
SSTL18 DC Differential Voltage Specification
VID (DC)
DC input differential voltage
Table 66 • SSTL18 AC Specifications (Applicable to DDRIO Bank Only)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
SSTL18 AC Differential Voltage Specification
VDIFF
(AC)
AC input differential voltage
–
0.5
–
–
V
Vx (AC)
AC differential
voltage
–
0.5 × VDDI –
0.175
–
0.5 × VDDI +
0.175
V
cross
point
Revision 1
37
IGLOO2 FPGA Automotive Grade 1
Table 66 • SSTL18 AC Specifications (Applicable to DDRIO Bank Only) (continued)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
600
Mbps
SSTL18 Maximum AC Switching Speed
Dmax
Maximum data
DDRIO I/O Bank)
rate
(for AC
loading:
per
JEDEC specification
SSTL18 Impedance Specifications
Rref
Supported
output
driver
Reference resistor
calibrated impedance (for
= 150 
DDRIO I/O Bank)
–
20, 42
–

RTT
Effective
(ODT)
–
50, 75,
150
–

impedance
value Reference resistor
= 150 
SSTL18 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data
path
–
–
0.9
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable
path (tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
Rtt_test
Reference resistance for data
test path for SSTL18 Class I
(tDP)
–
–
50
–

Rtt_test
Reference resistance for data
test path for SSTL18 Class II
(tDP)
–
–
25
–

Cload
Capacitive loading for data
path (tDP)
–
–
5
–
pF
8.7.4.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 67 • SSTL18 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.71 V
Speed Grade
–1
On-Die Termination (ODT) in 
tPY
Units
SSTL18 (for DDRIO I/O Bank with Fixed Codes)
Pseudo differential
None
1.641
ns
True differential
None
1.659
ns
Revision 1
38
IGLOO2 FPGA Automotive Grade 1
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 68 • SSTL18 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.71 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.698
3.111
3.105
3.311
3.317
ns
Differential
2.673
2.457
2.46
5.363
4.964
ns
Single Ended
2.591
3.004
2.997
3.33
3.334
ns
Differential
2.558
2.427
2.423
4.488
4.131
ns
SSTL18 Class I (for DDRIO I/O Bank)
SSTL18 Class II (for DDRIO I/O Bank)
8.7.5 Stub-Series Terminated Logic 1.5 V (SSTL15)
SSTL15 Class I and Class II are supported in IGLOO2 FPGAs. IGLOO2 FPGA I/Os support both standards for singleended signaling and differential signaling for SSTL18. This standard requires a differential amplifier input buffer and a
push-pull output buffer.
8.7.5.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 69 •
SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only)
Symbols
Parameters
Min
Typ
Max
Units
Recommended DC Operating Conditions
VDDI
Supply voltage
1.425
1.5
1.575
V
VTT
Termination voltage
0.698
0.750
0.803
V
VREF
Input reference voltage
0.698
0.750
0.803
V
SSTL15 DC Input Voltage Specification
VIH(DC)
DC input logic High
VREF + 0.1
–
1.575
V
VIL(DC)
DC input logic Low
–0.3
–
VREF – 0.1
V
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
SSTL15 DC Output Voltage Specification
SSTL15 Class I
VOH
DC output logic High
0.8 x VDDI
–
–
V
VOL
DC output logic Low
–
–
0.2 x VDDI
V
IOH at VOH
Output
current
6.5
–
–
mA
IOL at VOL
Output minimum sink current
–6.5
–
–
mA
minimum
source
DC
SSTL15 Class II
VOH
DC output logic High
0.8 × VDDI
–
–
V
VOL
DC output logic Low
–
–
0.2 x VDDI
V
IOH at VOH
Output
current
7.6
–
–
mA
minimum
source
DC
Revision 1
39
IGLOO2 FPGA Automotive Grade 1
Table 69 •
SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only) (continued)
Symbols
IOL at VOL
Parameters
Output minimum sink current
Min
Typ
Max
Units
–7.6
–
–
mA
0.2
–
–
V
SSTL15 Differential Voltage Specification
VID
DC input differential voltage
Table 70 • SSTL15 AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
SSTL15 AC Differential Voltage Specification
VDIFF
AC input differential voltage
–
0.3
–
–
V
Vx
AC differential
voltage
–
0.5 × VDDI
– 0.150
–
0.5 × VDDI
+ 0.150
V
–
–
600
Mbps
cross
point
SSTL15 Maximum AC Switching Speed (for DDRIO I/O Banks Only)
Dmax
AC
loading:
per
JEDEC specifications
Maximum data rate
SSTL15 AC Calibrated Impedance Option
Rref
Supported
output
calibrated impedance
driver Reference resistor
= 240 
–
34, 40
–

RTT
Effective
(ODT)
value Reference resistor
= 240 
–
20, 30,
40, 60,
120
–

impedance
SSTL15 AC Test Parameters Specifications
Vtrip
Measuring/trip point for data
path
–
–
0.75
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable
path (tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
Rtt_test
Reference resistance for data
test path for SSTL15 Class I
(tDP)
–
–
50
–

Rtt_test
Reference resistance for data
test path for SSTL15 Class II
(tDP)
–
–
25
–

Cload
Capacitive loading for data
path (tDP)
–
–
5
–
pF
Revision 1
40
IGLOO2 FPGA Automotive Grade 1
8.7.5.2. AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 71 • STTL15 AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.425 V
Speed Grade
–1
ODT (On Die Termination)
in 
tPY
Units
SSTL15 (for DDRIO I/O Bank) – Calibration Mode Only
Pseudo-Differential
None
2.71
ns
True-Differential
None
1.705
ns
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 72 • SSTL15 AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 1.425 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
Single Ended
2.861
2.796
2.797
4.5
3.996
ns
Differential
2.85
2.882
2.877
3.379
2.813
ns
Single Ended
2.862
2.789
2.789
4.534
3.953
ns
Differential
2.847
2.847
2.871
3.385
2.816
ns
SSTL15 Class I (for DDRIO I/O Bank)
SSTL15 Class II (for DDRIO I/O Bank)
8.8 Differential I/O Standards
Configuration of the I/O modules as a differential pair is handled by Microsemi SoC Products Group Libero® Systemon-Chip (SoC) software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be
used in conjunction with the embedded Input register (InReg), Output register (OutReg), Enable register (EnReg), and
Double Data Rate registers (DDR).
8.8.1 LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard.
8.8.1.1 Minimum and Maximum Input and Output Levels
Table 73 • LVDS DC Voltage Specification
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVDS Recommended DC Operating Conditions
VDDI
Supply voltage
2.5 V range
2.375
2.5
2.625
V
VDDI
Supply voltage
3.3 V range
3.15
3.3
3.45
V
LVDS DC Input Voltage Specification
VI
DC Input voltage
2.5 V range
0
–
2.925
V
VI
DC input voltage
3.3 V range
0
–
3.45
V
IIH (DC)
Input current High
–
Revision 1
Refer to Table 19 on page 15
–
41
IGLOO2 FPGA Automotive Grade 1
Table 73 • LVDS DC Voltage Specification (continued)
Symbols
IIL (DC)
Parameters
Conditions
Input current Low
Min
Typ
Max
Units
–
Refer to Table 19 on page 15
–
LVDS DC Output Voltage Specification
VOH
DC output logic High
–
1.25
1.425
1.6
V
VOL
DC output logic Low
–
0.9
1.075
1.25
V
LVDS Differential Voltage Specification
VOD
Differential output voltage swing
–
250
350
450
mV
VOCM
Output common mode voltage
–
1.125
1.25
1.375
V
VICM
Input common mode voltage
–
0.05
1.25
2.35
V
VID
Input differential voltage
–
100
350
600
mV
Table 74 • LVDS AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
LVDS Maximum AC Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC loading: 12 pF / 100 
differential load
–
–
480
Mbps
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC loading: 10 pF / 100 
differential load
–
–
480
Mbps
–
–
100
–

LVDS Impedance Specification
Rt
Termination resistance
LVDS AC Test Parameters Specifications
Vtrip
Measuring/trip point for data path
–
–
Cross point
–
V
Rent
Resistance for enable path (tZH, tZL,
tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
8.8.1.2 LVDS25 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 75 • LVDS25 Receiver Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
LVDS (for MSIO I/O Bank)
LVDS (for MSIOD I/O Bank)
On-Die Termination (ODT) in 
tPY
Units
None
3.085
ns
100
3.081
ns
None
2.814
ns
100
2.809
ns
Revision 1
42
IGLOO2 FPGA Automotive Grade 1
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 76 • LVDS25 Transmitter Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
2.324
2.63
2.617
2.466
2.382
ns
No pre-emphasis
1.675
1.865
1.858
2.264
2.135
ns
Min pre-emphasis
1.6
1.889
1.886
2.295
2.169
ns
Med pre-emphasis
1.576
1.914
1.907
2.329
2.195
ns
LVDS (for MSIO I/O Bank)
LVDS (for MSIOD I/O Bank)
8.8.1.3 LVDS33 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 77 • LVDS33 Receiver Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
On Die Termination (ODT) in 
tPY
Units
None
2.784
ns
100
2.781
ns
LVDS33 (for MSIO I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 78 • LVDS33 Transmitter Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 3.15 V
Speed Grade
–1
LVDS33 (for MSIO I/O Bank)
tDP
tZL
tZH
tHZ
tLZ
Units
2.091
2.134
2.128
2.154
2.092
ns
8.8.2 B-LVDS
Bus LVDS (B-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications.
Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers.
8.8.2.1 Minimum and Maximum AC/DC Input and Output Levels Specification
Table 79 • B-LVDS DC Voltage Specification
Symbols
Parameters
Min
Typ
Max
Units
2.375
2.5
2.625
V
0
–
2.925
V
Bus-LVDS Recommended DC Operating Conditions
VDDI
Supply voltage
Bus-LVDS DC Input Voltage Specification
VI
DC input voltage
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
Revision 1
43
IGLOO2 FPGA Automotive Grade 1
Table 79 • B-LVDS DC Voltage Specification (continued)
Symbols
Parameters
Min
Typ
Max
Units
Bus-LVDS DC Output Voltage Specification (for MSIO I/O Bank only)
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
Bus-LVDS Differential Voltage Specification
VOD
Differential output voltage swing (for
MSIO I/O Bank only)
65
–
460
mV
VOCM
Output common mode voltage (for MSIO
I/O Bank only)
1.1
–
1.5
V
VICM
Input common mode voltage
0.05
–
2.4
V
VID
Input differential voltage
0.1
–
VDDI
V
Table 80 • B-LVDS AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
AC loading: 2 pF / 100 
differential load
–
–
450
Mbps
–
–
27
–

Bus-LVDS Maximum AC Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
Bus-LVDS Impedance Specifications
Rt
Termination resistance
Bus-LVDS AC Test Parameters Specifications
Vtrip
Measuring/trip point for data
path
–
–
Cross
point
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable
path (tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
8.8.2.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 81 • B-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
Bus-LVDS (for MSIO I/O Bank)
Bus-LVDS (for MSIOD I/O Bank)
On-Die Termination (ODT) in 
tPY
Units
None
3.036
ns
100
3.031
ns
None
2.744
ns
100
2.747
ns
Revision 1
44
IGLOO2 FPGA Automotive Grade 1
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 82 • B-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
Bus-LVDS (for MSIO I/O Bank)
tDP
tZL
tZH
tHZ
tLZ
Units
2.81
2.66
2.645
2.477
2.537
ns
8.8.3 M-LVDS
M-LVDS specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop
and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers.
8.8.3.1 Minimum and Maximum Input and Output Levels
Table 83 • M-LVDS DC Voltage Specification
Symbols
Parameters
Min
Typ
Max
Units
Notes
2.375
2.5
2.625
V
*
0
–
2.925
V
–
M-LVDS Recommended DC Operating Conditions
VDDI
Supply voltage
M-LVDS DC Input Voltage Specification
VI
DC input voltage
IIH (DC)
Input current High
Refer to Table 19 on page 15
–
–
IIL (DC)
Input current Low
Refer to Table 19 on page 15
–
–
M-LVDS DC Output Voltage Specification (for MSIO I/O Bank Only)
VOH
DC output logic High
1.25
1.425
1.6
V
–
VOL
DC output logic Low
0.9
1.075
1.25
V
–
M-LVDS Differential Voltage Specification
VOD
Differential output voltage Swing
(for MSIO I/O Bank only)
300
–
650
mV
–
VOCM
Output common mode voltage (for
MSIO I/O Bank only)
0.3
–
2.1
V
–
VICM
Input common mode voltage
0.3
–
1.2
V
–
VID
Input differential voltage
50
–
2400
mV
–
Note: *Only M-LVDS TYPE I is supported.
Table 84 • M-LVDS AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
AC loading: 2 pF / 100 
differential load
–
–
450
Mbps
–
–
50
–

M-LVDS Maximum AC Switching Speeds
Dmax
Maximum data rate
(for MSIO I/O Bank)
M-LVDS Impedance Specification
Rt
Termination resistance
Revision 1
45
IGLOO2 FPGA Automotive Grade 1
Table 84 • M-LVDS AC Specifications (continued)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
M-LVDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data path
–
–
Cross
point
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
8.8.3.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 85 • M-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Automotive Grade 1 conditions: TJ = 135°C, VDD = 1.14 V, VDDI= 2.375 V
Speed Grade
–1
On-Die Termination (ODT) in 
tPY
Units
None
3.036
ns
100
3.031
ns
None
2.744
ns
100
2.747
ns
M-LVDS (for MSIO I/O Bank)
M-LVDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 86 • M-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Automotive Grade 1 conditions: TJ = 135°C, VDD = 1.14 V, VDDI= 2.375 V
Speed Grade
–1
M-LVDS (for MSIO I/O Bank)
tDP
tZL
tZH
tHZ
tLZ
Units
2.81
2.66
2.644
2.539
2.455
ns
8.8.4 Mini-LVDS
Mini-LVDS is an unidirectional interface from the timing controller to the column drivers and is designed to the Texas
Instruments Standard SLDA007A.
8.8.4.1 Mini-LVDS Minimum and Maximum Input and Output Levels
Table 87 • Mini-LVDS DC Voltage Specification
Symbols
Parameters
Min
Typ
Max
Units
2.375
2.5
2.625
V
0
–
2.925
V
Recommended DC Operating Conditions
VDDI
Supply voltage
Mini-LVDS DC Input Voltage Specification
VI
DC Input voltage
Mini-LVDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
Revision 1
46
IGLOO2 FPGA Automotive Grade 1
Table 87 • Mini-LVDS DC Voltage Specification (continued)
Symbols
Parameters
Min
Typ
Max
Units
300
–
600
mV
1
–
1.4
V
Mini-LVDS Differential Voltage Specification
VOD
Differential output voltage swing
VOCM
Output common mode voltage
VICM
Input common mode voltage
0.3
–
1.2
V
VID
Input differential voltage
100
–
600
mV
Table 88 • Mini-LVDS AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
460
Mbps
–
–
480
Mbps
–
–
100
–

Mini-LVDS Maximum AC Switching Speed
AC loading:
differential load
2 pF / 100 
Dmax
Maximum data rate (MSIO I/O Bank)
Dmax
Maximum data rate (MSIOD I/O AC loading: 10 pF / 100 
Bank)
differential load
Mini-LVDS Impedance Specification
Rt
Termination resistance
Mini-LVDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data path
–
–
Cross
point
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable path
(tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
8.8.4.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 89 • Mini-LVDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
Mini-LVDS (for MSIO I/O Bank)
Mini-LVDS (for MSIOD I/O Bank)
On-Die Termination (ODT) in 
tPY
Units
None
3.137
ns
100
3.132
ns
None
2.945
ns
100
2.934
ns
Revision 1
47
IGLOO2 FPGA Automotive Grade 1
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 90 • Mini-LVDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
2.325
2.63
2.618
2.466
2.382
ns
No pre-emphasis
1.67
1.86
1.853
2.26
2.131
ns
Min pre-emphasis
1.67
1.86
1.853
2.26
2.131
ns
Med pre-emphasis
1.594
1.889
1.88
2.166
2.306
ns
Max pre-emphasis
1.573
1.915
1.904
2.198
2.339
ns
Mini-LVDS (for MSIO I/O Bank)
Mini-LVDS (for MSIOD I/O Bank)
8.8.5 RSDS
Reduced Swing Differential Signaling (RSDS) is similar to an LVDS high-speed interface using differential signaling.
RSDS has a similar implementation to LVDS devices and is only intended for point-to-point applications.
8.8.5.1 Minimum and Maximum Input and Output Levels
Table 91 • RSDS DC Voltage Specification
Symbols
Parameters
Min
Typ
Max
Units
2.375
2.5
2.625
V
0
–
2.925
V
Recommended DC Operating Conditions
VDDI
Supply voltage
RSDS DC Input Voltage Specification
VI
DC input voltage
RSDS DC Output Voltage Specification
VOH
DC output logic High
1.25
1.425
1.6
V
VOL
DC output logic Low
0.9
1.075
1.25
V
RSDS Differential Voltage Specification
VOD
Differential output voltage swing
100
–
600
mV
VOCM
Output common mode voltage
0.5
–
1.5
V
VICM
Input common mode voltage
0.3
–
1.5
V
VID
Input differential voltage
100
–
600
mV
Table 92 • RSDS AC Specifications
Symbols
Parameters
Conditions
Min
Typ
Max
Units
–
–
460
Mbps
–
–
480
Mbps
–
100
–

RSDS Maximum AC Switching Speed
Dmax
Maximum data rate
(for MSIO I/O Bank)
AC
loading:
differential load
2 pF / 100 
Dmax
Maximum data rate
(for MSIOD I/O Bank)
AC
loading:
differential load
10 pF / 100 
RSDS Impedance Specification
Rt
Termination resistance
–
Revision 1
48
IGLOO2 FPGA Automotive Grade 1
Table 92 • RSDS AC Specifications (continued)
Symbols
Parameters
Conditions
Min
Typ
Max
Units
RSDS AC Test Parameters Specifications
VTrip
Measuring/trip point for data
path
–
–
Cross
point
–
V
Rent
Resistance for enable path
(tZH, tZL, tHZ, tLZ)
–
–
2k
–

Cent
Capacitive loading for enable
path (tZH, tZL, tHZ, tLZ)
–
–
5
–
pF
8.8.5.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 93 • RSDS AC Switching Characteristics for Receiver (Input Buffers)
Worst-case Automotive Grade 1 conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
On-Die Termination (ODT) in 
tPY
Units
None
3.137
ns
100
3.132
ns
None
2.855
ns
100
2.844
ns
RSDS (for MSIO I/O Bank)
RSDS (for MSIOD I/O Bank)
AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Table 94 • RSDS AC Switching Characteristics for Transmitter (Output and Tristate Buffers)
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 2.375 V
Speed Grade
–1
tDP
tZL
tZH
tHZ
tLZ
Units
2.28
2.511
2.498
2.068
2.165
ns
No pre-emphasis
1.678
1.665
1.662
1.626
1.706
ns
Min pre-emphasis
1.669
1.859
1.852
2.132
2.27
ns
Med pre-emphasis
1.593
1.888
1.879
2.166
2.306
ns
Max pre-emphasis
1.572
1.913
1.902
2.198
2.339
ns
RSDS (for MSIO I/O Bank)
RSDS (for MSIOD I/O Bank)
8.8.6 LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit
be carried through two signal lines. Similar to LVDS, two pins are needed. It also requires external resistor termination.
IGLOO2 FPGAs support only LVPECL receivers and do not support LVPECL transmitters.
8.8.6.1 Minimum and Maximum Input and Output Levels
Table 95 • LVPECL DC Voltage Specification (Applicable to MSIO I/O Banks Only)
Symbols
Parameters
Min
Typ
Max
Units
3.15
3.3
3.45
V
Recommended DC Operating Conditions
VDDI
Supply voltage
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Table 95 • LVPECL DC Voltage Specification (Applicable to MSIO I/O Banks Only) (continued)
Symbols
Parameters
Min
Typ
Max
Units
0
–
3.45
V
2.8
V
1,000
mV
LVPECL DC Input Voltage Specification
VI
DC input voltage
LVPECL Differential Voltage Specification
VICM
Input common mode voltage
0.3
VIDIFF
Input differential voltage
100
300
Table 96 • LVPECL Maximum AC Switching Speeds (Applicable to MSIO I/O Banks Only)
Symbols
Parameters
Min
Typ
Max
Units
–
–
810
Mbps
LVPECL AC Specifications
Fmax
Maximum data rate (for MSIO I/O Bank)
8.8.6.2 AC Switching Characteristics
AC Switching Characteristics for Receiver (Input Buffers)
Table 97 • LVPECL Receiver Characteristics
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V, VDDI = 3.15 V
tPY
On-Die Termination (ODT) in 
Speed Grade
–1
Units
None
2.784
ns
100
2.781
ns
LVPECL (for MSIO I/O Bank)
8.9 I/O Register Specifications
8.9.1 Input Register
D
EN
Input I/O Buffer
ALn
F
A
B
C
D
Q
ALn
SLn
SLE
SD
SD
LAT
CLK
Q
EN
ADn
ADn
SLn
G
D
LAT
E
CLK
Figure 6 • Timing Model for Input Register
Revision 1
50
IGLOO2 FPGA Automotive Grade 1
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Figure 7 • I/O Register Input Timing Diagram
Table 98 • Input Data Register Propagation Delays
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Measuring
Nodes
(From, To)*
Speed
Grade
–1
Units
tIBYP
Bypass Delay of the Input Register
F, G
0.365
ns
tICLKQ
Clock-to-Q of the Input Register
E, G
0.166
ns
tISUD
Data Setup Time for the Input Register
A, E
0.37
ns
tIHD
Data Hold Time for the Input Register
A, E
0
ns
tISUE
Enable Setup Time for the Input Register
B, E
0.477
ns
tIHE
Enable Hold Time for the Input Register
B, E
0
ns
tISUSL
Synchronous Load Setup Time for the Input Register
D, E
0.477
ns
tIHSL
Synchronous Load Hold Time for the Input Register
D, E
0
ns
Asynchronous Clear-to-Q of the Input Register (ADn=1)
C, G
0.65
ns
Asynchronous Preset-to-Q of the Input Register (ADn=0)
C, G
0.608
ns
tIREMALn
Asynchronous Load Removal Time for the Input Register
C, E
0
ns
tIRECALn
Asynchronous Load Recovery Time for the Input Register
C, E
0.077
ns
tIWALn
Asynchronous Load Minimum Pulse Width for the Input Register
C, C
0.315
ns
tIALn2Q
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Table 98 • Input Data Register Propagation Delays
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Parameter
Description
Measuring
Nodes
(From, To)*
Speed
Grade
–1
Units
tICKMPWH
Clock Minimum Pulse Width High for the Input Register
E, E
0.078
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Register
E, E
0.165
ns
8.9.2 Output/Enable Register
A
D
EN
ALn
F
D
B
EN
C
ADn
D
SLn
LAT
LAT
D2
SLE
SD
SD
CLK
Q
ALn
ADn
SLn
G
E
J
CLK
H
I
D
Q
EN
ALn
ADn
SLn
Output I/O Buffer
with Enable Control
SLE
SD
LAT
CLK
Output/Enable Registers
Figure 8 • Timing Model for Output/Enable Register
Revision 1
52
IGLOO2 FPGA Automotive Grade 1
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Figure 9 • I/O Register Output Timing Diagram
Table 99 • Output/Enable Data Register Propagation Delays
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Measuring
Nodes
(From, To)
Speed
Grade
–1
Units
tOBYP
Bypass Delay of the Output/Enable Register
F, G or H, I
0.365
ns
tOCLKQ
Clock-to-Q of the Output/Enable Register
E, G or E, I
0.273
ns
tOSUD
Data Setup Time for the Output/Enable Register
A, E or J, E
0.197
ns
tOHD
Data Hold Time for the Output/Enable Register
A, E or J, E
0
ns
tOSUE
Enable Setup Time for the Output/Enable Register
B, E
0.434
ns
tOHE
Enable Hold Time for the Output/Enable Register
B, E
0
ns
tOSUSL
Synchronous Load Setup Time for the Output/Enable Register
D, E
0.203
ns
tOHSL
Synchronous Load Hold Time for the Output/Enable Register
D, E
0
ns
Asynchronous Clear-to-Q of the Output/Enable Register
(ADn=1)
C, G or C, I
0.525
ns
Asynchronous Preset-to-Q of the Output/Enable Register
(ADn=0)
C, G or C, I
0.547
ns
tOREMALn
Asynchronous Load Removal Time for the Output/Enable
Register
C, E
0
ns
tORECALn
Asynchronous Load Recovery Time for the Output/Enable
Register
C, E
0.035
ns
tOALn2Q
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Table 99 • Output/Enable Data Register Propagation Delays
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Parameter
Description
Measuring
Nodes
(From, To)
Speed
Grade
–1
Units
tOWALn
Asynchronous Load Minimum Pulse Width for the Output/Enable
Register
C, C
0.266
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output/Enable Register
E, E
0.065
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output/Enable Register
E, E
0.139
ns
8.10 DDR Module Specification
8.10.1 Input DDR Module
D
EN
ALn
A
D
E
EN
F
ADn
G
SLn
SLE
SD
SD
LAT
LAT
CLK
QR
ALn
ADn
SLn
C
Q
B
CLK
D
ALn
ADn
Q
D
D
Q
EN
Latch
QF
ALn
ADn
SLn
CLK
SLE
SD
LAT
CLK
DDR_IN
Figure 10 • Input DDR Module
Revision 1
54
IGLOO2 FPGA Automotive Grade 1
8.10.2 Input DDR Timing Diagram
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Figure 11 • Input DDR Timing Diagram
Revision 1
55
IGLOO2 FPGA Automotive Grade 1
8.10.3 Timing Characteristics
Table 100 • Input DDR Propagation Delays
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Measuring Nodes Speed Grade
(From, To)
–1
Description
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
B, C
0.166
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
B, D
0.173
ns
tDDRISUD
Data Setup for Input DDR
A, B
0.374
ns
tDDRIHD
Data Hold for Input DDR
A, B
0
ns
tDDRISUE
Enable Setup for Input DDR
E, B
0.477
ns
tDDRIHE
Enable Hold for Input DDR
E, B
0
ns
tDDRISUSLn
Synchronous Load Setup for Input DDR
G, B
0.477
ns
tDDRIHSLn
Synchronous Load Hold for Input DDR
G, B
0
ns
tDDRIAL2Q1
Asynchronous Load-to-Out QR for Input DDR
F, C
0.608
ns
tDDRIAL2Q2
Asynchronous Load-to-Out QF for Input DDR
F, D
0.56
ns
tDDRIREMAL
Asynchronous Load Removal time for Input DDR
F, B
0
ns
tDDRIRECAL
Asynchronous Load Recovery time for Input DDR
F, B
0.077
ns
tDDRIWAL
Asynchronous Load Minimum Pulse Width for Input
DDR
F, F
0.315
ns
tDDRICKMPWH
Clock Minimum Pulse Width High for Input DDR
B, B
0.078
ns
tDDRICKMPWL
Clock Minimum Pulse Width Low for Input DDR
B, B
0.165
ns
Revision 1
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IGLOO2 FPGA Automotive Grade 1
8.10.4 Output DDR Module
A
DR
EN
ALn
D
B
C
ADn
D
SLn
SD
SD
LAT
LAT
CLK
DF
QR
ALn
ADn
SLn
Q
EN
E
SLE
1
G
Q
CLK
F
D
Q
EN
QF
ALn
ADn
SLn
SLE
SD
0
LAT
CLK
DDR_ OUT
Figure 12 • Output DDR Module
Revision 1
57
IGLOO2 FPGA Automotive Grade 1
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Figure 13 • Output DDR Timing Diagram
Revision 1
58
IGLOO2 FPGA Automotive Grade 1
8.10.5 Timing Characteristics
Table 101 • Output DDR Propagation Delays
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Measuring Nodes
(From, To)
Speed Grade
–1
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
E, G
0.273
ns
tDDROSUDF
DF Data Setup for Output DDR
F, E
0.148
ns
tDDROSUDR
DR Data Setup for Output DDR
A, E
0.197
ns
tDDROHDF
DF Data Hold for Output DDR
F, E
0
ns
tDDROHDR
DR Data Hold for Output DDR
A, E
0
ns
tDDROSUE
Enable Setup for Output DDR
B, E
0.434
ns
tDDROHE
Enable Hold for Output DDR
B, E
0
ns
tDDROSUSLn
Synchronous Load Setup for Output DDR
D, E
0.203
ns
tDDROHSLn
Synchronous Load Hold for Output DDR
D, E
0
ns
tDDROAL2Q
Asynchronous Load-to-Out for Output DDR
C, G
0.547
ns
tDDROREMAL
Asynchronous Load Removal time for
Output DDR
C, E
0
ns
tDDRORECAL
Asynchronous Load Recovery time for
Output DDR
C, E
0.035
ns
tDDROWAL
Asynchronous Load Minimum Pulse Width
for Output DDR
C, C
0.266
ns
tDDROCKMPWH
Clock Minimum Pulse Width High for the
Output DDR
E, E
0.065
ns
tDDROCKMPWL
Clock Minimum Pulse Width Low for the
Output DDR
E, E
0.139
ns
Revision 1
59
IGLOO2 FPGA Automotive Grade 1
9. Logic Element Specifications
9.1 4-input LUT (LUT-4)
The IGLOO2 FPGAs offer a fully permutable 4-input LUT. In this section, timing characteristics are presented for a
sample of the library. For more details, refer to the SmartFusion2 and IGLOO2 Macro Library Guide.
tPD
A
PAD
B
PAD
AND4 OR
Any
Combinational
Logic
C
PAD
PAD
D/S (where
applicable)
PAD
VDD
A, B, C, D, S
Y
50%
tPD = Max(tPD(RR), tPD(RF), tPD(FF), tPD(FR))
50%
where edges are applicable for the particular
combinatorial cell
GND
VDD
50%
50%
OUT
tPD
tPD
(RR)
(FF)
GND
VDD
tPD
OUT
tPD
50%
(RF)
(FR)
50%
GND
Figure 14 • LUT-4
9.1.1 Timing Characteristics
Table 102 • Combinatorial Cell Propagation Delays
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Combinatorial Cell
Equation
Parameter
Speed Grade
–1
Units
INV
Y = !A
tPD
0.104
ns
AND2
Y=A·B
tPD
0.17
ns
NAND2
Y = !(A · B)
tPD
0.153
ns
OR2
Y=A+B
tPD
0.17
ns
NOR2
Y = !(A + B)
tPD
0.153
ns
XOR2
Y=AB
tPD
0.17
ns
XOR3
Y=ABC
tPD
0.234
ns
AND3
Y=A·B·C
tPD
0.218
ns
AND4
Y=A·B·C·D
tPD
0.293
ns
Revision 1
60
IGLOO2 FPGA Automotive Grade 1
9.2 Sequential Module
IGLOO2 FPGAs offer a separate flip-flop which can be used independently from the LUT. The flip-flop can be
configured as a register or a latch and has a data input and optional enable, synchronous load (clear or preset), and
asynchronous load (clear or preset).
D
Q
EN
ALn
ADn
SLn
SLE
SD
LAT
CLK
Figure 15 • Sequential Module
Figure 16 shows a configuration with SD = 0 (synchronous clear) and ADn = 1 (asynchronous clear) for a flip-flop
(LAT = 0).
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Figure 16 • Sequential Module Timing Diagram
Revision 1
61
IGLOO2 FPGA Automotive Grade 1
9.2.1 Timing Characteristics
Table 103 • Register Delays
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Speed Grade
–1
Units
tCLKQ
Clock-to-Q of the Core Register
0.112
ns
tSUD
Data Setup Time for the Core Register
0.263
ns
tHD
Data Hold Time for the Core Register
0
ns
tSUE
Enable Setup Time for the Core Register
0.347
ns
tHE
Enable Hold Time for the Core Register
0
ns
tSUSL
Synchronous Load Setup Time for the Core Register
0.347
ns
tHSL
Synchronous Load Hold Time for the Core Register
0
ns
Asynchronous Clear-to-Q of the Core Register (ADn=1)
0.492
ns
Asynchronous Preset-to-Q of the Core Register (ADn=0)
0.468
ns
tREMALn
Asynchronous Load Removal Time for the Core Register
0
ns
tRECALn
Asynchronous Load Recovery Time for the Core Register
0.366
ns
tWALn
Asynchronous Load Minimum Pulse Width for the Core Register
0.266
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.065
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.139
ns
tALn2Q
10. Global Resource Characteristics
The IGLOO2 FPGA devices offer a powerful, low skew global routing network which provides an effective clock
distribution throughout the FPGA fabric. Refer to the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric
User Guide for the positions of various global routing resources.
Table 104 • M2GL090 Device Global Resource
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
0.918
0.98
ns
tRCKH
Input High Delay for Global Clock
1.702
1.815
ns
tRCKSW
Maximum Skew for Global Clock
–
0.113
ns
Table 105 • M2GL060 Device Global Resource
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
1.031
1.08
ns
tRCKH
Input High Delay for Global Clock
1.833
1.915
ns
tRCKSW
Maximum Skew for Global Clock
–
0.082
ns
Revision 1
62
IGLOO2 FPGA Automotive Grade 1
Table 106 • M2GL025 Device Global Resource
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
0.791
0.847
ns
tRCKH
Input High Delay for Global Clock
1.41
1.506
ns
tRCKSW
Maximum Skew for Global Clock
–
0.096
ns
Table 107 • M2GL010 Device Global Resource
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
0.61
0.66
ns
tRCKH
Input High Delay for Global Clock
1.114
1.209
ns
tRCKSW
Maximum Skew for Global Clock
–
0.095
ns
Table 108 • M2GL005 Device Global Resource
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
tRCKL
Input Low Delay for Global Clock
0.736
0.789
ns
tRCKH
Input High Delay for Global Clock
0.927
0.995
ns
tRCKSW
Maximum Skew for Global Clock
–
0.068
ns
11. FPGA Fabric SRAM
Refer to the UG0445: IGLOO2 FPGA and SmartFusion2 SoC FPGA Fabric User Guide for more information.
11.1 FPGA Fabric Large SRAM (LSRAM)
Table 109 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tCY
Clock Period
tCLKMPWH
Clock Minimum Pulse Width High
1.5
–
ns
tCLKMPWL
Clock Minimum pulse Width Low
1.5
–
ns
tPLCY
Pipelined Clock Period
3.333
–
ns
tPLCLKMPWH
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tPLCLKMPWL
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Revision 1
63
IGLOO2 FPGA Automotive Grade 1
Table 109 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 1Kx18
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
tCLK2Q
Description
Min
Max
Units
Read Access Time with Pipeline Register
–
0.348
ns
Read Access Time without Pipeline Register
–
2.355
ns
Access Time with Feed-Through Write Timing
–
1.584
ns
tADDRSU
Address Setup Time
0.457
–
ns
tADDRHD
Address Hold Time
0.284
–
ns
tDSU
Data Setup Time
0.353
–
ns
tDHD
Data Hold Time
0.111
–
ns
tBLKSU
Block Select Setup Time
0.215
–
ns
tBLKHD
Block Select Hold Time
0.224
–
ns
tBLK2Q
Block Select to Out Disable Time
(when Pipe-Lined Registered is Disabled)
–
1.584
ns
tBLKMPW
Block Select Minimum Pulse Width
0.218
–
ns
tRDESU
Read Enable Setup Time
0.465
–
ns
tRDEHD
Read Enable Hold Time
0.174
–
ns
tRDPLESU
Pipelined Read Enable Setup Time
(A_DOUT_EN, B_DOUT_EN)
0.257
–
ns
tRDPLEHD
Pipelined Read Enable Hold Time
(A_DOUT_EN, B_DOUT_EN)
0.106
–
ns
tR2Q
Asynchronous Reset to Output Propagation Delay
–
1.567
ns
tRSTREM
Asynchronous Reset Removal Time
0.524
–
ns
tRSTREC
Asynchronous Reset Recovery Time
0.005
–
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tPLRSTREM
Pipelined Register Asynchronous Reset Removal Time
-0.289
–
ns
tPLRSTREC
Pipelined Register Asynchronous Reset Recovery Time
0.339
–
ns
tPLRSTMPW
Pipelined Register Asynchronous Reset Minimum Pulse
Width
0.33
–
ns
tSRSTSU
Synchronous Reset Setup Time
0.234
–
ns
tSRSTHD
Synchronous Reset Hold Time
0.038
–
ns
tWESU
Write Enable Setup Time
0.404
–
ns
tWEHD
Write Enable Hold Time
0.251
–
ns
Fmax
Maximum Frequency
–
300
MHz
Revision 1
64
IGLOO2 FPGA Automotive Grade 1
Table 110 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2Kx9
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tCY
Clock Period
tCLKMPWH
Clock Minimum Pulse Width High
1.5
–
ns
tCLKMPWL
Clock Minimum pulse Width Low
1.5
–
ns
tPLCY
Pipelined Clock Period
3.333
–
ns
tPLCLKMPWH
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tPLCLKMPWL
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.348
ns
Read Access Time without Pipeline Register
–
2.355
ns
Access Time with Feed-Through Write Timing
–
1.585
ns
tCLK2Q
tADDRSU
Address Setup Time
0.492
–
ns
tADDRHD
Address Hold Time
0.284
–
ns
tDSU
Data Setup Time
0.348
–
ns
tDHD
Data Hold Time
0.084
–
ns
tBLKSU
Block Select Setup Time
0.215
–
ns
tBLKHD
Block Select Hold Time
0.224
–
ns
tBLK2Q
Block Select to Out Disable Time
(when Pipe-Lined Registered is Disabled)
–
1.585
ns
tBLKMPW
Block Select Minimum Pulse Width
0.218
–
ns
tRDESU
Read Enable Setup Time
0.502
–
ns
tRDEHD
Read Enable Hold Time
0.073
–
ns
tRDPLESU
Pipelined Read Enable Setup Time
(A_DOUT_EN, B_DOUT_EN)
0.257
–
ns
tRDPLEHD
Pipelined Read Enable Hold Time
(A_DOUT_EN, B_DOUT_EN)
0.106
–
ns
tR2Q
Asynchronous Reset to Output Propagation Delay
–
1.575
ns
tRSTREM
Asynchronous Reset Removal Time
0.524
–
ns
tRSTREC
Asynchronous Reset Recovery Time
0.005
–
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tPLRSTREM
Pipelined Register Asynchronous Reset Removal Time
-0.289
–
ns
tPLRSTREC
Pipelined Register Asynchronous Reset Recovery Time
0.339
–
ns
tPLRSTMPW
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tSRSTSU
Synchronous Reset Setup Time
0.234
–
ns
tSRSTHD
Synchronous Reset Hold Time
0.038
–
ns
tWESU
Write Enable Setup Time
0.43
–
ns
Revision 1
65
IGLOO2 FPGA Automotive Grade 1
Table 110 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 2Kx9
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
tWEHD
Write Enable Hold Time
Fmax
Maximum Frequency
Min
Max
Units
0.05
–
ns
–
300
MHz
Table 111 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4Kx4
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tCY
Clock Period
tCLKMPWH
Clock Minimum Pulse Width High
1.5
–
ns
tCLKMPWL
Clock Minimum pulse Width Low
1.5
–
ns
tPLCY
Pipelined Clock Period
3.333
–
ns
tPLCLKMPWH
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tPLCLKMPWL
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.336
ns
Read Access Time without Pipeline Register
–
2.355
ns
Access Time with Feed-Through Write Timing
–
1.566
ns
tCLK2Q
tADDRSU
Address Setup Time
0.562
–
ns
tADDRHD
Address Hold Time
0.284
–
ns
tDSU
Data Setup Time
0.346
–
ns
tDHD
Data Hold Time
0.084
–
ns
tBLKSU
Block Select Setup Time
0.215
–
ns
tBLKHD
Block Select Hold Time
0.224
–
ns
tBLK2Q
Block Select to Out Disable Time (when Pipe-Lined Registered
is Disabled)
–
1.566
ns
tBLKMPW
Block Select Minimum Pulse Width
0.218
–
ns
tRDESU
Read Enable Setup Time
0.535
–
ns
tRDEHD
Read Enable Hold Time
0.073
–
ns
tRDPLESU
Pipelined Read Enable Setup Time (A_DOUT_EN,
B_DOUT_EN)
0.257
–
ns
tRDPLEHD
Pipelined Read Enable Hold Time (A_DOUT_EN,
B_DOUT_EN)
0.106
–
ns
tR2Q
Asynchronous Reset to Output Propagation Delay
–
1.568
ns
tRSTREM
Asynchronous Reset Removal Time
0.524
–
ns
tRSTREC
Asynchronous Reset Recovery Time
0.005
–
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
Revision 1
66
IGLOO2 FPGA Automotive Grade 1
Table 111 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 4Kx4
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tPLRSTREM
Pipelined Register Asynchronous Reset Removal Time
-0.289
–
ns
tPLRSTREC
Pipelined Register Asynchronous Reset Recovery Time
0.339
–
ns
tPLRSTMPW
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tSRSTSU
Synchronous Reset Setup Time
0.234
–
ns
tSRSTHD
Synchronous Reset Hold Time
0.038
–
ns
tWESU
Write Enable Setup Time
0.475
–
ns
tWEHD
Write Enable Hold Time
0.05
–
ns
Fmax
Maximum Frequency
–
300
MHz
Table 112 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8Kx2
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tCY
Clock Period
tCLKMPWH
Clock Minimum Pulse Width High
1.5
–
ns
tCLKMPWL
Clock Minimum pulse Width Low
1.5
–
ns
tPLCY
Pipelined Clock Period
3.333
–
ns
tPLCLKMPWH
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tPLCLKMPWL
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0333
ns
Read Access Time without Pipeline Register
–
2.355
ns
Access Time with Feed-Through Write Timing
–
1.566
ns
tCLK2Q
tADDRSU
Address Setup Time
0.634
–
ns
tADDRHD
Address Hold Time
0.284
–
ns
tDSU
Data Setup Time
0.342
–
ns
tDHD
Data Hold Time
0.084
–
ns
tBLKSU
Block Select Setup Time
0.215
–
ns
tBLKHD
Block Select Hold Time
0.224
–
ns
tBLK2Q
Block Select to Out Disable Time
(when Pipe-Lined Registered is Disabled)
–
1.566
ns
tBLKMPW
Block Select Minimum Pulse Width
0.218
–
ns
tRDESU
Read Enable Setup Time
0.548
–
ns
tRDEHD
Read Enable Hold Time
0.073
–
ns
tRDPLESU
Pipelined Read Enable Setup Time
(A_DOUT_EN, B_DOUT_EN)
0.257
–
ns
Revision 1
67
IGLOO2 FPGA Automotive Grade 1
Table 112 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 8Kx2
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
0.106
–
ns
–
1.59
ns
tRDPLEHD
Pipelined Read Enable Hold Time
(A_DOUT_EN, B_DOUT_EN)
tR2Q
Asynchronous Reset to Output Propagation Delay
tRSTREM
Asynchronous Reset Removal Time
0.524
–
ns
tRSTREC
Asynchronous Reset Recovery Time
0.005
–
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tPLRSTREM
Pipelined Register Asynchronous Reset Removal Time
-0.289
–
ns
tPLRSTREC
Pipelined Register Asynchronous Reset Recovery Time
0.339
–
ns
tPLRSTMPW
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tSRSTSU
Synchronous Reset Setup Time
0.234
–
ns
tSRSTHD
Synchronous Reset Hold Time
0.038
–
ns
tWESU
Write Enable Setup Time
0.506
–
ns
tWEHD
Write Enable Hold Time
0.05
–
ns
Fmax
Maximum Frequency
–
300
MHz
Table 113 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16Kx1
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
3.333
–
ns
tCY
Clock Period
tCLKMPWH
Clock Minimum Pulse Width High
1.5
–
ns
tCLKMPWL
Clock Minimum pulse Width Low
1.5
–
ns
tPLCY
Pipelined Clock Period
3.333
–
ns
tPLCLKMPWH
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tPLCLKMPWL
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.333
ns
Read Access Time without Pipeline Register
–
2.351
ns
Access Time with Feed-Through Write Timing
–
1.565
ns
tCLK2Q
tADDRSU
Address Setup Time
0.649
–
ns
tADDRHD
Address Hold Time
0.284
–
ns
tDSU
Data Setup Time
0.333
–
ns
tDHD
Data Hold Time
0.084
–
ns
tBLKSU
Block Select Setup Time
0.215
–
ns
tBLKHD
Block Select Hold Time
0.224
–
ns
Revision 1
68
IGLOO2 FPGA Automotive Grade 1
Table 113 • RAM1K18 – Dual-Port Mode for Depth × Width Configuration 16Kx1
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tBLK2Q
Block Select to Out Disable Time (when Pipe-Lined Registered is
Disabled)
–
1.565
ns
tBLKMPW
Block Select Minimum Pulse Width
0.218
–
ns
tRDESU
Read Enable Setup Time
0.549
–
ns
tRDEHD
Read Enable Hold Time
0.073
–
ns
tRDPLESU
Pipelined Read Enable Setup Time (A_DOUT_EN, B_DOUT_EN)
0.257
–
ns
tRDPLEHD
Pipelined Read Enable Hold Time (A_DOUT_EN, B_DOUT_EN)
0.106
–
ns
tR2Q
Asynchronous Reset to Output Propagation Delay
–
1.609
ns
tRSTREM
Asynchronous Reset Removal Time
0.524
–
ns
tRSTREC
Asynchronous Reset Recovery Time
0.005
–
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tPLRSTREM
Pipelined Register Asynchronous Reset Removal Time
-0.289
–
ns
tPLRSTREC
Pipelined Register Asynchronous Reset Recovery Time
0.339
–
ns
tPLRSTMPW
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tSRSTSU
Synchronous Reset Setup Time
0.234
–
ns
tSRSTHD
Synchronous Reset Hold Time
0.038
–
ns
tWESU
Write Enable Setup Time
0.47
–
ns
tWEHD
Write Enable Hold Time
0.05
–
ns
Fmax
Maximum Frequency
–
300
MHz
Speed Grade
–1
Units
Table 114 • RAM1K18 – Two-Port Mode for Depth × Width Configuration 512x36
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Min
Max
3.333
–
ns
tCY
Clock Period
tCLKMPWH
Clock Minimum Pulse Width High
1.5
–
ns
tCLKMPWL
Clock Minimum pulse Width Low
1.5
–
ns
tPLCY
Pipelined Clock Period
3.333
–
ns
tPLCLKMPWH
Pipelined Clock Minimum Pulse Width High
1.5
–
ns
tPLCLKMPWL
Pipelined Clock Minimum pulse Width Low
1.5
–
ns
Read Access Time with Pipeline Register
–
0.347
ns
Read Access Time without Pipeline Register
–
2.331
ns
tCLK2Q
tADDRSU
Address Setup Time
0.324
–
ns
tADDRHD
Address Hold Time
0.284
–
ns
tDSU
Data Setup Time
0.349
–
ns
Revision 1
69
IGLOO2 FPGA Automotive Grade 1
Table 114 • RAM1K18 – Two-Port Mode for Depth × Width Configuration 512x36
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tDHD
Data Hold Time
0.115
–
ns
tBLKSU
Block Select Setup Time
0.215
–
ns
tBLKHD
Block Select Hold Time
0.209
–
ns
tBLK2Q
Block Select to Out Disable Time (when Pipe-Lined Registered
is Disabled)
–
2.331
ns
tBLKMPW
Block Select Minimum Pulse Width
0.218
–
ns
tRDESU
Read Enable Setup Time
0.465
–
ns
tRDEHD
Read Enable Hold Time
0.174
–
ns
tRDPLESU
Pipelined Read Enable Setup Time (A_DOUT_EN,
B_DOUT_EN)
0.257
–
ns
tRDPLEHD
Pipelined Read Enable Hold Time (A_DOUT_EN,
B_DOUT_EN)
0.106
–
ns
tR2Q
Asynchronous Reset to Output Propagation Delay
–
1.567
ns
tRSTREM
Asynchronous Reset Removal Time
0.524
–
ns
tRSTREC
Asynchronous Reset Recovery Time
0.005
–
ns
tRSTMPW
Asynchronous Reset Minimum Pulse Width
0.352
–
ns
tPLRSTREM
Pipelined Register Asynchronous Reset Removal Time
-0.289
–
ns
tPLRSTREC
Pipelined Register Asynchronous Reset Recovery Time
0.339
–
ns
tPLRSTMPW
Pipelined Register Asynchronous Reset Minimum Pulse Width
0.33
–
ns
tSRSTSU
Synchronous Reset Setup Time
0.234
–
ns
tSRSTHD
Synchronous Reset Hold Time
0.038
–
ns
tWESU
Write Enable Setup Time
0.404
–
ns
tWEHD
Write Enable Hold Time
0.251
–
ns
Fmax
Maximum Frequency
–
300
MHz
Revision 1
70
IGLOO2 FPGA Automotive Grade 1
11.2 FPGA Fabric Micro SRAM (uSRAM)
Table 115 • uSRAM (RAM64x18) in 64x18 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tCY
Read Clock Period
tCLKMPWH
Read Clock Minimum Pulse Width High
1.8
–
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
1.8
–
ns
tPLCY
Read Pipe-line clock period
4
–
ns
tPLCLKMPWH
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tPLCLKMPWL
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.277
ns
Read Access Time without Pipeline Register
–
1.745
ns
Read Address Setup Time in Synchronous Mode
0.312
–
ns
Read Address Setup Time in Asynchronous Mode
1.924
–
ns
Read Address Hold Time in Synchronous Mode
0.094
–
ns
Read Address Hold Time in Asynchronous Mode
-0.806
–
ns
tRDENSU
Read Enable Setup Time
0.288
–
ns
tRDENHD
Read Enable Hold Time
0.059
–
ns
tBLKSU
Read Block Select Setup Time
1.905
–
ns
tBLKHD
Read Block Select Hold Time
-0.674
–
ns
tBLK2Q
Read Block Select to Out Disable Time
(when Pipe-Lined Registered is Disabled)
–
2.11
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
-0.151
–
ns
Read Asynchronous Reset Removal Time
(Non-Pipelined Clock)
0.048
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.526
–
ns
Read Asynchronous Reset Recovery Time
(Non-Pipelined Clock)
0.245
–
ns
–
0.873
ns
tCLK2Q
tADDRSU
tADDRHD
tRSTREM
tRSTREC
tR2Q
Read Asynchronous Reset to Output Propagation Delay
(with Pipe-Line Register Enabled)
tSRSTSU
Read Synchronous Reset Setup Time
0.281
–
ns
tSRSTHD
Read Synchronous Reset Hold Time
0.063
–
ns
tCCY
Write Clock Period
4
–
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
1.8
–
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.8
–
ns
tBLKCSU
Write Block Setup Time
0.419
–
ns
tBLKCHD
Write Block Hold Time
0.007
–
ns
tDINCSU
Write Input Data setup Time
0.119
–
ns
Revision 1
71
IGLOO2 FPGA Automotive Grade 1
Table 115 • uSRAM (RAM64x18) in 64x18 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tDINCHD
Write Input Data hold Time
0.156
–
ns
tADDRCSU
Write Address Setup Time
0.091
–
ns
tADDRCHD
Write Address Hold Time
0.132
–
ns
tWECSU
Write Enable Setup Time
0.412
–
ns
tWECHD
Write Enable Hold Time
-0.027
–
ns
Fmax
Maximum Frequency
–
250
MHz
Table 116 • uSRAM (RAM64x16) in 64x16 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tCY
Read Clock Period
tCLKMPWH
Read Clock Minimum Pulse Width High
1.8
–
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
1.8
–
ns
tPLCY
Read Pipe-line clock period
4
–
ns
tPLCLKMPWH
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tPLCLKMPWL
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.277
ns
Read Access Time without Pipeline Register
–
1.745
ns
Read Address Setup Time in Synchronous Mode
0.312
–
ns
Read Address Setup Time in Asynchronous Mode
1.924
–
ns
Read Address Hold Time in Synchronous Mode
0.094
–
ns
Read Address Hold Time in Asynchronous Mode
-0.806
–
ns
tRDENSU
Read Enable Setup Time
0.288
–
ns
tRDENHD
Read Enable Hold Time
0.059
–
ns
tBLKSU
Read Block Select Setup Time
1.905
–
ns
tBLKHD
Read Block Select Hold Time
-0.674
–
ns
tBLK2Q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.11
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
-0.151
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
Clock)
0.048
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.526
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
Clock)
0.245
–
ns
tCLK2Q
tADDRSU
tADDRHD
tRSTREM
tRSTREC
Revision 1
72
IGLOO2 FPGA Automotive Grade 1
Table 116 • uSRAM (RAM64x16) in 64x16 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tR2Q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
–
0.869
ns
tSRSTSU
Read Synchronous Reset Setup Time
0.281
–
ns
tSRSTHD
Read Synchronous Reset Hold Time
0.063
tCCY
Write Clock Period
tCCLKMPWH
ns
4
–
ns
Write Clock Minimum Pulse Width High
1.8
–
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.8
–
ns
tBLKCSU
Write Block Setup Time
0.419
–
ns
tBLKCHD
Write Block Hold Time
0.007
–
ns
tDINCSU
Write Input Data setup Time
0.119
–
ns
tDINCHD
Write Input Data hold Time
0.156
–
ns
tADDRCSU
Write Address Setup Time
0.091
–
ns
tADDRCHD
Write Address Hold Time
0.132
–
ns
tWECSU
Write Enable Setup Time
0.412
–
ns
tWECHD
Write Enable Hold Time
-0.027
–
ns
Fmax
Maximum Frequency
–
250
MHz
Table 117 • uSRAM (RAM128x9) in 128x9 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tCY
Read Clock Period
tCLKMPWH
Read Clock Minimum Pulse Width High
1.8
–
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
1.8
–
ns
tPLCY
Read Pipe-line clock period
4
–
ns
tPLCLKMPWH
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tPLCLKMPWL
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.277
ns
Read Access Time without Pipeline Register
–
1.783
ns
Read Address Setup Time in Synchronous Mode
0.312
–
ns
Read Address Setup Time in Asynchronous Mode
1.967
–
ns
Read Address Hold Time in Synchronous Mode
0.125
–
ns
Read Address Hold Time in Asynchronous Mode
-0.707
–
ns
tRDENSU
Read Enable Setup Time
0.288
–
ns
tRDENHD
Read Enable Hold Time
0.059
–
ns
tCLK2Q
tADDRSU
tADDRHD
Revision 1
73
IGLOO2 FPGA Automotive Grade 1
Table 117 • uSRAM (RAM128x9) in 128x9 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tBLKSU
Read Block Select Setup Time
1.905
–
ns
tBLKHD
Read Block Select Hold Time
-0.674
–
ns
tBLK2Q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.148
ns
-0.151
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
0.048
Clock)
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.526
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
0.245
Clock)
–
ns
–
0.869
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
tRSTREM
tRSTREC
tR2Q
Read Asynchronous Reset to Output Propagation Delay (with
Pipe-Line Register Enabled)
tSRSTSU
Read Synchronous Reset Setup Time
0.281
–
ns
tSRSTHD
Read Synchronous Reset Hold Time
0.063
–
ns
tCCY
Write Clock Period
4
–
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
1.8
–
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.8
–
ns
tBLKCSU
Write Block Setup Time
0.419
–
ns
tBLKCHD
Write Block Hold Time
0.007
–
ns
tDINCSU
Write Input Data setup Time
0.104
–
ns
tDINCHD
Write Input Data hold Time
0.142
–
ns
tADDRCSU
Write Address Setup Time
0.091
–
ns
tADDRCHD
Write Address Hold Time
0.241
–
ns
tWECSU
Write Enable Setup Time
0.412
–
ns
tWECHD
Write Enable Hold Time
-0.027
–
ns
Fmax
Maximum Frequency
–
250
MHz
Table 118 • uSRAM (RAM128x8) in 128x8 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tCY
Read Clock Period
tCLKMPWH
Read Clock Minimum Pulse Width High
1.8
–
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
1.8
–
ns
tPLCY
Read Pipe-line clock period
4
–
ns
tPLCLKMPWH
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
Revision 1
74
IGLOO2 FPGA Automotive Grade 1
Table 118 • uSRAM (RAM128x8) in 128x8 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
1.8
–
ns
Read Access Time with Pipeline Register
–
0.277
ns
Read Access Time without Pipeline Register
–
1.783
ns
Read Address Setup Time in Synchronous Mode
0.312
–
ns
Read Address Setup Time in Asynchronous Mode
1.967
–
ns
Read Address Hold Time in Synchronous Mode
0.125
–
ns
Read Address Hold Time in Asynchronous Mode
-0.707
–
ns
tRDENSU
Read Enable Setup Time
0.288
–
ns
tRDENHD
Read Enable Hold Time
0.059
–
ns
tBLKSU
Read Block Select Setup Time
1.905
–
ns
tBLKHD
Read Block Select Hold Time
-0.674
–
ns
tBLK2Q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.148
ns
-0.151
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
0.048
Clock)
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.526
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
0.245
Clock)
–
ns
–
0.869
ns
tPLCLKMPWL
tCLK2Q
tADDRSU
tADDRHD
Read Pipe-line clock Minimum Pulse Width Low
Read Asynchronous Reset Removal Time (Pipelined Clock)
tRSTREM
tRSTREC
tR2Q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
tSRSTSU
Read Synchronous Reset Setup Time
0.281
–
ns
tSRSTHD
Read Synchronous Reset Hold Time
0.063
–
ns
tCCY
Write Clock Period
4
–
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
1.8
–
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.8
–
ns
tBLKCSU
Write Block Setup Time
0.419
–
ns
tBLKCHD
Write Block Hold Time
0.007
–
ns
tDINCSU
Write Input Data setup Time
0.104
–
ns
tDINCHD
Write Input Data hold Time
0.142
–
ns
tADDRCSU
Write Address Setup Time
0.091
–
ns
tADDRCHD
Write Address Hold Time
0.241
–
ns
tWECSU
Write Enable Setup Time
0.412
–
ns
tWECHD
Write Enable Hold Time
-0.027
–
ns
Fmax
Maximum Frequency
–
250
MHz
Revision 1
75
IGLOO2 FPGA Automotive Grade 1
Table 119 • uSRAM (RAM256x4) in 256x4 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tCY
Read Clock Period
tCLKMPWH
Read Clock Minimum Pulse Width High
1.8
–
ns
tCLKMPWL
Read Clock Minimum pulse Width Low
1.8
–
ns
tPLCY
Read Pipe-line clock period
4
–
ns
tPLCLKMPWH
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tPLCLKMPWL
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.277
ns
Read Access Time without Pipeline Register
–
1.819
ns
Read Address Setup Time in Synchronous Mode
0.312
–
ns
Read Address Setup Time in Asynchronous Mode
2.001
–
ns
Read Address Hold Time in Synchronous Mode
0.125
–
ns
Read Address Hold Time in Asynchronous Mode
-0.672
–
ns
tRDENSU
Read Enable Setup Time
0.288
–
ns
tRDENHD
Read Enable Hold Time
0.059
–
ns
tBLKSU
Read Block Select Setup Time
1.905
–
ns
tBLKHD
Read Block Select Hold Time
-0.674
–
ns
tBLK2Q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.175
ns
-0.151
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
0.048
Clock)
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.526
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
0.245
Clock)
–
ns
–
0.866
ns
tCLK2Q
tADDRSU
tADDRHD
Read Asynchronous Reset Removal Time (Pipelined Clock)
tRSTREM
tRSTREC
tR2Q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
tSRSTSU
Read Synchronous Reset Setup Time
0.281
–
ns
tSRSTHD
Read Synchronous Reset Hold Time
0.063
–
ns
tCCY
Write Clock Period
4
–
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
1.8
–
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.8
–
ns
tBLKCSU
Write Block Setup Time
0.419
–
ns
tBLKCHD
Write Block Hold Time
0.007
–
ns
tDINCSU
Write Input Data setup Time
0.104
–
ns
tDINCHD
Write Input Data hold Time
0.142
–
ns
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Table 119 • uSRAM (RAM256x4) in 256x4 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tADDRCSU
Write Address Setup Time
0.091
–
ns
tADDRCHD
Write Address Hold Time
0.254
–
ns
tWECSU
Write Enable Setup Time
0.412
–
ns
tWECHD
Write Enable Hold Time
-0.027
–
ns
Fmax
Maximum Frequency
–
250
MHz
Table 120 • uSRAM (RAM512x2) in 512x2 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tCY
Read Clock Period
tCLKMPWH
Read Clock Minimum Pulse Width High
1.8
tCLKMPWL
Read Clock Minimum pulse Width Low
1.8
–
ns
tPLCY
Read Pipe-line clock period
4
–
ns
tPLCLKMPWH
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tPLCLKMPWL
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.277
ns
Read Access Time without Pipeline Register
–
1.831
ns
Read Address Setup Time in Synchronous Mode
0.312
–
ns
Read Address Setup Time in Asynchronous Mode
2.031
–
ns
Read Address Hold Time in Synchronous Mode
0.142
–
ns
Read Address Hold Time in Asynchronous Mode
-0.602
–
ns
tRDENSU
Read Enable Setup Time
0.288
–
ns
tRDENHD
Read Enable Hold Time
0.059
–
ns
tBLKSU
Read Block Select Setup Time
1.905
–
ns
tBLKHD
Read Block Select Hold Time
-0.674
–
ns
tBLK2Q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
–
2.228
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
-0.151
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
Clock)
0.048
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.526
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
Clock)
0.245
–
ns
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
–
0.865
ns
tCLK2Q
tADDRSU
tADDRHD
tRSTREM
tRSTREC
tR2Q
Revision 1
ns
77
IGLOO2 FPGA Automotive Grade 1
Table 120 • uSRAM (RAM512x2) in 512x2 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
tSRSTSU
Read Synchronous Reset Setup Time
0.281
–
ns
tSRSTHD
Read Synchronous Reset Hold Time
0.063
–
ns
tCCY
Write Clock Period
4
–
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
1.8
–
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.8
–
ns
tBLKCSU
Write Block Setup Time
0.419
–
ns
tBLKCHD
Write Block Hold Time
0.007
–
ns
tDINCSU
Write Input Data setup Time
0.104
–
ns
tDINCHD
Write Input Data hold Time
0.142
–
ns
tADDRCSU
Write Address Setup Time
0.091
–
ns
tADDRCHD
Write Address Hold Time
0.256
–
ns
tWECSU
Write Enable Setup Time
0.412
–
ns
tWECHD
Write Enable Hold Time
-0.027
–
ns
Fmax
Maximum Frequency
–
250
MHz
Table 121 • uSRAM (RAM1024x1) in 1024x1 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Parameter
Description
Min
Max
Units
4
–
ns
tCY
Read Clock Period
tCLKMPWH
Read Clock Minimum Pulse Width High
1.8
tCLKMPWL
Read Clock Minimum pulse Width Low
1.8
–
ns
tPLCY
Read Pipe-line clock period
4
–
ns
tPLCLKMPWH
Read Pipe-line clock Minimum Pulse Width High
1.8
–
ns
tPLCLKMPWL
Read Pipe-line clock Minimum Pulse Width Low
1.8
–
ns
Read Access Time with Pipeline Register
–
0.275
ns
Read Access Time without Pipeline Register
–
1.846
ns
Read Address Setup Time in Synchronous Mode
0.312
–
ns
Read Address Setup Time in Asynchronous Mode
2.05
–
ns
Read Address Hold Time in Synchronous Mode
0.142
–
ns
Read Address Hold Time in Asynchronous Mode
-0.626
–
ns
tRDENSU
Read Enable Setup Time
0.288
–
ns
tRDENHD
Read Enable Hold Time
0.059
–
ns
tBLKSU
Read Block Select Setup Time
1.905
–
ns
tCLK2Q
tADDRSU
tADDRHD
Revision 1
ns
78
IGLOO2 FPGA Automotive Grade 1
Table 121 • uSRAM (RAM1024x1) in 1024x1 Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Speed Grade
–1
Parameter
Description
Min
Max
Units
-0.674
–
ns
–
2.245
ns
Read Asynchronous Reset Removal Time (Pipelined Clock)
-0.151
–
ns
Read Asynchronous Reset Removal Time (Non-Pipelined
Clock)
0.048
–
ns
Read Asynchronous Reset Recovery Time (Pipelined Clock)
0.526
–
ns
Read Asynchronous Reset Recovery Time (Non-Pipelined
Clock)
0.245
–
ns
tR2Q
Read Asynchronous Reset to Output Propagation Delay (With
Pipe-Line Register Enabled)
–
0.865
ns
tSRSTSU
Read Synchronous Reset Setup Time
0.281
–
ns
tSRSTHD
Read Synchronous Reset Hold Time
0.063
–
ns
tCCY
Write Clock Period
4
–
ns
tCCLKMPWH
Write Clock Minimum Pulse Width High
1.8
–
ns
tCCLKMPWL
Write Clock Minimum Pulse Width Low
1.8
–
ns
tBLKCSU
Write Block Setup Time
0.419
–
ns
tBLKCHD
Write Block Hold Time
0.007
–
ns
tDINCSU
Write Input Data setup Time
0.003
–
ns
tDINCHD
Write Input Data hold Time
0.142
–
ns
tADDRCSU
Write Address Setup Time
0.091
–
ns
tADDRCHD
Write Address Hold Time
0.256
–
ns
tWECSU
Write Enable Setup Time
0.412
–
ns
tWECHD
Write Enable Hold Time
-0.027
–
ns
Fmax
Maximum Frequency
–
250
MHz
tBLKHD
Read Block Select Hold Time
tBLK2Q
Read Block Select to Out Disable Time (when Pipe-Lined
Registered is Disabled)
tRSTREM
tRSTREC
Revision 1
79
IGLOO2 FPGA Automotive Grade 1
12. Embedded NVM (eNVM) Characteristics
Table 122 • eNVM Read Performance
Worst-Case Conditions: VDD = 1.14 V, VPPNVM = VPP = 2.375 V
Symbol
TJ
Description
Operating Temperature Range
Unit
-40°C to 135°C
°C
Junction Temperature Range
Speed grade –
-1
–
–
FMAXREAD
25
–
MHz
eNVM Maximum Read Frequency
Table 123 • eNVM Page Programming
Worst-Case Conditions: VDD = 1.14 V, VPPNVM = VPP = 2.375 V
Symbol
TJ
Description
Operating Temperature Range
Unit
-40°C to 135°C
°C
Junction Temperature Range
Speed grade –
tPAGEPGM
eNVM Page Programming Time
-1
–
–
40
–
ms
13. Crystal Oscillator
Table 124 describes the electrical characteristics of the crystal oscillator in the IGLOO2 FPGAs.
Table 124 • Electrical Characteristics of the Crystal Oscillator – High Gain Mode (20 MHz)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
FXTAL
Operating frequency
–
20
–
MHz
ACCXTAL
Accuracy
–
–
0.008
%
CYCXTAL
Output duty cycle
–
49-51
47-53
%
JITPERXTAL
Output Period Jitter (peak to peak)
–
200
460
ps
JITCYCXTAL
Output Cycle to Cycle Jitter (peak to
peak)
–
200
850
ps
IDYNXTAL
Operating current
–
1.5
–
mA
VIHXTAL
Input logic level High
0.9 × VPP
–
–
V
VILXTAL
Input logic level Low
–
–
0.1 × VPP
V
SUXTAL
Startup time (with regard to
oscillator output)
–
–
1.2
ms
stable
Table 125 • Electrical Characteristics of the Crystal Oscillator – Medium Gain Mode (2 MHz)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
FXTAL
Operating frequency
–
2
–
MHz
ACCXTAL
Accuracy
–
–
0.003
%
CYCXTAL
Output duty cycle
–
49–51
46-54
%
JITPERXTAL
Output Period Jitter (peak to peak)
–
1
5
ns
JITCYCXTAL
Output Cycle to Cycle Jitter (peak to
peak)
–
1
5
ns
Revision 1
80
IGLOO2 FPGA Automotive Grade 1
Table 125 • Electrical Characteristics of the Crystal Oscillator – Medium Gain Mode (2 MHz)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Parameter
Description
Min
Typ
Max
Units
–
0.3
–
mA
IDYNXTAL
Operating current
VIHXTAL
Input logic level High
0.9 × VPP
–
–
V
VILXTAL
Input logic level Low
–
–
0.1 × VPP
V
SUXTAL
Startup time (with regard to stable
oscillator output)
–
–
9
ms
Table 126 • Electrical Characteristics of the Crystal Oscillator – Low Gain Mode (32 kHz)
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Min
Typ
Max
Units
FXTAL
Operating frequency
–
32
–
kHz
ACCXTAL
Accuracy
–
–
0.009
%
CYCXTAL
Output duty cycle
–
49–51
44-56
%
JITPERXTAL
Output Period Jitter (peak to peak)
–
150
300
ns
JITCYCXTAL
Output Cycle to Cycle Jitter (peak to peak)
–
150
300
ns
IDYNXTAL
Operating current
–
0.044
–
mA
VIHXTAL
Input logic level High
0.9 × VPP
–
–
V
VILXTAL
Input logic level Low
–
–
0.1 × VPP
V
SUXTAL
Startup time (with
oscillator output)
–
–
152
ms
regard
to
stable
14. On-Chip Oscillator
Table 127 and Table 128 describe the electrical characteristics of the available on-chip oscillators in the IGLOO2
FPGAs.
Table 127 • Electrical Characteristics of the 50 MHz RC Oscillator
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Condition
Min
Typ
Max
Units
F50RC
Operating frequency
–
–
50
–
MHz
ACC50RC
Accuracy
–
–
1
10
%
CYC50RC
Output duty cycle
–
–
49–
51
46–54
%
JIT50RC
Output jitter (peak to peak)
Period Jitter
200
550
ps
Cycle-to-Cycle Jitter
320
930
ps
IDYN50RC
Operating current
8.5
–
mA
–
Revision 1
–
81
IGLOO2 FPGA Automotive Grade 1
Table 128 • Electrical Characteristics of the 1 MHz RC Oscillator
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Description
Condition
Min
Typ
Max
Units
F1RC
Operating frequency
–
–
1
–
MHz
ACC1RC
Accuracy
–
–
1
7
%
CYC1RC
Output duty cycle
–
–
49–51
46.5–53.5
%
JIT1RC
Output jitter (peak to peak)
Period Jitter
–
10
36
ps
Cycle-to-Cycle Jitter
–
10
50
ps
IDYN1RC
Operating current
–
–
0.1
–
mA
SU1RC
Startup time
–
–
–
24
µs
15. Clock Conditioning Circuits (CCC)
Table 129 • IGLOO2 FPGAs CCC/PLL Specification
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Min
Typ
Max
Units
Notes
1
–
200
MHz
–
32 kHz Capable CCC
0.032
–
200
MHz
–
Clock conditioning circuitry
output frequency fOUT_CCC
–
0.078
–
400
MHz
1
PLL VCO frequency
–
500
–
1000
MHz
2
Delay increments in
programmable delay blocks
–
–
75
100
ps
–
Number of programmable
values in each programmable –
delay block
–
–
64
–
–
fIN >= 1 MHz
–
70
100
µs
–
fIN = 32 kHz
–
1
16
ms
1 MHz ≤ fIN_CCC ≤ 25 MHz
10
–
90
%
–
25 MHz ≤ fIN_CCC ≤ 100 MHz
25
–
75
%
–
100 MHz ≤ fIN_CCC ≤ 150 MHz
35
–
65
%
–
150 MHz ≤ fIN_CCC ≤ 200 MHz
45
–
55
%
–
Clock conditioning circuitry
input frequency fIN_CCC
Acquisition time
Conditions
All CCC
Internal Feedback
Input duty cycle
(Reference Clock)
External Feedback (CCC, FPGA, Off-chip)
Output duty cycle
1 MHz ≤ fIN_CCC ≤ 25 MHz
25
–
75
%
–
25 MHz ≤ fIN_CCC ≤ 35 MHz
35
–
65
%
–
35 MHz ≤ fIN_CCC ≤ 50 MHz
45
–
55
%
–
005, 010, and 025 Devices
46
–
52
%
–
090 Devices
44
–
52
%
–
Revision 1
82
IGLOO2 FPGA Automotive Grade 1
Table 129 • IGLOO2 FPGAs CCC/PLL Specification
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
Parameter
Conditions
Min
Typ
Max
Units
Notes
Modulation frequency range
–
25
35
50
kHz
–
Modulation depth range
–
0
–
1.5
%
–
Modulation depth control
–
–
0.5
–
%
–
Spread Spectrum Characteristics
Notes:
1. The minimum output clock frequency is limited by the PLL. For more information refer to the
UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide.
2. The PLL is used in conjunction with the Clock Conditioning Circuitry. Performance will be limited by the CCC output
frequency.
Table 130 • IGLOO2 FPGAs CCC/PLL Jitter Specifications
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Parameter
Conditions/Package Combinations
Units Notes
CCC Output Peak-to-Peak Period Jitter fOUT_CCC
010 FGG484 Packages
0 < SSO
<= 2
SSO = 0
20 MHz to 100 MHz
Max(110, ± 1% x (1/fOUT_CCC))
100 MHz to 400 MHz
120
025 FGG484 Package
SSO
<= 4
SSO
<= 16
–
*
Max(150, ± 1% x (1/fOUT_CCC))
ps
–
ps
–
150
SSO
<= 8
170
0 < SSO <=16
*
20 MHz to 74 MHz
± 1% x (1/fOUT_CCC)
ps
–
74 MHz to 400 MHz
210
ps
–
005 FGG484 Package
0 < SSO <=16
*
20 MHz to 53 MHz
± 1% x (1/fOUT_CCC)
ps
–
53 MHz to 400 MHz
270
ps
–
060 FG676 Package
0 < SSO <=16
*
20 MHz to 100 MHz
± 1% x (1/fOUT_CCC)
ps
–
100 MHz to 400 MHz
150
ps
–
090
FGG484
FGG676
and
0 < SSO <=16
*
20 MHz to 100 MHz
± 1% x (1/fOUT_CCC)
ps
–
100 MHz to 400 MHz
150
ps
–
Note: *SSO Data is based on LVCMOS 2.5 V MSIO and/or MSIOD Bank I/Os.
Revision 1
83
IGLOO2 FPGA Automotive Grade 1
Table 131 • Programming Times
Typical Automotive Grade 1 Conditions: TJ = 25°C, VDD = 1.2 V
SPI
CLK
=
12.5
MHz
47
27
28
sec
M2GL010
568784
28
18
7
23
12
10
26
14
77
35
35
sec
M2GL025
1223504
51
26
14
33
23
21
39
29
150
42
41
sec
M2GL060
2418896
77
54
39
61
50
44
65
54
291
83
82
sec
M2GL090
3645968
113
126
60
84
73
66
90
79
427
109
108
sec
M2GL005
137536
39
4
2
37
5
3
42
4
41
48
49
sec
M2GL010
274816
78
9
4
76
11
4
82
7
86
87
87
sec
M2GL025
274816
78
9
4
78
10
4
82
8
87
85
86
sec
M2GL060
268480
76
8
5
76
22
6
80
8
78
86
86
sec
M2GL090
544496
154
15
10
152
43
10
157
15
154
162
162
sec
M2GL005
439296
59
11
6
56
11
9
61
11
87
67
66
sec
M2GL010
842688
107
20
11
100
21
15
107
21
161
113
113
sec
M2GL025
1497408
120
35
19
113
32
26
121
35
229
120
121
sec
M2GL060
2686464
158
70
43
137
70
48
143
60
368
161
158
sec
M2GL090
4190208
266
147
68
236
115
75
244
91
582
261
260
sec
Units
8
Program
19
Program
6
Program
6
Verify
17
Program
4
Program
10
Verify
22
Program
302672
Image Size
Bytes
Authenticate
SPI
CLK
= 25
MHz
Verify
SPI
CLK
= 100
KHz
M2GL005
Device
Fabric Only
eNVM Only
Fabric + eNVM
MSS/Cortex-M3
ISP (SmartFusion2
Only)
2 Step IAP
Authenticate
JTAG
Prog
Auto
ram
Prog Auto ming
ram Upda Reco
ming
te
very
Notes:
• External SPI flash part# AT25DF641-s3H is used during this measurement.
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IGLOO2 FPGA Automotive Grade 1
Table 132 • Programming Times
Worst-case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
SPI
CLK
=
12.5
MHz
8
69
49
50
sec
M2GL010
568784
50
18
7
45
12
10
48
14
99
57
57
sec
M2GL025
1223504
73
26
14
55
23
21
61
29
150
64
63
sec
M2GL060
2418896
99
54
39
83
50
44
87
54
313
105
104
sec
M2GL090
3645968
135
126
60
106
73
66
112
79
449
131
130
sec
M2GL005
137536
61
4
2
59
5
3
64
4
63
70
71
sec
M2GL010
274816
100
9
4
98
11
4
104
7
108
109
109
sec
M2GL025
274816
100
9
4
100
10
4
104
8
109
107
108
sec
M2GL060
268480
98
8
5
98
22
6
102
8
100
108
108
sec
M2GL090
544496
176
15
10
174
43
10
179
15
176
184
184
sec
M2GL005
439296
71
11
6
78
11
9
83
11
109
89
88
sec
M2GL010
842688
129
20
11
122
21
15
129
21
183
135
135
sec
M2GL025
1497408
142
35
19
135
32
26
143
35
251
142
143
sec
M2GL060
2686464
180
70
43
159
70
48
165
60
390
183
180
sec
M2GL090
4190208
288
147
68
258
115
75
266
91
604
283
282
sec
Verify
Units
41
Program
6
Program
6
Program
39
Program
4
Program
10
Verify
44
Program
302672
Image Size
Bytes
Authenticate
SPI
CLK
= 25
MHz
Verify
SPI
CLK
=
100
KHz
M2GL005
Device
Fabric Only
eNVM Only
Fabric + eNVM
2 Step IAP
Authenticate
JTAG
MSS/Cortex-M3
ISP
(SmartFusion2
Only)
Prog
Auto
ram
Prog Auto ming
ram Upd Reco
ming ate very
Notes:
• External SPI flash part# AT25DF641-s3H is used during this measurement.
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IGLOO2 FPGA Automotive Grade 1
16. JTAG
Table 133 • JTAG 1532
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
-1 Speed Grade
Parameter
Description
005
010
025
060
090
Units
tTCK2Q
Clock to Q (data out)
7.71
7.91
7.95
8.61
9.21
ns
tRSTB2Q
Reset to Q (data out)
7.91
6.54
6.27
8.79
7.94
ns
tDISU
Test Data Input Setup Time
-1.07
-0.70
-0.70
-1.20
-1.33
ns
tDIHD
Test Data Input Hold Time
2.43
2.38
2.47
2.57
2.71
ns
tTMSSU
Test Mode Select Setup Time
-0.75
-0.86
-1.13
-0.99
-1.03
ns
tTMDHD
Test Mode Select Hold Time
1.41
1.48
1.98
1.72
1.69
ns
tTRSTREM
ResetB Removal Time
-0.81
-1.1
-1.38
-1.24
-0.8
ns
tTRSTREC
ResetB Recovery Time
-0.81
-1.1
-1.38
-1.25
-0.8
ns
FTCKMAX
TCK Maximum frequency
25
25
25
25
25
MHz
17. DEVRST_N Characteristics
Table 134 • DEVRST_N Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
All Devices/Speed Grades
Symbol
Description
Min
Typ
Max
Units
Notes
TRAMPDEVRSTN
DEVRST_N ramp rate
–
–
1
µs
–
FMAXPDEVRSTN
DEVRST_N cycling rate
–
–
100
kHz
–
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IGLOO2 FPGA Automotive Grade 1
18. System Controller SPI Characteristics Table 135 • System Controller SPI Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
All Devices/Speed
Grades
Symbol
Description
Conditions
Min
Typ
Max
Units Notes
–
sp1
SC_SPI_SCK minimum period
–
20
–
–
ns
–
sp2
SC_SPI_SCK minimum pulse width
high
–
10
–
–
ns
–
sp3
SC_SPI_SCK minimum pulse width
low
–
10
–
–
ns
–
–
1.239
–
ns
*
–
1.245
–
ns
*
sp4
sp5
SC_SPI_SCK, SC_SPI_SDO,
SC_SPI_SS rise time
(10%-90%) 1
SC_SPI_SCK, SC_SPI_SDO,
SC_SPI_SS fall time
(10%-90%) 1
I/O Configuration: LVTTL
3.3V- 20mA
AC Loading: 35pF
Test Conditions:
Voltage, 25C
Typical
I/O Configuration: LVTTL
3.3V- 20mA
AC Loading: 35pF
Test Conditions:
Voltage, 25C
Typical
sp6
Data from master (SC_SPI_SDO)
setup time
–
160
–
–
ns
–
sp7
Data from master (SC_SPI_SDO) hold
–
time
160
–
–
ns
–
sp8
SC_SPI_SDI setup time
–
20
–
–
ns
–
sp9
SC_SPI_SDI hold time
–
20
–
–
ns
–
Note: *For specific Rise/Fall Times, board design considerations and detailed output buffer resistances, use the
corresponding IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models. Use the supported I/O Configurations
for the System Controller SPI in Table 136.
Table 136 • Supported I/O Configurations for System Controller SPI (for MSIO Bank Only)
Voltage Supply
I/O Drive Configuration
Units
3.3 V
20
mA
2.5 V
16
mA
1.8 V
12
mA
1.5 V
8
mA
1.2 V
4
mA
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19. Mathblock Timing Characteristics
The fundamental building block in any digital signal processing algorithm is the multiply-accumulate function. Each
IGLOO2 mathblock supports 18 x 18 signed multiplication, dot product, and built-in addition, subtraction, and
accumulation units to combine multiplication results efficiently.
Table 137 • Mathblocks With All Registers Used
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Mathblock With All Registers Used
Parameter
Description
Min
Max
Units
tMISU
Input, Control Register Setup time
0.155
–
ns
tMIHD
Input, Control Register Hold time
0.083
–
ns
tMOCDINSU
CDIN Input Setup time
1.741
–
ns
tMOCDINHD
CDIN Input Hold time
-0.434
–
ns
tMSRSTENSU
Synchronous Reset/Enable Setup time
0.192
–
ns
tMSRSTENHD
Synchronous Reset/Enable Hold time
0.012
–
ns
tMARSTREM
Asynchronous Reset Removal time
0
–
ns
tMARSTREC
Asynchronous Reset Recovery time
0.091
–
ns
tMOCQ
Output Register Clock to Out delay
–
0.241
ns
tMCLKMP
CLK Minimum period
2.327
–
ns
Table 138 • Mathblock With Input Bypassed and Output Registers Used
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Mathblock With Input Bypassed and Output Registers Used
Speed Grade
–1
Parameter
Min
Max
Units
Description
tMOSU
Output Register Setup time
2.378
–
ns
tMOHD
Output Register Hold time
-0.46
–
ns
tMOCDINSU
CDIN Input Setup time
1.741
–
ns
tMOCDINHD
CDIN Input Hold time
-0.434
–
ns
tMSRSTENSU
Synchronous Reset/Enable Setup time
0.119
–
ns
tMSRSTENHD
Synchronous Reset/Enable Hold time
0.012
–
ns
tMARSTREM
Asynchronous Reset Removal time
0
–
ns
tMARSTREC
Asynchronous Reset Recovery time
0.015
–
ns
tMOCQ
Output Register Clock to Out delay
–
0.241
ns
tMCLKMP
CLK Minimum period
2.258
–
ns
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IGLOO2 FPGA Automotive Grade 1
Table 139 • Mathblock With Input Register Used and Output in Bypass Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Mathblock With Input Register Used and Output in Bypass Mode
Speed Grade
–1
Parameter
Min
Max
Units
Description
tMISU
Input Register Setup time
0.155
–
ns
tMIHD
Input Register Hold time
0.083
–
ns
tMSRSTENSU
Synchronous Reset/Enable Setup time
0.192
–
ns
tMSRSTENHD
Synchronous Reset/Enable Hold time
-0.013
–
ns
tMARSTREM
Asynchronous Reset Removal time
-0.005
–
ns
tMARSTREC
Asynchronous Reset Recovery time
0.091
–
ns
tMICQ
Input Register Clock to Output delay
–
2.611
ns
tMCDIN2Q
CDIN to Output delay
–
2.022
ns
Table 140 • Mathblock With Input and Output in Bypass Mode
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Speed Grade
–1
Mathblock With Input and Output in Bypass Mode
Parameter
Description
Min
Max
Units
tMIQ
Input to Output delay
–
2.662
ns
tMCDIN2Q
CDIN to Output delay
–
2.022
ns
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20. Flash*Freeze Timing Characteristics
Table 141 • Flash*Freeze Entry and Exit Times
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Symbols
Parameters
TFF_ENTRY Entry time
Conditions
Entry/Exit
Timing
FCLK=100 MHz
Entry/Exit
Timing
FCLK=3 MHz
Units
Notes
eNVM and MSS/HPMS PLL = ON
170
340
μs
–
eNVM and MSS/HPMS PLL =
OFF
230
460
μs
–
eNVM and MSS/HPMS PLL = ON
during F*F
110
150
μs
–
150
200
μs
–
210
300
μs
–
210
300
μs
–
1.5
1.5
ms
*
1.5
1.5
ms
*
30
30
μs
–
70
70
μs
–
eNVM = ON and MSS/HPMS PLL
=OFF
during
F*F
and
Exit
Time MSS/HPMS PLL turned back on
with respect at exit
to MSS PLL eNVM and MSS PLL = OFF
Lock
during F*F and both are turned
back on at exit
TFF_EXIT
eNVM = OFF and MSS PLL = ON
during F*F and eNVM turned
back on at exit
eNVM and MSS/HPMS PLL = ON
Exit
Time during F*F
with respect
to
Fabric eNVM and MSS PLL = OFF
during F*F and both are turned
PLL Lock
back on at exit
eNVM and MSS/HPMS PLL = ON
Exit
Time during F*F
with respect
to
Fabric eNVM and MSS PLL =O FF
buffer output during F*F and both are turned
back on at exit
Notes:
•
* PLL Lock Delay set to 1024 cycles (default)
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IGLOO2 FPGA Automotive Grade 1
21. IGLOO2 Specifications
21.1 HPMS Clock Frequency
Table 142 • Maximum Frequency for HPMS Main Clock
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
Symbol
Description
HPMS_CLK
Speed Grade
–1
Units
133
MHz
Maximum Frequency for the HPMS Main Clock (FCLK)
21.2 IGLOO2 Serial Peripheral Interface (SPI) Characteristics
This section describes the DC and switching of the SPI interface. Unless otherwise noted, all output characteristics
given are for a 35 pF load on the pins and all sequential timing characteristics are related to SPI_0_CLK. For timing
parameter definitions, refer to Figure 17 on page 93.
Table 143 • SPI Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V
All Devices/Speed Grades
Symbol
SPIFMAX
Description
Min
Typ
Max
Unit
Notes
Maximum operating frequency
of SPI interface
–
–
20
MHz
–
SPI_[0|1]_CLK = PCLK/2
12
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
48.2
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
0.1
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
0.19
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
0.39
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128
0.77
–
–
µs
–
SPI_[0|1]_CLK = PCLK/2
6
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
12.05
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
0.05
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
0.095
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
0.195
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128
0.385
–
–
µs
–
SPI_[0|1]_CLK minimum period
sp1
SPI_[0|1]_CLK minimum pulse width high
sp2
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IGLOO2 FPGA Automotive Grade 1
Table 143 • SPI Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
All Devices/Speed Grades
Symbol
Description
Min
Typ
Max
Unit
Notes
SPI_[0|1]_CLK = PCLK/2
6
–
–
ns
–
SPI_[0|1]_CLK = PCLK/4
12.05
–
–
ns
–
SPI_[0|1]_CLK = PCLK/8
24.1
–
–
ns
–
SPI_[0|1]_CLK = PCLK/16
0.05
–
–
µs
–
SPI_[0|1]_CLK = PCLK/32
0.095
–
–
µs
–
SPI_[0|1]_CLK = PCLK/64
0.195
–
–
µs
–
SPI_[0|1]_CLK = PCLK/128
0.385
–
–
µs
–
SPI_[0|1]_CLK minimum pulse width low
sp3
sp4
SPI_[0|1]_CLK, SPI_[0|1]_DO,
SPI_[0|1]_SS rise time (10%90%)
–
2.77
–
ns
1
sp5
SPI_[0|1]_CLK, SPI_[0|1]_DO,
SPI_[0|1]_SS fall time (10%90%)
–
2.906
–
ns
1
SPI Master Configuration (Applicable to 005, 010 and 025)
sp6m
SPI_[0|1]_DO setup time
(SPI_x_CLK_period/2) – 7.5
–
–
ns
2
sp7m
SPI_[0|1]_DO hold time
(SPI_x_CLK_period/2) – 2.5
–
–
ns
2
sp8m
SPI_[0|1]_DI setup time
12.5
–
–
ns
2
sp9m
SPI_[0|1]_DI hold time
2.5
–
–
ns
2
SPI Slave Configuration (Applicable to 005, 010 and 025)
sp6s
SPI_[0|1]_DO setup time
(SPI_x_CLK_period/2) – 16.5
–
–
ns
2
sp7s
SPI_[0|1]_DO hold time
(SPI_x_CLK_period/2) + 3.0
–
–
ns
2
sp8s
SPI_[0|1]_DI setup time
2
–
–
ns
2
sp9s
SPI_[0|1]_DI hold time
7.5
–
–
ns
2
SPI Master Configuration (Applicable to 060 and 090)
sp6m
SPI_[0|1]_DO setup time
(SPI_x_CLK_period/2) – 6.5
–
–
ns
2
sp7m
SPI_[0|1]_DO hold time
(SPI_x_CLK_period/2) – 9
–
–
ns
2
sp8m
SPI_[0|1]_DI setup time
15.5
–
–
ns
2
sp9m
SPI_[0|1]_DI hold time
-2
–
–
ns
2
SPI Slave Configuration (Applicable to 060 and 090)
sp6s
SPI_[0|1]_DO setup time
(SPI_x_CLK_period/2) – 15.5
–
–
ns
2
sp7s
SPI_[0|1]_DO hold time
(SPI_x_CLK_period/2) – 3
–
–
ns
2
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Table 143 • SPI Characteristics
Worst-Case Automotive Grade 1 Conditions: TJ = 135°C, VDD = 1.14 V (continued)
All Devices/Speed Grades
Symbol
Description
Min
Typ
Max
Unit
Notes
sp8s
SPI_[0|1]_DI setup time
3.5
–
–
ns
2
sp9s
SPI_[0|1]_DI hold time
3
–
–
ns
2
Notes:
1. For specific Rise/Fall Times board design considerations and detailed output buffer resistances, use the corresponding
IBIS models located on the Microsemi SoC Products Group website:
http://www.microsemi.com/products/fpga-soc/design-resources/ibis-models.
2. For allowable pclk configurations, refer to the Serial Peripheral Interface Controller section in the UG0331:
SmartFusion2 Microcontroller Subsystem User Guide.
SP1
SP4
SP2
50% 50%
SPI_0_CLK
SPO = 0
SP5
SP3
90%
50%
10%
10%
SPI_0_CLK
SPO = 1
90%
90%
SPI_0_SS
10%
1 0%
SP4
SP5
SP6
SPI_0_DO
5 0%
MSB
90%
9 0%
5 0%
10%
SP8
SPI_0_DI
SP7
50%
SP9
MSB
SP5
10%
SP4
50%
Figure 17 • SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Datasheet Information
List of Changes
The following table shows important changes made in this document for each revision.
Revision
Revision 1
(March 2016)
Changes
Initial release.
Page
NA
Revision 1
94
IGLOO2 FPGA Automotive Grade 1
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheet parameters are published before
data has been fully characterized from silicon devices. The data provided for a given device, as
highlighted in Table 1 on page 1 is designated as either "Product Brief," "Advance," "Preliminary," or
"Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general
product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be
used when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is
believed to be correct, but changes are possible.
Production
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR).
They could require an approved export license prior to export from the United States. An export includes
release of product or disclosure of technology to a foreign national inside or outside the United States.
Revision 1
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IGLOO2 FPGA Automotive Grade 1
Safety Critical, Life Support, and High-Reliability Applications
Policy
The products described in this advance status document may not have completed the Microsemi
qualification process. Products may be amended or enhanced during the product introduction and
qualification process, resulting in changes in device functionality or performance. It is the responsibility of
each customer to ensure the fitness of any product (but especially a new product) for a particular
purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications.
Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating
to life-support applications.
For more information covering all of the SoC Products Group’s products refer to the Reliability Report.
Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures.
Contact your local Sales office for additional reliability information.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo, CA 92656 USA. Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
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Revision 1
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Communication solutions, security technologies and scalable anti-tamper products; Ethernet
solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and
services. Microsemi is headquartered in Aliso Viejo, Calif., and has approximately 4,800
employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
© 2016 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
51700138-1/03.16
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