Key Sheet AD7176-2 One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com Highlights of the AD7176-2—24-Bit, 250 kSPS Sigma-Delta ADC with 20 µs Settling AVDD1 IOVDD REGCAPD AVDD2 REGCAPA REF– REF+ REFOUT BUFFERED PRECISION REFERENCE 1.8V LDO 1.8V LDO INT REF AIN0 CS AIN1 Σ-Δ ADC AIN2 DIGITAL FILTER SERIAL INTERFACE AND CONTROL SCLK DIN DOUT/RDY AIN3 I/O CONTROL AD7176-2 CROSSPOINT MULTIPLEXER AVSS GPIO0 GPIO1 XTAL1 CLKIO/XTAL2 DGND 11266-001 AIN4 SYNC/ERROR XTAL AND INTERNAL CLOCK OSCILLATOR CIRCUITRY Figure 1. Functional Block Diagram GENERAL DESCRIPTION FEATURES AND BENEFITS This key sheet provides users with an overview of the AD7176-2. Key attributes of the part include the following: The AD7176-2 offers the following features and benefits: 1 • • • • • • 1 Designed for process control: PLC/DCS modules, temperature and pressure measurement, medical and scientific multichannel instrumentation, and chromatography. Fast settling, highly accurate, high resolution, multiplexed, 24-bit Sigma-Delta (Σ-Δ) ADC for low bandwidth input signals with a fully flexible output data rate (ODR) between 5 SPS and 250 kSPS. Combines two fully differential or four pseudo differential input channels, selected via the integrated crosspoint multiplexer. With an ODR of 250 kSPS, the AD7176-2 boasts an rms noise of 9.7 µV when operating with the default Sinc5 + Sinc1 filter. User friendly, with the part being fully configurable over a 4-wire serial interface. Available in a small 24-lead TSSOP package, allowing a reduced board size. • • • • • • • • • Simultaneous 50 Hz and 60 Hz rejection at 27 SPS ODR Internal oscillator adds functionality and reduces external component count Optional split supply operation of ±2.5 V with AVDD1 referenced to AVSS System offset and gain errors can be corrected on a per channel basis Low noise performance across the ODR range Fully compatible with SPI, QSPI™, MICROWIRE®, and DSP Sinc5 + Sinc1, Sinc3, and enhanced 50 Hz and 60 Hz rejection digital filter options (see the Frequently Asked Questions section for more information) SPI configuration control 3- or 4-wire serial digital interface (Schmitt trigger on SCLK) This document provides users with an overview of the AD7176-2; it is not a notice of performance or intent. Refer to the AD7176-2 data sheet for performance and more specific information about this product. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2013 Analog Devices, Inc. All rights reserved. AD7176-2 Key Sheet KEY CHARACTERISTICS FUNDAMENTAL SPECIFICATIONS Table 1. Parameter ADC Type Number of Input Channels Min Resolution Output Data Rate (ODR) Differential Input Voltage Range Power Supply Voltage AVDD1 with Respect to AVSS AVDD2 with Respect to AVSS IOVDD with Respect to DGND Offset Error Gain Error Integral Nonlinearity (INL) With 2.5 V Reference With 5 V Reference Power Dissipation (AVDD1 = 5 V, AVDD2 = 2 V, IOVDD = 2 V) With External Clock and Reference With Internal Clock and Reference Operating Temperature Range Typ Max Σ- Δ ADC Two fully differential or four pseudo differential input channels 24 24 5 250,000 ±VREF 4.5 2 2 5.5 5.5 5.5 ±40 ±10 ±50 Unit Bits SPS V V V V µV ppm/FSR ±2.5 ±7 ±7 ppm of FSR ppm of FSR 20.1 22.25 23.15 25.9 +105 mW mW °C −40 NOISE Table 2. RMS Noise and Peak-to-Peak Resolution vs. Output Data Rate 1 Output Data Rate (SPS) 250,000 62,500 10,000 1000 60 50 16.7 5 1 Sinc5 + Sinc1 Filter (Default) Noise (µV rms) Peak-to-Peak Resolution (Bits) 9.7 17.2 5.4 18.2 2.5 19 0.82 20.8 0.46 21.4 0.42 21.7 0.42 21.7 0.32 22.2 Selected rates only; 1000 samples. Rev. 0 | Page 2 of 6 Noise (µV rms) 220 5.1 1.8 0.62 0.32 0.31 0.29 0.29 Sinc3 Filter Peak-to-Peak Resolution (Bits) 12.8 18.3 19.8 21 22 22 22.4 22.4 Key Sheet AD7176-2 OPERATING THE AD7176-2 ADC and Interface Mode Configuration DATA INTERFACE The data interface for the AD7176-2 is • • • Performed using a 4- or 3-wire SPI Compatible with SPI, QSPI, MICROWIRE, and DSP Allows a user to both write to and read from the AD7176-2 on the same data bus Indicates when transferred data is available by bringing the DOUT/RDY signal and the RDY bit in the status register low • AD7176-2 (SLAVE) CS1 ADC Mode Register The ADC mode register is used primarily to set the conversion mode of the ADC to either continuous or single conversion. The user can also select the standby and power-down modes as well as any of the calibration modes. In addition, this register contains the clock source select bits and the internal reference enable bits. Interface Mode Register The interface mode register is used to configure the digital interface operation. This register allows the user to control data-word length, CRC enable, and continuous read mode, as well as whether status bits are appended to the data that is read. SCLK DOUT/RDY The ADC mode register and the interface mode register (see Block A in Figure 3) configure the core peripherals to be used by the AD7176-2 and the mode for the digital interface. DSP/FPGA DIN (IF CS IS REQUIRED AS A DECODING SIGNAL, IT CAN BE GENERATED FROM A PORT PIN.) DATA MODES 11266-002 1CS IS PERMANENTLY TIED LOW IN THE 3-WIRE INTERFACE. There are three data modes available: continuous conversion mode, continuous read mode, and single conversion mode. Figure 2. AD7176-2 Data Interface, 4-Wire Table 3. 4-Wire Serial Interface Pin Functions Continuous Conversion Mode (Default) Pin CS1 Continuous conversion is the default power-up mode. In this mode, the AD7176-2 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is complete. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The user can read this register additional times, if required. SCLK DOUT/RDY DIN 1 Function Selects the ADC (also applicable in systems with multiple devices on the serial bus). Determines when data transfers (either on DIN or DOUT/RDY) occur. Accesses data from the on-chip registers. Indicates when the transferred data is available. Transfers data into the on-chip registers. CS is permanently tied low in the 3-wire interface. (If CS is required as a decoding signal, it can be generated from a port pin.) ACCESSING THE ADC REGISTER MAP The communications register controls access to the full register map of the ADC. This register is an 8-bit write only register. All communication begins by writing to the communications register. Figure 3 provides an overview of the configuration flow, which is divided into three blocks. A When several channels are enabled, the ADC automatically sequences through the enabled channels, performing one conversion on each channel. When all channels have been converted, the sequence starts again with the first channel. CS DIN DATA REQUEST WRITE TO ADC MODE REGISTER AND INTERFACE MODE REGISTER; SET UP HIGH LEVEL ADC PERIPHERALS AND INTERFACE DATA SET UP CONFIGURATION; FOUR POSSIBLE ADC SETUPS USING DEDICATED FILTER, OFFSET, AND GAIN REGISTERS DATA 11266-004 DOUT/RDY B DATA REQUEST SCLK C SELECT THE POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL AND MAP EACH CHANNEL TO A SETUP 11266-003 Figure 4. Continuous Conversion Mode Figure 3. Configuration Flow As Figure 3 shows, three configuration stages are required to set up the part. Continuous Read Mode In continuous read mode, it is not required to write to the communications register before reading ADC data; just apply the required number of SCLKs after DOUT/RDY goes low to indicate the end of a conversion. When the conversion is read, Rev. 0 | Page 3 of 6 AD7176-2 Key Sheet If several channels are enabled, the ADC automatically sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/RDY goes high and remains high until a valid conversion is available and CS is low. As soon as a conversion is available, DOUT/RDY goes low. The ADC then selects the next channel and begins another conversion. The user can read the present conversion while the next conversion is being performed. The two LSBs of the status register indicate the channel to which the conversion corresponds. DOUT/RDY returns high until the next conversion is available. In this mode, the data can be read only once. If multiple ADC channels are enabled, each channel is output in turn, with the status bits being appended to the data if DATA_STAT is set in the interface mode register. The status register indicates the channel to which the conversion corresponds. CS DIN CS DATA DATA DATA 11266-007 DOUT/RDY SCLK DATA REQUEST DIN Figure 5. Continuous Read Mode DATA DOUT/RDY In single conversion mode, the AD7176-2 performs a single conversion and is placed in standby mode after the conversion is complete. DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY goes high. The data register can be read several times, if required, even when DOUT/RDY has gone high. 11266-005 Single Conversion Mode SCLK Figure 6. Single Conversion Mode TYPICAL APPLICATION DIAGRAM GPIO0 AND GPIO1 OUTPUT HIGH = AVDD OUTPUT LOW = AVSS FOR SINGLE SUPPLY CASE OUTPUT HIGH = 5V OUTPUT LOW = GND GPIO0 GPIO1 16MHz 19 20 GPIO0 GPIO1 OPTIONAL EXTERNAL CRYSTAL CIRCUITRY CAPACITORS XTAL1 9 21 AIN0 IN0 CX2 CX1 CLKI0/XTAL2 10 DOUT/RDY 11 DOUT/RDY 22 AIN1 IN1 DIN DIN 12 IN2 23 AIN2 SCLK 13 24 AIN3 SYNC/ERROR 15 SCLK CS CS 14 IN3 SYNC/ERROR AD7176-2 AIN4 IN4 1 CLKIN OPTIONAL EXTERNAL CLOCK INPUT IOVDD IOVDD 16 AIN4 0.1µF DGND 17 1 VIN TP 2 VIN 0.1µF 0.1µF 1µF AVDD1 AVDD1 7 ADR445BRZ 0.1µF AVDD2 4 GND VOUT 6 TRIM TP 5 8 3 0.1µF 4.7µF REF+ AVDD2 0.1µF 8 0.1µF 2 REF– 4 REFOUT REGCAPA 5 2.5V REFERENCE OUTPUT 0.1µF AVSS 6 Figure 7. Typical Application Diagram Rev. 0 | Page 4 of 6 0.1µF 1µF 11266-006 4.7µF REGCAPD 18 3 NC NC 7 Key Sheet AD7176-2 FREQUENTLY ASKED QUESTIONS How fast can the AD7176-2 output data? The maximum ODR is 250 kSPS, but the AD7176-2 can be configured to output data at an ODR from 5 SPS to 250 kSPS. The AD7176-2 has a maximum ODR of 250 kSPS but a channel scan rate of 50 kSPS/channel. What does this mean? When operating the AD7176-2 with a single channel enabled, the device can output data at an ODR of up to 250 kSPS. However, when more than one channel is enabled, the full filter settling time must be allowed for each channel. The data rate for fully settled data is 50 kSPS. Therefore, if two channels are enabled, the output data rate for each channel is 50 kSPS/2, or 25 kSPS. What digital filtering options are available? The AD7176-2 has three filter options: Sinc5 + Sinc1, Sinc3, and enhanced 50 Hz and 60 Hz filters. The Sinc5 + Sinc1 filter is most suitable for multichannel applications in which fast multiplexing is required. The Sinc3 filter is best for singlechannel applications running at lower output data rates. In applications in which rejection of 50 Hz and 60 Hz is important, the enhanced 50 Hz and 60 Hz rejection filters should be used because they provide better performance than the Sinc5 + Sinc1 or Sinc3 filter and allow the user to trade off settling time or rejection to meet the needs of a given application. For more on digital filters, read Section 6: Digital Filters in Mixed-Signal and DSP Design Techniques (Analog Devices, 2000). How do I interface with the part? The part can be configured by using a 4-wire SPI interface; this interface is also used as the data interface. After the AD7176-2 is configured on the board, the SPI interface allows the user to read the status of the part and to change the setup to optimize performance. Are there any ESD protection schemes that should be considered for the AD7176-2? This converter is manufactured on a standard CMOS process; therefore, all standard practices and protection schemes that apply to other CMOS devices also apply to this device. There are ESD protection diodes on all the inputs that protect the device from possible ESD damage due to handling and production. To determine the appropriate ESD precautions, refer to the AD7176-2 data sheet for information about the absolute maximum ratings. What information is provided in the noise tables of the AD7176-2 data sheet, and what are the sources of this noise? The noise tables in the AD7176-2 data sheet show the output rms noise for different combinations of ODRs and filters. The values given are for bipolar input ranges with an external 5 V reference. The noise values indicated are typical and are generated at an analog input voltage of 0 V based on 1000 conversion results at the specified ODR. It is important to note that the peak-to-peak resolution is calculated based on the peak-to-peak noise. What per channel configurability is available on the AD7176-2? Each channel of the AD7176-2 can be configured with different • • • • Rev. 0 | Page 5 of 6 Gain and offset correction Filter type Output data rate Reference source selection (internal or external) AD7176-2 Key Sheet LEARN MORE AND START DESIGNING To learn more about the AD7176-2 and compatible products or to sample and buy the AD7176-2 device, click on the links provided or contact an Analog Devices, Inc., sales representative. COMPATIBLE DEVICES Table 4. Recommended Compatible Devices 1 Linear Regulators ADP3309 family ADP7104 family 1 Precision References ADR44x family ADC Driver Amplifiers AD8606 family AD8475 family ADA4940-2/ADA4941 family Circuits from the Lab™ CN-0310: Precision 24-Bit, 250 kSPS Single-Supply Sigma-Delta ADC System for Industrial Signal Levels Information about additional companion products is provided on the AD7176-2 product page. PACKAGE DIAGRAM 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 8. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters GETTING STARTED AD7176-2 DATA SHEET SAMPLE AND BUY THE AD7176-2 ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG11266-0-3/13(0) Rev. 0 | Page 6 of 6 Evaluation Board AD7176-2 evaluation board